+
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+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/diagram1.html
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm (revision 264)
@@ -0,0 +1,189 @@
+
+
+softransmit.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SOFTransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (SOFEnable , SOFSent , SOFSyncEn , SOFTimerClr , SOFTimer , clk , rst , sendPacketArbiterGnt , sendPacketArbiterReq , sendPacketRdy , sendPacketWEn );
+input SOFEnable ; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn ;
+input [15 :0 ] SOFTimer ;
+input clk ;
+input rst ;
+input sendPacketArbiterGnt ;
+input sendPacketRdy ;
+output SOFSent ; // single cycle pulse
+output SOFTimerClr ; // Single cycle pulse
+output sendPacketArbiterReq ;
+output sendPacketWEn ;
+
+wire SOFEnable ;
+reg SOFSent , next_SOFSent ;
+wire SOFSyncEn ;
+reg SOFTimerClr , next_SOFTimerClr ;
+wire [15 :0 ] SOFTimer ;
+wire clk ;
+wire rst ;
+wire sendPacketArbiterGnt ;
+reg sendPacketArbiterReq , next_sendPacketArbiterReq ;
+wire sendPacketRdy ;
+reg sendPacketWEn , next_sendPacketWEn ;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2 :0 ] CurrState_SOFTx ;
+reg [2 :0 ] NextState_SOFTx ;
+
+
+//--------------------------------------------------------------------
+// Machine: SOFTx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx )
+begin : SOFTx_NextState
+ NextState_SOFTx <= CurrState_SOFTx ;
+ // Set default values for outputs and signals
+ next_sendPacketArbiterReq <= sendPacketArbiterReq ;
+ next_sendPacketWEn <= sendPacketWEn ;
+ next_SOFTimerClr <= SOFTimerClr ;
+ next_SOFSent <= SOFSent ;
+ case (CurrState_SOFTx ) // synopsys parallel_case full_case
+ `START_STX :
+ NextState_SOFTx <= `WAIT_SOF_NEAR ;
+ `WAIT_SOF_NEAR :
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1 ))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT ;
+ next_sendPacketArbiterReq <= 1'b1 ;
+ end
+ `WAIT_SP_GNT :
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1 )
+ NextState_SOFTx <= `WAIT_SOF_NOW ;
+ `WAIT_SOF_NOW :
+ if (SOFTimer >= `SOF_TX_TIME )
+ begin
+ NextState_SOFTx <= `SOF_FIN ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_SOFTimerClr <= 1'b1 ;
+ next_SOFSent <= 1'b1 ;
+ end
+ else if (SOFEnable == 1'b0 )
+ begin
+ NextState_SOFTx <= `SOF_FIN ;
+ next_SOFTimerClr <= 1'b1 ;
+ end
+ `SOF_FIN :
+ begin
+ next_sendPacketWEn <= 1'b0 ;
+ next_SOFTimerClr <= 1'b0 ;
+ next_SOFSent <= 1'b0 ;
+ NextState_SOFTx <= `WAIT_SOF_NEAR ;
+ next_sendPacketArbiterReq <= 1'b0 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : SOFTx_CurrentState
+ if (rst )
+ CurrState_SOFTx <= `START_STX ;
+ else
+ CurrState_SOFTx <= NextState_SOFTx ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : SOFTx_RegOutput
+ if (rst )
+ begin
+ SOFSent <= 1'b0 ;
+ SOFTimerClr <= 1'b0 ;
+ sendPacketArbiterReq <= 1'b0 ;
+ sendPacketWEn <= 1'b0 ;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent ;
+ SOFTimerClr <= next_SOFTimerClr ;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq ;
+ sendPacketWEn <= next_sendPacketWEn ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm (revision 264)
@@ -0,0 +1,104 @@
+
+
+hostSlaveMuxBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+ module hostSlaveMuxBI (dataIn , dataOut , writeEn , strobe_i , clk , rst ,
+ hostMode , hostSlaveMuxSel );
+
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+input hostSlaveMuxSel ;
+output hostMode ;
+
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+wire hostSlaveMuxSel ;
+reg hostMode ;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk )
+begin
+ if (rst == 1'b1 )
+ hostMode <= 1'b0 ;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 )
+ hostMode <= dataIn [0 ];
+ end
+end
+
+
+// async read mux
+always @(hostMode )
+begin
+ dataOut <= {7'h0 , hostMode };
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm (revision 264)
@@ -0,0 +1,135 @@
+
+
+usbSlaveControl_h.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS ) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+
+
+
+
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_PREAM_PKT.png
===================================================================
Cannot display: file marked as a binary type.
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm (revision 264)
@@ -0,0 +1,195 @@
+
+
+sofcontroller.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SOFController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:07 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (HCTxPortCntl , HCTxPortData , HCTxPortGnt , HCTxPortRdy , HCTxPortReq , HCTxPortWEn , SOFEnable , SOFTimerClr , SOFTimer , clk , rst );
+input HCTxPortGnt ;
+input HCTxPortRdy ;
+input SOFEnable ;
+input SOFTimerClr ;
+input clk ;
+input rst ;
+output [7 :0 ] HCTxPortCntl ;
+output [7 :0 ] HCTxPortData ;
+output HCTxPortReq ;
+output HCTxPortWEn ;
+output [15 :0 ] SOFTimer ;
+
+reg [7 :0 ] HCTxPortCntl , next_HCTxPortCntl ;
+reg [7 :0 ] HCTxPortData , next_HCTxPortData ;
+wire HCTxPortGnt ;
+wire HCTxPortRdy ;
+reg HCTxPortReq , next_HCTxPortReq ;
+reg HCTxPortWEn , next_HCTxPortWEn ;
+wire SOFEnable ;
+wire SOFTimerClr ;
+reg [15 :0 ] SOFTimer , next_SOFTimer ;
+wire clk ;
+wire rst ;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2 :0 ] CurrState_sofCntl ;
+reg [2 :0 ] NextState_sofCntl ;
+
+
+//--------------------------------------------------------------------
+// Machine: sofCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl )
+begin : sofCntl_NextState
+ NextState_sofCntl <= CurrState_sofCntl ;
+ // Set default values for outputs and signals
+ next_HCTxPortReq <= HCTxPortReq ;
+ next_HCTxPortWEn <= HCTxPortWEn ;
+ next_HCTxPortData <= HCTxPortData ;
+ next_HCTxPortCntl <= HCTxPortCntl ;
+ next_SOFTimer <= SOFTimer ;
+ case (CurrState_sofCntl ) // synopsys parallel_case full_case
+ `START_SC :
+ NextState_sofCntl <= `WAIT_SOF_EN ;
+ `WAIT_SOF_EN :
+ if (SOFEnable == 1'b1 )
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT ;
+ next_HCTxPortReq <= 1'b1 ;
+ end
+ `WAIT_SEND_RESUME :
+ if (HCTxPortRdy == 1'b1 )
+ begin
+ NextState_sofCntl <= `CLR_WEN ;
+ next_HCTxPortWEn <= 1'b1 ;
+ next_HCTxPortData <= 8'h00 ;
+ next_HCTxPortCntl <= `TX_RESUME_START ;
+ end
+ `INC_TIMER :
+ begin
+ next_HCTxPortReq <= 1'b0 ;
+ if (SOFTimerClr == 1'b1 )
+ next_SOFTimer <= 16'h0000 ;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1 ;
+ if (SOFEnable == 1'b0 )
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN ;
+ next_SOFTimer <= 16'h0000 ;
+ end
+ end
+ `SC_WAIT_GNT :
+ if (HCTxPortGnt == 1'b1 )
+ NextState_sofCntl <= `WAIT_SEND_RESUME ;
+ `CLR_WEN :
+ begin
+ next_HCTxPortWEn <= 1'b0 ;
+ NextState_sofCntl <= `INC_TIMER ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : sofCntl_CurrentState
+ if (rst )
+ CurrState_sofCntl <= `START_SC ;
+ else
+ CurrState_sofCntl <= NextState_sofCntl ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : sofCntl_RegOutput
+ if (rst )
+ begin
+ SOFTimer <= 16'h0000 ;
+ HCTxPortCntl <= 8'h00 ;
+ HCTxPortData <= 8'h00 ;
+ HCTxPortWEn <= 1'b0 ;
+ HCTxPortReq <= 1'b0 ;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer ;
+ HCTxPortCntl <= next_HCTxPortCntl ;
+ HCTxPortData <= next_HCTxPortData ;
+ HCTxPortWEn <= next_HCTxPortWEn ;
+ HCTxPortReq <= next_HCTxPortReq ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
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===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.png
___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm (revision 264)
@@ -0,0 +1,416 @@
+
+
+usbHostControl.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module usbHostControl (
+ clk , rst ,
+ //sendPacket
+ TxFifoRE , TxFifoData , TxFifoEmpty ,
+ //getPacket
+ RxFifoWE , RxFifoData , RxFifoFull ,
+ RxByteStatus , RxData , RxDataValid ,
+ SIERxTimeOut ,
+ //speedCtrlMux
+ fullSpeedRate , fullSpeedPol ,
+ //HCTxPortArbiter
+ HCTxPortEn , HCTxPortRdy ,
+ HCTxPortData , HCTxPortCtrl ,
+ //rxStatusMonitor
+ connectStateIn ,
+ resumeDetectedIn ,
+ //USBHostControlBI
+ busAddress ,
+ busDataIn ,
+ busDataOut ,
+ busWriteEn ,
+ busStrobe_i ,
+ SOFSentIntOut ,
+ connEventIntOut ,
+ resumeIntOut ,
+ transDoneIntOut ,
+ hostControlSelect
+ );
+
+input clk , rst ;
+//sendPacket
+output TxFifoRE ;
+input [7 :0 ] TxFifoData ;
+input TxFifoEmpty ;
+//getPacket
+output RxFifoWE ;
+output [7 :0 ] RxFifoData ;
+input RxFifoFull ;
+input [7 :0 ] RxByteStatus ;
+input [7 :0 ] RxData ;
+input RxDataValid ;
+input SIERxTimeOut ;
+//speedCtrlMux
+output fullSpeedRate ;
+output fullSpeedPol ;
+//HCTxPortArbiter
+output HCTxPortEn ;
+input HCTxPortRdy ;
+output [7 :0 ] HCTxPortData ;
+output [7 :0 ] HCTxPortCtrl ;
+//rxStatusMonitor
+input [1 :0 ] connectStateIn ;
+input resumeDetectedIn ;
+//USBHostControlBI
+input [3 :0 ] busAddress ;
+input [7 :0 ] busDataIn ;
+output [7 :0 ] busDataOut ;
+input busWriteEn ;
+input busStrobe_i ;
+output SOFSentIntOut ;
+output connEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+input hostControlSelect ;
+
+wire clk ;
+wire rst ;
+wire [10 :0 ] frameNum ;
+wire SOFSent ;
+wire TxFifoRE ;
+wire [7 :0 ] TxFifoData ;
+wire TxFifoEmpty ;
+wire RxFifoWE ;
+wire [7 :0 ] RxFifoData ;
+wire RxFifoFull ;
+wire [7 :0 ] RxByteStatus ;
+wire [7 :0 ] RxData ;
+wire RxDataValid ;
+wire SIERxTimeOut ;
+wire fullSpeedRate ;
+wire fullSpeedPol ;
+wire HCTxPortEn ;
+wire HCTxPortRdy ;
+wire [7 :0 ] HCTxPortData ;
+wire [7 :0 ] HCTxPortCtrl ;
+wire [1 :0 ] connectStateIn ;
+wire resumeDetectedIn ;
+wire [3 :0 ] busAddress ;
+wire [7 :0 ] busDataIn ;
+wire [7 :0 ] busDataOut ;
+wire busWriteEn ;
+wire busStrobe_i ;
+wire SOFSentIntOut ;
+wire connEventIntOut ;
+wire resumeIntOut ;
+wire transDoneIntOut ;
+wire hostControlSelect ;
+
+//internal wiring
+wire SOFTimerClr ;
+wire getPacketREn ;
+wire getPacketRdy ;
+wire HCTxGnt ;
+wire HCTxReq ;
+wire [3 :0 ] HC_PID ;
+wire HC_SP_WEn ;
+wire SOFTxGnt ;
+wire SOFTxReq ;
+wire SOF_SP_WEn ;
+wire SOFEnable ;
+wire SOFSyncEn ;
+wire sendPacketCPReadyIn ;
+wire sendPacketCPReadyOut ;
+wire [3 :0 ] sendPacketCPPIDIn ;
+wire [3 :0 ] sendPacketCPPIDOut ;
+wire sendPacketCPWEnIn ;
+wire sendPacketCPWEnOut ;
+wire sendPacketCPFSRate ;
+wire sendPacketCPFSPol ;
+wire sendPacketCPGrabLine ;
+wire [7 :0 ] SOFCntlCntl ;
+wire [7 :0 ] SOFCntlData ;
+wire SOFCntlGnt ;
+wire SOFCntlReq ;
+wire SOFCntlWEn ;
+wire [7 :0 ] directCntlCntl ;
+wire [7 :0 ] directCntlData ;
+wire directCntlGnt ;
+wire directCntlReq ;
+wire directCntlWEn ;
+wire [7 :0 ] sendPacketCntl ;
+wire [7 :0 ] sendPacketData ;
+wire sendPacketGnt ;
+wire sendPacketReq ;
+wire sendPacketWEn ;
+wire [15 :0 ] SOFTimer ;
+wire clrTxReq ;
+wire transDone ;
+wire transReq ;
+wire [1 :0 ] transType ;
+wire preAmbleEnable ;
+wire [1 :0 ] directLineState ;
+wire directLineCtrlEn ;
+wire [6 :0 ] TxAddr ;
+wire [3 :0 ] TxEndP ;
+wire [7 :0 ] RxPktStatus ;
+wire [3 :0 ] RxPID ;
+wire directCtrlRate ;
+wire directCtrlPol ;
+wire [1 :0 ] connectStateOut ;
+wire resumeIntFromRxStatusMon ;
+wire connectionEventFromRxStatusMon ;
+
+USBHostControlBI u_USBHostControlBI
+ (.address (busAddress ),
+ .dataIn (busDataIn ),
+ .dataOut (busDataOut ),
+ .writeEn (busWriteEn ),
+ .strobe_i (busStrobe_i ),
+ .clk (clk ),
+ .rst (rst ),
+ .SOFSentIntOut (SOFSentIntOut ),
+ .connEventIntOut (connEventIntOut ),
+ .resumeIntOut (resumeIntOut ),
+ .transDoneIntOut (transDoneIntOut ),
+ .TxTransTypeReg (transType ),
+ .TxSOFEnableReg (SOFEnable ),
+ .TxAddrReg (TxAddr ),
+ .TxEndPReg (TxEndP ),
+ .frameNumIn (frameNum ),
+ .RxPktStatusIn (RxPktStatus ),
+ .RxPIDIn (RxPID ),
+ .connectStateIn (connectStateOut ),
+ .SOFSentIn (SOFSent ),
+ .connEventIn (connectionEventFromRxStatusMon ),
+ .resumeIntIn (resumeIntFromRxStatusMon ),
+ .transDoneIn (transDone ),
+ .hostControlSelect (hostControlSelect ),
+ .clrTransReq (clrTxReq ),
+ .preambleEn (preAmbleEnable ),
+ .SOFSync (SOFSyncEn ),
+ .TxLineState (directLineState ),
+ .LineDirectControlEn (directLineCtrlEn ),
+ .fullSpeedPol (directCtrlPol ),
+ .fullSpeedRate (directCtrlRate ),
+ .transReq (transReq )
+
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus (RxPktStatus ),
+ .clearTXReq (clrTxReq ),
+ .clk (clk ),
+ .getPacketREn (getPacketREn ),
+ .getPacketRdy (getPacketRdy ),
+ .rst (rst ),
+ .sendPacketArbiterGnt (HCTxGnt ),
+ .sendPacketArbiterReq (HCTxReq ),
+ .sendPacketPID (HC_PID ),
+ .sendPacketRdy (sendPacketCPReadyOut ),
+ .sendPacketWEn (HC_SP_WEn ),
+ .transDone (transDone ),
+ .transReq (transReq ),
+ .transType (transType ) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl (SOFCntlCntl ),
+ .HCTxPortData (SOFCntlData ),
+ .HCTxPortGnt (SOFCntlGnt ),
+ .HCTxPortRdy (HCTxPortRdy ),
+ .HCTxPortReq (SOFCntlReq ),
+ .HCTxPortWEn (SOFCntlWEn ),
+ .SOFEnable (SOFEnable ),
+ .SOFTimerClr (SOFTimerClr ),
+ .SOFTimer (SOFTimer ),
+ .clk (clk ),
+ .rst (rst ) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable (SOFEnable ),
+ .SOFSent (SOFSent ),
+ .SOFSyncEn (SOFSyncEn ),
+ .SOFTimerClr (SOFTimerClr ),
+ .SOFTimer (SOFTimer ),
+ .clk (clk ),
+ .rst (rst ),
+ .sendPacketArbiterGnt (SOFTxGnt ),
+ .sendPacketArbiterReq (SOFTxReq ),
+ .sendPacketRdy (sendPacketCPReadyOut ),
+ .sendPacketWEn (SOF_SP_WEn ) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt (HCTxGnt ),
+ .HCTxReq (HCTxReq ),
+ .HC_PID (HC_PID ),
+ .HC_SP_WEn (HC_SP_WEn ),
+ .SOFTxGnt (SOFTxGnt ),
+ .SOFTxReq (SOFTxReq ),
+ .SOF_SP_WEn (SOF_SP_WEn ),
+ .clk (clk ),
+ .rst (rst ),
+ .sendPacketPID (sendPacketCPPIDIn ),
+ .sendPacketWEnable (sendPacketCPWEnIn ) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID (sendPacketCPPIDIn ),
+ .clk (clk ),
+ .fullSpeedBitRate (sendPacketCPFSRate ),
+ .fullSpeedPolarity (sendPacketCPFSPol ),
+ .grabLineControl (sendPacketCPGrabLine ),
+ .preAmbleEnable (preAmbleEnable ),
+ .rst (rst ),
+ .sendPacketCPReady (sendPacketCPReadyOut ),
+ .sendPacketCPWEn (sendPacketCPWEnIn ),
+ .sendPacketPID (sendPacketCPPIDOut ),
+ .sendPacketRdy (sendPacketCPReadyIn ),
+ .sendPacketWEn (sendPacketCPWEnOut ) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl (sendPacketCntl ),
+ .HCTxPortData (sendPacketData ),
+ .HCTxPortGnt (sendPacketGnt ),
+ .HCTxPortRdy (HCTxPortRdy ),
+ .HCTxPortReq (sendPacketReq ),
+ .HCTxPortWEn (sendPacketWEn ),
+ .PID (sendPacketCPPIDOut ),
+ .TxAddr (TxAddr ),
+ .TxEndP (TxEndP ),
+ .clk (clk ),
+ .fifoData (TxFifoData ),
+ .fifoEmpty (TxFifoEmpty ),
+ .fifoReadEn (TxFifoRE ),
+ .frameNum (frameNum ),
+ .rst (rst ),
+ .sendPacketRdy (sendPacketCPReadyIn ),
+ .sendPacketWEn (sendPacketCPWEnOut ) );
+
+directControl u_directControl
+ (.HCTxPortCntl (directCntlCntl ),
+ .HCTxPortData (directCntlData ),
+ .HCTxPortGnt (directCntlGnt ),
+ .HCTxPortRdy (HCTxPortRdy ),
+ .HCTxPortReq (directCntlReq ),
+ .HCTxPortWEn (directCntlWEn ),
+ .clk (clk ),
+ .directControlEn (directLineCtrlEn ),
+ .directControlLineState (directLineState ),
+ .rst (rst ) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl (HCTxPortCtrl ),
+ .HCTxPortData (HCTxPortData ),
+ .HCTxPortWEnable (HCTxPortEn ),
+ .SOFCntlCntl (SOFCntlCntl ),
+ .SOFCntlData (SOFCntlData ),
+ .SOFCntlGnt (SOFCntlGnt ),
+ .SOFCntlReq (SOFCntlReq ),
+ .SOFCntlWEn (SOFCntlWEn ),
+ .clk (clk ),
+ .directCntlCntl (directCntlCntl ),
+ .directCntlData (directCntlData ),
+ .directCntlGnt (directCntlGnt ),
+ .directCntlReq (directCntlReq ),
+ .directCntlWEn (directCntlWEn ),
+ .rst (rst ),
+ .sendPacketCntl (sendPacketCntl ),
+ .sendPacketData (sendPacketData ),
+ .sendPacketGnt (sendPacketGnt ),
+ .sendPacketReq (sendPacketReq ),
+ .sendPacketWEn (sendPacketWEn ) );
+
+getPacket u_getPacket
+ (.RXDataIn (RxData ),
+ .RXDataValid (RxDataValid ),
+ .RXFifoData (RxFifoData ),
+ .RXFifoFull (RxFifoFull ),
+ .RXFifoWEn (RxFifoWE ),
+ .RXPacketRdy (getPacketRdy ),
+ .RXPktStatus (RxPktStatus ),
+ .RXStreamStatusIn (RxByteStatus ),
+ .RxPID (RxPID ),
+ .SIERxTimeOut (SIERxTimeOut ),
+ .clk (clk ),
+ .getPacketEn (getPacketREn ),
+ .rst (rst ) );
+
+speedCtrlMux u_speedCtrlMux
+ (.directCtrlRate (directCtrlRate ),
+ .directCtrlPol (directCtrlPol ),
+ .sendPacketRate (sendPacketCPFSRate ),
+ .sendPacketPol (sendPacketCPFSPol ),
+ .sendPacketSel (sendPacketCPGrabLine ),
+ .fullSpeedRate (fullSpeedRate ),
+ .fullSpeedPol (fullSpeedPol ) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn (connectStateIn ),
+ .connectStateOut (connectStateOut ),
+ .resumeDetectedIn (resumeDetectedIn ),
+ .connectionEventOut (connectionEventFromRxStatusMon ),
+ .resumeIntOut (resumeIntFromRxStatusMon ),
+ .clk (clk ),
+ .rst (rst ) );
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm (revision 264)
@@ -0,0 +1,124 @@
+
+
+usbHostControl_h.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl_h.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+`define SOF_TX_MARGIN 2
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm (revision 264)
@@ -0,0 +1,235 @@
+
+
+sendpacketcheckpreamble.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacketCheckPreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk , fullSpeedBitRate , fullSpeedPolarity , grabLineControl , preAmbleEnable , rst , sendPacketCPPID , sendPacketCPReady , sendPacketCPWEn , sendPacketPID , sendPacketRdy , sendPacketWEn );
+input clk ;
+input preAmbleEnable ;
+input rst ;
+input [3 :0 ] sendPacketCPPID ;
+input sendPacketCPWEn ;
+input sendPacketRdy ;
+output fullSpeedBitRate ;
+output fullSpeedPolarity ;
+output grabLineControl ; // mux select
+output sendPacketCPReady ;
+output [3 :0 ] sendPacketPID ;
+output sendPacketWEn ;
+
+wire clk ;
+reg fullSpeedBitRate , next_fullSpeedBitRate ;
+reg fullSpeedPolarity , next_fullSpeedPolarity ;
+reg grabLineControl , next_grabLineControl ;
+wire preAmbleEnable ;
+wire rst ;
+wire [3 :0 ] sendPacketCPPID ;
+reg sendPacketCPReady , next_sendPacketCPReady ;
+wire sendPacketCPWEn ;
+reg [3 :0 ] sendPacketPID , next_sendPacketPID ;
+wire sendPacketRdy ;
+reg sendPacketWEn , next_sendPacketWEn ;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3 :0 ] CurrState_sendPktCP ;
+reg [3 :0 ] NextState_sendPktCP ;
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktCP
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP )
+begin : sendPktCP_NextState
+ NextState_sendPktCP <= CurrState_sendPktCP ;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady ;
+ next_sendPacketWEn <= sendPacketWEn ;
+ next_sendPacketPID <= sendPacketPID ;
+ next_fullSpeedBitRate <= fullSpeedBitRate ;
+ next_fullSpeedPolarity <= fullSpeedPolarity ;
+ next_grabLineControl <= grabLineControl ;
+ case (CurrState_sendPktCP ) // synopsys parallel_case full_case
+ `SPC_WAIT_EN :
+ if (sendPacketCPWEn == 1'b1 )
+ begin
+ NextState_sendPktCP <= `CHK_PREAM ;
+ next_sendPacketCPReady <= 1'b0 ;
+ end
+ `START_SPC :
+ NextState_sendPktCP <= `SPC_WAIT_EN ;
+ `CHK_PREAM :
+ if (preAmbleEnable == 1'b1 )
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1 ;
+ else
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1 ;
+ `READY :
+ begin
+ next_sendPacketCPReady <= 1'b1 ;
+ NextState_sendPktCP <= `SPC_WAIT_EN ;
+ end
+ `PREAM_PKT_SND_PREAM :
+ begin
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `PREAMBLE ;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2 ;
+ next_sendPacketWEn <= 1'b0 ;
+ end
+ `PREAM_PKT_WAIT_RDY1 :
+ if (sendPacketRdy == 1'b1 )
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM ;
+ next_fullSpeedBitRate <= 1'b1 ;
+ next_fullSpeedPolarity <= 1'b1 ;
+ next_grabLineControl <= 1'b1 ;
+ end
+ `PREAM_PKT_WAIT_RDY2 :
+ if (sendPacketRdy == 1'b1 )
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID ;
+ next_fullSpeedBitRate <= 1'b1 ;
+ end
+ `PREAM_PKT_SND_PID :
+ begin
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= sendPacketCPPID ;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3 ;
+ next_sendPacketWEn <= 1'b0 ;
+ end
+ `PREAM_PKT_WAIT_RDY3 :
+ if (sendPacketRdy == 1'b1 )
+ begin
+ NextState_sendPktCP <= `READY ;
+ next_grabLineControl <= 1'b0 ;
+ end
+ `REG_PKT_SEND_PID :
+ begin
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= sendPacketCPPID ;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY ;
+ end
+ `REG_PKT_WAIT_RDY1 :
+ if (sendPacketRdy == 1'b1 )
+ NextState_sendPktCP <= `REG_PKT_SEND_PID ;
+ `REG_PKT_WAIT_RDY :
+ begin
+ next_sendPacketWEn <= 1'b0 ;
+ NextState_sendPktCP <= `READY ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : sendPktCP_CurrentState
+ if (rst )
+ CurrState_sendPktCP <= `START_SPC ;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : sendPktCP_RegOutput
+ if (rst )
+ begin
+ sendPacketWEn <= 1'b0 ;
+ sendPacketPID <= 4'b0 ;
+ fullSpeedBitRate <= 1'b0 ;
+ fullSpeedPolarity <= 1'b0 ;
+ grabLineControl <= 1'b0 ;
+ sendPacketCPReady <= 1'b1 ;
+ end
+ else
+ begin
+ sendPacketWEn <= next_sendPacketWEn ;
+ sendPacketPID <= next_sendPacketPID ;
+ fullSpeedBitRate <= next_fullSpeedBitRate ;
+ fullSpeedPolarity <= next_fullSpeedPolarity ;
+ grabLineControl <= next_grabLineControl ;
+ sendPacketCPReady <= next_sendPacketCPReady ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm (revision 264)
@@ -0,0 +1,94 @@
+
+
+speedCtrlMux.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module speedCtrlMux (directCtrlRate , directCtrlPol , sendPacketRate , sendPacketPol , sendPacketSel , fullSpeedRate , fullSpeedPol );
+input directCtrlRate ;
+input directCtrlPol ;
+input sendPacketRate ;
+input sendPacketPol ;
+input sendPacketSel ;
+output fullSpeedRate ;
+output fullSpeedPol ;
+
+wire directCtrlRate ;
+wire directCtrlPol ;
+wire sendPacketRate ;
+wire sendPacketPol ;
+wire sendPacketSel ;
+reg fullSpeedRate ;
+reg fullSpeedPol ;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel )
+begin
+ if (sendPacketSel == 1'b1 )
+ begin
+ fullSpeedRate <= sendPacketRate ;
+ fullSpeedPol <= sendPacketPol ;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate ;
+ fullSpeedPol <= directCtrlPol ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm (revision 264)
@@ -0,0 +1,88 @@
+
+
+usbConstants_h.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbConstants_h.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+//// USB global constants as defined by USB spec 1.1
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm (revision 264)
@@ -0,0 +1,91 @@
+
+
+wishBoneBus_h.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBus_h.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_CRC.png
===================================================================
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___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_IDLE.png
===================================================================
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___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_SPCL.png
===================================================================
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html (revision 264)
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_BYTE1.png
===================================================================
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___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_HS.png
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_HS.png
___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_RES_ST.png
===================================================================
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html
===================================================================
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html (nonexistent)
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm (revision 264)
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+
+
+hostSlaveMux.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE ,
+ SIEPortCtrlInFromHost ,
+ SIEPortCtrlInFromSlave ,
+ SIEPortDataInToSIE ,
+ SIEPortDataInFromHost ,
+ SIEPortDataInFromSlave ,
+ SIEPortWEnToSIE ,
+ SIEPortWEnFromHost ,
+ SIEPortWEnFromSlave ,
+ fullSpeedPolarityToSIE ,
+ fullSpeedPolarityFromHost ,
+ fullSpeedPolarityFromSlave ,
+ fullSpeedBitRateToSIE ,
+ fullSpeedBitRateFromHost ,
+ fullSpeedBitRateFromSlave ,
+ dataIn ,
+ dataOut ,
+ writeEn ,
+ strobe_i ,
+ clk ,
+ rst ,
+ hostSlaveMuxSel );
+
+
+output [7 :0 ] SIEPortCtrlInToSIE ;
+input [7 :0 ] SIEPortCtrlInFromHost ;
+input [7 :0 ] SIEPortCtrlInFromSlave ;
+output [7 :0 ] SIEPortDataInToSIE ;
+input [7 :0 ] SIEPortDataInFromHost ;
+input [7 :0 ] SIEPortDataInFromSlave ;
+output SIEPortWEnToSIE ;
+input SIEPortWEnFromHost ;
+input SIEPortWEnFromSlave ;
+output fullSpeedPolarityToSIE ;
+input fullSpeedPolarityFromHost ;
+input fullSpeedPolarityFromSlave ;
+output fullSpeedBitRateToSIE ;
+input fullSpeedBitRateFromHost ;
+input fullSpeedBitRateFromSlave ;
+//hostSlaveMuxBI
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+input hostSlaveMuxSel ;
+
+reg [7 :0 ] SIEPortCtrlInToSIE ;
+wire [7 :0 ] SIEPortCtrlInFromHost ;
+wire [7 :0 ] SIEPortCtrlInFromSlave ;
+reg [7 :0 ] SIEPortDataInToSIE ;
+wire [7 :0 ] SIEPortDataInFromHost ;
+wire [7 :0 ] SIEPortDataInFromSlave ;
+reg SIEPortWEnToSIE ;
+wire SIEPortWEnFromHost ;
+wire SIEPortWEnFromSlave ;
+reg fullSpeedPolarityToSIE ;
+wire fullSpeedPolarityFromHost ;
+wire fullSpeedPolarityFromSlave ;
+reg fullSpeedBitRateToSIE ;
+wire fullSpeedBitRateFromHost ;
+wire fullSpeedBitRateFromSlave ;
+//hostSlaveMuxBI
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+wire [7 :0 ] dataOut ;
+wire hostSlaveMuxSel ;
+
+//internal wires and regs
+wire hostMode ;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave )
+begin
+ if (hostMode == 1'b1 )
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost ;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost ;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost ;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost ;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost ;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave ;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave ;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave ;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave ;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave ;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn (dataIn ),
+ .dataOut (dataOut ),
+ .writeEn (writeEn ),
+ .strobe_i (strobe_i ),
+ .clk (clk ),
+ .rst (rst ),
+ .hostMode (hostMode ),
+ .hostSlaveMuxSel (hostSlaveMuxSel ) );
+
+
+endmodule
+
+
+
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm (revision 264)
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+
+
+usbSerialInterfaceEngine_h.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine_h.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+ // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
+`define OVER_SAMPLE_RATE 4
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 6
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+
+
+
+
+
+
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm (revision 264)
@@ -0,0 +1,717 @@
+
+
+SIETransmitter.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (CRC16En , CRC16Result , CRC16UpdateRdy , CRC5En , CRC5Result , CRC5UpdateRdy , CRC5_8Bit , CRCData , JBit , KBit , SIEPortCtrlIn , SIEPortDataIn , SIEPortTxRdy , SIEPortWEn , TxByteOutCtrl , TxByteOut , USBWireCtrl , USBWireData , USBWireGnt , USBWireRdy , USBWireReq , USBWireWEn , clk , processTxByteRdy , processTxByteWEn , rst , rstCRC );
+input [15 :0 ] CRC16Result ;
+input CRC16UpdateRdy ;
+input [4 :0 ] CRC5Result ;
+input CRC5UpdateRdy ;
+input [1 :0 ] JBit ;
+input [1 :0 ] KBit ;
+input [7 :0 ] SIEPortCtrlIn ;
+input [7 :0 ] SIEPortDataIn ;
+input SIEPortWEn ;
+input USBWireGnt ;
+input USBWireRdy ;
+input clk ;
+input processTxByteRdy ;
+input rst ;
+output CRC16En ;
+output CRC5En ;
+output CRC5_8Bit ;
+output [7 :0 ] CRCData ;
+output SIEPortTxRdy ;
+output [7 :0 ] TxByteOutCtrl ;
+output [7 :0 ] TxByteOut ;
+output USBWireCtrl ;
+output [1 :0 ] USBWireData ;
+output USBWireReq ;
+output USBWireWEn ;
+output processTxByteWEn ;
+output rstCRC ;
+
+reg CRC16En , next_CRC16En ;
+wire [15 :0 ] CRC16Result ;
+wire CRC16UpdateRdy ;
+reg CRC5En , next_CRC5En ;
+wire [4 :0 ] CRC5Result ;
+wire CRC5UpdateRdy ;
+reg CRC5_8Bit , next_CRC5_8Bit ;
+reg [7 :0 ] CRCData , next_CRCData ;
+wire [1 :0 ] JBit ;
+wire [1 :0 ] KBit ;
+wire [7 :0 ] SIEPortCtrlIn ;
+wire [7 :0 ] SIEPortDataIn ;
+reg SIEPortTxRdy , next_SIEPortTxRdy ;
+wire SIEPortWEn ;
+reg [7 :0 ] TxByteOutCtrl , next_TxByteOutCtrl ;
+reg [7 :0 ] TxByteOut , next_TxByteOut ;
+reg USBWireCtrl , next_USBWireCtrl ;
+reg [1 :0 ] USBWireData , next_USBWireData ;
+wire USBWireGnt ;
+wire USBWireRdy ;
+reg USBWireReq , next_USBWireReq ;
+reg USBWireWEn , next_USBWireWEn ;
+wire clk ;
+wire processTxByteRdy ;
+reg processTxByteWEn , next_processTxByteWEn ;
+wire rst ;
+reg rstCRC , next_rstCRC ;
+
+// diagram signals declarations
+reg [7 :0 ]SIEPortCtrl , next_SIEPortCtrl ;
+reg [7 :0 ]SIEPortData , next_SIEPortData ;
+reg [4 :0 ]i , next_i ;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define IDLE_CHK_FIN 6'b000001
+`define DIR_CTL_CHK_FIN 6'b000010
+`define PKT_ST_CHK_PID 6'b000011
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
+`define PKT_ST_SPCL_PKT_SENT 6'b000101
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
+`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
+`define PKT_ST_HS_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define IDLE_STX_WAIT_GNT 6'b011001
+`define IDLE_STX_WAIT_RDY 6'b011010
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
+`define DIR_CTL_WAIT_GNT 6'b100001
+`define RES_ST_WAIT_GNT 6'b100010
+`define PKT_ST_HS_WAIT_RDY 6'b100011
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
+`define PKT_ST_SPCL_WAIT_RDY 6'b100101
+`define RES_ST_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
+`define DIR_CTL_WAIT_RDY 6'b101011
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
+`define PKT_ST_WAIT_RDY_PKT 6'b101110
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
+`define PKT_ST_WAIT_RDY_WIRE 6'b110000
+`define PKT_ST_WAIT_GNT 6'b110001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
+
+reg [5 :0 ] CurrState_SIETx ;
+reg [5 :0 ] NextState_SIETx ;
+
+
+//--------------------------------------------------------------------
+// Machine: SIETx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SIEPortDataIn or SIEPortCtrlIn or i or SIEPortData or JBit or CRC16Result or CRC5Result or KBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx )
+begin : SIETx_NextState
+ NextState_SIETx <= CurrState_SIETx ;
+ // Set default values for outputs and signals
+ next_processTxByteWEn <= processTxByteWEn ;
+ next_TxByteOut <= TxByteOut ;
+ next_TxByteOutCtrl <= TxByteOutCtrl ;
+ next_USBWireData <= USBWireData ;
+ next_USBWireCtrl <= USBWireCtrl ;
+ next_USBWireReq <= USBWireReq ;
+ next_USBWireWEn <= USBWireWEn ;
+ next_rstCRC <= rstCRC ;
+ next_CRCData <= CRCData ;
+ next_CRC5En <= CRC5En ;
+ next_CRC5_8Bit <= CRC5_8Bit ;
+ next_CRC16En <= CRC16En ;
+ next_SIEPortTxRdy <= SIEPortTxRdy ;
+ next_SIEPortData <= SIEPortData ;
+ next_SIEPortCtrl <= SIEPortCtrl ;
+ next_i <= i ;
+ case (CurrState_SIETx ) // synopsys parallel_case full_case
+ `START_SIETX :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ next_TxByteOut <= 8'h00 ;
+ next_TxByteOutCtrl <= 8'h00 ;
+ next_USBWireData <= 2'b00 ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireReq <= 1'b0 ;
+ next_USBWireWEn <= 1'b0 ;
+ next_rstCRC <= 1'b0 ;
+ next_CRCData <= 8'h00 ;
+ next_CRC5En <= 1'b0 ;
+ next_CRC5_8Bit <= 1'b0 ;
+ next_CRC16En <= 1'b0 ;
+ next_SIEPortTxRdy <= 1'b0 ;
+ next_SIEPortData <= 8'h00 ;
+ next_SIEPortCtrl <= 8'h00 ;
+ next_i <= 5'h0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `STX_CHK_ST :
+ if (SIEPortCtrl == `TX_PACKET_START )
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_GNT ;
+ next_USBWireReq <= 1'b1 ;
+ end
+ else if (SIEPortCtrl == `TX_IDLE )
+ begin
+ NextState_SIETx <= `IDLE_STX_WAIT_GNT ;
+ next_USBWireReq <= 1'b1 ;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL )
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT ;
+ next_USBWireReq <= 1'b1 ;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START )
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT ;
+ next_USBWireReq <= 1'b1 ;
+ next_i <= 5'h0 ;
+ end
+ `STX_WAIT_BYTE :
+ begin
+ next_SIEPortTxRdy <= 1'b1 ;
+ if (SIEPortWEn == 1'b1 )
+ begin
+ NextState_SIETx <= `STX_CHK_ST ;
+ next_SIEPortData <= SIEPortDataIn ;
+ next_SIEPortCtrl <= SIEPortCtrlIn ;
+ next_SIEPortTxRdy <= 1'b0 ;
+ end
+ end
+ `DIR_CTL_CHK_FIN :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ next_i <= i + 1'b1 ;
+ if (i == 5'h7 )
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ next_USBWireReq <= 1'b0 ;
+ end
+ else
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY ;
+ end
+ `DIR_CTL_WAIT_GNT :
+ begin
+ next_i <= 5'h0 ;
+ if (USBWireGnt == 1'b1 )
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY ;
+ end
+ `DIR_CTL_WAIT_RDY :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN ;
+ next_USBWireData <= SIEPortData [1 :0 ];
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ `IDLE_CHK_FIN :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ next_i <= i + 1'b1 ;
+ if (i == 5'h7 )
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ next_USBWireReq <= 1'b0 ;
+ end
+ else
+ NextState_SIETx <= `IDLE_STX_WAIT_RDY ;
+ end
+ `IDLE_STX_WAIT_GNT :
+ begin
+ next_i <= 5'h0 ;
+ if (USBWireGnt == 1'b1 )
+ NextState_SIETx <= `IDLE_STX_WAIT_RDY ;
+ end
+ `IDLE_STX_WAIT_RDY :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `IDLE_CHK_FIN ;
+ next_USBWireData <= 2'b00 ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ `PKT_ST_CHK_PID :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ if (SIEPortData [1 :0 ] == `HANDSHAKE )
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY ;
+ else if (SIEPortData [1 :0 ] == `TOKEN )
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY ;
+ else if (SIEPortData [1 :0 ] == `SPECIAL )
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY ;
+ else if (SIEPortData [1 :0 ] == `DATA )
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY ;
+ end
+ `PKT_ST_WAIT_RDY_PKT :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ next_USBWireReq <= 1'b0 ;
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= `SYNC_BYTE ;
+ next_TxByteOutCtrl <= `DATA_START ;
+ end
+ end
+ `PKT_ST_WAIT_RDY_WIRE :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT ;
+ //actively drive the first J bit
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ `PKT_ST_WAIT_GNT :
+ if (USBWireGnt == 1'b1 )
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE ;
+ `PKT_ST_DATA_CRC_PKT_SENT1 :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2 ;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2 :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1 :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1 ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= ~CRC16Result [7 :0 ];
+ next_TxByteOutCtrl <= `DATA_STREAM ;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2 :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2 ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= ~CRC16Result [15 :8 ];
+ next_TxByteOutCtrl <= `DATA_STOP ;
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP :
+ if (SIEPortCtrl == `TX_PACKET_STOP )
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1 ;
+ else
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY ;
+ `PKT_ST_DATA_DATA_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE ;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC :
+ begin
+ next_CRCData <= SIEPortData ;
+ next_CRC16En <= 1'b1 ;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY ;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE :
+ begin
+ next_SIEPortTxRdy <= 1'b1 ;
+ if (SIEPortWEn == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP ;
+ next_SIEPortData <= SIEPortDataIn ;
+ next_SIEPortCtrl <= SIEPortCtrlIn ;
+ next_SIEPortTxRdy <= 1'b0 ;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY :
+ begin
+ next_CRC16En <= 1'b0 ;
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STREAM ;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY :
+ if (CRC16UpdateRdy == 1'b1 )
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC ;
+ `PKT_ST_DATA_PID_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ next_rstCRC <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE ;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STREAM ;
+ next_rstCRC <= 1'b1 ;
+ end
+ `PKT_ST_HS_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `PKT_ST_HS_WAIT_RDY :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STOP ;
+ end
+ `PKT_ST_SPCL_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE ;
+ end
+ `PKT_ST_SPCL_SEND_IDLE1 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE2 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE3 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `PKT_ST_SPCL_WAIT_RDY :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STOP ;
+ end
+ `PKT_ST_SPCL_WAIT_WIRE :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1 :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE ;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC :
+ begin
+ next_CRCData <= SIEPortData ;
+ next_CRC5_8Bit <= 1'b1 ;
+ next_CRC5En <= 1'b1 ;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY ;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE :
+ begin
+ next_SIEPortTxRdy <= 1'b1 ;
+ if (SIEPortWEn == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY ;
+ next_SIEPortData <= SIEPortDataIn ;
+ next_SIEPortCtrl <= SIEPortCtrlIn ;
+ next_SIEPortTxRdy <= 1'b0 ;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY :
+ begin
+ next_CRC5En <= 1'b0 ;
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1 ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STREAM ;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY :
+ if (CRC5UpdateRdy == 1'b1 )
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC ;
+ `PKT_ST_TKN_CRC_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC :
+ begin
+ next_CRCData <= SIEPortData ;
+ next_CRC5_8Bit <= 1'b0 ;
+ next_CRC5En <= 1'b1 ;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY ;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE :
+ begin
+ next_SIEPortTxRdy <= 1'b1 ;
+ if (SIEPortWEn == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY ;
+ next_SIEPortData <= SIEPortDataIn ;
+ next_SIEPortCtrl <= SIEPortCtrlIn ;
+ next_SIEPortTxRdy <= 1'b0 ;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY :
+ begin
+ next_CRC5En <= 1'b0 ;
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= {~CRC5Result , SIEPortData [2 :0 ] };
+ next_TxByteOutCtrl <= `DATA_STOP ;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY :
+ if (CRC5UpdateRdy == 1'b1 )
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC ;
+ `PKT_ST_TKN_PID_PKT_SENT :
+ begin
+ next_processTxByteWEn <= 1'b0 ;
+ next_rstCRC <= 1'b0 ;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE ;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY :
+ if (processTxByteRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT ;
+ next_processTxByteWEn <= 1'b1 ;
+ next_TxByteOut <= SIEPortData ;
+ next_TxByteOutCtrl <= `DATA_STREAM ;
+ next_rstCRC <= 1'b1 ;
+ end
+ `RES_ST_CHK_FIN :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (i == `RESUME_LEN )
+ NextState_SIETx <= `RES_ST_S1 ;
+ else
+ NextState_SIETx <= `RES_ST_WAIT_RDY ;
+ end
+ `RES_ST_S1 :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `RES_ST_S3 ;
+ next_USBWireData <= `SE0 ;
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ `RES_ST_S3 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `RES_ST_S4 ;
+ next_USBWireData <= `SE0 ;
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ end
+ `RES_ST_S4 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `RES_ST_S5 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ end
+ `RES_ST_S5 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `RES_ST_S6 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireWEn <= 1'b1 ;
+ end
+ end
+ `RES_ST_S6 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ next_USBWireReq <= 1'b0 ;
+ NextState_SIETx <= `STX_WAIT_BYTE ;
+ end
+ `RES_ST_WAIT_GNT :
+ if (USBWireGnt == 1'b1 )
+ NextState_SIETx <= `RES_ST_WAIT_RDY ;
+ `RES_ST_WAIT_RDY :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN ;
+ next_USBWireData <= KBit ;
+ next_USBWireCtrl <= `DRIVE ;
+ next_USBWireWEn <= 1'b1 ;
+ next_i <= i + 1'b1 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : SIETx_CurrentState
+ if (rst )
+ CurrState_SIETx <= `START_SIETX ;
+ else
+ CurrState_SIETx <= NextState_SIETx ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : SIETx_RegOutput
+ if (rst )
+ begin
+ SIEPortData <= 8'h00 ;
+ SIEPortCtrl <= 8'h00 ;
+ i <= 5'h0 ;
+ processTxByteWEn <= 1'b0 ;
+ TxByteOut <= 8'h00 ;
+ TxByteOutCtrl <= 8'h00 ;
+ USBWireData <= 2'b00 ;
+ USBWireCtrl <= `TRI_STATE ;
+ USBWireReq <= 1'b0 ;
+ USBWireWEn <= 1'b0 ;
+ rstCRC <= 1'b0 ;
+ CRCData <= 8'h00 ;
+ CRC5En <= 1'b0 ;
+ CRC5_8Bit <= 1'b0 ;
+ CRC16En <= 1'b0 ;
+ SIEPortTxRdy <= 1'b0 ;
+ end
+ else
+ begin
+ SIEPortData <= next_SIEPortData ;
+ SIEPortCtrl <= next_SIEPortCtrl ;
+ i <= next_i ;
+ processTxByteWEn <= next_processTxByteWEn ;
+ TxByteOut <= next_TxByteOut ;
+ TxByteOutCtrl <= next_TxByteOutCtrl ;
+ USBWireData <= next_USBWireData ;
+ USBWireCtrl <= next_USBWireCtrl ;
+ USBWireReq <= next_USBWireReq ;
+ USBWireWEn <= next_USBWireWEn ;
+ rstCRC <= next_rstCRC ;
+ CRCData <= next_CRCData ;
+ CRC5En <= next_CRC5En ;
+ CRC5_8Bit <= next_CRC5_8Bit ;
+ CRC16En <= next_CRC16En ;
+ SIEPortTxRdy <= next_SIEPortTxRdy ;
+ end
+end
+
+endmodule
+
+
+
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Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PID.png
___________________________________________________________________
Added: svn:executable
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===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_TKN.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm (revision 264)
@@ -0,0 +1,31 @@
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm (revision 264)
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm (revision 264)
@@ -0,0 +1,31 @@
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm (revision 264)
@@ -0,0 +1,31 @@
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm (revision 264)
@@ -0,0 +1,31 @@
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm (revision 264)
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
___________________________________________________________________
Added: svn:executable
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
___________________________________________________________________
Added: svn:executable
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
___________________________________________________________________
Added: svn:executable
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===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
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+ ]]>
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
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Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html (revision 264)
@@ -0,0 +1,45 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm (revision 264)
@@ -0,0 +1,94 @@
+
+
+lineControlUpdate.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate (fullSpeedPolarity , fullSpeedBitRate , JBit , KBit );
+input fullSpeedPolarity ;
+input fullSpeedBitRate ;
+output [1 :0 ] JBit ;
+output [1 :0 ] KBit ;
+
+wire fullSpeedPolarity ;
+wire fullSpeedBitRate ;
+reg [1 :0 ] JBit ;
+reg [1 :0 ] KBit ;
+
+
+
+always @(fullSpeedPolarity )
+begin
+ if (fullSpeedPolarity == 1'b1 )
+ begin
+ JBit = `ONE_ZERO ;
+ KBit = `ZERO_ONE ;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE ;
+ KBit = `ONE_ZERO ;
+ end
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html (revision 264)
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
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\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
___________________________________________________________________
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\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html (revision 264)
@@ -0,0 +1,70 @@
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
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+ <![CDATA[
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+ <p>This page uses frames, but your browser doesn't support them. <br></p>
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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Added: svn:mime-type
## -0,0 +1 ##
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html (revision 264)
@@ -0,0 +1,45 @@
+
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+
+
+
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+
+
+
+
+
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+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
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\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html (revision 264)
@@ -0,0 +1,45 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html (revision 264)
@@ -0,0 +1,70 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
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+ ]]>
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
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Added: svn:mime-type
## -0,0 +1 ##
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
___________________________________________________________________
Added: svn:executable
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Added: svn:mime-type
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html (revision 264)
@@ -0,0 +1,70 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
___________________________________________________________________
Added: svn:executable
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm (revision 264)
@@ -0,0 +1,499 @@
+
+
+processRxByte.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:34 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (CRC16En , CRC16Result , CRC16UpdateRdy , CRC5En , CRC5Result , CRC5UpdateRdy , CRC5_8Bit , CRCData , RxByteIn , RxCtrlIn , RxCtrlOut , RxDataOutWEn , RxDataOut , clk , processRxByteRdy , processRxDataInWEn , rst , rstCRC );
+input [15 :0 ] CRC16Result ;
+input CRC16UpdateRdy ;
+input [4 :0 ] CRC5Result ;
+input CRC5UpdateRdy ;
+input [7 :0 ] RxByteIn ;
+input [7 :0 ] RxCtrlIn ;
+input clk ;
+input processRxDataInWEn ;
+input rst ;
+output CRC16En ;
+output CRC5En ;
+output CRC5_8Bit ;
+output [7 :0 ] CRCData ;
+output [7 :0 ] RxCtrlOut ;
+output RxDataOutWEn ;
+output [7 :0 ] RxDataOut ;
+output processRxByteRdy ;
+output rstCRC ;
+
+reg CRC16En , next_CRC16En ;
+wire [15 :0 ] CRC16Result ;
+wire CRC16UpdateRdy ;
+reg CRC5En , next_CRC5En ;
+wire [4 :0 ] CRC5Result ;
+wire CRC5UpdateRdy ;
+reg CRC5_8Bit , next_CRC5_8Bit ;
+reg [7 :0 ] CRCData , next_CRCData ;
+wire [7 :0 ] RxByteIn ;
+wire [7 :0 ] RxCtrlIn ;
+reg [7 :0 ] RxCtrlOut , next_RxCtrlOut ;
+reg RxDataOutWEn , next_RxDataOutWEn ;
+reg [7 :0 ] RxDataOut , next_RxDataOut ;
+wire clk ;
+reg processRxByteRdy , next_processRxByteRdy ;
+wire processRxDataInWEn ;
+wire rst ;
+reg rstCRC , next_rstCRC ;
+
+// diagram signals declarations
+reg ACKRxed , next_ACKRxed ;
+reg CRCError , next_CRCError ;
+reg NAKRxed , next_NAKRxed ;
+reg [2 :0 ]RXByteStMachCurrState , next_RXByteStMachCurrState ;
+reg [9 :0 ]RXDataByteCnt , next_RXDataByteCnt ;
+reg [7 :0 ]RxByte , next_RxByte ;
+reg [7 :0 ]RxCtrl , next_RxCtrl ;
+reg RxOverflow , next_RxOverflow ;
+reg [7 :0 ]RxStatus ;
+reg RxTimeOut , next_RxTimeOut ;
+reg Signal1 , next_Signal1 ;
+reg bitStuffError , next_bitStuffError ;
+reg dataSequence , next_dataSequence ;
+reg stallRxed , next_stallRxed ;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3 :0 ] CurrState_prRxByte ;
+reg [3 :0 ] NextState_prRxByte ;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+ next_RxOverflow or next_NAKRxed or
+ next_stallRxed or next_ACKRxed or
+ next_dataSequence )
+begin
+ RxStatus <=
+ {1'b0 , next_dataSequence ,
+ next_ACKRxed ,
+ next_stallRxed , next_NAKRxed ,
+ next_RxOverflow ,
+ next_bitStuffError , next_CRCError };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: prRxByte
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte )
+begin : prRxByte_NextState
+ NextState_prRxByte <= CurrState_prRxByte ;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte ;
+ next_RxCtrl <= RxCtrl ;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState ;
+ next_CRCError <= CRCError ;
+ next_bitStuffError <= bitStuffError ;
+ next_RxOverflow <= RxOverflow ;
+ next_RxTimeOut <= RxTimeOut ;
+ next_NAKRxed <= NAKRxed ;
+ next_stallRxed <= stallRxed ;
+ next_ACKRxed <= ACKRxed ;
+ next_dataSequence <= dataSequence ;
+ next_RxDataOut <= RxDataOut ;
+ next_RxCtrlOut <= RxCtrlOut ;
+ next_RxDataOutWEn <= RxDataOutWEn ;
+ next_rstCRC <= rstCRC ;
+ next_CRCData <= CRCData ;
+ next_CRC5En <= CRC5En ;
+ next_CRC5_8Bit <= CRC5_8Bit ;
+ next_CRC16En <= CRC16En ;
+ next_RXDataByteCnt <= RXDataByteCnt ;
+ next_processRxByteRdy <= processRxByteRdy ;
+ case (CurrState_prRxByte ) // synopsys parallel_case full_case
+ `CHK_ST :
+ if (RXByteStMachCurrState == `TOKEN_BYTE_ST )
+ NextState_prRxByte <= `TOKEN_WAIT_CRC ;
+ else if (RXByteStMachCurrState == `HS_BYTE_ST )
+ NextState_prRxByte <= `HSHAKE_CHK ;
+ else if (RXByteStMachCurrState == `CHECK_PID_ST )
+ NextState_prRxByte <= `CHK_PID_DO_CHK ;
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST )
+ NextState_prRxByte <= `CHK_SYNC_DO ;
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST )
+ NextState_prRxByte <= `IDLE_CHK_START ;
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST )
+ NextState_prRxByte <= `DATA_WAIT_CRC ;
+ `START_PRBY :
+ begin
+ next_RxByte <= 8'h00 ;
+ next_RxCtrl <= 8'h00 ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ next_CRCError <= 1'b0 ;
+ next_bitStuffError <= 1'b0 ;
+ next_RxOverflow <= 1'b0 ;
+ next_RxTimeOut <= 1'b0 ;
+ next_NAKRxed <= 1'b0 ;
+ next_stallRxed <= 1'b0 ;
+ next_ACKRxed <= 1'b0 ;
+ next_dataSequence <= 1'b0 ;
+ next_RxDataOut <= 8'h00 ;
+ next_RxCtrlOut <= 8'h00 ;
+ next_RxDataOutWEn <= 1'b0 ;
+ next_rstCRC <= 1'b0 ;
+ next_CRCData <= 8'h00 ;
+ next_CRC5En <= 1'b0 ;
+ next_CRC5_8Bit <= 1'b0 ;
+ next_CRC16En <= 1'b0 ;
+ next_RXDataByteCnt <= 10'h00 ;
+ next_processRxByteRdy <= 1'b1 ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ end
+ `WAIT_BYTE :
+ if (processRxDataInWEn == 1'b1 )
+ begin
+ NextState_prRxByte <= `CHK_ST ;
+ next_RxByte <= RxByteIn ;
+ next_RxCtrl <= RxCtrlIn ;
+ next_processRxByteRdy <= 1'b0 ;
+ end
+ `HSHAKE_FIN :
+ begin
+ next_RxDataOutWEn <= 1'b0 ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ `HSHAKE_CHK :
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN ;
+ if (RxCtrl != `DATA_STOP ) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RxDataOutWEn <= 1'b1 ;
+ end
+ `CHK_PID_DO_CHK :
+ if ((RxByte [7 :4 ] ^ RxByte [3 :0 ] ) != 4'hf )
+ begin
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC ;
+ next_CRCError <= 1'b0 ;
+ next_bitStuffError <= 1'b0 ;
+ next_RxOverflow <= 1'b0 ;
+ next_NAKRxed <= 1'b0 ;
+ next_stallRxed <= 1'b0 ;
+ next_ACKRxed <= 1'b0 ;
+ next_dataSequence <= 1'b0 ;
+ next_RxTimeOut <= 1'b0 ;
+ next_RXDataByteCnt <= 0 ;
+ next_RxDataOut <= RxByte ;
+ next_RxCtrlOut <= `RX_PACKET_START ;
+ next_RxDataOutWEn <= 1'b1 ;
+ next_rstCRC <= 1'b1 ;
+ end
+ `CHK_PID_FIRST_BYTE_PROC :
+ begin
+ next_rstCRC <= 1'b0 ;
+ next_RxDataOutWEn <= 1'b0 ;
+ case (RxByte [1 :0 ] )
+ `SPECIAL : //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ `TOKEN : //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST ;
+ next_RXDataByteCnt <= 0 ;
+ end
+ `HANDSHAKE : //Handshake PID
+ begin
+ case (RxByte [3 :2 ] )
+ 2'b00 :
+ next_ACKRxed <= 1'b1 ;
+ 2'b10 :
+ next_NAKRxed <= 1'b1 ;
+ 2'b11 :
+ next_stallRxed <= 1'b1 ;
+ default :
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n" );
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST ;
+ end
+ `DATA : //Data PID
+ begin
+ case (RxByte [3 :2 ] )
+ 2'b00 :
+ next_dataSequence <= 1'b0 ;
+ 2'b10 :
+ next_dataSequence <= 1'b1 ;
+ default :
+ $display ("Invalid DATA PID detected in ProcessRXByte\n" );
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST ;
+ next_RXDataByteCnt <= 0 ;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ `DATA_FIN :
+ begin
+ next_CRC16En <= 1'b0 ;
+ next_RxDataOutWEn <= 1'b0 ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ `DATA_CHK_STRM :
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1 ;
+ case (RxCtrl )
+ `DATA_STOP :
+ begin
+ if (CRC16Result != 16'hb001 )
+ next_CRCError <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ end
+ `DATA_BIT_STUFF_ERROR :
+ begin
+ next_bitStuffError <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ end
+ `DATA_STREAM :
+ begin
+ next_RxDataOut <= RxByte ;
+ next_RxCtrlOut <= `RX_PACKET_STREAM ;
+ next_CRCData <= RxByte ;
+ next_CRC16En <= 1'b1 ;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1 ;
+ NextState_prRxByte <= `DATA_FIN ;
+ end
+ `DATA_WAIT_CRC :
+ if (CRC16UpdateRdy == 1'b1 )
+ NextState_prRxByte <= `DATA_CHK_STRM ;
+ `TOKEN_CHK_STRM :
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1 ;
+ case (RxCtrl )
+ `DATA_STOP :
+ begin
+ if (CRC5Result != 5'h6 )
+ next_CRCError <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ end
+ `DATA_BIT_STUFF_ERROR :
+ begin
+ next_bitStuffError <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ end
+ `DATA_STREAM :
+ begin
+ if (RXDataByteCnt > 10'h2 )
+ begin
+ next_RxOverflow <= 1'b1 ;
+ next_RxDataOut <= RxStatus ;
+ next_RxCtrlOut <= `RX_PACKET_STOP ;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte ;
+ next_RxCtrlOut <= `RX_PACKET_STREAM ;
+ next_CRCData <= RxByte ;
+ next_CRC5_8Bit <= 1'b1 ;
+ next_CRC5En <= 1'b1 ;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1 ;
+ NextState_prRxByte <= `TOKEN_FIN ;
+ end
+ `TOKEN_FIN :
+ begin
+ next_CRC5En <= 1'b0 ;
+ next_RxDataOutWEn <= 1'b0 ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ `TOKEN_WAIT_CRC :
+ if (CRC5UpdateRdy == 1'b1 )
+ NextState_prRxByte <= `TOKEN_CHK_STRM ;
+ `CHK_SYNC_DO :
+ begin
+ if (RxByte == `SYNC_BYTE )
+ next_RXByteStMachCurrState = `CHECK_PID_ST ;
+ else
+ next_RXByteStMachCurrState = `IDLE_BYTE_ST ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ `IDLE_CHK_START :
+ begin
+ if (RxCtrl == `DATA_START )
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST ;
+ NextState_prRxByte <= `WAIT_BYTE ;
+ next_processRxByteRdy <= 1'b1 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : prRxByte_CurrentState
+ if (rst )
+ CurrState_prRxByte <= `START_PRBY ;
+ else
+ CurrState_prRxByte <= NextState_prRxByte ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : prRxByte_RegOutput
+ if (rst )
+ begin
+ RxByte <= 8'h00 ;
+ RxCtrl <= 8'h00 ;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST ;
+ CRCError <= 1'b0 ;
+ bitStuffError <= 1'b0 ;
+ RxOverflow <= 1'b0 ;
+ RxTimeOut <= 1'b0 ;
+ NAKRxed <= 1'b0 ;
+ stallRxed <= 1'b0 ;
+ ACKRxed <= 1'b0 ;
+ dataSequence <= 1'b0 ;
+ RXDataByteCnt <= 10'h00 ;
+ RxDataOut <= 8'h00 ;
+ RxCtrlOut <= 8'h00 ;
+ RxDataOutWEn <= 1'b0 ;
+ rstCRC <= 1'b0 ;
+ CRCData <= 8'h00 ;
+ CRC5En <= 1'b0 ;
+ CRC5_8Bit <= 1'b0 ;
+ CRC16En <= 1'b0 ;
+ processRxByteRdy <= 1'b1 ;
+ end
+ else
+ begin
+ RxByte <= next_RxByte ;
+ RxCtrl <= next_RxCtrl ;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState ;
+ CRCError <= next_CRCError ;
+ bitStuffError <= next_bitStuffError ;
+ RxOverflow <= next_RxOverflow ;
+ RxTimeOut <= next_RxTimeOut ;
+ NAKRxed <= next_NAKRxed ;
+ stallRxed <= next_stallRxed ;
+ ACKRxed <= next_ACKRxed ;
+ dataSequence <= next_dataSequence ;
+ RXDataByteCnt <= next_RXDataByteCnt ;
+ RxDataOut <= next_RxDataOut ;
+ RxCtrlOut <= next_RxCtrlOut ;
+ RxDataOutWEn <= next_RxDataOutWEn ;
+ rstCRC <= next_rstCRC ;
+ CRCData <= next_CRCData ;
+ CRC5En <= next_CRC5En ;
+ CRC5_8Bit <= next_CRC5_8Bit ;
+ CRC16En <= next_CRC16En ;
+ processRxByteRdy <= next_processRxByteRdy ;
+ end
+end
+
+endmodule
+
+
+
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===================================================================
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm (revision 264)
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+
+
+processRxBit.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxBit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:23 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (JBit , KBit , RxBitsIn , RxCtrlOut , RxDataOut , clk , processRxBitRdy , processRxBitsWEn , processRxByteRdy , processRxByteWEn , resumeDetected , rst );
+input [1 :0 ] JBit ;
+input [1 :0 ] KBit ;
+input [1 :0 ] RxBitsIn ;
+input clk ;
+input processRxBitsWEn ;
+input processRxByteRdy ;
+input rst ;
+output [7 :0 ] RxCtrlOut ;
+output [7 :0 ] RxDataOut ;
+output processRxBitRdy ;
+output processRxByteWEn ;
+output resumeDetected ;
+
+wire [1 :0 ] JBit ;
+wire [1 :0 ] KBit ;
+wire [1 :0 ] RxBitsIn ;
+reg [7 :0 ] RxCtrlOut , next_RxCtrlOut ;
+reg [7 :0 ] RxDataOut , next_RxDataOut ;
+wire clk ;
+reg processRxBitRdy , next_processRxBitRdy ;
+wire processRxBitsWEn ;
+wire processRxByteRdy ;
+reg processRxByteWEn , next_processRxByteWEn ;
+reg resumeDetected , next_resumeDetected ;
+wire rst ;
+
+// diagram signals declarations
+reg [3 :0 ]RXBitCount , next_RXBitCount ;
+reg [1 :0 ]RXBitStMachCurrState , next_RXBitStMachCurrState ;
+reg [7 :0 ]RXByte , next_RXByte ;
+reg [3 :0 ]RXSameBitCount , next_RXSameBitCount ;
+reg [1 :0 ]RxBits , next_RxBits ;
+reg bitStuffError , next_bitStuffError ;
+reg [1 :0 ]oldRXBits , next_oldRXBits ;
+reg [3 :0 ]resumeWaitCnt , next_resumeWaitCnt ;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3 :0 ] CurrState_prRxBit ;
+reg [3 :0 ] NextState_prRxBit ;
+
+
+//--------------------------------------------------------------------
+// Machine: prRxBit
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit )
+begin : prRxBit_NextState
+ NextState_prRxBit <= CurrState_prRxBit ;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn ;
+ next_RxCtrlOut <= RxCtrlOut ;
+ next_RxDataOut <= RxDataOut ;
+ next_resumeDetected <= resumeDetected ;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState ;
+ next_RxBits <= RxBits ;
+ next_RXSameBitCount <= RXSameBitCount ;
+ next_RXBitCount <= RXBitCount ;
+ next_oldRXBits <= oldRXBits ;
+ next_RXByte <= RXByte ;
+ next_bitStuffError <= bitStuffError ;
+ next_resumeWaitCnt <= resumeWaitCnt ;
+ next_processRxBitRdy <= processRxBitRdy ;
+ case (CurrState_prRxBit ) // synopsys parallel_case full_case
+ `START :
+ begin
+ next_processRxByteWEn <= 1'b0 ;
+ next_RxCtrlOut <= 8'h00 ;
+ next_RxDataOut <= 8'h00 ;
+ next_resumeDetected <= 1'b0 ;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ next_RxBits <= 2'b00 ;
+ next_RXSameBitCount <= 4'h0 ;
+ next_RXBitCount <= 4'h0 ;
+ next_oldRXBits <= 2'b00 ;
+ next_RXByte <= 8'h00 ;
+ next_bitStuffError <= 1'b0 ;
+ next_resumeWaitCnt <= 4'h0 ;
+ next_processRxBitRdy <= 1'b1 ;
+ NextState_prRxBit <= `WAIT_BITS ;
+ end
+ `WAIT_BITS :
+ if ((processRxBitsWEn == 1'b1 ) && (RXBitStMachCurrState == `WAIT_RESUME_ST ))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK ;
+ next_RxBits <= RxBitsIn ;
+ next_processRxBitRdy <= 1'b0 ;
+ end
+ else if ((processRxBitsWEn == 1'b1 ) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST ))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0 ;
+ next_RxBits <= RxBitsIn ;
+ next_processRxBitRdy <= 1'b0 ;
+ end
+ else if ((processRxBitsWEn == 1'b1 ) && (RXBitStMachCurrState == `IDLE_BIT_ST ))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT ;
+ next_RxBits <= RxBitsIn ;
+ next_processRxBitRdy <= 1'b0 ;
+ end
+ else if ((processRxBitsWEn == 1'b1 ) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST ))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1 ;
+ next_RxBits <= RxBitsIn ;
+ next_processRxBitRdy <= 1'b0 ;
+ end
+ `IDLE_FIRST_BIT :
+ begin
+ next_processRxByteWEn <= 1'b0 ;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST ;
+ next_RXSameBitCount <= 4'h1 ;
+ next_RXBitCount <= 4'h1 ;
+ next_oldRXBits <= RxBits ;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00 ;
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `IDLE_CHK_KBIT :
+ if (RxBits == KBit )
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY ;
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `IDLE_WAIT_PRB_RDY :
+ if (processRxByteRdy == 1'b1 )
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT ;
+ next_RxDataOut <= 8'h00 ;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START ;
+ //start of packet
+ next_processRxByteWEn <= 1'b1 ;
+ end
+ `DATA_RX_LAST_BIT :
+ begin
+ next_processRxByteWEn <= 1'b0 ;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `DATA_RX_CHK_SE0 :
+ begin
+ next_bitStuffError <= 1'b0 ;
+ if (RxBits == `SE0 )
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY ;
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF ;
+ if (RxBits == oldRXBits ) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1 ;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS ) //if 'RXSameBitCount' == 7 there has been a bit stuff error
+ next_bitStuffError <= 1'b1 ;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1 ;
+ if (RXBitCount != 4'h7 ) begin
+ next_processRxBitRdy <= 1'b1 ;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1 , RXByte [7 :1 ]};
+ //RZ bit = 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS ) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1 ;
+ if (RXBitCount != 4'h7 ) begin
+ next_processRxBitRdy <= 1'b1 ;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0 , RXByte [7 :1 ]};
+ //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h1 ;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits ;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY :
+ if (processRxByteRdy == 1'b1 )
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT ;
+ next_RxDataOut <= 8'h00 ;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP ;
+ //end of packet
+ next_processRxByteWEn <= 1'b1 ;
+ end
+ `DATA_RX_DATA_DESTUFF :
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0 )
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY ;
+ else if (bitStuffError == 1'b1 )
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY ;
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `DATA_RX_BYTE_SEND2 :
+ begin
+ next_processRxByteWEn <= 1'b0 ;
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `DATA_RX_BYTE_WAIT_RDY :
+ if (processRxByteRdy == 1'b1 )
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2 ;
+ next_RXBitCount <= 4'h0 ;
+ next_RxDataOut <= RXByte ;
+ next_RxCtrlOut <= `DATA_STREAM ;
+ next_processRxByteWEn <= 1'b1 ;
+ end
+ `DATA_RX_ERROR_CHK_RES :
+ begin
+ next_processRxByteWEn <= 1'b0 ;
+ if (RxBits == JBit ) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST ;
+ //check for resume
+ next_resumeWaitCnt <= 0 ;
+ end
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `DATA_RX_ERROR_WAIT_RDY :
+ if (processRxByteRdy == 1'b1 )
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES ;
+ next_RxDataOut <= 8'h00 ;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR ;
+ next_processRxByteWEn <= 1'b1 ;
+ end
+ `RES_RX_CHK :
+ begin
+ if (RxBits != KBit ) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1 ;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1 )
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST ;
+ next_resumeDetected <= 1'b1 ;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ `RES_END_CHK1 :
+ begin
+ if (RxBits != KBit ) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ next_resumeDetected <= 1'b0 ;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS ;
+ next_processRxBitRdy <= 1'b1 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : prRxBit_CurrentState
+ if (rst )
+ CurrState_prRxBit <= `START ;
+ else
+ CurrState_prRxBit <= NextState_prRxBit ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : prRxBit_RegOutput
+ if (rst )
+ begin
+ RXBitStMachCurrState <= `IDLE_BIT_ST ;
+ RxBits <= 2'b00 ;
+ RXSameBitCount <= 4'h0 ;
+ RXBitCount <= 4'h0 ;
+ oldRXBits <= 2'b00 ;
+ RXByte <= 8'h00 ;
+ bitStuffError <= 1'b0 ;
+ resumeWaitCnt <= 4'h0 ;
+ processRxByteWEn <= 1'b0 ;
+ RxCtrlOut <= 8'h00 ;
+ RxDataOut <= 8'h00 ;
+ resumeDetected <= 1'b0 ;
+ processRxBitRdy <= 1'b1 ;
+ end
+ else
+ begin
+ RXBitStMachCurrState <= next_RXBitStMachCurrState ;
+ RxBits <= next_RxBits ;
+ RXSameBitCount <= next_RXSameBitCount ;
+ RXBitCount <= next_RXBitCount ;
+ oldRXBits <= next_oldRXBits ;
+ RXByte <= next_RXByte ;
+ bitStuffError <= next_bitStuffError ;
+ resumeWaitCnt <= next_resumeWaitCnt ;
+ processRxByteWEn <= next_processRxByteWEn ;
+ RxCtrlOut <= next_RxCtrlOut ;
+ RxDataOut <= next_RxDataOut ;
+ resumeDetected <= next_resumeDetected ;
+ processRxBitRdy <= next_processRxBitRdy ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm
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===================================================================
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html (nonexistent)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm (nonexistent)
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+ <![CDATA[
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+ <p>This page uses frames, but your browser doesn't support them. <br></p>
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+
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm (nonexistent)
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+ <![CDATA[
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===================================================================
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html (nonexistent)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html (revision 264)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html (nonexistent)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html (nonexistent)
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm (nonexistent)
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+ ]]>
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm (revision 264)
@@ -0,0 +1,31 @@
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===================================================================
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html (revision 264)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html (revision 264)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm (revision 264)
@@ -0,0 +1,31 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_STOP.png
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_STOP.png
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm (revision 264)
@@ -0,0 +1,210 @@
+
+
+readUSBWireData.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn , RxDataInTick , RxBitsOut , SIERxRdyIn , SIERxWEn , fullSpeedRate , disableWireRead , clk , rst );
+input [1 :0 ] RxBitsIn ;
+output RxDataInTick ;
+input SIERxRdyIn ;
+input clk ;
+input fullSpeedRate ;
+input rst ;
+input disableWireRead ;
+output [1 :0 ] RxBitsOut ;
+output SIERxWEn ;
+
+wire [1 :0 ] RxBitsIn ;
+reg RxDataInTick ;
+wire SIERxRdyIn ;
+wire clk ;
+wire fullSpeedRate ;
+wire rst ;
+reg [1 :0 ] RxBitsOut ;
+reg SIERxWEn ;
+
+// local registers
+reg [1 :0 ]buffer0 ;
+reg [1 :0 ]buffer1 ;
+reg [1 :0 ]buffer2 ;
+reg [1 :0 ]buffer3 ;
+reg [2 :0 ]bufferCnt ;
+reg [1 :0 ]bufferInIndex ;
+reg [1 :0 ]bufferOutIndex ;
+reg decBufferCnt ;
+reg [4 :0 ]i ;
+reg incBufferCnt ;
+reg [1 :0 ]oldRxBitsIn ;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1 :0 ] bufferOutStMachCurrState ;
+
+
+always @(posedge clk ) begin
+ if (rst == 1'b1 )
+ begin
+ bufferCnt <= 3'b000 ;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0 )
+ bufferCnt <= bufferCnt + 1'b1 ;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1 )
+ bufferCnt <= bufferCnt - 1'b1 ;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk ) begin
+ if (rst == 1'b1 )
+ begin
+ i <= 5'b00000 ;
+ incBufferCnt <= 1'b0 ;
+ bufferInIndex <= 2'b00 ;
+ buffer0 <= 2'b00 ;
+ buffer1 <= 2'b00 ;
+ buffer2 <= 2'b00 ;
+ buffer3 <= 2'b00 ;
+ RxDataInTick <= 1'b0 ;
+ end
+ else begin
+ incBufferCnt <= 1'b0 ; //default value
+ oldRxBitsIn <= RxBitsIn ;
+ if (oldRxBitsIn != RxBitsIn ) //if edge detected then
+ i <= 5'b00000 ; //reset the counter
+ else
+ i <= i + 1'b1 ;
+ if ( (fullSpeedRate == 1'b1 && i [1 :0 ] == 2'b10 ) || (fullSpeedRate == 1'b0 && i == 5'b10000 ) )
+ begin
+ RxDataInTick <= !RxDataInTick ;
+ if (disableWireRead != 1'b1 ) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1 ;
+ bufferInIndex <= bufferInIndex + 1'b1 ;
+ case (bufferInIndex )
+ 2'b00 : buffer0 <= RxBitsIn ;
+ 2'b01 : buffer1 <= RxBitsIn ;
+ 2'b10 : buffer2 <= RxBitsIn ;
+ 2'b11 : buffer3 <= RxBitsIn ;
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk ) begin
+ if (rst == 1'b1 )
+ begin
+ decBufferCnt <= 1'b0 ;
+ bufferOutIndex <= 2'b00 ;
+ RxBitsOut <= 2'b00 ;
+ SIERxWEn <= 1'b0 ;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY ;
+ end
+ else begin
+ case (bufferOutStMachCurrState )
+ `WAIT_BUFFER_NOT_EMPTY :
+ begin
+ if (bufferCnt != 3'b000 )
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY ;
+ end
+ `WAIT_SIE_RX_READY :
+ begin
+ if (SIERxRdyIn == 1'b1 )
+ begin
+ SIERxWEn <= 1'b1 ;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE ;
+ decBufferCnt <= 1'b1 ;
+ bufferOutIndex <= bufferOutIndex + 1'b1 ;
+ case (bufferOutIndex )
+ 2'b00 : RxBitsOut <= buffer0 ;
+ 2'b01 : RxBitsOut <= buffer1 ;
+ 2'b10 : RxBitsOut <= buffer2 ;
+ 2'b11 : RxBitsOut <= buffer3 ;
+ endcase
+ end
+ end
+ `SIE_RX_WRITE :
+ begin
+ SIERxWEn <= 1'b0 ;
+ decBufferCnt <= 1'b0 ;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY ;
+ end
+ endcase
+ end
+end
+
+
+
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html (revision 264)
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html (revision 264)
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm (revision 264)
@@ -0,0 +1,31 @@
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+ <![CDATA[
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm
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===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_SEND_BYTE.png
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html (revision 264)
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===================================================================
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html (revision 264)
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===================================================================
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+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm
___________________________________________________________________
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm
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===================================================================
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+
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm (nonexistent)
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+
+
+processTxByte.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (JBit , KBit , TxByteCtrlIn , TxByteIn , USBWireCtrl , USBWireData , USBWireGnt , USBWireRdy , USBWireReq , USBWireWEn , clk , processTxByteRdy , processTxByteWEn , rst );
+input [1 :0 ] JBit ;
+input [1 :0 ] KBit ;
+input [7 :0 ] TxByteCtrlIn ;
+input [7 :0 ] TxByteIn ;
+input USBWireGnt ;
+input USBWireRdy ;
+input clk ;
+input processTxByteWEn ;
+input rst ;
+output USBWireCtrl ;
+output [1 :0 ] USBWireData ;
+output USBWireReq ;
+output USBWireWEn ;
+output processTxByteRdy ;
+
+wire [1 :0 ] JBit ;
+wire [1 :0 ] KBit ;
+wire [7 :0 ] TxByteCtrlIn ;
+wire [7 :0 ] TxByteIn ;
+reg USBWireCtrl , next_USBWireCtrl ;
+reg [1 :0 ] USBWireData , next_USBWireData ;
+wire USBWireGnt ;
+wire USBWireRdy ;
+reg USBWireReq , next_USBWireReq ;
+reg USBWireWEn , next_USBWireWEn ;
+wire clk ;
+reg processTxByteRdy , next_processTxByteRdy ;
+wire processTxByteWEn ;
+wire rst ;
+
+// diagram signals declarations
+reg [1 :0 ]TXLineState , next_TXLineState ;
+reg [3 :0 ]TXOneCount , next_TXOneCount ;
+reg [7 :0 ]TxByteCtrl , next_TxByteCtrl ;
+reg [7 :0 ]TxByte , next_TxByte ;
+reg [3 :0 ]i , next_i ;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 4'b0000
+`define PTBY_WAIT_EN 4'b0001
+`define SEND_BYTE_UPDATE_BYTE 4'b0010
+`define SEND_BYTE_WAIT_RDY 4'b0011
+`define SEND_BYTE_CHK 4'b0100
+`define SEND_BYTE_BIT_STUFF 4'b0101
+`define SEND_BYTE_WAIT_RDY2 4'b0110
+`define SEND_BYTE_CHK_FIN 4'b0111
+`define PTBY_WAIT_GNT 4'b1000
+`define STOP_SND_SE0_2 4'b1001
+`define STOP_SND_SE0_1 4'b1010
+`define STOP_CHK 4'b1011
+`define STOP_SND_J 4'b1100
+`define STOP_SND_IDLE 4'b1101
+`define STOP_FIN 4'b1110
+
+reg [3 :0 ] CurrState_prcTxB ;
+reg [3 :0 ] NextState_prcTxB ;
+
+
+//--------------------------------------------------------------------
+// Machine: prcTxB
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB )
+begin : prcTxB_NextState
+ NextState_prcTxB <= CurrState_prcTxB ;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy ;
+ next_USBWireData <= USBWireData ;
+ next_USBWireCtrl <= USBWireCtrl ;
+ next_USBWireReq <= USBWireReq ;
+ next_USBWireWEn <= USBWireWEn ;
+ next_i <= i ;
+ next_TxByte <= TxByte ;
+ next_TxByteCtrl <= TxByteCtrl ;
+ next_TXLineState <= TXLineState ;
+ next_TXOneCount <= TXOneCount ;
+ case (CurrState_prcTxB ) // synopsys parallel_case full_case
+ `START_PTBY :
+ begin
+ next_processTxByteRdy <= 1'b0 ;
+ next_USBWireData <= 2'b00 ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ next_USBWireReq <= 1'b0 ;
+ next_USBWireWEn <= 1'b0 ;
+ next_i <= 4'h0 ;
+ next_TxByte <= 8'h00 ;
+ next_TxByteCtrl <= 8'h00 ;
+ next_TXLineState <= 2'b0 ;
+ next_TXOneCount <= 4'h0 ;
+ NextState_prcTxB <= `PTBY_WAIT_EN ;
+ end
+ `PTBY_WAIT_EN :
+ begin
+ next_processTxByteRdy <= 1'b1 ;
+ if ((processTxByteWEn == 1'b1 ) && (TxByteCtrlIn == `DATA_START ))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT ;
+ next_processTxByteRdy <= 1'b0 ;
+ next_TxByte <= TxByteIn ;
+ next_TxByteCtrl <= TxByteCtrlIn ;
+ next_TXOneCount <= 1 ;
+ next_TXLineState <= JBit ;
+ next_USBWireReq <= 1'b1 ;
+ end
+ else if (processTxByteWEn == 1'b1 )
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE ;
+ next_processTxByteRdy <= 1'b0 ;
+ next_TxByte <= TxByteIn ;
+ next_TxByteCtrl <= TxByteCtrlIn ;
+ next_i <= 4'h0 ;
+ end
+ end
+ `PTBY_WAIT_GNT :
+ if (USBWireGnt == 1'b1 )
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE ;
+ next_i <= 4'h0 ;
+ end
+ `SEND_BYTE_UPDATE_BYTE :
+ begin
+ next_i <= i + 1'b1 ;
+ next_TxByte <= {1'b0 , TxByte [7 :1 ] };
+ if (TxByte [0 ] == 1'b1 ) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1 ;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h1 ;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit ) next_TXLineState <= KBit ;
+ //toggle the line state
+ else next_TXLineState <= JBit ;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY ;
+ end
+ `SEND_BYTE_WAIT_RDY :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= TXLineState ;
+ next_USBWireCtrl <= `DRIVE ;
+ end
+ `SEND_BYTE_CHK :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (TXOneCount == 4'h6 )
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF ;
+ else if (i != 4'h8 )
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE ;
+ else
+ NextState_prcTxB <= `STOP_CHK ;
+ end
+ `SEND_BYTE_BIT_STUFF :
+ begin
+ next_TXOneCount <= 4'h1 ;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit ) next_TXLineState <= KBit ;
+ //toggle the line state
+ else next_TXLineState <= JBit ;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2 ;
+ end
+ `SEND_BYTE_WAIT_RDY2 :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= TXLineState ;
+ next_USBWireCtrl <= `DRIVE ;
+ end
+ `SEND_BYTE_CHK_FIN :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (i == 4'h8 )
+ NextState_prcTxB <= `STOP_CHK ;
+ else
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE ;
+ end
+ `STOP_SND_SE0_2 :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `STOP_SND_J ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= `SE0 ;
+ next_USBWireCtrl <= `DRIVE ;
+ end
+ end
+ `STOP_SND_SE0_1 :
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2 ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= `SE0 ;
+ next_USBWireCtrl <= `DRIVE ;
+ end
+ `STOP_CHK :
+ if (TxByteCtrl == `DATA_STOP )
+ NextState_prcTxB <= `STOP_SND_SE0_1 ;
+ else
+ NextState_prcTxB <= `PTBY_WAIT_EN ;
+ `STOP_SND_J :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `DRIVE ;
+ end
+ end
+ `STOP_SND_IDLE :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ if (USBWireRdy == 1'b1 )
+ begin
+ NextState_prcTxB <= `STOP_FIN ;
+ next_USBWireWEn <= 1'b1 ;
+ next_USBWireData <= JBit ;
+ next_USBWireCtrl <= `TRI_STATE ;
+ end
+ end
+ `STOP_FIN :
+ begin
+ next_USBWireWEn <= 1'b0 ;
+ next_USBWireReq <= 1'b0 ;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : prcTxB_CurrentState
+ if (rst )
+ CurrState_prcTxB <= `START_PTBY ;
+ else
+ CurrState_prcTxB <= NextState_prcTxB ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : prcTxB_RegOutput
+ if (rst )
+ begin
+ i <= 4'h0 ;
+ TxByte <= 8'h00 ;
+ TxByteCtrl <= 8'h00 ;
+ TXLineState <= 2'b0 ;
+ TXOneCount <= 4'h0 ;
+ processTxByteRdy <= 1'b0 ;
+ USBWireData <= 2'b00 ;
+ USBWireCtrl <= `TRI_STATE ;
+ USBWireReq <= 1'b0 ;
+ USBWireWEn <= 1'b0 ;
+ end
+ else
+ begin
+ i <= next_i ;
+ TxByte <= next_TxByte ;
+ TxByteCtrl <= next_TxByteCtrl ;
+ TXLineState <= next_TXLineState ;
+ TXOneCount <= next_TXOneCount ;
+ processTxByteRdy <= next_processTxByteRdy ;
+ USBWireData <= next_USBWireData ;
+ USBWireCtrl <= next_USBWireCtrl ;
+ USBWireReq <= next_USBWireReq ;
+ USBWireWEn <= next_USBWireWEn ;
+ end
+end
+
+endmodule
+
+
+
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm (nonexistent)
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm (nonexistent)
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
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===================================================================
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===================================================================
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm (nonexistent)
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+
+
+siereceiver.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:47 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (RxBitsOut , RxWireDataIn , RxWireDataWEn , SIERxRdyOut , clk , connectState , processRxBitRdyIn , processRxBitsWEn , rst );
+input [1 :0 ] RxWireDataIn ;
+input RxWireDataWEn ;
+input clk ;
+input processRxBitRdyIn ;
+input rst ;
+output [1 :0 ] RxBitsOut ;
+output SIERxRdyOut ;
+output [1 :0 ] connectState ;
+output processRxBitsWEn ;
+
+reg [1 :0 ] RxBitsOut , next_RxBitsOut ;
+wire [1 :0 ] RxWireDataIn ;
+wire RxWireDataWEn ;
+reg SIERxRdyOut , next_SIERxRdyOut ;
+wire clk ;
+reg [1 :0 ] connectState , next_connectState ;
+wire processRxBitRdyIn ;
+reg processRxBitsWEn , next_processRxBitsWEn ;
+wire rst ;
+
+// diagram signals declarations
+reg [3 :0 ]RXStMachCurrState , next_RXStMachCurrState ;
+reg [7 :0 ]RXWaitCount , next_RXWaitCount ;
+reg [1 :0 ]RxBits , next_RxBits ;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define LS_CONN_PROC_RX_BITS 4'b0110
+`define FS_CONN_CHK_RX_BITS1 4'b0111
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
+`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
+`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
+`define FS_CONN_PROC_RX_BITS1 4'b1100
+
+reg [3 :0 ] CurrState_rcvr ;
+reg [3 :0 ] NextState_rcvr ;
+
+
+//--------------------------------------------------------------------
+// Machine: rcvr
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or processRxBitRdyIn or SIERxRdyOut or connectState or RxBitsOut or processRxBitsWEn or CurrState_rcvr )
+begin : rcvr_NextState
+ NextState_rcvr <= CurrState_rcvr ;
+ // Set default values for outputs and signals
+ next_RxBits <= RxBits ;
+ next_SIERxRdyOut <= SIERxRdyOut ;
+ next_RXStMachCurrState <= RXStMachCurrState ;
+ next_RXWaitCount <= RXWaitCount ;
+ next_connectState <= connectState ;
+ next_RxBitsOut <= RxBitsOut ;
+ next_processRxBitsWEn <= processRxBitsWEn ;
+ case (CurrState_rcvr ) // synopsys parallel_case full_case
+ `WAIT_BIT :
+ if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST ))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST ))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST ))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1 ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST ))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST ))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2 ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `DISCONNECT_ST ))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ else if ((RxWireDataWEn == 1'b1 ) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST ))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS ;
+ next_RxBits <= RxWireDataIn ;
+ next_SIERxRdyOut <= 1'b0 ;
+ end
+ `START_SRX :
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST ;
+ next_RXWaitCount <= 8'h00 ;
+ next_connectState <= `DISCONNECT ;
+ next_RxBits <= 2'b00 ;
+ next_RxBitsOut <= 2'b00 ;
+ next_processRxBitsWEn <= 1'b0 ;
+ next_SIERxRdyOut <= 1'b1 ;
+ NextState_rcvr <= `WAIT_BIT ;
+ end
+ `DISCNCT_CHK_RXBITS :
+ if (RxBits == `ZERO_ONE )
+ begin
+ NextState_rcvr <= `WAIT_BIT ;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST ;
+ next_RXWaitCount <= 8'h00 ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ else if (RxBits == `ONE_ZERO )
+ begin
+ NextState_rcvr <= `WAIT_BIT ;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST ;
+ next_RXWaitCount <= 8'h00 ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS :
+ begin
+ if (RxBits == `ONE_ZERO )
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1 ;
+ if (RXWaitCount == `CONNECT_WAIT_TIME )
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT ;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST ;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState = `DISCONNECT_ST ;
+ end
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS :
+ begin
+ if (RxBits == `ZERO_ONE )
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1 ;
+ if (RXWaitCount == `CONNECT_WAIT_TIME )
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT ;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST ;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState = `DISCONNECT_ST ;
+ end
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `LS_CONN_CHK_RX_BITS :
+ if (processRxBitRdyIn == 1'b1 )
+ begin
+ NextState_rcvr <= `LS_CONN_PROC_RX_BITS ;
+ if (RxBits == `SE0 )
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST ;
+ next_RXWaitCount <= 0 ;
+ end
+ next_processRxBitsWEn <= 1'b1 ;
+ next_RxBitsOut <= RxBits ;
+ end
+ `LS_CONN_PROC_RX_BITS :
+ begin
+ next_processRxBitsWEn <= 1'b0 ;
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `FS_CONN_CHK_RX_BITS1 :
+ if (processRxBitRdyIn == 1'b1 )
+ begin
+ NextState_rcvr <= `FS_CONN_PROC_RX_BITS1 ;
+ if (RxBits == `SE0 )
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST ;
+ next_RXWaitCount <= 0 ;
+ end
+ next_processRxBitsWEn <= 1'b1 ;
+ next_RxBitsOut <= RxBits ;
+ next_SIERxRdyOut <= 1'b1 ;
+ //early indication of ready
+ end
+ `FS_CONN_PROC_RX_BITS1 :
+ begin
+ next_processRxBitsWEn <= 1'b0 ;
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS :
+ if (processRxBitRdyIn == 1'b1 )
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS ;
+ if (RxBits == `SE0 )
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1 ;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME )
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST ;
+ next_connectState = `DISCONNECT ;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState = `CONNECT_LOW_SPEED_ST ;
+ end
+ next_processRxBitsWEn <= 1'b1 ;
+ end
+ `WAIT_LS_DIS_PROC_RX_BITS :
+ begin
+ next_processRxBitsWEn <= 1'b0 ;
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `WAIT_FS_DIS_PROC_RX_BITS2 :
+ begin
+ next_processRxBitsWEn <= 1'b0 ;
+ NextState_rcvr <= `WAIT_BIT ;
+ next_SIERxRdyOut <= 1'b1 ;
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2 :
+ if (processRxBitRdyIn == 1'b1 )
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2 ;
+ if (RxBits == `SE0 )
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1 ;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME )
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST ;
+ next_connectState = `DISCONNECT ;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState = `CONNECT_FULL_SPEED_ST ;
+ end
+ next_processRxBitsWEn <= 1'b1 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : rcvr_CurrentState
+ if (rst )
+ CurrState_rcvr <= `START_SRX ;
+ else
+ CurrState_rcvr <= NextState_rcvr ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : rcvr_RegOutput
+ if (rst )
+ begin
+ RXStMachCurrState <= `DISCONNECT_ST ;
+ RXWaitCount <= 8'h00 ;
+ RxBits <= 2'b00 ;
+ connectState <= `DISCONNECT ;
+ RxBitsOut <= 2'b00 ;
+ processRxBitsWEn <= 1'b0 ;
+ SIERxRdyOut <= 1'b1 ;
+ end
+ else
+ begin
+ RXStMachCurrState <= next_RXStMachCurrState ;
+ RXWaitCount <= next_RXWaitCount ;
+ RxBits <= next_RxBits ;
+ connectState <= next_connectState ;
+ RxBitsOut <= next_RxBitsOut ;
+ processRxBitsWEn <= next_processRxBitsWEn ;
+ SIERxRdyOut <= next_SIERxRdyOut ;
+ end
+end
+
+endmodule
+
+
+
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===================================================================
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html (revision 264)
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm (revision 264)
@@ -0,0 +1,129 @@
+
+
+updateCRC5.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:03 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC5 (rstCRC , CRCResult , CRCEn , CRC5_8BitIn , dataIn , ready , clk , rst );
+input rstCRC ;
+input CRCEn ;
+input CRC5_8BitIn ;
+input [7 :0 ] dataIn ;
+input clk ;
+input rst ;
+output [4 :0 ] CRCResult ;
+output ready ;
+
+wire rstCRC ;
+wire CRCEn ;
+wire CRC5_8BitIn ;
+wire [7 :0 ] dataIn ;
+wire clk ;
+wire rst ;
+reg [4 :0 ] CRCResult ;
+reg ready ;
+
+reg doUpdateCRC ;
+reg [7 :0 ] data ;
+reg [3 :0 ] loopEnd ;
+reg [3 :0 ] i ;
+
+always @(posedge clk )
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1 ) begin
+ doUpdateCRC <= 1'b0 ;
+ i <= 4'h0 ;
+ CRCResult <= 5'h1f ;
+ ready <= 1'b1 ;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0 ) begin
+ if (CRCEn == 1'b1 ) begin
+ ready <= 1'b0 ;
+ doUpdateCRC <= 1'b1 ;
+ data <= dataIn ;
+ if (CRC5_8BitIn == 1'b1 ) begin
+ loopEnd <= 4'h7 ;
+ end
+ else begin
+ loopEnd <= 4'h2 ;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1 ;
+ if ( (CRCResult [0 ] ^ data [0 ]) == 1'b1 ) begin
+ CRCResult <= {1'b0 , CRCResult [4 :1 ]} ^ 5'h14 ;
+ end
+ else begin
+ CRCResult <= {1'b0 , CRCResult [4 :1 ]};
+ end
+ data <= {1'b0 , data [7 :1 ]};
+ if (i == loopEnd ) begin
+ doUpdateCRC <= 1'b0 ;
+ i <= 4'h0 ;
+ ready <= 1'b1 ;
+ end
+ end
+ end
+end
+
+
+endmodule
+
+
+
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html (revision 264)
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+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
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+*
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm (revision 264)
@@ -0,0 +1,406 @@
+
+
+USBSlaveControlBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address , dataIn , dataOut , writeEn ,
+ strobe_i ,
+ clk , rst ,
+ SOFRxedIntOut , resetEventIntOut , resumeIntOut , transDoneIntOut , NAKSentIntOut ,
+ endP0TransTypeReg , endP0NAKTransTypeReg ,
+ endP1TransTypeReg , endP1NAKTransTypeReg ,
+ endP2TransTypeReg , endP2NAKTransTypeReg ,
+ endP3TransTypeReg , endP3NAKTransTypeReg ,
+ endP0ControlReg ,
+ endP1ControlReg ,
+ endP2ControlReg ,
+ endP3ControlReg ,
+ EP0StatusReg ,
+ EP1StatusReg ,
+ EP2StatusReg ,
+ EP3StatusReg ,
+ SCAddrReg , frameNum ,
+ connectStateIn ,
+ SOFRxedIn , resetEventIn , resumeIntIn , transDoneIn , NAKSentIn ,
+ slaveControlSelect ,
+ clrEP0Ready , clrEP1Ready , clrEP2Ready , clrEP3Ready ,
+ TxLineState ,
+ LineDirectControlEn ,
+ fullSpeedPol ,
+ fullSpeedRate ,
+ SCGlobalEn
+ );
+input [4 :0 ] address ;
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+output SOFRxedIntOut ;
+output resetEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+output NAKSentIntOut ;
+
+input [1 :0 ] endP0TransTypeReg ;
+input [1 :0 ] endP0NAKTransTypeReg ;
+input [1 :0 ] endP1TransTypeReg ;
+input [1 :0 ] endP1NAKTransTypeReg ;
+input [1 :0 ] endP2TransTypeReg ;
+input [1 :0 ] endP2NAKTransTypeReg ;
+input [1 :0 ] endP3TransTypeReg ;
+input [1 :0 ] endP3NAKTransTypeReg ;
+output [3 :0 ] endP0ControlReg ;
+output [3 :0 ] endP1ControlReg ;
+output [3 :0 ] endP2ControlReg ;
+output [3 :0 ] endP3ControlReg ;
+input [7 :0 ] EP0StatusReg ;
+input [7 :0 ] EP1StatusReg ;
+input [7 :0 ] EP2StatusReg ;
+input [7 :0 ] EP3StatusReg ;
+output [6 :0 ] SCAddrReg ;
+input [10 :0 ] frameNum ;
+input [1 :0 ] connectStateIn ;
+input SOFRxedIn ;
+input resetEventIn ;
+input resumeIntIn ;
+input transDoneIn ;
+input NAKSentIn ;
+input slaveControlSelect ;
+input clrEP0Ready ;
+input clrEP1Ready ;
+input clrEP2Ready ;
+input clrEP3Ready ;
+output [1 :0 ] TxLineState ;
+output LineDirectControlEn ;
+output fullSpeedPol ;
+output fullSpeedRate ;
+output SCGlobalEn ;
+
+wire [4 :0 ] address ;
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+
+reg SOFRxedIntOut ;
+reg resetEventIntOut ;
+reg resumeIntOut ;
+reg transDoneIntOut ;
+reg NAKSentIntOut ;
+
+wire [1 :0 ] endP0TransTypeReg ;
+wire [1 :0 ] endP0NAKTransTypeReg ;
+wire [1 :0 ] endP1TransTypeReg ;
+wire [1 :0 ] endP1NAKTransTypeReg ;
+wire [1 :0 ] endP2TransTypeReg ;
+wire [1 :0 ] endP2NAKTransTypeReg ;
+wire [1 :0 ] endP3TransTypeReg ;
+wire [1 :0 ] endP3NAKTransTypeReg ;
+reg [3 :0 ] endP0ControlReg ;
+reg [3 :0 ] endP1ControlReg ;
+reg [3 :0 ] endP2ControlReg ;
+reg [3 :0 ] endP3ControlReg ;
+wire [7 :0 ] EP0StatusReg ;
+wire [7 :0 ] EP1StatusReg ;
+wire [7 :0 ] EP2StatusReg ;
+wire [7 :0 ] EP3StatusReg ;
+reg [6 :0 ] SCAddrReg ;
+reg [3 :0 ] TxEndPReg ;
+wire [10 :0 ] frameNum ;
+wire [1 :0 ] connectStateIn ;
+
+wire SOFRxedIn ;
+wire resetEventIn ;
+wire resumeIntIn ;
+wire transDoneIn ;
+wire NAKSentIn ;
+wire slaveControlSelect ;
+wire clrEP0Ready ;
+wire clrEP1Ready ;
+wire clrEP2Ready ;
+wire clrEP3Ready ;
+reg [1 :0 ] TxLineState ;
+reg LineDirectControlEn ;
+reg fullSpeedPol ;
+reg fullSpeedRate ;
+reg SCGlobalEn ;
+
+//internal wire and regs
+reg [5 :0 ] SCControlReg ;
+reg clrNAKReq ;
+reg clrSOFReq ;
+reg clrResetReq ;
+reg clrResInReq ;
+reg clrTransDoneReq ;
+reg SOFRxedInt ;
+reg resetEventInt ;
+reg resumeInt ;
+reg transDoneInt ;
+reg NAKSentInt ;
+reg [4 :0 ] interruptMaskReg ;
+reg EP0SetReady ;
+reg EP1SetReady ;
+reg EP2SetReady ;
+reg EP3SetReady ;
+reg EP0SendStall ;
+reg EP1SendStall ;
+reg EP2SendStall ;
+reg EP3SendStall ;
+reg EP0DataSequence ;
+reg EP1DataSequence ;
+reg EP2DataSequence ;
+reg EP3DataSequence ;
+reg EP0Enable ;
+reg EP1Enable ;
+reg EP2Enable ;
+reg EP3Enable ;
+reg EP0Ready ;
+reg EP1Ready ;
+reg EP2Ready ;
+reg EP3Ready ;
+
+
+//sync write demux
+always @(posedge clk )
+begin
+ clrNAKReq <= 1'b0 ;
+ clrSOFReq <= 1'b0 ;
+ clrResetReq <= 1'b0 ;
+ clrResInReq <= 1'b0 ;
+ clrTransDoneReq <= 1'b0 ;
+ EP0SetReady <= 1'b0 ;
+ EP1SetReady <= 1'b0 ;
+ EP2SetReady <= 1'b0 ;
+ EP3SetReady <= 1'b0 ;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1 )
+ begin
+ case (address )
+ `EP0_CTRL_REG : begin
+ EP0SendStall <= dataIn [3 ];
+ EP0DataSequence <= dataIn [2 ];
+ EP0SetReady <= dataIn [1 ];
+ EP0Enable <= dataIn [0 ];
+ end
+ `EP1_CTRL_REG : begin
+ EP1SendStall <= dataIn [3 ];
+ EP1DataSequence <= dataIn [2 ];
+ EP1SetReady <= dataIn [1 ];
+ EP1Enable <= dataIn [0 ];
+ end
+ `EP2_CTRL_REG : begin
+ EP2SendStall <= dataIn [3 ];
+ EP2DataSequence <= dataIn [2 ];
+ EP2SetReady <= dataIn [1 ];
+ EP2Enable <= dataIn [0 ];
+ end
+ `EP3_CTRL_REG : begin
+ EP3SendStall <= dataIn [3 ];
+ EP3DataSequence <= dataIn [2 ];
+ EP3SetReady <= dataIn [1 ];
+ EP3Enable <= dataIn [0 ];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn [5 :0 ];
+ `SC_ADDRESS : SCAddrReg <= dataIn [6 :0 ];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn [4 ];
+ clrSOFReq <= dataIn [3 ];
+ clrResetReq <= dataIn [2 ];
+ clrResInReq <= dataIn [1 ];
+ clrTransDoneReq <= dataIn [0 ];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn [4 :0 ];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk )
+begin
+ if (NAKSentIn == 1'b1 )
+ NAKSentInt <= 1'b1 ;
+ else if (clrNAKReq == 1'b1 )
+ NAKSentInt <= 1'b0 ;
+
+ if (SOFRxedIn == 1'b1 )
+ SOFRxedInt <= 1'b1 ;
+ else if (clrSOFReq == 1'b1 )
+ SOFRxedInt <= 1'b0 ;
+
+ if (resetEventIn == 1'b1 )
+ resetEventInt <= 1'b1 ;
+ else if (clrResetReq == 1'b1 )
+ resetEventInt <= 1'b0 ;
+
+ if (resumeIntIn == 1'b1 )
+ resumeInt <= 1'b1 ;
+ else if (clrResInReq == 1'b1 )
+ resumeInt <= 1'b0 ;
+
+ if (transDoneIn == 1'b1 )
+ transDoneInt <= 1'b1 ;
+ else if (clrTransDoneReq == 1'b1 )
+ transDoneInt <= 1'b0 ;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt ) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg [`TRANS_DONE_BIT ];
+ resumeIntOut <= resumeInt & interruptMaskReg [`RESUME_INT_BIT ];
+ resetEventIntOut <= resetEventInt & interruptMaskReg [`RESET_EVENT_BIT ];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg [`SOF_RECEIVED_BIT ];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg [`NAK_SENT_INT_BIT ];
+end
+
+//end point ready, set/clear
+always @(posedge clk )
+begin
+ if (EP0SetReady == 1'b1 )
+ EP0Ready <= 1'b1 ;
+ else if (clrEP0Ready == 1'b1 )
+ EP0Ready <= 1'b0 ;
+
+ if (EP1SetReady == 1'b1 )
+ EP1Ready <= 1'b1 ;
+ else if (clrEP1Ready == 1'b1 )
+ EP1Ready <= 1'b0 ;
+
+ if (EP2SetReady == 1'b1 )
+ EP2Ready <= 1'b1 ;
+ else if (clrEP2Ready == 1'b1 )
+ EP2Ready <= 1'b0 ;
+
+ if (EP3SetReady == 1'b1 )
+ EP3Ready <= 1'b1 ;
+ else if (clrEP3Ready == 1'b1 )
+ EP3Ready <= 1'b0 ;
+end
+
+//break out control signals
+always @(SCControlReg ) begin
+ SCGlobalEn <= SCControlReg [`SC_GLOBAL_ENABLE_BIT ];
+ TxLineState <= SCControlReg [`SC_TX_LINE_STATE_MSBIT :`SC_TX_LINE_STATE_LSBIT ];
+ LineDirectControlEn <= SCControlReg [`SC_DIRECT_CONTROL_BIT ];
+ fullSpeedPol <= SCControlReg [`SC_FULL_SPEED_LINE_POLARITY_BIT ];
+ fullSpeedRate <= SCControlReg [`SC_FULL_SPEED_LINE_RATE_BIT ];
+end
+
+//combine endpoint control signals
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable )
+begin
+ endP0ControlReg <= {EP0SendStall , EP0DataSequence , EP0Ready , EP0Enable };
+ endP1ControlReg <= {EP1SendStall , EP1DataSequence , EP1Ready , EP1Enable };
+ endP2ControlReg <= {EP2SendStall , EP2DataSequence , EP2Ready , EP2Enable };
+ endP3ControlReg <= {EP3SendStall , EP3DataSequence , EP3Ready , EP3Enable };
+end
+
+
+ // async read mux
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+ endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+ endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
+ endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNum )
+begin
+ case (address )
+ `EP0_CTRL_REG : dataOut <= endP0ControlReg ;
+ `EP0_STS_REG : dataOut <= EP0StatusReg ;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg ;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg ;
+ `EP1_CTRL_REG : dataOut <= endP1ControlReg ;
+ `EP1_STS_REG : dataOut <= EP1StatusReg ;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg ;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg ;
+ `EP2_CTRL_REG : dataOut <= endP2ControlReg ;
+ `EP2_STS_REG : dataOut <= EP2StatusReg ;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg ;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg ;
+ `EP3_CTRL_REG : dataOut <= endP3ControlReg ;
+ `EP3_STS_REG : dataOut <= EP3StatusReg ;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg ;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg ;
+ `SC_CONTROL_REG : dataOut <= SCControlReg ;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000 , connectStateIn };
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000 , NAKSentInt , SOFRxedInt , resetEventInt , resumeInt , transDoneInt };
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000 , interruptMaskReg };
+ `SC_ADDRESS : dataOut <= {1'b0 , SCAddrReg };
+ `SC_FRAME_NUM_MSP : dataOut <= frameNum [10 :3 ];
+ `SC_FRAME_NUM_LSP : dataOut <= {5'b00000 , frameNum [2 :0 ]};
+ default : dataOut <= 8'h00 ;
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm
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+*
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_CONN.png
===================================================================
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+*
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+application/octet-stream
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html (revision 264)
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+*
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm (revision 264)
@@ -0,0 +1,122 @@
+
+
+updateCRC16.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC16 (rstCRC , CRCResult , CRCEn , dataIn , ready , clk , rst );
+input rstCRC ;
+input CRCEn ;
+input [7 :0 ] dataIn ;
+input clk ;
+input rst ;
+output [15 :0 ] CRCResult ;
+output ready ;
+
+wire rstCRC ;
+wire CRCEn ;
+wire [7 :0 ] dataIn ;
+wire clk ;
+wire rst ;
+reg [15 :0 ] CRCResult ;
+reg ready ;
+
+reg doUpdateCRC ;
+reg [7 :0 ] data ;
+reg [3 :0 ] i ;
+
+always @(posedge clk )
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1 ) begin
+ doUpdateCRC <= 1'b0 ;
+ i <= 4'h0 ;
+ CRCResult <= 16'hffff ;
+ ready <= 1'b1 ;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0 )
+ begin
+ if (CRCEn == 1'b1 ) begin
+ doUpdateCRC = 1'b1 ;
+ data <= dataIn ;
+ ready <= 1'b0 ;
+ end
+ end
+ else begin
+ i <= i + 1'b1 ;
+ if ( (CRCResult [0 ] ^ data [0 ]) == 1'b1 ) begin
+ CRCResult <= {1'b0 , CRCResult [15 :1 ]} ^ 16'ha001 ;
+ end
+ else begin
+ CRCResult <= {1'b0 , CRCResult [15 :1 ]};
+ end
+ data <= {1'b0 , data [7 :1 ]};
+ if (i == 4'h7 )
+ begin
+ doUpdateCRC <= 1'b0 ;
+ i <= 4'h0 ;
+ ready <= 1'b1 ;
+ end
+ end
+ end
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html
===================================================================
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+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_LS_CONN.png
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm (nonexistent)
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+
+
+usbSerialInterfaceEngine.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSerialInterfaceEngine (
+ clk , rst ,
+ //readUSBWireData
+ USBWireDataIn ,
+ USBWireDataInTick ,
+ //writeUSBWireData
+ USBWireDataOut ,
+ USBWireCtrlOut ,
+ USBWireDataOutTick ,
+ //SIEReceiver
+ connectState ,
+ //processRxBit
+ resumeDetected ,
+ //processRxByte
+ RxCtrlOut ,
+ RxDataOutWEn ,
+ RxDataOut ,
+ //SIETransmitter
+ SIEPortCtrlIn ,
+ SIEPortDataIn ,
+ SIEPortTxRdy ,
+ SIEPortWEn ,
+ //lineControlUpdate
+ fullSpeedPolarity ,
+ fullSpeedBitRate ,
+ noActivityTimeOut
+);
+
+input clk , rst ;
+//readUSBWireData
+input [1 :0 ] USBWireDataIn ;
+output USBWireDataInTick ;
+
+//writeUSBWireData
+output [1 :0 ] USBWireDataOut ;
+output USBWireCtrlOut ;
+output noActivityTimeOut ;
+output USBWireDataOutTick ;
+
+//SIEReceiver
+output [1 :0 ] connectState ;
+//processRxBit
+output resumeDetected ;
+//processRxByte
+output [7 :0 ] RxCtrlOut ;
+output RxDataOutWEn ;
+output [7 :0 ] RxDataOut ;
+//SIETransmitter
+input [7 :0 ] SIEPortCtrlIn ;
+input [7 :0 ] SIEPortDataIn ;
+output SIEPortTxRdy ;
+input SIEPortWEn ;
+//lineControlUpdate
+input fullSpeedPolarity ;
+input fullSpeedBitRate ;
+
+wire clk , rst ;
+//readUSBWireData
+wire [1 :0 ] USBWireDataIn ;
+wire USBWireDataInTick ;
+//writeUSBWireData
+wire [1 :0 ] USBWireDataOut ;
+wire USBWireCtrlOut ;
+wire noActivityTimeOut ;
+wire USBWireDataOutTick ;
+//SIEReceiver
+wire [1 :0 ] connectState ;
+//processRxBit
+wire resumeDetected ;
+//processRxByte
+wire [7 :0 ] RxCtrlOut ;
+wire RxDataOutWEn ;
+wire [7 :0 ] RxDataOut ;
+//SIETransmitter
+wire [7 :0 ] SIEPortCtrlIn ;
+wire [7 :0 ] SIEPortDataIn ;
+wire SIEPortTxRdy ;
+wire SIEPortWEn ;
+//lineControlUpdate
+wire fullSpeedPolarity ;
+wire fullSpeedBitRate ;
+
+//internal wiring
+wire [1 :0 ] RxBitsFromSIERxToPrRxBit ;
+wire processRxBitsWEn ;
+wire processRxBitRdy ;
+wire [1 :0 ] RxWireDataFromWireRxToSIERx ;
+wire RxWireDataWEn ;
+wire SIERxRdyOut ;
+wire disableWireRead ;
+wire [1 :0 ] TxBitsFromArbToWire ;
+wire TxCtrlFromArbToWire ;
+wire USBWireRdy ;
+wire USBWireWEn ;
+wire USBWireReadyFromTxArb ;
+wire prcTxByteCtrl ;
+wire [1 :0 ] prcTxByteData ;
+wire prcTxByteGnt ;
+wire prcTxByteReq ;
+wire prcTxByteWEn ;
+wire SIETxCtrl ;
+wire [1 :0 ] SIETxData ;
+wire SIETxGnt ;
+wire SIETxReq ;
+wire SIETxWEn ;
+wire [7 :0 ] TxByteFromSIEToPrcTxByte ;
+wire [7 :0 ] TxCtrlFromSIEToPrcTxByte ;
+wire [1 :0 ] JBit ;
+wire [1 :0 ] KBit ;
+wire processRxByteWEn ;
+wire [7 :0 ] RxDataFromPrcRxBitToPrcRxByte ;
+wire [7 :0 ] RxCtrlFromPrcRxBitToPrcRxByte ;
+wire processRxByteRdy ;
+//Rx CRC
+wire RxCRC16En ;
+wire [15 :0 ] RxCRC16Result ;
+wire RxCRC16UpdateRdy ;
+wire RxCRC5En ;
+wire [4 :0 ] RxCRC5Result ;
+wire RxCRC5_8Bit ;
+wire [7 :0 ] RxCRCData ;
+wire RxRstCRC ;
+wire RxCRC5UpdateRdy ;
+//Tx CRC
+wire TxCRC16En ;
+wire [15 :0 ] TxCRC16Result ;
+wire TxCRC16UpdateRdy ;
+wire TxCRC5En ;
+wire [4 :0 ] TxCRC5Result ;
+wire TxCRC5_8Bit ;
+wire [7 :0 ] TxCRCData ;
+wire TxRstCRC ;
+wire TxCRC5UpdateRdy ;
+
+wire processTxByteRdy ;
+wire processTxByteWEn ;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity (fullSpeedPolarity ),
+ .fullSpeedBitRate (fullSpeedBitRate ),
+ .JBit (JBit ),
+ .KBit (KBit ) );
+
+SIEReceiver u_SIEReceiver
+ (.RxBitsOut (RxBitsFromSIERxToPrRxBit ),
+ .RxWireDataIn (RxWireDataFromWireRxToSIERx ),
+ .RxWireDataWEn (RxWireDataWEn ),
+ .SIERxRdyOut (SIERxRdyOut ),
+ .clk (clk ),
+ .connectState (connectState ),
+ .processRxBitRdyIn (processRxBitRdy ),
+ .processRxBitsWEn (processRxBitsWEn ),
+ .rst (rst ) );
+
+processRxBit u_processRxBit
+ (.JBit (JBit ),
+ .KBit (KBit ),
+ .RxBitsIn (RxBitsFromSIERxToPrRxBit ),
+ .RxCtrlOut (RxCtrlFromPrcRxBitToPrcRxByte ),
+ .RxDataOut (RxDataFromPrcRxBitToPrcRxByte ),
+ .clk (clk ),
+ .processRxBitRdy (processRxBitRdy ),
+ .processRxBitsWEn (processRxBitsWEn ),
+ .processRxByteWEn (processRxByteWEn ),
+ .resumeDetected (resumeDetected ),
+ .rst (rst ),
+ .processRxByteRdy (processRxByteRdy ) );
+
+processRxByte u_processRxByte
+ (.CRC16En (RxCRC16En ),
+ .CRC16Result (RxCRC16Result ),
+ .CRC16UpdateRdy (RxCRC16UpdateRdy ),
+ .CRC5En (RxCRC5En ),
+ .CRC5Result (RxCRC5Result ),
+ .CRC5_8Bit (RxCRC5_8Bit ),
+ .CRC5UpdateRdy (RxCRC5UpdateRdy ),
+ .CRCData (RxCRCData ),
+ .RxByteIn (RxDataFromPrcRxBitToPrcRxByte ),
+ .RxCtrlIn (RxCtrlFromPrcRxBitToPrcRxByte ),
+ .RxCtrlOut (RxCtrlOut ),
+ .RxDataOutWEn (RxDataOutWEn ),
+ .RxDataOut (RxDataOut ),
+ .clk (clk ),
+ .processRxDataInWEn (processRxByteWEn ),
+ .rst (rst ),
+ .rstCRC (RxRstCRC ),
+ .processRxByteRdy (processRxByteRdy ) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC (RxRstCRC ),
+ .CRCResult (RxCRC5Result ),
+ .CRCEn (RxCRC5En ),
+ .CRC5_8BitIn (RxCRC5_8Bit ),
+ .dataIn (RxCRCData ),
+ .ready (RxCRC5UpdateRdy ),
+ .clk (clk ),
+ .rst (rst ) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC (RxRstCRC ),
+ .CRCResult (RxCRC16Result ),
+ .CRCEn (RxCRC16En ),
+ .dataIn (RxCRCData ),
+ .ready (RxCRC16UpdateRdy ),
+ .clk (clk ),
+ .rst (rst ) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En (TxCRC16En ),
+ .CRC16Result (TxCRC16Result ),
+ .CRC5En (TxCRC5En ),
+ .CRC5Result (TxCRC5Result ),
+ .CRC5_8Bit (TxCRC5_8Bit ),
+ .CRCData (TxCRCData ),
+ .CRC5UpdateRdy (TxCRC5UpdateRdy ),
+ .CRC16UpdateRdy (TxCRC16UpdateRdy ),
+ .JBit (JBit ),
+ .KBit (KBit ),
+ .SIEPortCtrlIn (SIEPortCtrlIn ),
+ .SIEPortDataIn (SIEPortDataIn ),
+ .SIEPortTxRdy (SIEPortTxRdy ),
+ .SIEPortWEn (SIEPortWEn ),
+ .TxByteOutCtrl (TxCtrlFromSIEToPrcTxByte ),
+ .TxByteOut (TxByteFromSIEToPrcTxByte ),
+ .USBWireCtrl (SIETxCtrl ),
+ .USBWireData (SIETxData ),
+ .USBWireGnt (SIETxGnt ),
+ .USBWireRdy (USBWireReadyFromTxArb ),
+ .USBWireReq (SIETxReq ),
+ .USBWireWEn (SIETxWEn ),
+ .clk (clk ),
+ .processTxByteRdy (processTxByteRdy ),
+ .processTxByteWEn (processTxByteWEn ),
+ .rst (rst ),
+ .rstCRC (TxRstCRC ) );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC (TxRstCRC ),
+ .CRCResult (TxCRC5Result ),
+ .CRCEn (TxCRC5En ),
+ .CRC5_8BitIn (TxCRC5_8Bit ),
+ .dataIn (TxCRCData ),
+ .ready (TxCRC5UpdateRdy ),
+ .clk (clk ),
+ .rst (rst ) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC (TxRstCRC ),
+ .CRCResult (TxCRC16Result ),
+ .CRCEn (TxCRC16En ),
+ .dataIn (TxCRCData ),
+ .ready (TxCRC16UpdateRdy ),
+ .clk (clk ),
+ .rst (rst ) );
+
+processTxByte u_processTxByte
+ (.JBit (JBit ),
+ .KBit (KBit ),
+ .TxByteCtrlIn (TxCtrlFromSIEToPrcTxByte ),
+ .TxByteIn (TxByteFromSIEToPrcTxByte ),
+ .USBWireCtrl (prcTxByteCtrl ),
+ .USBWireData (prcTxByteData ),
+ .USBWireGnt (prcTxByteGnt ),
+ .USBWireRdy (USBWireReadyFromTxArb ),
+ .USBWireReq (prcTxByteReq ),
+ .USBWireWEn (prcTxByteWEn ),
+ .clk (clk ),
+ .processTxByteRdy (processTxByteRdy ),
+ .processTxByteWEn (processTxByteWEn ),
+ .rst (rst ) );
+
+USBWireTxArbiter u_USBWireTxArbiter
+ (.SIETxCtrl (SIETxCtrl ),
+ .SIETxData (SIETxData ),
+ .SIETxGnt (SIETxGnt ),
+ .SIETxReq (SIETxReq ),
+ .SIETxWEn (SIETxWEn ),
+ .TxBits (TxBitsFromArbToWire ),
+ .TxCtl (TxCtrlFromArbToWire ),
+ .USBWireRdyIn (USBWireRdy ),
+ .USBWireRdyOut (USBWireReadyFromTxArb ),
+ .USBWireWEn (USBWireWEn ),
+ .clk (clk ),
+ .prcTxByteCtrl (prcTxByteCtrl ),
+ .prcTxByteData (prcTxByteData ),
+ .prcTxByteGnt (prcTxByteGnt ),
+ .prcTxByteReq (prcTxByteReq ),
+ .prcTxByteWEn (prcTxByteWEn ),
+ .rst (rst ) );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn (TxBitsFromArbToWire ),
+ .TxBitsOut (USBWireDataOut ),
+ .TxDataOutTick (USBWireDataOutTick ),
+ .TxCtrlIn (TxCtrlFromArbToWire ),
+ .TxCtrlOut (USBWireCtrlOut ),
+ .USBWireRdy (USBWireRdy ),
+ .USBWireWEn (USBWireWEn ),
+ .disableWireReadOut (disableWireRead ),
+ .fullSpeedRate (fullSpeedBitRate ),
+ .clk (clk ),
+ .rst (rst ),
+ .noActivityTimeOut (noActivityTimeOut ) );
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn (USBWireDataIn ),
+ .RxDataInTick (USBWireDataInTick ),
+ .RxBitsOut (RxWireDataFromWireRxToSIERx ),
+ .SIERxRdyIn (SIERxRdyOut ),
+ .SIERxWEn (RxWireDataWEn ),
+ .fullSpeedRate (fullSpeedBitRate ),
+ .disableWireRead (disableWireRead ),
+ .clk (clk ),
+ .rst (rst ) );
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.png
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm (revision 264)
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+
+
+endpMux.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk ,
+ rst ,
+ currEndP ,
+ NAKSent ,
+ stallSent ,
+ CRCError ,
+ bitStuffError ,
+ RxOverflow ,
+ RxTimeOut ,
+ dataSequence ,
+ ACKRxed ,
+ transType ,
+ transTypeNAK ,
+ endPControlReg ,
+ clrEPRdy ,
+ endPMuxErrorsWEn ,
+ endP0ControlReg ,
+ endP1ControlReg ,
+ endP2ControlReg ,
+ endP3ControlReg ,
+ endP0StatusReg ,
+ endP1StatusReg ,
+ endP2StatusReg ,
+ endP3StatusReg ,
+ endP0TransTypeReg ,
+ endP1TransTypeReg ,
+ endP2TransTypeReg ,
+ endP3TransTypeReg ,
+ endP0NAKTransTypeReg ,
+ endP1NAKTransTypeReg ,
+ endP2NAKTransTypeReg ,
+ endP3NAKTransTypeReg ,
+ clrEP0Rdy ,
+ clrEP1Rdy ,
+ clrEP2Rdy ,
+ clrEP3Rdy );
+
+
+input clk ;
+input rst ;
+input [3 :0 ] currEndP ;
+input NAKSent ;
+input stallSent ;
+input CRCError ;
+input bitStuffError ;
+input RxOverflow ;
+input RxTimeOut ;
+input dataSequence ;
+input ACKRxed ;
+input [1 :0 ] transType ;
+input [1 :0 ] transTypeNAK ;
+output [3 :0 ] endPControlReg ;
+input clrEPRdy ;
+input endPMuxErrorsWEn ;
+input [3 :0 ] endP0ControlReg ;
+input [3 :0 ] endP1ControlReg ;
+input [3 :0 ] endP2ControlReg ;
+input [3 :0 ] endP3ControlReg ;
+output [7 :0 ] endP0StatusReg ;
+output [7 :0 ] endP1StatusReg ;
+output [7 :0 ] endP2StatusReg ;
+output [7 :0 ] endP3StatusReg ;
+output [1 :0 ] endP0TransTypeReg ;
+output [1 :0 ] endP1TransTypeReg ;
+output [1 :0 ] endP2TransTypeReg ;
+output [1 :0 ] endP3TransTypeReg ;
+output [1 :0 ] endP0NAKTransTypeReg ;
+output [1 :0 ] endP1NAKTransTypeReg ;
+output [1 :0 ] endP2NAKTransTypeReg ;
+output [1 :0 ] endP3NAKTransTypeReg ;
+output clrEP0Rdy ;
+output clrEP1Rdy ;
+output clrEP2Rdy ;
+output clrEP3Rdy ;
+
+wire clk ;
+wire rst ;
+wire [3 :0 ] currEndP ;
+wire NAKSent ;
+wire stallSent ;
+wire CRCError ;
+wire bitStuffError ;
+wire RxOverflow ;
+wire RxTimeOut ;
+wire dataSequence ;
+wire ACKRxed ;
+wire [1 :0 ] transType ;
+wire [1 :0 ] transTypeNAK ;
+reg [3 :0 ] endPControlReg ;
+wire clrEPRdy ;
+wire endPMuxErrorsWEn ;
+wire [3 :0 ] endP0ControlReg ;
+wire [3 :0 ] endP1ControlReg ;
+wire [3 :0 ] endP2ControlReg ;
+wire [3 :0 ] endP3ControlReg ;
+reg [7 :0 ] endP0StatusReg ;
+reg [7 :0 ] endP1StatusReg ;
+reg [7 :0 ] endP2StatusReg ;
+reg [7 :0 ] endP3StatusReg ;
+reg [1 :0 ] endP0TransTypeReg ;
+reg [1 :0 ] endP1TransTypeReg ;
+reg [1 :0 ] endP2TransTypeReg ;
+reg [1 :0 ] endP3TransTypeReg ;
+reg [1 :0 ] endP0NAKTransTypeReg ;
+reg [1 :0 ] endP1NAKTransTypeReg ;
+reg [1 :0 ] endP2NAKTransTypeReg ;
+reg [1 :0 ] endP3NAKTransTypeReg ;
+reg clrEP0Rdy ;
+reg clrEP1Rdy ;
+reg clrEP2Rdy ;
+reg clrEP3Rdy ;
+
+//internal wires and regs
+reg [7 :0 ] endPStatusCombine ;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk )
+begin
+ case (currEndP [1 :0 ])
+ 2'b00 : begin
+ endPControlReg <= endP0ControlReg ;
+ clrEP0Rdy <= clrEPRdy ;
+ end
+ 2'b01 : begin
+ endPControlReg <= endP1ControlReg ;
+ clrEP1Rdy <= clrEPRdy ;
+ end
+ 2'b10 : begin
+ endPControlReg <= endP2ControlReg ;
+ clrEP2Rdy <= clrEPRdy ;
+ end
+ 2'b11 : begin
+ endPControlReg <= endP3ControlReg ;
+ clrEP3Rdy <= clrEPRdy ;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk )
+begin
+ if (rst ) begin
+ endP0NAKTransTypeReg <= 2'b00 ;
+ endP1NAKTransTypeReg <= 2'b00 ;
+ endP2NAKTransTypeReg <= 2'b00 ;
+ endP3NAKTransTypeReg <= 2'b00 ;
+ endP0TransTypeReg <= 2'b00 ;
+ endP1TransTypeReg <= 2'b00 ;
+ endP2TransTypeReg <= 2'b00 ;
+ endP3TransTypeReg <= 2'b00 ;
+ endP0StatusReg <= 4'h0 ;
+ endP1StatusReg <= 4'h0 ;
+ endP2StatusReg <= 4'h0 ;
+ endP3StatusReg <= 4'h0 ;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1 ) begin
+ if (NAKSent == 1'b1 ) begin
+ case (currEndP [1 :0 ])
+ 2'b00 : begin
+ endP0NAKTransTypeReg <= transTypeNAK ;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK ;
+ end
+ 2'b01 : begin
+ endP1NAKTransTypeReg <= transTypeNAK ;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK ;
+ end
+ 2'b10 : begin
+ endP2NAKTransTypeReg <= transTypeNAK ;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK ;
+ end
+ 2'b11 : begin
+ endP3NAKTransTypeReg <= transTypeNAK ;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK ;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP [1 :0 ])
+ 2'b00 : begin
+ endP0TransTypeReg <= transType ;
+ endP0StatusReg <= endPStatusCombine ;
+ end
+ 2'b01 : begin
+ endP1TransTypeReg <= transType ;
+ endP1StatusReg <= endPStatusCombine ;
+ end
+ 2'b10 : begin
+ endP2TransTypeReg <= transType ;
+ endP2StatusReg <= endPStatusCombine ;
+ end
+ 2'b11 : begin
+ endP3TransTypeReg <= transType ;
+ endP3StatusReg <= endPStatusCombine ;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError )
+begin
+ endPStatusCombine <= {dataSequence , ACKRxed , stallSent , 1'b0 , RxTimeOut , RxOverflow , bitStuffError , CRCError };
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
___________________________________________________________________
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+*
\ No newline at end of property
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+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
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+
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+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html (revision 264)
@@ -0,0 +1,70 @@
+
+
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+
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+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm (revision 264)
@@ -0,0 +1,320 @@
+
+
+writeUSBWireData.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn ,
+ TxBitsOut ,
+ TxDataOutTick ,
+ TxCtrlIn ,
+ TxCtrlOut ,
+ USBWireRdy ,
+ USBWireWEn ,
+ disableWireReadOut ,
+ fullSpeedRate ,
+ clk ,
+ rst ,
+ noActivityTimeOut );
+
+input [1 :0 ] TxBitsIn ;
+input TxCtrlIn ;
+input USBWireWEn ;
+input clk ;
+input fullSpeedRate ;
+input rst ;
+output [1 :0 ] TxBitsOut ;
+output TxDataOutTick ;
+output TxCtrlOut ;
+output USBWireRdy ;
+output disableWireReadOut ;
+output noActivityTimeOut ;
+
+wire [1 :0 ] TxBitsIn ;
+reg [1 :0 ] TxBitsOut ;
+reg TxDataOutTick ;
+wire TxCtrlIn ;
+reg TxCtrlOut ;
+reg USBWireRdy ;
+wire USBWireWEn ;
+wire clk ;
+wire fullSpeedRate ;
+wire rst ;
+reg disableWireReadOut ;
+reg noActivityTimeOut ;
+
+// local registers
+reg [2 :0 ]buffer0 ;
+reg [2 :0 ]buffer1 ;
+reg [2 :0 ]buffer2 ;
+reg [2 :0 ]buffer3 ;
+reg [2 :0 ]bufferCnt ;
+reg [1 :0 ]bufferInIndex ;
+reg [1 :0 ]bufferOutIndex ;
+reg decBufferCnt ;
+reg [4 :0 ]i ;
+reg incBufferCnt ;
+reg fullSpeedTick ;
+reg lowSpeedTick ;
+reg [15 :0 ] timeOutCnt ;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1 :0 ] bufferInStMachCurrState ;
+reg [1 :0 ] bufferOutStMachCurrState ;
+
+// buffer control
+always @(posedge clk )
+begin
+ if (rst == 1'b1 )
+ begin
+ bufferCnt <= 3'b000 ;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0 )
+ bufferCnt <= bufferCnt + 1'b1 ;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1 )
+ bufferCnt <= bufferCnt - 1'b1 ;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk ) begin
+ if (rst == 1'b1 ) begin
+ incBufferCnt <= 1'b0 ;
+ bufferInIndex <= 2'b00 ;
+ buffer0 <= 3'b000 ;
+ buffer1 <= 3'b000 ;
+ buffer2 <= 3'b000 ;
+ buffer3 <= 3'b000 ;
+ USBWireRdy <= 1'b0 ;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL ;
+ end
+ else begin
+ case (bufferInStMachCurrState )
+ `WAIT_BUFFER_NOT_FULL :
+ begin
+ if (bufferCnt != `BUFFER_FULL )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ ;
+ USBWireRdy <= 1'b1 ;
+ end
+ end
+ `WAIT_WRITE_REQ :
+ begin
+ if (USBWireWEn == 1'b1 )
+ begin
+ incBufferCnt <= 1'b1 ;
+ USBWireRdy <= 1'b0 ;
+ bufferInIndex <= bufferInIndex + 1'b1 ;
+ case (bufferInIndex )
+ 2'b00 : buffer0 <= {TxBitsIn , TxCtrlIn };
+ 2'b01 : buffer1 <= {TxBitsIn , TxCtrlIn };
+ 2'b10 : buffer2 <= {TxBitsIn , TxCtrlIn };
+ 2'b11 : buffer3 <= {TxBitsIn , TxCtrlIn };
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT ;
+ end
+ end
+ `CLR_INC_BUFFER_CNT :
+ begin
+ incBufferCnt <= 1'b0 ;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1 ) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ ;
+ USBWireRdy <= 1'b1 ;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL ;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk ) begin
+ if (rst == 1'b1 )
+ begin
+ i <= 5'b00000 ;
+ fullSpeedTick <= 1'b0 ;
+ lowSpeedTick <= 1'b0 ;
+ end
+ else
+ begin
+ i <= i + 1'b1 ;
+ if (i [1 :0 ] == 2'b00 )
+ fullSpeedTick <= 1'b1 ;
+ else
+ fullSpeedTick <= 1'b0 ;
+ if (i == 5'b00000 )
+ lowSpeedTick <= 1'b1 ;
+ else
+ lowSpeedTick <= 1'b0 ;
+ end
+end
+
+//buffer output state machine
+//After reset, waits for the output buffer to become full.
+//Once the buffer is full then it is constantly emptied at either
+//the full or low speed rate with no under run protection
+always @(posedge clk ) begin
+ if (rst == 1'b1 )
+ begin
+ bufferOutIndex <= 2'b00 ;
+ decBufferCnt <= 1'b0 ;
+ TxBitsOut <= 2'b00 ;
+ TxCtrlOut <= `TRI_STATE ;
+ TxDataOutTick <= 1'b0 ;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_FULL ;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState )
+ `WAIT_BUFFER_FULL :
+ begin
+ if (bufferCnt == `BUFFER_FULL )
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE ;
+ end
+ `WAIT_LINE_WRITE :
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1 ) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1 ) )
+ begin
+ TxDataOutTick <= !TxDataOutTick ;
+ bufferOutStMachCurrState <= `LINE_WRITE ;
+ decBufferCnt <= 1'b1 ;
+ bufferOutIndex <= bufferOutIndex + 1'b1 ;
+ case (bufferOutIndex )
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0 [2 :1 ];
+ TxCtrlOut <= buffer0 [0 ];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1 [2 :1 ];
+ TxCtrlOut <= buffer1 [0 ];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2 [2 :1 ];
+ TxCtrlOut <= buffer2 [0 ];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3 [2 :1 ];
+ TxCtrlOut <= buffer3 [0 ];
+ end
+ endcase
+ end
+ end
+ `LINE_WRITE :
+ begin
+ decBufferCnt <= 1'b0 ;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE ;
+ end
+ endcase
+ end
+end
+
+// control 'disableWireReadOut'
+always @(TxCtrlOut )
+begin
+ if (TxCtrlOut == `DRIVE )
+ disableWireReadOut <= 1'b1 ;
+ else
+ disableWireReadOut <= 1'b0 ;
+end
+
+//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
+always @(posedge clk ) begin
+ if (rst ) begin
+ timeOutCnt <= 16'h0000 ;
+ noActivityTimeOut <= 1'b0 ;
+ end
+ else begin
+ if (TxCtrlOut == `DRIVE )
+ timeOutCnt <= 16'h0000 ;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1 ;
+ //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+ if (timeOutCnt == 16'h200 ) //temporary fix
+ noActivityTimeOut <= 1'b1 ;
+ else
+ noActivityTimeOut <= 1'b0 ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html (revision 264)
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html (revision 264)
@@ -0,0 +1,70 @@
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html (revision 264)
@@ -0,0 +1,70 @@
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
___________________________________________________________________
Added: svn:executable
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\ No newline at end of property
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html (revision 264)
@@ -0,0 +1,48 @@
+
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html (revision 264)
@@ -0,0 +1,70 @@
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm (revision 264)
@@ -0,0 +1,215 @@
+
+
+usbTxWireArbiter.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBWireTxArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:07 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbConstants_h.v"
+
+module USBWireTxArbiter (SIETxCtrl , SIETxData , SIETxGnt , SIETxReq , SIETxWEn , TxBits , TxCtl , USBWireRdyIn , USBWireRdyOut , USBWireWEn , clk , prcTxByteCtrl , prcTxByteData , prcTxByteGnt , prcTxByteReq , prcTxByteWEn , rst );
+input SIETxCtrl ;
+input [1 :0 ] SIETxData ;
+input SIETxReq ;
+input SIETxWEn ;
+input USBWireRdyIn ;
+input clk ;
+input prcTxByteCtrl ;
+input [1 :0 ] prcTxByteData ;
+input prcTxByteReq ;
+input prcTxByteWEn ;
+input rst ;
+output SIETxGnt ;
+output [1 :0 ] TxBits ;
+output TxCtl ;
+output USBWireRdyOut ;
+output USBWireWEn ;
+output prcTxByteGnt ;
+
+wire SIETxCtrl ;
+wire [1 :0 ] SIETxData ;
+reg SIETxGnt , next_SIETxGnt ;
+wire SIETxReq ;
+wire SIETxWEn ;
+reg [1 :0 ] TxBits , next_TxBits ;
+reg TxCtl , next_TxCtl ;
+wire USBWireRdyIn ;
+reg USBWireRdyOut , next_USBWireRdyOut ;
+reg USBWireWEn , next_USBWireWEn ;
+wire clk ;
+wire prcTxByteCtrl ;
+wire [1 :0 ] prcTxByteData ;
+reg prcTxByteGnt , next_prcTxByteGnt ;
+wire prcTxByteReq ;
+wire prcTxByteWEn ;
+wire rst ;
+
+// diagram signals declarations
+reg muxSIENotPTXB , next_muxSIENotPTXB ;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1 :0 ] CurrState_txWireArb ;
+reg [1 :0 ] NextState_txWireArb ;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn )
+begin
+ USBWireRdyOut <= USBWireRdyIn ;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl )
+begin
+ if (muxSIENotPTXB == 1'b1 )
+ begin
+ USBWireWEn <= SIETxWEn ;
+ TxBits <= SIETxData ;
+ TxCtl <= SIETxCtrl ;
+ end
+ else
+ begin
+ USBWireWEn <= prcTxByteWEn ;
+ TxBits <= prcTxByteData ;
+ TxCtl <= prcTxByteCtrl ;
+ end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: txWireArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb )
+begin : txWireArb_NextState
+ NextState_txWireArb <= CurrState_txWireArb ;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt ;
+ next_muxSIENotPTXB <= muxSIENotPTXB ;
+ next_SIETxGnt <= SIETxGnt ;
+ case (CurrState_txWireArb ) // synopsys parallel_case full_case
+ `START_TARB :
+ NextState_txWireArb <= `TARB_WAIT_REQ ;
+ `TARB_WAIT_REQ :
+ if (prcTxByteReq == 1'b1 )
+ begin
+ NextState_txWireArb <= `PTXB_ACT ;
+ next_prcTxByteGnt <= 1'b1 ;
+ next_muxSIENotPTXB <= 1'b0 ;
+ end
+ else if (SIETxReq == 1'b1 )
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT ;
+ next_SIETxGnt <= 1'b1 ;
+ next_muxSIENotPTXB <= 1'b1 ;
+ end
+ `PTXB_ACT :
+ if (prcTxByteReq == 1'b0 )
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ ;
+ next_prcTxByteGnt <= 1'b0 ;
+ end
+ `SIE_TX_ACT :
+ if (SIETxReq == 1'b0 )
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ ;
+ next_SIETxGnt <= 1'b0 ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : txWireArb_CurrentState
+ if (rst )
+ CurrState_txWireArb <= `START_TARB ;
+ else
+ CurrState_txWireArb <= NextState_txWireArb ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : txWireArb_RegOutput
+ if (rst )
+ begin
+ muxSIENotPTXB <= 1'b0 ;
+ prcTxByteGnt <= 1'b0 ;
+ SIETxGnt <= 1'b0 ;
+ end
+ else
+ begin
+ muxSIENotPTXB <= next_muxSIENotPTXB ;
+ prcTxByteGnt <= next_prcTxByteGnt ;
+ SIETxGnt <= next_SIETxGnt ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm (revision 264)
@@ -0,0 +1,229 @@
+
+
+fifoMux.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module fifoMux (
+ currEndP ,
+ //TxFifo
+ TxFifoREn ,
+ TxFifoEP0REn ,
+ TxFifoEP1REn ,
+ TxFifoEP2REn ,
+ TxFifoEP3REn ,
+ TxFifoData ,
+ TxFifoEP0Data ,
+ TxFifoEP1Data ,
+ TxFifoEP2Data ,
+ TxFifoEP3Data ,
+ TxFifoEmpty ,
+ TxFifoEP0Empty ,
+ TxFifoEP1Empty ,
+ TxFifoEP2Empty ,
+ TxFifoEP3Empty ,
+ //RxFifo
+ RxFifoWEn ,
+ RxFifoEP0WEn ,
+ RxFifoEP1WEn ,
+ RxFifoEP2WEn ,
+ RxFifoEP3WEn ,
+ RxFifoFull ,
+ RxFifoEP0Full ,
+ RxFifoEP1Full ,
+ RxFifoEP2Full ,
+ RxFifoEP3Full
+ );
+
+
+input [3 :0 ] currEndP ;
+//TxFifo
+input TxFifoREn ;
+output TxFifoEP0REn ;
+output TxFifoEP1REn ;
+output TxFifoEP2REn ;
+output TxFifoEP3REn ;
+output [7 :0 ] TxFifoData ;
+input [7 :0 ] TxFifoEP0Data ;
+input [7 :0 ] TxFifoEP1Data ;
+input [7 :0 ] TxFifoEP2Data ;
+input [7 :0 ] TxFifoEP3Data ;
+output TxFifoEmpty ;
+input TxFifoEP0Empty ;
+input TxFifoEP1Empty ;
+input TxFifoEP2Empty ;
+input TxFifoEP3Empty ;
+ //RxFifo
+input RxFifoWEn ;
+output RxFifoEP0WEn ;
+output RxFifoEP1WEn ;
+output RxFifoEP2WEn ;
+output RxFifoEP3WEn ;
+output RxFifoFull ;
+input RxFifoEP0Full ;
+input RxFifoEP1Full ;
+input RxFifoEP2Full ;
+input RxFifoEP3Full ;
+
+wire [3 :0 ] currEndP ;
+//TxFifo
+wire TxFifoREn ;
+reg TxFifoEP0REn ;
+reg TxFifoEP1REn ;
+reg TxFifoEP2REn ;
+reg TxFifoEP3REn ;
+reg [7 :0 ] TxFifoData ;
+wire [7 :0 ] TxFifoEP0Data ;
+wire [7 :0 ] TxFifoEP1Data ;
+wire [7 :0 ] TxFifoEP2Data ;
+wire [7 :0 ] TxFifoEP3Data ;
+reg TxFifoEmpty ;
+wire TxFifoEP0Empty ;
+wire TxFifoEP1Empty ;
+wire TxFifoEP2Empty ;
+wire TxFifoEP3Empty ;
+ //RxFifo
+wire RxFifoWEn ;
+reg RxFifoEP0WEn ;
+reg RxFifoEP1WEn ;
+reg RxFifoEP2WEn ;
+reg RxFifoEP3WEn ;
+reg RxFifoFull ;
+wire RxFifoEP0Full ;
+wire RxFifoEP1Full ;
+wire RxFifoEP2Full ;
+wire RxFifoEP3Full ;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full )
+begin
+ case (currEndP [1 :0 ])
+ 2'b00 : begin
+ TxFifoEP0REn <= TxFifoREn ;
+ TxFifoEP1REn <= 1'b0 ;
+ TxFifoEP2REn <= 1'b0 ;
+ TxFifoEP3REn <= 1'b0 ;
+ TxFifoData <= TxFifoEP0Data ;
+ TxFifoEmpty <= TxFifoEP0Empty ;
+ RxFifoEP0WEn <= RxFifoWEn ;
+ RxFifoEP1WEn <= 1'b0 ;
+ RxFifoEP2WEn <= 1'b0 ;
+ RxFifoEP3WEn <= 1'b0 ;
+ RxFifoFull <= RxFifoEP0Full ;
+ end
+ 2'b01 : begin
+ TxFifoEP0REn <= 1'b0 ;
+ TxFifoEP1REn <= TxFifoREn ;
+ TxFifoEP2REn <= 1'b0 ;
+ TxFifoEP3REn <= 1'b0 ;
+ TxFifoData <= TxFifoEP1Data ;
+ TxFifoEmpty <= TxFifoEP1Empty ;
+ RxFifoEP0WEn <= 1'b0 ;
+ RxFifoEP1WEn <= RxFifoWEn ;
+ RxFifoEP2WEn <= 1'b0 ;
+ RxFifoEP3WEn <= 1'b0 ;
+ RxFifoFull <= RxFifoEP1Full ;
+ end
+ 2'b10 : begin
+ TxFifoEP0REn <= 1'b0 ;
+ TxFifoEP1REn <= 1'b0 ;
+ TxFifoEP2REn <= TxFifoREn ;
+ TxFifoEP3REn <= 1'b0 ;
+ TxFifoData <= TxFifoEP2Data ;
+ TxFifoEmpty <= TxFifoEP2Empty ;
+ RxFifoEP0WEn <= 1'b0 ;
+ RxFifoEP1WEn <= 1'b0 ;
+ RxFifoEP2WEn <= RxFifoWEn ;
+ RxFifoEP3WEn <= 1'b0 ;
+ RxFifoFull <= RxFifoEP2Full ;
+ end
+ 2'b11 : begin
+ TxFifoEP0REn <= 1'b0 ;
+ TxFifoEP1REn <= 1'b0 ;
+ TxFifoEP2REn <= 1'b0 ;
+ TxFifoEP3REn <= TxFifoREn ;
+ TxFifoData <= TxFifoEP3Data ;
+ TxFifoEmpty <= TxFifoEP3Empty ;
+ RxFifoEP0WEn <= 1'b0 ;
+ RxFifoEP1WEn <= 1'b0 ;
+ RxFifoEP2WEn <= 1'b0 ;
+ RxFifoEP3WEn <= RxFifoWEn ;
+ RxFifoFull <= RxFifoEP3Full ;
+ end
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm (revision 264)
@@ -0,0 +1,216 @@
+
+
+sctxportarbiter.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+
+module SCTxPortArbiter (SCTxPortCntl , SCTxPortData , SCTxPortRdyIn , SCTxPortRdyOut , SCTxPortWEnable , clk , directCntlCntl , directCntlData , directCntlGnt , directCntlReq , directCntlWEn , rst , sendPacketCntl , sendPacketData , sendPacketGnt , sendPacketReq , sendPacketWEn );
+input SCTxPortRdyIn ;
+input clk ;
+input [7 :0 ] directCntlCntl ;
+input [7 :0 ] directCntlData ;
+input directCntlReq ;
+input directCntlWEn ;
+input rst ;
+input [7 :0 ] sendPacketCntl ;
+input [7 :0 ] sendPacketData ;
+input sendPacketReq ;
+input sendPacketWEn ;
+output [7 :0 ] SCTxPortCntl ;
+output [7 :0 ] SCTxPortData ;
+output SCTxPortRdyOut ;
+output SCTxPortWEnable ;
+output directCntlGnt ;
+output sendPacketGnt ;
+
+reg [7 :0 ] SCTxPortCntl , next_SCTxPortCntl ;
+reg [7 :0 ] SCTxPortData , next_SCTxPortData ;
+wire SCTxPortRdyIn ;
+reg SCTxPortRdyOut , next_SCTxPortRdyOut ;
+reg SCTxPortWEnable , next_SCTxPortWEnable ;
+wire clk ;
+wire [7 :0 ] directCntlCntl ;
+wire [7 :0 ] directCntlData ;
+reg directCntlGnt , next_directCntlGnt ;
+wire directCntlReq ;
+wire directCntlWEn ;
+wire rst ;
+wire [7 :0 ] sendPacketCntl ;
+wire [7 :0 ] sendPacketData ;
+reg sendPacketGnt , next_sendPacketGnt ;
+wire sendPacketReq ;
+wire sendPacketWEn ;
+
+// diagram signals declarations
+reg muxDCEn , next_muxDCEn ;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1 :0 ] CurrState_SCTxArb ;
+reg [1 :0 ] NextState_SCTxArb ;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn )
+begin
+ SCTxPortRdyOut = SCTxPortRdyIn ;
+end
+always @(muxDCEn or
+ directCntlWEn or directCntlData or directCntlCntl or
+ directCntlWEn or directCntlData or directCntlCntl or
+ sendPacketWEn or sendPacketData or sendPacketCntl )
+begin
+if (muxDCEn == 1'b1 )
+ begin
+ SCTxPortWEnable <= directCntlWEn ;
+ SCTxPortData <= directCntlData ;
+ SCTxPortCntl <= directCntlCntl ;
+ end
+else
+ begin
+ SCTxPortWEnable <= sendPacketWEn ;
+ SCTxPortData <= sendPacketData ;
+ SCTxPortCntl <= sendPacketCntl ;
+ end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb )
+begin : SCTxArb_NextState
+ NextState_SCTxArb <= CurrState_SCTxArb ;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt ;
+ next_muxDCEn <= muxDCEn ;
+ next_directCntlGnt <= directCntlGnt ;
+ case (CurrState_SCTxArb ) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ :
+ if (sendPacketReq == 1'b1 )
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET ;
+ next_sendPacketGnt <= 1'b1 ;
+ next_muxDCEn <= 1'b0 ;
+ end
+ else if (directCntlReq == 1'b1 )
+ begin
+ NextState_SCTxArb <= `SARB_DC ;
+ next_directCntlGnt <= 1'b1 ;
+ next_muxDCEn <= 1'b1 ;
+ end
+ `SARB_SEND_PACKET :
+ if (sendPacketReq == 1'b0 )
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ ;
+ next_sendPacketGnt <= 1'b0 ;
+ end
+ `SARB_DC :
+ if (directCntlReq == 1'b0 )
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ ;
+ next_directCntlGnt <= 1'b0 ;
+ end
+ `START_SARB :
+ NextState_SCTxArb <= `SARB1_WAIT_REQ ;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : SCTxArb_CurrentState
+ if (rst )
+ CurrState_SCTxArb <= `START_SARB ;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : SCTxArb_RegOutput
+ if (rst )
+ begin
+ muxDCEn <= 1'b0 ;
+ sendPacketGnt <= 1'b0 ;
+ directCntlGnt <= 1'b0 ;
+ end
+ else
+ begin
+ muxDCEn <= next_muxDCEn ;
+ sendPacketGnt <= next_sendPacketGnt ;
+ directCntlGnt <= next_directCntlGnt ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html (revision 264)
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
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+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
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+ ]]>
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm (revision 264)
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+
+
+slaveGetpacket.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:35 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed , CRCError , RXDataIn , RXDataValid , RXFifoData , RXFifoFull , RXFifoWEn , RXOverflow , RXPacketRdy , RXStreamStatusIn , RXTimeOut , RxPID , SIERxTimeOut , bitStuffError , clk , dataSequence , getPacketEn , rst );
+input [7 :0 ] RXDataIn ;
+input RXDataValid ;
+input RXFifoFull ;
+input [7 :0 ] RXStreamStatusIn ;
+input SIERxTimeOut ; // Single cycle pulse
+input clk ;
+input getPacketEn ;
+input rst ;
+output ACKRxed ;
+output CRCError ;
+output [7 :0 ] RXFifoData ;
+output RXFifoWEn ;
+output RXOverflow ;
+output RXPacketRdy ;
+output RXTimeOut ;
+output [3 :0 ] RxPID ;
+output bitStuffError ;
+output dataSequence ;
+
+reg ACKRxed , next_ACKRxed ;
+reg CRCError , next_CRCError ;
+wire [7 :0 ] RXDataIn ;
+wire RXDataValid ;
+reg [7 :0 ] RXFifoData , next_RXFifoData ;
+wire RXFifoFull ;
+reg RXFifoWEn , next_RXFifoWEn ;
+reg RXOverflow , next_RXOverflow ;
+reg RXPacketRdy , next_RXPacketRdy ;
+wire [7 :0 ] RXStreamStatusIn ;
+reg RXTimeOut , next_RXTimeOut ;
+reg [3 :0 ] RxPID , next_RxPID ;
+wire SIERxTimeOut ;
+reg bitStuffError , next_bitStuffError ;
+wire clk ;
+reg dataSequence , next_dataSequence ;
+wire getPacketEn ;
+wire rst ;
+
+// diagram signals declarations
+reg [7 :0 ]RXByteOld , next_RXByteOld ;
+reg [7 :0 ]RXByteOldest , next_RXByteOldest ;
+reg [7 :0 ]RXByte , next_RXByte ;
+reg [7 :0 ]RXStreamStatus , next_RXStreamStatus ;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4 :0 ] CurrState_slvGetPkt ;
+reg [4 :0 ] NextState_slvGetPkt ;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt )
+begin : slvGetPkt_NextState
+ NextState_slvGetPkt <= CurrState_slvGetPkt ;
+ // Set default values for outputs and signals
+ next_CRCError <= CRCError ;
+ next_bitStuffError <= bitStuffError ;
+ next_RXOverflow <= RXOverflow ;
+ next_RXTimeOut <= RXTimeOut ;
+ next_ACKRxed <= ACKRxed ;
+ next_dataSequence <= dataSequence ;
+ next_RXByte <= RXByte ;
+ next_RXStreamStatus <= RXStreamStatus ;
+ next_RxPID <= RxPID ;
+ next_RXPacketRdy <= RXPacketRdy ;
+ next_RXByteOldest <= RXByteOldest ;
+ next_RXByteOld <= RXByteOld ;
+ next_RXFifoWEn <= RXFifoWEn ;
+ next_RXFifoData <= RXFifoData ;
+ case (CurrState_slvGetPkt ) // synopsys parallel_case full_case
+ `START_GP :
+ NextState_slvGetPkt <= `WAIT_EN ;
+ `WAIT_PKT :
+ begin
+ next_CRCError <= 1'b0 ;
+ next_bitStuffError <= 1'b0 ;
+ next_RXOverflow <= 1'b0 ;
+ next_RXTimeOut <= 1'b0 ;
+ next_ACKRxed <= 1'b0 ;
+ next_dataSequence <= 1'b0 ;
+ if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START ;
+ next_RXByte <= RXDataIn ;
+ next_RXStreamStatus <= RXStreamStatusIn ;
+ end
+ end
+ `CHK_PKT_START :
+ if (RXStreamStatus == `RX_PACKET_START )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID ;
+ next_RxPID <= RXByte [3 :0 ];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY ;
+ next_RXTimeOut <= 1'b1 ;
+ end
+ `WAIT_EN :
+ begin
+ next_RXPacketRdy <= 1'b0 ;
+ if (getPacketEn == 1'b1 )
+ NextState_slvGetPkt <= `WAIT_PKT ;
+ end
+ `PKT_RDY :
+ begin
+ next_RXPacketRdy <= 1'b1 ;
+ NextState_slvGetPkt <= `WAIT_EN ;
+ end
+ `PROC_PKT_CHK_PID :
+ if (RXByte [1 :0 ] == `HANDSHAKE )
+ NextState_slvGetPkt <= `PROC_PKT_HS ;
+ else if (RXByte [1 :0 ] == `DATA )
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1 ;
+ else
+ NextState_slvGetPkt <= `PKT_RDY ;
+ `PROC_PKT_HS :
+ if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PKT_RDY ;
+ next_RXOverflow <= RXDataIn [`RX_OVERFLOW_BIT ];
+ next_ACKRxed <= RXDataIn [`ACK_RXED_BIT ];
+ end
+ `PROC_PKT_DATA_W_D1 :
+ if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1 ;
+ next_RXByte <= RXDataIn ;
+ next_RXStreamStatus <= RXStreamStatusIn ;
+ end
+ `PROC_PKT_DATA_CHK_D1 :
+ if (RXStreamStatus == `RX_PACKET_STREAM )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2 ;
+ next_RXByteOldest <= RXByte ;
+ end
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN ;
+ `PROC_PKT_DATA_W_D2 :
+ if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2 ;
+ next_RXByte <= RXDataIn ;
+ next_RXStreamStatus <= RXStreamStatusIn ;
+ end
+ `PROC_PKT_DATA_FIN :
+ begin
+ next_CRCError <= RXByte [`CRC_ERROR_BIT ];
+ next_bitStuffError <= RXByte [`BIT_STUFF_ERROR_BIT ];
+ next_dataSequence <= RXByte [`DATA_SEQUENCE_BIT ];
+ NextState_slvGetPkt <= `PKT_RDY ;
+ end
+ `PROC_PKT_DATA_CHK_D2 :
+ if (RXStreamStatus == `RX_PACKET_STREAM )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3 ;
+ next_RXByteOld <= RXByte ;
+ end
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN ;
+ `PROC_PKT_DATA_W_D3 :
+ if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3 ;
+ next_RXByte <= RXDataIn ;
+ next_RXStreamStatus <= RXStreamStatusIn ;
+ end
+ `PROC_PKT_DATA_CHK_D3 :
+ if (RXStreamStatus == `RX_PACKET_STREAM )
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO ;
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN ;
+ `PROC_PKT_DATA_LOOP_CHK_FIFO :
+ if (RXFifoFull == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL ;
+ next_RXOverflow <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D ;
+ next_RXFifoWEn <= 1'b1 ;
+ next_RXFifoData <= RXByteOldest ;
+ next_RXByteOldest <= RXByteOld ;
+ next_RXByteOld <= RXByte ;
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL :
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D ;
+ `PROC_PKT_DATA_LOOP_W_D :
+ begin
+ next_RXFifoWEn <= 1'b0 ;
+ if ((RXDataValid == 1'b1 ) && (RXStreamStatusIn == `RX_PACKET_STREAM ))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY ;
+ next_RXByte <= RXDataIn ;
+ end
+ else if (RXDataValid == 1'b1 )
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN ;
+ next_RXByte <= RXDataIn ;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY :
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO ;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : slvGetPkt_CurrentState
+ if (rst )
+ CurrState_slvGetPkt <= `START_GP ;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : slvGetPkt_RegOutput
+ if (rst )
+ begin
+ RXByteOld <= 8'h00 ;
+ RXByteOldest <= 8'h00 ;
+ RXByte <= 8'h00 ;
+ RXStreamStatus <= 8'h00 ;
+ RXPacketRdy <= 1'b0 ;
+ RXFifoWEn <= 1'b0 ;
+ RXFifoData <= 8'h00 ;
+ CRCError <= 1'b0 ;
+ bitStuffError <= 1'b0 ;
+ RXOverflow <= 1'b0 ;
+ RXTimeOut <= 1'b0 ;
+ ACKRxed <= 1'b0 ;
+ dataSequence <= 1'b0 ;
+ RxPID <= 4'h0 ;
+ end
+ else
+ begin
+ RXByteOld <= next_RXByteOld ;
+ RXByteOldest <= next_RXByteOldest ;
+ RXByte <= next_RXByte ;
+ RXStreamStatus <= next_RXStreamStatus ;
+ RXPacketRdy <= next_RXPacketRdy ;
+ RXFifoWEn <= next_RXFifoWEn ;
+ RXFifoData <= next_RXFifoData ;
+ CRCError <= next_CRCError ;
+ bitStuffError <= next_bitStuffError ;
+ RXOverflow <= next_RXOverflow ;
+ RXTimeOut <= next_RXTimeOut ;
+ ACKRxed <= next_ACKRxed ;
+ dataSequence <= next_dataSequence ;
+ RxPID <= next_RxPID ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
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--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html (revision 264)
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+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm (revision 264)
@@ -0,0 +1,112 @@
+
+
+slaveRxStatusMonitor.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:36 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module slaveRxStatusMonitor (connectStateIn , connectStateOut , resumeDetectedIn , resetEventOut , resumeIntOut , clk , rst );
+
+input [1 :0 ] connectStateIn ;
+input resumeDetectedIn ;
+input clk ;
+input rst ;
+output resetEventOut ;
+output [1 :0 ] connectStateOut ;
+output resumeIntOut ;
+
+wire [1 :0 ] connectStateIn ;
+wire resumeDetectedIn ;
+reg resetEventOut ;
+reg [1 :0 ] connectStateOut ;
+reg resumeIntOut ;
+wire clk ;
+wire rst ;
+
+reg [1 :0 ]oldConnectState ;
+reg oldResumeDetected ;
+
+always @(connectStateIn )
+begin
+ connectStateOut <= connectStateIn ;
+end
+
+
+always @(posedge clk )
+begin
+ if (rst == 1'b1 )
+ begin
+ oldConnectState <= connectStateIn ;
+ oldResumeDetected <= resumeDetectedIn ;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn ;
+ oldResumeDetected <= resumeDetectedIn ;
+ if (oldConnectState != connectStateIn )
+ resetEventOut <= 1'b1 ;
+ else
+ resetEventOut <= 1'b0 ;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0 )
+ resumeIntOut <= 1'b1 ;
+ else
+ resumeIntOut <= 1'b0 ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm (revision 264)
@@ -0,0 +1,265 @@
+
+
+slaveSendpacket.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveSendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (PID , SCTxPortCntl , SCTxPortData , SCTxPortGnt , SCTxPortRdy , SCTxPortReq , SCTxPortWEn , clk , fifoData , fifoEmpty , fifoReadEn , rst , sendPacketRdy , sendPacketWEn );
+input [3 :0 ] PID ;
+input SCTxPortGnt ;
+input SCTxPortRdy ;
+input clk ;
+input [7 :0 ] fifoData ;
+input fifoEmpty ;
+input rst ;
+input sendPacketWEn ;
+output [7 :0 ] SCTxPortCntl ;
+output [7 :0 ] SCTxPortData ;
+output SCTxPortReq ;
+output SCTxPortWEn ;
+output fifoReadEn ;
+output sendPacketRdy ;
+
+wire [3 :0 ] PID ;
+reg [7 :0 ] SCTxPortCntl , next_SCTxPortCntl ;
+reg [7 :0 ] SCTxPortData , next_SCTxPortData ;
+wire SCTxPortGnt ;
+wire SCTxPortRdy ;
+reg SCTxPortReq , next_SCTxPortReq ;
+reg SCTxPortWEn , next_SCTxPortWEn ;
+wire clk ;
+wire [7 :0 ] fifoData ;
+wire fifoEmpty ;
+reg fifoReadEn , next_fifoReadEn ;
+wire rst ;
+reg sendPacketRdy , next_sendPacketRdy ;
+wire sendPacketWEn ;
+
+// diagram signals declarations
+reg [7 :0 ]PIDNotPID ;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3 :0 ] CurrState_slvSndPkt ;
+reg [3 :0 ] NextState_slvSndPkt ;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID )
+begin
+ PIDNotPID <= { (PID ^ 4'hf ), PID };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: slvSndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt )
+begin : slvSndPkt_NextState
+ NextState_slvSndPkt <= CurrState_slvSndPkt ;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy ;
+ next_SCTxPortReq <= SCTxPortReq ;
+ next_SCTxPortWEn <= SCTxPortWEn ;
+ next_SCTxPortData <= SCTxPortData ;
+ next_SCTxPortCntl <= SCTxPortCntl ;
+ next_fifoReadEn <= fifoReadEn ;
+ case (CurrState_slvSndPkt ) // synopsys parallel_case full_case
+ `START_SP1 :
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE ;
+ `SP_WAIT_ENABLE :
+ if (sendPacketWEn == 1'b1 )
+ begin
+ NextState_slvSndPkt <= `SP1_WAIT_GNT ;
+ next_sendPacketRdy <= 1'b0 ;
+ next_SCTxPortReq <= 1'b1 ;
+ end
+ `SP1_WAIT_GNT :
+ if (SCTxPortGnt == 1'b1 )
+ NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY ;
+ `FIN_SP1 :
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE ;
+ next_sendPacketRdy <= 1'b1 ;
+ next_SCTxPortReq <= 1'b0 ;
+ end
+ `SP_NOT_DATA :
+ NextState_slvSndPkt <= `FIN_SP1 ;
+ `SP_SEND_PID_WAIT_RDY :
+ if (SCTxPortRdy == 1'b1 )
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_FIN ;
+ next_SCTxPortWEn <= 1'b1 ;
+ next_SCTxPortData <= PIDNotPID ;
+ next_SCTxPortCntl <= `TX_PACKET_START ;
+ end
+ `SP_SEND_PID_FIN :
+ begin
+ next_SCTxPortWEn <= 1'b0 ;
+ if (PID == `DATA0 || PID == `DATA1 )
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY ;
+ else
+ NextState_slvSndPkt <= `SP_NOT_DATA ;
+ end
+ `SP_D0_D1_READ_FIFO :
+ begin
+ next_SCTxPortWEn <= 1'b1 ;
+ next_SCTxPortData <= fifoData ;
+ next_SCTxPortCntl <= `TX_PACKET_STREAM ;
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN ;
+ end
+ `SP_D0_D1_WAIT_READ_FIFO :
+ if (SCTxPortRdy == 1'b1 )
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_REN ;
+ next_fifoReadEn <= 1'b1 ;
+ end
+ `SP_D0_D1_FIFO_EMPTY :
+ if (fifoEmpty == 1'b0 )
+ NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO ;
+ else
+ NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE ;
+ `SP_D0_D1_FIN :
+ begin
+ next_SCTxPortWEn <= 1'b0 ;
+ NextState_slvSndPkt <= `FIN_SP1 ;
+ end
+ `SP_D0_D1_TERM_BYTE :
+ if (SCTxPortRdy == 1'b1 )
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIN ;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_SCTxPortWEn <= 1'b1 ;
+ next_SCTxPortData <= 8'h00 ;
+ next_SCTxPortCntl <= `TX_PACKET_STOP ;
+ end
+ `SP_D0_D1_CLR_WEN :
+ begin
+ next_SCTxPortWEn <= 1'b0 ;
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY ;
+ end
+ `SP_D0_D1_CLR_REN :
+ begin
+ next_fifoReadEn <= 1'b0 ;
+ NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : slvSndPkt_CurrentState
+ if (rst )
+ CurrState_slvSndPkt <= `START_SP1 ;
+ else
+ CurrState_slvSndPkt <= NextState_slvSndPkt ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : slvSndPkt_RegOutput
+ if (rst )
+ begin
+ sendPacketRdy <= 1'b1 ;
+ SCTxPortReq <= 1'b0 ;
+ SCTxPortWEn <= 1'b0 ;
+ SCTxPortData <= 8'h00 ;
+ SCTxPortCntl <= 8'h00 ;
+ fifoReadEn <= 1'b0 ;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy ;
+ SCTxPortReq <= next_SCTxPortReq ;
+ SCTxPortWEn <= next_SCTxPortWEn ;
+ SCTxPortData <= next_SCTxPortData ;
+ SCTxPortCntl <= next_SCTxPortCntl ;
+ fifoReadEn <= next_fifoReadEn ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html (revision 264)
@@ -0,0 +1,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
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Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html (revision 264)
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html (revision 264)
@@ -0,0 +1,51 @@
+
+
+
+
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+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html (revision 264)
@@ -0,0 +1,70 @@
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html (revision 264)
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+
+
+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html (revision 264)
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html (revision 264)
@@ -0,0 +1,70 @@
+
+
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+
+
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+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
___________________________________________________________________
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+*
\ No newline at end of property
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html (revision 264)
@@ -0,0 +1,57 @@
+
+
+
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+
+
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+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html (revision 264)
@@ -0,0 +1,45 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
___________________________________________________________________
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm (revision 264)
@@ -0,0 +1,210 @@
+
+
+slaveDirectcontrol.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:26 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl , SCTxPortData , SCTxPortGnt , SCTxPortRdy , SCTxPortReq , SCTxPortWEn , clk , directControlEn , directControlLineState , rst );
+input SCTxPortGnt ;
+input SCTxPortRdy ;
+input clk ;
+input directControlEn ;
+input [1 :0 ] directControlLineState ;
+input rst ;
+output [7 :0 ] SCTxPortCntl ;
+output [7 :0 ] SCTxPortData ;
+output SCTxPortReq ;
+output SCTxPortWEn ;
+
+reg [7 :0 ] SCTxPortCntl , next_SCTxPortCntl ;
+reg [7 :0 ] SCTxPortData , next_SCTxPortData ;
+wire SCTxPortGnt ;
+wire SCTxPortRdy ;
+reg SCTxPortReq , next_SCTxPortReq ;
+reg SCTxPortWEn , next_SCTxPortWEn ;
+wire clk ;
+wire directControlEn ;
+wire [1 :0 ] directControlLineState ;
+wire rst ;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2 :0 ] CurrState_slvDrctCntl ;
+reg [2 :0 ] NextState_slvDrctCntl ;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl )
+begin : slvDrctCntl_NextState
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl ;
+ // Set default values for outputs and signals
+ next_SCTxPortReq <= SCTxPortReq ;
+ next_SCTxPortWEn <= SCTxPortWEn ;
+ next_SCTxPortData <= SCTxPortData ;
+ next_SCTxPortCntl <= SCTxPortCntl ;
+ case (CurrState_slvDrctCntl ) // synopsys parallel_case full_case
+ `START_SDC :
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL ;
+ `CHK_DRCT_CNTL :
+ if (directControlEn == 1'b1 )
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT ;
+ next_SCTxPortReq <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT ;
+ next_SCTxPortReq <= 1'b1 ;
+ end
+ `DRCT_CNTL_WAIT_GNT :
+ if (SCTxPortGnt == 1'b1 )
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY ;
+ `DRCT_CNTL_CHK_LOOP :
+ begin
+ next_SCTxPortWEn <= 1'b0 ;
+ if (directControlEn == 1'b0 )
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL ;
+ next_SCTxPortReq <= 1'b0 ;
+ end
+ else
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY ;
+ end
+ `DRCT_CNTL_WAIT_RDY :
+ if (SCTxPortRdy == 1'b1 )
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP ;
+ next_SCTxPortWEn <= 1'b1 ;
+ next_SCTxPortData <= {6'b000000 , directControlLineState };
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL ;
+ end
+ `IDLE_FIN :
+ begin
+ next_SCTxPortWEn <= 1'b0 ;
+ next_SCTxPortReq <= 1'b0 ;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL ;
+ end
+ `IDLE_WAIT_GNT :
+ if (SCTxPortGnt == 1'b1 )
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY ;
+ `IDLE_WAIT_RDY :
+ if (SCTxPortRdy == 1'b1 )
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN ;
+ next_SCTxPortWEn <= 1'b1 ;
+ next_SCTxPortData <= 8'h00 ;
+ next_SCTxPortCntl <= `TX_IDLE ;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : slvDrctCntl_CurrentState
+ if (rst )
+ CurrState_slvDrctCntl <= `START_SDC ;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : slvDrctCntl_RegOutput
+ if (rst )
+ begin
+ SCTxPortCntl <= 8'h00 ;
+ SCTxPortData <= 8'h00 ;
+ SCTxPortWEn <= 1'b0 ;
+ SCTxPortReq <= 1'b0 ;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl ;
+ SCTxPortData <= next_SCTxPortData ;
+ SCTxPortWEn <= next_SCTxPortWEn ;
+ SCTxPortReq <= next_SCTxPortReq ;
+ end
+end
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html (revision 264)
@@ -0,0 +1,45 @@
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+
+
+
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+
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+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html (revision 264)
@@ -0,0 +1,70 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html (revision 264)
@@ -0,0 +1,45 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html (revision 264)
@@ -0,0 +1,70 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html (revision 264)
@@ -0,0 +1,45 @@
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+
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html (revision 264)
@@ -0,0 +1,70 @@
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm (revision 264)
@@ -0,0 +1,31 @@
+
+
+
+
+ <![CDATA[
+ <body>
+ <p>This page uses frames, but your browser doesn't support them. <br></p>
+ </body>
+ ]]>
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm (revision 264)
@@ -0,0 +1,449 @@
+
+
+slavecontroller.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/????/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:21 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+`timescale 1 ns / 1 ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError , NAKSent , RxByte , RxDataWEn , RxOverflow , RxStatus , RxTimeOut , SCGlobalEn , SOFRxed , USBEndPControlReg , USBEndPNakTransTypeReg , USBEndPTransTypeReg , USBEndP , USBTgtAddress , bitStuffError , clk , clrEPRdy , endPMuxErrorsWEn , frameNum , getPacketREn , getPacketRdy , rst , sendPacketPID , sendPacketRdy , sendPacketWEn , stallSent , transDone );
+input CRCError ;
+input [7 :0 ] RxByte ;
+input RxDataWEn ;
+input RxOverflow ;
+input [7 :0 ] RxStatus ;
+input RxTimeOut ;
+input SCGlobalEn ;
+input [3 :0 ] USBEndPControlReg ;
+input [6 :0 ] USBTgtAddress ;
+input bitStuffError ;
+input clk ;
+input getPacketRdy ;
+input rst ;
+input sendPacketRdy ;
+output NAKSent ;
+output SOFRxed ;
+output [1 :0 ] USBEndPNakTransTypeReg ;
+output [1 :0 ] USBEndPTransTypeReg ;
+output [3 :0 ] USBEndP ;
+output clrEPRdy ;
+output endPMuxErrorsWEn ;
+output [10 :0 ] frameNum ;
+output getPacketREn ;
+output [3 :0 ] sendPacketPID ;
+output sendPacketWEn ;
+output stallSent ;
+output transDone ;
+
+wire CRCError ;
+reg NAKSent , next_NAKSent ;
+wire [7 :0 ] RxByte ;
+wire RxDataWEn ;
+wire RxOverflow ;
+wire [7 :0 ] RxStatus ;
+wire RxTimeOut ;
+wire SCGlobalEn ;
+reg SOFRxed , next_SOFRxed ;
+wire [3 :0 ] USBEndPControlReg ;
+reg [1 :0 ] USBEndPNakTransTypeReg , next_USBEndPNakTransTypeReg ;
+reg [1 :0 ] USBEndPTransTypeReg , next_USBEndPTransTypeReg ;
+reg [3 :0 ] USBEndP , next_USBEndP ;
+wire [6 :0 ] USBTgtAddress ;
+wire bitStuffError ;
+wire clk ;
+reg clrEPRdy , next_clrEPRdy ;
+reg endPMuxErrorsWEn , next_endPMuxErrorsWEn ;
+reg [10 :0 ] frameNum , next_frameNum ;
+reg getPacketREn , next_getPacketREn ;
+wire getPacketRdy ;
+wire rst ;
+reg [3 :0 ] sendPacketPID , next_sendPacketPID ;
+wire sendPacketRdy ;
+reg sendPacketWEn , next_sendPacketWEn ;
+reg stallSent , next_stallSent ;
+reg transDone , next_transDone ;
+
+// diagram signals declarations
+reg [7 :0 ]PIDByte , next_PIDByte ;
+reg [6 :0 ]USBAddress , next_USBAddress ;
+reg [7 :0 ]addrEndPTemp , next_addrEndPTemp ;
+reg [7 :0 ]endpCRCTemp , next_endpCRCTemp ;
+reg [1 :0 ]tempUSBEndPTransTypeReg , next_tempUSBEndPTransTypeReg ;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4 :0 ] CurrState_slvCntrl ;
+reg [4 :0 ] NextState_slvCntrl ;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or RxDataWEn or RxStatus or PIDByte or USBEndPControlReg or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or frameNum or CurrState_slvCntrl )
+begin : slvCntrl_NextState
+ NextState_slvCntrl <= CurrState_slvCntrl ;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent ;
+ next_NAKSent <= NAKSent ;
+ next_SOFRxed <= SOFRxed ;
+ next_PIDByte <= PIDByte ;
+ next_transDone <= transDone ;
+ next_clrEPRdy <= clrEPRdy ;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn ;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg ;
+ next_getPacketREn <= getPacketREn ;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg ;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg ;
+ next_sendPacketWEn <= sendPacketWEn ;
+ next_sendPacketPID <= sendPacketPID ;
+ next_endpCRCTemp <= endpCRCTemp ;
+ next_addrEndPTemp <= addrEndPTemp ;
+ next_frameNum <= frameNum ;
+ next_USBAddress <= USBAddress ;
+ next_USBEndP <= USBEndP ;
+ case (CurrState_slvCntrl ) // synopsys parallel_case full_case
+ `WAIT_RX1 :
+ begin
+ next_stallSent <= 1'b0 ;
+ next_NAKSent <= 1'b0 ;
+ next_SOFRxed <= 1'b0 ;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte [1 :0 ] == `TOKEN )
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR ;
+ next_PIDByte <= RxByte ;
+ end
+ end
+ `FIN_SC :
+ begin
+ next_transDone <= 1'b0 ;
+ next_clrEPRdy <= 1'b0 ;
+ next_endPMuxErrorsWEn <= 1'b0 ;
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ end
+ `CHK_PID :
+ if (PIDByte [3 :0 ] == `SETUP )
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT ;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS ;
+ next_getPacketREn <= 1'b1 ;
+ end
+ else if (PIDByte [3 :0 ] == `OUT )
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT ;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS ;
+ next_getPacketREn <= 1'b1 ;
+ end
+ else if (PIDByte [3 :0 ] == `IN )
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY ;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS ;
+ end
+ else
+ NextState_slvCntrl <= `PID_ERROR ;
+ `PID_ERROR :
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ `CHK_RDY :
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT ] == 1'b1 )
+ begin
+ NextState_slvCntrl <= `FIN_SC ;
+ next_transDone <= 1'b1 ;
+ next_clrEPRdy <= 1'b1 ;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg ;
+ next_endPMuxErrorsWEn <= 1'b1 ;
+ end
+ else if (NAKSent == 1'b1 )
+ begin
+ NextState_slvCntrl <= `FIN_SC ;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg ;
+ next_endPMuxErrorsWEn <= 1'b1 ;
+ end
+ else
+ NextState_slvCntrl <= `FIN_SC ;
+ `SETUP_OUT_CHK :
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT ] == 1'b0 )
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `NAK ;
+ next_NAKSent <= 1'b1 ;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT ] == 1'b1 )
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `STALL ;
+ next_stallSent <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `ACK ;
+ end
+ `SETUP_OUT_SEND :
+ begin
+ next_sendPacketWEn <= 1'b0 ;
+ if (sendPacketRdy == 1'b1 )
+ NextState_slvCntrl <= `CHK_RDY ;
+ end
+ `SETUP_OUT_GET_PKT :
+ begin
+ next_getPacketREn <= 1'b0 ;
+ if ((getPacketRdy == 1'b1 ) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0 ))
+ NextState_slvCntrl <= `SETUP_OUT_CHK ;
+ else if (getPacketRdy == 1'b1 )
+ NextState_slvCntrl <= `CHK_RDY ;
+ end
+ `IN_NAK_STALL :
+ begin
+ next_sendPacketWEn <= 1'b0 ;
+ if (sendPacketRdy == 1'b1 )
+ NextState_slvCntrl <= `CHK_RDY ;
+ end
+ `IN_CHK_RDY :
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT ] == 1'b0 )
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `NAK ;
+ next_NAKSent <= 1'b1 ;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT ] == 1'b1 )
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `STALL ;
+ next_stallSent <= 1'b1 ;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT ] == 1'b0 )
+ begin
+ NextState_slvCntrl <= `IN_DATA ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `DATA0 ;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_DATA ;
+ next_sendPacketWEn <= 1'b1 ;
+ next_sendPacketPID <= `DATA1 ;
+ end
+ `IN_DATA :
+ begin
+ next_sendPacketWEn <= 1'b0 ;
+ if (sendPacketRdy == 1'b1 )
+ begin
+ NextState_slvCntrl <= `IN_GET_RESP ;
+ next_getPacketREn <= 1'b1 ;
+ end
+ end
+ `IN_GET_RESP :
+ begin
+ next_getPacketREn <= 1'b0 ;
+ if (getPacketRdy == 1'b1 )
+ NextState_slvCntrl <= `CHK_RDY ;
+ end
+ `START_S1 :
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ `GET_TOKEN_WAIT_CRC :
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM )
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP ;
+ next_endpCRCTemp <= RxByte ;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM )
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ `GET_TOKEN_WAIT_ADDR :
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM )
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC ;
+ next_addrEndPTemp <= RxByte ;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM )
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ `GET_TOKEN_WAIT_STOP :
+ if ((RxDataWEn == 1'b1 ) && (RxByte [`CRC_ERROR_BIT ] == 1'b0 &&
+ RxByte [`BIT_STUFF_ERROR_BIT ] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT ] == 1'b0 ))
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF ;
+ else if (RxDataWEn == 1'b1 )
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ `GET_TOKEN_CHK_SOF :
+ if (PIDByte [3 :0 ] == `SOF )
+ begin
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ next_frameNum <= {endpCRCTemp [2 :0 ],addrEndPTemp };
+ next_SOFRxed <= 1'b1 ;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY ;
+ next_USBAddress <= addrEndPTemp [6 :0 ];
+ next_USBEndP <= { endpCRCTemp [2 :0 ], addrEndPTemp [7 ]};
+ end
+ `GET_TOKEN_DELAY : // Insert delay to allow USBEndPControlReg to update
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR ;
+ `GET_TOKEN_CHK_ADDR :
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg [`ENDPOINT_ENABLE_BIT ] == 1'b1 )
+ NextState_slvCntrl <= `CHK_PID ;
+ else
+ NextState_slvCntrl <= `WAIT_RX1 ;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk )
+begin : slvCntrl_CurrentState
+ if (rst )
+ CurrState_slvCntrl <= `START_S1 ;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl ;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk )
+begin : slvCntrl_RegOutput
+ if (rst )
+ begin
+ tempUSBEndPTransTypeReg <= 2'b00 ;
+ addrEndPTemp <= 8'h00 ;
+ endpCRCTemp <= 8'h00 ;
+ USBAddress <= 7'b0000000 ;
+ PIDByte <= 8'h00 ;
+ transDone <= 1'b0 ;
+ getPacketREn <= 1'b0 ;
+ sendPacketPID <= 4'b0 ;
+ sendPacketWEn <= 1'b0 ;
+ clrEPRdy <= 1'b0 ;
+ USBEndPTransTypeReg <= 2'b00 ;
+ USBEndPNakTransTypeReg <= 2'b00 ;
+ NAKSent <= 1'b0 ;
+ stallSent <= 1'b0 ;
+ SOFRxed <= 1'b0 ;
+ endPMuxErrorsWEn <= 1'b0 ;
+ frameNum <= 11'b00000000000 ;
+ USBEndP <= 4'h0 ;
+ end
+ else
+ begin
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg ;
+ addrEndPTemp <= next_addrEndPTemp ;
+ endpCRCTemp <= next_endpCRCTemp ;
+ USBAddress <= next_USBAddress ;
+ PIDByte <= next_PIDByte ;
+ transDone <= next_transDone ;
+ getPacketREn <= next_getPacketREn ;
+ sendPacketPID <= next_sendPacketPID ;
+ sendPacketWEn <= next_sendPacketWEn ;
+ clrEPRdy <= next_clrEPRdy ;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg ;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg ;
+ NAKSent <= next_NAKSent ;
+ stallSent <= next_stallSent ;
+ SOFRxed <= next_SOFRxed ;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn ;
+ frameNum <= next_frameNum ;
+ USBEndP <= next_USBEndP ;
+ end
+end
+
+endmodule
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+usbSlaveControl.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:42 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSlaveControl (
+ clk , rst ,
+ //getPacket
+ RxByteStatus , RxData , RxDataValid ,
+ SIERxTimeOut , RxFifoData ,
+ //speedCtrlMux
+ fullSpeedRate , fullSpeedPol ,
+ //SCTxPortArbiter
+ SCTxPortEn , SCTxPortRdy ,
+ SCTxPortData , SCTxPortCtrl ,
+ //rxStatusMonitor
+ connectStateIn ,
+ resumeDetectedIn ,
+ //USBHostControlBI
+ busAddress ,
+ busDataIn ,
+ busDataOut ,
+ busWriteEn ,
+ busStrobe_i ,
+ SOFRxedIntOut ,
+ resetEventIntOut ,
+ resumeIntOut ,
+ transDoneIntOut ,
+ NAKSentIntOut ,
+ slaveControlSelect ,
+ //fifoMux
+ TxFifoEP0REn ,
+ TxFifoEP1REn ,
+ TxFifoEP2REn ,
+ TxFifoEP3REn ,
+ TxFifoEP0Data ,
+ TxFifoEP1Data ,
+ TxFifoEP2Data ,
+ TxFifoEP3Data ,
+ TxFifoEP0Empty ,
+ TxFifoEP1Empty ,
+ TxFifoEP2Empty ,
+ TxFifoEP3Empty ,
+ RxFifoEP0WEn ,
+ RxFifoEP1WEn ,
+ RxFifoEP2WEn ,
+ RxFifoEP3WEn ,
+ RxFifoEP0Full ,
+ RxFifoEP1Full ,
+ RxFifoEP2Full ,
+ RxFifoEP3Full
+ );
+
+input clk , rst ;
+//getPacket
+input [7 :0 ] RxByteStatus ;
+input [7 :0 ] RxData ;
+input RxDataValid ;
+input SIERxTimeOut ;
+output [7 :0 ] RxFifoData ;
+//speedCtrlMux
+output fullSpeedRate ;
+output fullSpeedPol ;
+//HCTxPortArbiter
+output SCTxPortEn ;
+input SCTxPortRdy ;
+output [7 :0 ] SCTxPortData ;
+output [7 :0 ] SCTxPortCtrl ;
+//rxStatusMonitor
+input [1 :0 ] connectStateIn ;
+input resumeDetectedIn ;
+//USBHostControlBI
+input [4 :0 ] busAddress ;
+input [7 :0 ] busDataIn ;
+output [7 :0 ] busDataOut ;
+input busWriteEn ;
+input busStrobe_i ;
+output SOFRxedIntOut ;
+output resetEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+output NAKSentIntOut ;
+input slaveControlSelect ;
+//fifoMux
+output TxFifoEP0REn ;
+output TxFifoEP1REn ;
+output TxFifoEP2REn ;
+output TxFifoEP3REn ;
+input [7 :0 ] TxFifoEP0Data ;
+input [7 :0 ] TxFifoEP1Data ;
+input [7 :0 ] TxFifoEP2Data ;
+input [7 :0 ] TxFifoEP3Data ;
+input TxFifoEP0Empty ;
+input TxFifoEP1Empty ;
+input TxFifoEP2Empty ;
+input TxFifoEP3Empty ;
+output RxFifoEP0WEn ;
+output RxFifoEP1WEn ;
+output RxFifoEP2WEn ;
+output RxFifoEP3WEn ;
+input RxFifoEP0Full ;
+input RxFifoEP1Full ;
+input RxFifoEP2Full ;
+input RxFifoEP3Full ;
+
+wire clk ;
+wire rst ;
+wire [7 :0 ] RxByteStatus ;
+wire [7 :0 ] RxData ;
+wire RxDataValid ;
+wire SIERxTimeOut ;
+wire [7 :0 ] RxFifoData ;
+wire fullSpeedRate ;
+wire fullSpeedPol ;
+wire [7 :0 ] SCTxPortData ;
+wire [7 :0 ] SCTxPortCtrl ;
+wire [1 :0 ] connectStateIn ;
+wire resumeDetectedIn ;
+wire [4 :0 ] busAddress ;
+wire [7 :0 ] busDataIn ;
+wire [7 :0 ] busDataOut ;
+wire busWriteEn ;
+wire busStrobe_i ;
+wire SOFRxedIntOut ;
+wire resetEventIntOut ;
+wire resumeIntOut ;
+wire transDoneIntOut ;
+wire NAKSentIntOut ;
+wire slaveControlSelect ;
+wire TxFifoEP0REn ;
+wire TxFifoEP1REn ;
+wire TxFifoEP2REn ;
+wire TxFifoEP3REn ;
+wire [7 :0 ] TxFifoEP0Data ;
+wire [7 :0 ] TxFifoEP1Data ;
+wire [7 :0 ] TxFifoEP2Data ;
+wire [7 :0 ] TxFifoEP3Data ;
+wire TxFifoEP0Empty ;
+wire TxFifoEP1Empty ;
+wire TxFifoEP2Empty ;
+wire TxFifoEP3Empty ;
+wire RxFifoEP0WEn ;
+wire RxFifoEP1WEn ;
+wire RxFifoEP2WEn ;
+wire RxFifoEP3WEn ;
+wire RxFifoEP0Full ;
+wire RxFifoEP1Full ;
+wire RxFifoEP2Full ;
+wire RxFifoEP3Full ;
+
+//internal wiring
+wire [7 :0 ] directCntlCntl ;
+wire [7 :0 ] directCntlData ;
+wire directCntlGnt ;
+wire directCntlReq ;
+wire directCntlWEn ;
+wire [7 :0 ] sendPacketCntl ;
+wire [7 :0 ] sendPacketData ;
+wire sendPacketGnt ;
+wire sendPacketReq ;
+wire sendPacketWEn ;
+wire SCTxPortArbRdyOut ;
+wire transDone ;
+wire [1 :0 ] directLineState ;
+wire directLineCtrlEn ;
+wire [3 :0 ] RxPID ;
+wire [1 :0 ] connectStateOut ;
+wire resumeIntFromRxStatusMon ;
+wire [1 :0 ] endP0TransTypeReg ;
+wire [1 :0 ] endP1TransTypeReg ;
+wire [1 :0 ] endP2TransTypeReg ;
+wire [1 :0 ] endP3TransTypeReg ;
+wire [1 :0 ] endP0NAKTransTypeReg ;
+wire [1 :0 ] endP1NAKTransTypeReg ;
+wire [1 :0 ] endP2NAKTransTypeReg ;
+wire [1 :0 ] endP3NAKTransTypeReg ;
+wire [3 :0 ] endP0ControlReg ;
+wire [3 :0 ] endP1ControlReg ;
+wire [3 :0 ] endP2ControlReg ;
+wire [3 :0 ] endP3ControlReg ;
+wire [7 :0 ] endP0StatusReg ;
+wire [7 :0 ] endP1StatusReg ;
+wire [7 :0 ] endP2StatusReg ;
+wire [7 :0 ] endP3StatusReg ;
+wire [6 :0 ] USBTgtAddress ;
+wire [10 :0 ] frameNum ;
+wire clrEP0Rdy ;
+wire clrEP1Rdy ;
+wire clrEP2Rdy ;
+wire clrEP3Rdy ;
+wire SCGlobalEn ;
+wire ACKRxed ;
+wire CRCError ;
+wire RXOverflow ;
+wire RXTimeOut ;
+wire bitStuffError ;
+wire dataSequence ;
+wire stallSent ;
+wire NAKSent ;
+wire SOFRxed ;
+wire [3 :0 ] endPControlReg ;
+wire [1 :0 ] transTypeNAK ;
+wire [1 :0 ] transType ;
+wire [3 :0 ] currEndP ;
+wire getPacketREn ;
+wire getPacketRdy ;
+wire [3 :0 ] slaveControllerPIDOut ;
+wire slaveControllerReadyIn ;
+wire slaveControllerWEnOut ;
+wire TxFifoRE ;
+wire [7 :0 ] TxFifoData ;
+wire TxFifoEmpty ;
+wire RxFifoWE ;
+wire RxFifoFull ;
+wire resetEventFromRxStatusMon ;
+wire clrEPRdy ;
+wire endPMuxErrorsWEn ;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address (busAddress ),
+ .dataIn (busDataIn ),
+ .dataOut (busDataOut ),
+ .writeEn (busWriteEn ),
+ .strobe_i (busStrobe_i ),
+ .clk (clk ),
+ .rst (rst ),
+ .SOFRxedIntOut (SOFRxedIntOut ),
+ .resetEventIntOut (resetEventIntOut ),
+ .resumeIntOut (resumeIntOut ),
+ .transDoneIntOut (transDoneIntOut ),
+ .NAKSentIntOut (NAKSentIntOut ),
+ .endP0TransTypeReg (endP0TransTypeReg ),
+ .endP0NAKTransTypeReg (endP0NAKTransTypeReg ),
+ .endP1TransTypeReg (endP1TransTypeReg ),
+ .endP1NAKTransTypeReg (endP1NAKTransTypeReg ),
+ .endP2TransTypeReg (endP2TransTypeReg ),
+ .endP2NAKTransTypeReg (endP2NAKTransTypeReg ),
+ .endP3TransTypeReg (endP3TransTypeReg ),
+ .endP3NAKTransTypeReg (endP3NAKTransTypeReg ),
+ .endP0ControlReg (endP0ControlReg ),
+ .endP1ControlReg (endP1ControlReg ),
+ .endP2ControlReg (endP2ControlReg ),
+ .endP3ControlReg (endP3ControlReg ),
+ .EP0StatusReg (endP0StatusReg ),
+ .EP1StatusReg (endP1StatusReg ),
+ .EP2StatusReg (endP2StatusReg ),
+ .EP3StatusReg (endP3StatusReg ),
+ .SCAddrReg (USBTgtAddress ),
+ .frameNum (frameNum ),
+ .connectStateIn (connectStateOut ),
+ .SOFRxedIn (SOFRxed ),
+ .resetEventIn (resetEventFromRxStatusMon ),
+ .resumeIntIn (resumeIntFromRxStatusMon ),
+ .transDoneIn (transDone ),
+ .NAKSentIn (NAKSent ),
+ .slaveControlSelect (slaveControlSelect ),
+ .clrEP0Ready (clrEP0Rdy ),
+ .clrEP1Ready (clrEP1Rdy ),
+ .clrEP2Ready (clrEP2Rdy ),
+ .clrEP3Ready (clrEP3Rdy ),
+ .TxLineState (directLineState ),
+ .LineDirectControlEn (directLineCtrlEn ),
+ .fullSpeedPol (fullSpeedPol ),
+ .fullSpeedRate (fullSpeedRate ),
+ .SCGlobalEn (SCGlobalEn )
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError (CRCError ),
+ .NAKSent (NAKSent ),
+ .RxByte (RxData ),
+ .RxDataWEn (RxDataValid ),
+ .RxOverflow (RXOverflow ),
+ .RxStatus (RxByteStatus ),
+ .RxTimeOut (RXTimeOut ),
+ .SCGlobalEn (SCGlobalEn ),
+ .SOFRxed (SOFRxed ),
+ .USBEndPControlReg (endPControlReg ),
+ .USBEndPNakTransTypeReg (transTypeNAK ),
+ .USBEndPTransTypeReg (transType ),
+ .USBEndP (currEndP ),
+ .USBTgtAddress (USBTgtAddress ),
+ .bitStuffError (bitStuffError ),
+ .clk (clk ),
+ .clrEPRdy (clrEPRdy ),
+ .endPMuxErrorsWEn (endPMuxErrorsWEn ),
+ .frameNum (frameNum ),
+ .getPacketREn (getPacketREn ),
+ .getPacketRdy (getPacketRdy ),
+ .rst (rst ),
+ .sendPacketPID (slaveControllerPIDOut ),
+ .sendPacketRdy (slaveControllerReadyIn ),
+ .sendPacketWEn (slaveControllerWEnOut ),
+ .stallSent (stallSent ),
+ .transDone (transDone )
+ );
+
+
+endpMux u_endpMux (
+ .clk (clk ),
+ .rst (rst ),
+ .currEndP (currEndP ),
+ .NAKSent (NAKSent ),
+ .stallSent (stallSent ),
+ .CRCError (CRCError ),
+ .bitStuffError (bitStuffError ),
+ .RxOverflow (RXOverflow ),
+ .RxTimeOut (RXTimeOut ),
+ .dataSequence (dataSequence ),
+ .ACKRxed (ACKRxed ),
+ .transType (transType ),
+ .transTypeNAK (transTypeNAK ),
+ .endPControlReg (endPControlReg ),
+ .clrEPRdy (clrEPRdy ),
+ .endPMuxErrorsWEn (endPMuxErrorsWEn ),
+ .endP0ControlReg (endP0ControlReg ),
+ .endP1ControlReg (endP1ControlReg ),
+ .endP2ControlReg (endP2ControlReg ),
+ .endP3ControlReg (endP3ControlReg ),
+ .endP0StatusReg (endP0StatusReg ),
+ .endP1StatusReg (endP1StatusReg ),
+ .endP2StatusReg (endP2StatusReg ),
+ .endP3StatusReg (endP3StatusReg ),
+ .endP0TransTypeReg (endP0TransTypeReg ),
+ .endP1TransTypeReg (endP1TransTypeReg ),
+ .endP2TransTypeReg (endP2TransTypeReg ),
+ .endP3TransTypeReg (endP3TransTypeReg ),
+ .endP0NAKTransTypeReg (endP0NAKTransTypeReg ),
+ .endP1NAKTransTypeReg (endP1NAKTransTypeReg ),
+ .endP2NAKTransTypeReg (endP2NAKTransTypeReg ),
+ .endP3NAKTransTypeReg (endP3NAKTransTypeReg ),
+ .clrEP0Rdy (clrEP0Rdy ),
+ .clrEP1Rdy (clrEP1Rdy ),
+ .clrEP2Rdy (clrEP2Rdy ),
+ .clrEP3Rdy (clrEP3Rdy )
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID (slaveControllerPIDOut ),
+ .SCTxPortCntl (sendPacketCntl ),
+ .SCTxPortData (sendPacketData ),
+ .SCTxPortGnt (sendPacketGnt ),
+ .SCTxPortRdy (SCTxPortArbRdyOut ),
+ .SCTxPortReq (sendPacketReq ),
+ .SCTxPortWEn (sendPacketWEn ),
+ .clk (clk ),
+ .fifoData (TxFifoData ),
+ .fifoEmpty (TxFifoEmpty ),
+ .fifoReadEn (TxFifoRE ),
+ .rst (rst ),
+ .sendPacketRdy (slaveControllerReadyIn ),
+ .sendPacketWEn (slaveControllerWEnOut ) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl (directCntlCntl ),
+ .SCTxPortData (directCntlData ),
+ .SCTxPortGnt (directCntlGnt ),
+ .SCTxPortRdy (SCTxPortArbRdyOut ),
+ .SCTxPortReq (directCntlReq ),
+ .SCTxPortWEn (directCntlWEn ),
+ .clk (clk ),
+ .directControlEn (directLineCtrlEn ),
+ .directControlLineState (directLineState ),
+ .rst (rst ) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl (SCTxPortCtrl ),
+ .SCTxPortData (SCTxPortData ),
+ .SCTxPortRdyIn (SCTxPortRdy ),
+ .SCTxPortRdyOut (SCTxPortArbRdyOut ),
+ .SCTxPortWEnable (SCTxPortEn ),
+ .clk (clk ),
+ .directCntlCntl (directCntlCntl ),
+ .directCntlData (directCntlData ),
+ .directCntlGnt (directCntlGnt ),
+ .directCntlReq (directCntlReq ),
+ .directCntlWEn (directCntlWEn ),
+ .rst (rst ),
+ .sendPacketCntl (sendPacketCntl ),
+ .sendPacketData (sendPacketData ),
+ .sendPacketGnt (sendPacketGnt ),
+ .sendPacketReq (sendPacketReq ),
+ .sendPacketWEn (sendPacketWEn ) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed (ACKRxed ),
+ .CRCError (CRCError ),
+ .RXDataIn (RxData ),
+ .RXDataValid (RxDataValid ),
+ .RXFifoData (RxFifoData ),
+ .RXFifoFull (RxFifoFull ),
+ .RXFifoWEn (RxFifoWE ),
+ .RXPacketRdy (getPacketRdy ),
+ .RXStreamStatusIn (RxByteStatus ),
+ .RxPID (RxPID ),
+ .SIERxTimeOut (SIERxTimeOut ),
+ .clk (clk ),
+ .RXOverflow (RXOverflow ),
+ .RXTimeOut (RXTimeOut ),
+ .bitStuffError (bitStuffError ),
+ .dataSequence (dataSequence ),
+ .getPacketEn (getPacketREn ),
+ .rst (rst ) );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn (connectStateIn ),
+ .connectStateOut (connectStateOut ),
+ .resumeDetectedIn (resumeDetectedIn ),
+ .resetEventOut (resetEventFromRxStatusMon ),
+ .resumeIntOut (resumeIntFromRxStatusMon ),
+ .clk (clk ),
+ .rst (rst ) );
+
+fifoMux u_fifoMux (
+ .currEndP (currEndP ),
+ //TxFifo
+ .TxFifoREn (TxFifoRE ),
+ .TxFifoEP0REn (TxFifoEP0REn ),
+ .TxFifoEP1REn (TxFifoEP1REn ),
+ .TxFifoEP2REn (TxFifoEP2REn ),
+ .TxFifoEP3REn (TxFifoEP3REn ),
+ .TxFifoData (TxFifoData ),
+ .TxFifoEP0Data (TxFifoEP0Data ),
+ .TxFifoEP1Data (TxFifoEP1Data ),
+ .TxFifoEP2Data (TxFifoEP2Data ),
+ .TxFifoEP3Data (TxFifoEP3Data ),
+ .TxFifoEmpty (TxFifoEmpty ),
+ .TxFifoEP0Empty (TxFifoEP0Empty ),
+ .TxFifoEP1Empty (TxFifoEP1Empty ),
+ .TxFifoEP2Empty (TxFifoEP2Empty ),
+ .TxFifoEP3Empty (TxFifoEP3Empty ),
+ //RxFifo
+ .RxFifoWEn (RxFifoWE ),
+ .RxFifoEP0WEn (RxFifoEP0WEn ),
+ .RxFifoEP1WEn (RxFifoEP1WEn ),
+ .RxFifoEP2WEn (RxFifoEP2WEn ),
+ .RxFifoEP3WEn (RxFifoEP3WEn ),
+ .RxFifoFull (RxFifoFull ),
+ .RxFifoEP0Full (RxFifoEP0Full ),
+ .RxFifoEP1Full (RxFifoEP1Full ),
+ .RxFifoEP2Full (RxFifoEP2Full ),
+ .RxFifoEP3Full (RxFifoEP3Full )
+ );
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/usbSlaveControl.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js (revision 264)
@@ -0,0 +1,461 @@
+
+var zoo = 100;
+var pzoo = 100;
+var zoom_inc = 2; //or 50
+var SCHEM = "DIAGRAM"
+var ViewX=w;
+var ViewY=h;
+var DEBUG_MODE = 1;
+//----------------------------------------------------------------------------
+IRoot = RootProject + "images/fsm/";
+OV = "over.gif";
+OD = "down.gif";
+//----------------------------------------------------------------------------
+function CodeView(){
+window.parent.location = SchemCode;
+}
+//----------------------------------------------------------------------------
+function GotoPage(){
+ if(PageNext==-1){
+ alert("no page");
+ return;
+ }
+window.parent.location = "./content"+PageNext+".html"
+}
+//----------------------------------------------------------------------------
+function fubclick(lnk){
+ if(lnk!="")
+ window.parent.location = lnk;
+}
+//----------------------------------------------------------------------------
+function DUMP() {
+ var dump_msg;
+ dump_msg= "w.........."+w+"\n";
+ dump_msg+="h.........."+h+"\n";
+ dump_msg+="zoo........"+zoo+"\n";
+ dump_msg+="pzoo......."+pzoo+"\n";
+ dump_msg+="zoo_inc...."+zoom_inc+"\n";
+ dump_msg+="schem......"+SCHEM+"\n";
+ dump_msg+="viewx......"+ViewX+"\n";
+ dump_msg+="viewy......"+ViewY+"\n";
+ dump_msg+="pagex......"+PageX+"\n";
+ dump_msg+="pagey......"+PageY+"\n";
+ dump_msg+="IE........."+ie+"\n";
+ dump_msg+="NN........."+nn+"\n";
+ alert(dump_msg);
+}
+function alertd(msg) {
+ if(DEBUG_MODE==1)
+ alert(msg)
+}
+//----------------------------------------------------------------------------
+var MyImage;
+var MyDoc;
+var MyWindow;
+//----------------------------------------------------------------------------
+function Init(){
+MyImage = window.parent.frames["xschem"].window.document.images[SCHEM];
+MyImage.src = SchemImage.src;
+MyDoc = window.parent.frames["xschem"].window.document;
+MyWindow = window.parent.frames["xschem"].window;
+//zoomfit();
+//‚¨¬ ¨¥ - çâ®, ¥á«¨ áâà ¨æ ¥ § £à㦥 ?
+//alert("init")
+}
+//----------------------------------------------------------------------------
+function ZRefresh(){
+ ViewX = w*zoo/100;
+ ViewY = h*zoo/100;
+
+ if(ViewX<=0 || ViewY<=0 || ViewX==NaN || ViewY==NaN){
+ alertd("Z-Error: " + ViewX + "##" + ViewY + "##" + zoo + "##" + pzoo);
+ DUMP();
+ ViewX=w;
+ ViewX=h;
+ zoo=100;
+ pzoo=100;
+ }
+
+ MyImage.width = ViewX;
+ MyImage.height = ViewY;
+
+ if(!ie&&!nn) //NN6
+ MyImage.src = SchemImage.src;
+ if(ie){
+ window.top.resizeBy(1, 1);
+ window.top.resizeBy(-1, -1);
+ }
+}
+function zoomin(){
+ pzoo=zoo;
+ zoo*=zoom_inc;
+ ZRefresh();
+}
+function zoomout(){
+ if(zoo<=zoom_inc) return;
+ pzoo=zoo;
+ zoo/=zoom_inc;
+ ZRefresh();
+}
+function zoomfit(){
+ pw=w;ph=h;
+ var cw;var ch;
+ if(ie || nn){
+ if(!MyDoc.body.clientWidth) {
+
+ if (self.screen) { // for NN4 and IE4
+ cw = screen.width/1.5 ; // What can I do for Opera
+ ch = screen.height/1.5; // What can I do for Opera
+ } else if (self.java) { // for NN3 with enabled Java
+ var jkit = java.awt.Toolkit.getDefaultToolkit();
+ var scrsize = jkit.getScreenSize();
+ cw = scrsize.width;
+ ch = scrsize.height;
+ } else
+ {
+ cw = w;
+ ch = h
+ }
+ }
+
+ else //FOR TRUE IE!!! with clientWidth
+ {
+ cw=MyDoc.body.clientWidth;
+ ch=MyDoc.body.clientHeight;
+
+ if (Math.round(ViewY)>ch) ch=ch+16;
+ if (Math.round(ViewX)>cw) cw=cw+16;
+
+ }
+ } else { //for TRUE NN :-) cheak It!!!
+ //alertd("nn"); //NN6 use it
+
+ cw=MyWindow.innerWidth*95/100;
+ ch=MyWindow.innerHeight*95/100;
+ //alertd("cw"+cw);
+ //alertd(""ch);
+ }
+
+ fw=100*(cw/pw);
+ fh=100*(ch/ph);
+ xzoo=fh;
+ if(fw=left && x<=right && y>=top && y<=bottom)
+ return 1;
+ return 0;
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+ for(i=0;i 0; i--){
+ for (j = n; j > 0; j--){
+ window.top.moveBy(0,i);
+ window.top.moveBy(i,0);
+ window.top.moveBy(0,-i);
+ window.top.moveBy(-i,0);
+ }//for
+ }//for
+ }//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+}
+//----------------------------------------------------------------------------
+function printit(){
+ var browser_name = navigator.appName;
+ if (browser_name == "Netscape") {
+ MyWindow.print() ;
+ } else {
+ var WebBrowser = '=left && x<=right && y>=top && y<=bottom)
+ return 1;
+ return 0;
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+ for(i=0;i 0; i--){
+ for (j = n; j > 0; j--){
+ window.top.moveBy(0,i);
+ window.top.moveBy(i,0);
+ window.top.moveBy(0,-i);
+ window.top.moveBy(-i,0);
+ }//for
+ }//for
+ }//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+}
+//----------------------------------------------------------------------------
+function printit(){
+ var browser_name = navigator.appName;
+ if (browser_name == "Netscape") {
+ MyWindow.print() ;
+ } else {
+ var WebBrowser = 'usbHostSlave.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlave.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+//// Top level module
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:45 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbHostSlave (
+ clk ,
+ rst ,
+ address_i ,
+ data_i ,
+ data_o ,
+ writeEn ,
+ strobe_i ,
+ ack_o ,
+ hostSOFSentIntOut ,
+ hostConnEventIntOut ,
+ hostResumeIntOut ,
+ hostTransDoneIntOut ,
+ slaveNAKSentIntOut ,
+ slaveSOFRxedIntOut ,
+ slaveResetEventIntOut ,
+ slaveResumeIntOut ,
+ slaveTransDoneIntOut ,
+ USBWireDataIn ,
+ USBWireDataInTick ,
+ USBWireDataOut ,
+ USBWireDataOutTick ,
+ USBWireCtrlOut
+ );
+ parameter HOST_FIFO_DEPTH = 64 ; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+ parameter HOST_FIFO_ADDR_WIDTH = 6 ;
+ parameter EP0_FIFO_DEPTH = 64 ;
+ parameter EP0_FIFO_ADDR_WIDTH = 6 ;
+ parameter EP1_FIFO_DEPTH = 64 ;
+ parameter EP1_FIFO_ADDR_WIDTH = 6 ;
+ parameter EP2_FIFO_DEPTH = 64 ;
+ parameter EP2_FIFO_ADDR_WIDTH = 6 ;
+ parameter EP3_FIFO_DEPTH = 64 ;
+ parameter EP3_FIFO_ADDR_WIDTH = 6 ;
+
+input clk ;
+input rst ;
+input [7 :0 ] address_i ;
+input [7 :0 ] data_i ;
+output [7 :0 ] data_o ;
+input writeEn ;
+input strobe_i ;
+output ack_o ;
+output hostSOFSentIntOut ;
+output hostConnEventIntOut ;
+output hostResumeIntOut ;
+output hostTransDoneIntOut ;
+output slaveSOFRxedIntOut ;
+output slaveResetEventIntOut ;
+output slaveResumeIntOut ;
+output slaveTransDoneIntOut ;
+output slaveNAKSentIntOut ;
+input [1 :0 ] USBWireDataIn ;
+output [1 :0 ] USBWireDataOut ;
+output USBWireDataOutTick ;
+output USBWireDataInTick ;
+output USBWireCtrlOut ;
+
+wire clk ;
+wire rst ;
+wire [7 :0 ] address_i ;
+wire [7 :0 ] data_i ;
+wire [7 :0 ] data_o ;
+wire writeEn ;
+wire strobe_i ;
+wire ack_o ;
+wire hostSOFSentIntOut ;
+wire hostConnEventIntOut ;
+wire hostResumeIntOut ;
+wire hostTransDoneIntOut ;
+wire slaveSOFRxedIntOut ;
+wire slaveResetEventIntOut ;
+wire slaveResumeIntOut ;
+wire slaveTransDoneIntOut ;
+wire slaveNAKSentIntOut ;
+wire [1 :0 ] USBWireDataIn ;
+wire [1 :0 ] USBWireDataOut ;
+wire USBWireDataOutTick ;
+wire USBWireDataInTick ;
+wire USBWireCtrlOut ;
+
+//internal wiring
+wire hostControlSel ;
+wire slaveControlSel ;
+wire hostRxFifoSel ;
+wire hostTxFifoSel ;
+wire hostSlaveMuxSel ;
+wire [7 :0 ] dataFromHostControl ;
+wire [7 :0 ] dataFromSlaveControl ;
+wire [7 :0 ] dataFromHostRxFifo ;
+wire [7 :0 ] dataFromHostTxFifo ;
+wire [7 :0 ] dataFromHostSlaveMux ;
+wire hostTxFifoRE ;
+wire [7 :0 ] hostTxFifoData ;
+wire hostTxFifoEmpty ;
+wire hostRxFifoWE ;
+wire [7 :0 ] hostRxFifoData ;
+wire hostRxFifoFull ;
+wire [7 :0 ] RxCtrlOut ;
+wire [7 :0 ] RxDataFromSIE ;
+wire RxDataOutWEn ;
+wire fullSpeedBitRateFromHost ;
+wire fullSpeedBitRateFromSlave ;
+wire fullSpeedPolarityFromHost ;
+wire fullSpeedPolarityFromSlave ;
+wire SIEPortWEnFromHost ;
+wire SIEPortWEnFromSlave ;
+wire SIEPortTxRdy ;
+wire [7 :0 ] SIEPortDataInFromHost ;
+wire [7 :0 ] SIEPortDataInFromSlave ;
+wire [7 :0 ] SIEPortCtrlInFromHost ;
+wire [7 :0 ] SIEPortCtrlInFromSlave ;
+wire [1 :0 ] connectState ;
+wire resumeDetected ;
+wire [7 :0 ] SIEPortDataInToSIE ;
+wire SIEPortWEnToSIE ;
+wire [7 :0 ] SIEPortCtrlInToSIE ;
+wire fullSpeedPolarityToSIE ;
+wire fullSpeedBitRateToSIE ;
+wire noActivityTimeOut ;
+wire TxFifoEP0REn ;
+wire TxFifoEP1REn ;
+wire TxFifoEP2REn ;
+wire TxFifoEP3REn ;
+wire [7 :0 ] TxFifoEP0Data ;
+wire [7 :0 ] TxFifoEP1Data ;
+wire [7 :0 ] TxFifoEP2Data ;
+wire [7 :0 ] TxFifoEP3Data ;
+wire TxFifoEP0Empty ;
+wire TxFifoEP1Empty ;
+wire TxFifoEP2Empty ;
+wire TxFifoEP3Empty ;
+wire RxFifoEP0WEn ;
+wire RxFifoEP1WEn ;
+wire RxFifoEP2WEn ;
+wire RxFifoEP3WEn ;
+wire RxFifoEP0Full ;
+wire RxFifoEP1Full ;
+wire RxFifoEP2Full ;
+wire RxFifoEP3Full ;
+wire [7 :0 ] slaveRxFifoData ;
+wire [7 :0 ] dataFromEP0RxFifo ;
+wire [7 :0 ] dataFromEP1RxFifo ;
+wire [7 :0 ] dataFromEP2RxFifo ;
+wire [7 :0 ] dataFromEP3RxFifo ;
+wire [7 :0 ] dataFromEP0TxFifo ;
+wire [7 :0 ] dataFromEP1TxFifo ;
+wire [7 :0 ] dataFromEP2TxFifo ;
+wire [7 :0 ] dataFromEP3TxFifo ;
+wire slaveEP0RxFifoSel ;
+wire slaveEP1RxFifoSel ;
+wire slaveEP2RxFifoSel ;
+wire slaveEP3RxFifoSel ;
+wire slaveEP0TxFifoSel ;
+wire slaveEP1TxFifoSel ;
+wire slaveEP2TxFifoSel ;
+wire slaveEP3TxFifoSel ;
+
+usbHostControl u_usbHostControl (
+ .clk (clk ),
+ .rst (rst ),
+ .TxFifoRE (hostTxFifoRE ),
+ .TxFifoData (hostTxFifoData ),
+ .TxFifoEmpty (hostTxFifoEmpty ),
+ .RxFifoWE (hostRxFifoWE ),
+ .RxFifoData (hostRxFifoData ),
+ .RxFifoFull (hostRxFifoFull ),
+ .RxByteStatus (RxCtrlOut ),
+ .RxData (RxDataFromSIE ),
+ .RxDataValid (RxDataOutWEn ),
+ .SIERxTimeOut (noActivityTimeOut ),
+ .fullSpeedRate (fullSpeedBitRateFromHost ),
+ .fullSpeedPol (fullSpeedPolarityFromHost ),
+ .HCTxPortEn (SIEPortWEnFromHost ),
+ .HCTxPortRdy (SIEPortTxRdy ),
+ .HCTxPortData (SIEPortDataInFromHost ),
+ .HCTxPortCtrl (SIEPortCtrlInFromHost ),
+ .connectStateIn (connectState ),
+ .resumeDetectedIn (resumeDetected ),
+ .busAddress (address_i [3 :0 ]),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromHostControl ),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .SOFSentIntOut (hostSOFSentIntOut ),
+ .connEventIntOut (hostConnEventIntOut ),
+ .resumeIntOut (hostResumeIntOut ),
+ .transDoneIntOut (hostTransDoneIntOut ),
+ .hostControlSelect (hostControlSel ) );
+
+
+usbSlaveControl u_usbSlaveControl (
+ .clk (clk ),
+ .rst (rst ),
+ .RxByteStatus (RxCtrlOut ),
+ .RxData (RxDataFromSIE ),
+ .RxDataValid (RxDataOutWEn ),
+ .SIERxTimeOut (noActivityTimeOut ),
+ .RxFifoData (slaveRxFifoData ),
+ .fullSpeedRate (fullSpeedBitRateFromSlave ),
+ .fullSpeedPol (fullSpeedPolarityFromSlave ),
+ .SCTxPortEn (SIEPortWEnFromSlave ),
+ .SCTxPortRdy (SIEPortTxRdy ),
+ .SCTxPortData (SIEPortDataInFromSlave ),
+ .SCTxPortCtrl (SIEPortCtrlInFromSlave ),
+ .connectStateIn (connectState ),
+ .resumeDetectedIn (resumeDetected ),
+ .busAddress (address_i [4 :0 ]),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromSlaveControl ),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .SOFRxedIntOut (slaveSOFRxedIntOut ),
+ .resetEventIntOut (slaveResetEventIntOut ),
+ .resumeIntOut (slaveResumeIntOut ),
+ .transDoneIntOut (slaveTransDoneIntOut ),
+ .NAKSentIntOut (slaveNAKSentIntOut ),
+ .slaveControlSelect (slaveControlSel ),
+ .TxFifoEP0REn (TxFifoEP0REn ),
+ .TxFifoEP1REn (TxFifoEP1REn ),
+ .TxFifoEP2REn (TxFifoEP2REn ),
+ .TxFifoEP3REn (TxFifoEP3REn ),
+ .TxFifoEP0Data (TxFifoEP0Data ),
+ .TxFifoEP1Data (TxFifoEP1Data ),
+ .TxFifoEP2Data (TxFifoEP2Data ),
+ .TxFifoEP3Data (TxFifoEP3Data ),
+ .TxFifoEP0Empty (TxFifoEP0Empty ),
+ .TxFifoEP1Empty (TxFifoEP1Empty ),
+ .TxFifoEP2Empty (TxFifoEP2Empty ),
+ .TxFifoEP3Empty (TxFifoEP3Empty ),
+ .RxFifoEP0WEn (RxFifoEP0WEn ),
+ .RxFifoEP1WEn (RxFifoEP1WEn ),
+ .RxFifoEP2WEn (RxFifoEP2WEn ),
+ .RxFifoEP3WEn (RxFifoEP3WEn ),
+ .RxFifoEP0Full (RxFifoEP0Full ),
+ .RxFifoEP1Full (RxFifoEP1Full ),
+ .RxFifoEP2Full (RxFifoEP2Full ),
+ .RxFifoEP3Full (RxFifoEP3Full )
+ );
+
+wishBoneBI u_wishBoneBI (
+ .address (address_i ),
+ .dataIn (data_i ),
+ .dataOut (data_o ),
+ .writeEn (writeEn ),
+ .strobe_i (strobe_i ),
+ .ack_o (ack_o ),
+ .clk (clk ),
+ .rst (rst ),
+ .hostControlSel (hostControlSel ),
+ .hostRxFifoSel (hostRxFifoSel ),
+ .hostTxFifoSel (hostTxFifoSel ),
+ .slaveControlSel (slaveControlSel ),
+ .slaveEP0RxFifoSel (slaveEP0RxFifoSel ),
+ .slaveEP1RxFifoSel (slaveEP1RxFifoSel ),
+ .slaveEP2RxFifoSel (slaveEP2RxFifoSel ),
+ .slaveEP3RxFifoSel (slaveEP3RxFifoSel ),
+ .slaveEP0TxFifoSel (slaveEP0TxFifoSel ),
+ .slaveEP1TxFifoSel (slaveEP1TxFifoSel ),
+ .slaveEP2TxFifoSel (slaveEP2TxFifoSel ),
+ .slaveEP3TxFifoSel (slaveEP3TxFifoSel ),
+ .hostSlaveMuxSel (hostSlaveMuxSel ),
+ .dataFromHostControl (dataFromHostControl ),
+ .dataFromHostRxFifo (dataFromHostRxFifo ),
+ .dataFromHostTxFifo (dataFromHostTxFifo ),
+ .dataFromSlaveControl (dataFromSlaveControl ),
+ .dataFromEP0RxFifo (dataFromEP0RxFifo ),
+ .dataFromEP1RxFifo (dataFromEP1RxFifo ),
+ .dataFromEP2RxFifo (dataFromEP2RxFifo ),
+ .dataFromEP3RxFifo (dataFromEP3RxFifo ),
+ .dataFromEP0TxFifo (dataFromEP0TxFifo ),
+ .dataFromEP1TxFifo (dataFromEP1TxFifo ),
+ .dataFromEP2TxFifo (dataFromEP2TxFifo ),
+ .dataFromEP3TxFifo (dataFromEP3TxFifo ),
+ .dataFromHostSlaveMux (dataFromHostSlaveMux )
+ );
+
+hostSlaveMux u_hostSlaveMux (
+ .SIEPortCtrlInToSIE (SIEPortCtrlInToSIE ),
+ .SIEPortCtrlInFromHost (SIEPortCtrlInFromHost ),
+ .SIEPortCtrlInFromSlave (SIEPortCtrlInFromSlave ),
+ .SIEPortDataInToSIE (SIEPortDataInToSIE ),
+ .SIEPortDataInFromHost (SIEPortDataInFromHost ),
+ .SIEPortDataInFromSlave (SIEPortDataInFromSlave ),
+ .SIEPortWEnToSIE (SIEPortWEnToSIE ),
+ .SIEPortWEnFromHost (SIEPortWEnFromHost ),
+ .SIEPortWEnFromSlave (SIEPortWEnFromSlave ),
+ .fullSpeedPolarityToSIE (fullSpeedPolarityToSIE ),
+ .fullSpeedPolarityFromHost (fullSpeedPolarityFromHost ),
+ .fullSpeedPolarityFromSlave (fullSpeedPolarityFromSlave ),
+ .fullSpeedBitRateToSIE (fullSpeedBitRateToSIE ),
+ .fullSpeedBitRateFromHost (fullSpeedBitRateFromHost ),
+ .fullSpeedBitRateFromSlave (fullSpeedBitRateFromSlave ),
+ .dataIn (data_i ),
+ .dataOut (dataFromHostSlaveMux ),
+ .writeEn (writeEn ),
+ .strobe_i (strobe_i ),
+ .clk (clk ),
+ .rst (rst ),
+ .hostSlaveMuxSel (hostSlaveMuxSel ) );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine (
+ .clk (clk ),
+ .rst (rst ),
+ .USBWireDataIn (USBWireDataIn ),
+ .USBWireDataOut (USBWireDataOut ),
+ .USBWireDataInTick (USBWireDataInTick ),
+ .USBWireDataOutTick (USBWireDataOutTick ),
+ .USBWireCtrlOut (USBWireCtrlOut ),
+ .connectState (connectState ),
+ .resumeDetected (resumeDetected ),
+ .RxCtrlOut (RxCtrlOut ),
+ .RxDataOutWEn (RxDataOutWEn ),
+ .RxDataOut (RxDataFromSIE ),
+ .SIEPortCtrlIn (SIEPortCtrlInToSIE ),
+ .SIEPortDataIn (SIEPortDataInToSIE ),
+ .SIEPortTxRdy (SIEPortTxRdy ),
+ .SIEPortWEn (SIEPortWEnToSIE ),
+ .fullSpeedPolarity (fullSpeedPolarityToSIE ),
+ .fullSpeedBitRate (fullSpeedBitRateToSIE ),
+ .noActivityTimeOut (noActivityTimeOut )
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH , HOST_FIFO_ADDR_WIDTH ) HostTxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoREn (hostTxFifoRE ),
+ .fifoEmpty (hostTxFifoEmpty ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (hostTxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromHostTxFifo ),
+ .fifoDataOut (hostTxFifoData ) );
+
+
+RxFifo #(HOST_FIFO_DEPTH , HOST_FIFO_ADDR_WIDTH ) HostRxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoWEn (hostRxFifoWE ),
+ .fifoFull (hostRxFifoFull ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (hostRxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromHostRxFifo ),
+ .fifoDataIn (hostRxFifoData ) );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH , EP0_FIFO_ADDR_WIDTH ) EP0TxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoREn (TxFifoEP0REn ),
+ .fifoEmpty (TxFifoEP0Empty ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP0TxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP0TxFifo ),
+ .fifoDataOut (TxFifoEP0Data ) );
+
+TxFifo #(EP1_FIFO_DEPTH , EP1_FIFO_ADDR_WIDTH ) EP1TxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoREn (TxFifoEP1REn ),
+ .fifoEmpty (TxFifoEP1Empty ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP1TxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP1TxFifo ),
+ .fifoDataOut (TxFifoEP1Data ) );
+
+ TxFifo #(EP2_FIFO_DEPTH , EP2_FIFO_ADDR_WIDTH ) EP2TxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoREn (TxFifoEP2REn ),
+ .fifoEmpty (TxFifoEP2Empty ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP2TxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP2TxFifo ),
+ .fifoDataOut (TxFifoEP2Data ) );
+
+ TxFifo #(EP3_FIFO_DEPTH , EP3_FIFO_ADDR_WIDTH ) EP3TxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoREn (TxFifoEP3REn ),
+ .fifoEmpty (TxFifoEP3Empty ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP3TxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP3TxFifo ),
+ .fifoDataOut (TxFifoEP3Data ) );
+
+RxFifo #(EP0_FIFO_DEPTH , EP0_FIFO_ADDR_WIDTH ) EP0RxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoWEn (RxFifoEP0WEn ),
+ .fifoFull (RxFifoEP0Full ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP0RxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP0RxFifo ),
+ .fifoDataIn (slaveRxFifoData ) );
+
+RxFifo #(EP1_FIFO_DEPTH , EP1_FIFO_ADDR_WIDTH ) EP1RxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoWEn (RxFifoEP1WEn ),
+ .fifoFull (RxFifoEP1Full ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP1RxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP1RxFifo ),
+ .fifoDataIn (slaveRxFifoData ) );
+
+RxFifo #(EP2_FIFO_DEPTH , EP2_FIFO_ADDR_WIDTH ) EP2RxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoWEn (RxFifoEP2WEn ),
+ .fifoFull (RxFifoEP2Full ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP2RxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP2RxFifo ),
+ .fifoDataIn (slaveRxFifoData ) );
+
+RxFifo #(EP3_FIFO_DEPTH , EP3_FIFO_ADDR_WIDTH ) EP3RxFifo (
+ .clk (clk ),
+ .rst (rst ),
+ .fifoWEn (RxFifoEP3WEn ),
+ .fifoFull (RxFifoEP3Full ),
+ .busAddress (address_i [2 :0 ]),
+ .busWriteEn (writeEn ),
+ .busStrobe_i (strobe_i ),
+ .busFifoSelect (slaveEP3RxFifoSel ),
+ .busDataIn (data_i ),
+ .busDataOut (dataFromEP3RxFifo ),
+ .fifoDataIn (slaveRxFifoData ) );
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/wrapper/usbHostSlave.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js (revision 264)
@@ -0,0 +1,3 @@
+
+var nn = (document.layers) ? 1:0;
+var ie = (document.all) ? 1:0;
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js (revision 264)
@@ -0,0 +1,178 @@
+
+// styles definition
+
+document.writeln ('');
+
+// paths
+
+var TreePath = "./" + RootProject + "images/tree/";
+var TabsPath = "./" + RootProject + "images/tab/";
+if (DownTabs == 1)
+ TabsPath = "./" + RootProject + "images/itab/";
+var ExtPath = "./" + RootProject + "images/ext/";
+
+// preloading images
+
+LeftNot = new Image ();
+RightNot = new Image ();
+
+LeftSel = new Image ();
+RightSel = new Image ();
+
+SelNot = new Image ();
+NotSel = new Image ();
+NotNot = new Image ();
+
+TabNot = new Image ();
+TabSel = new Image ();
+
+Project = new Image ();
+VHD = new Image ();
+V = new Image ();
+EDN = new Image ();
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image ();
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+UNDEF = new Image ();
+
+Empty = new Image ();
+
+LeftNot.src = TabsPath + "left_n.bmp";
+RightNot.src = TabsPath + "right_n.bmp";
+
+LeftSel.src = TabsPath + "left_s.bmp";
+RightSel.src = TabsPath + "right_s.bmp";
+
+SelNot.src = TabsPath + "s_n.bmp";
+NotSel.src = TabsPath + "n_s.bmp";
+NotNot.src = TabsPath + "n_n.bmp";
+
+TabNot.src = TabsPath + "tab_n.bmp";
+TabSel.src = TabsPath + "tab_s.bmp";
+
+Project.src = TreePath + "project.bmp";
+
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+UNDEF.src = ExtPath + "undef.gif";
+
+Empty.src = TabsPath + "empty.gif";
+
+// working with tab
+
+var ID = 0;
+
+function SetTab (Type, Name, URL)
+ {
+ var str;
+ str = '';
+ str += ''; ChangeButtons
+ str += ' ';
+ str += ' ');
+ }
+
+function EndTabs ()
+ {
+ document.writeln ('
');
+ ChangeButtons (0);
+ }
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt (revision 264)
@@ -0,0 +1,5 @@
+USBHostSlave has been successfully compiled using Quartus 4.1
+However, you will need to set the path to the include files before you get it to compile.
+Assignments>>EDA Tool Settings>>User Libraries.
+Remove the existing library mapping, and add absolute path to USBHostSlave/rtl/include
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf (revision 264)
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.1"
+DATE = "05:38:41 October 04, 2004"
+
+
+# Revisions
+
+PROJECT_REVISION = "usbHostSlave"
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v (revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifoBI.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ fifoEmpty,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v (revision 264)
@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoRTL.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH-1:0]bufferInIndex;
+reg [ADDR_WIDTH-1:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || forceEmpty == 1'b1)
+ begin
+ bufferCnt <= 0;
+ fifoFull <= 1'b0;
+ fifoEmpty <= 1'b1;
+ bufferInIndex <= 0;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ end
+ fifoREnDelayed <= fifoREn;
+ if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+ bufferCnt <= bufferCnt + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferCnt <= bufferCnt - 1;
+ bufferOutIndex <= bufferOutIndex + 1;
+ end
+ else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferOutIndex <= bufferOutIndex + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ if (bufferCnt[ADDR_WIDTH] == 1'b1)
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ if (|bufferCnt == 1'b0)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
+ .addrIn(bufferInIndex),
+ .addrOut(bufferOutIndex),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: directcontrol.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+END
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+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
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+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
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+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
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+ 47285,153175 50048,167625 56316,171290 62585,174956\
+ 84856,175714 96012,175820
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+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
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+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
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+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
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+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
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+ 171826,160150 159742,169266 150997,171704 142252,174142\
+ 120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
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+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
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+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
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+I 162 0 2 Builtin InPort | 162999,244717 "" ""
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+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf (revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: hctxportarbiter.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+GRID=OFF
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+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+ 259846,282068 289467,282068 298484,284234 307501,286400\
+ 313949,295065 315460,307759 316972,320453 316568,362568\
+ 311430,375060 306292,387553 286404,388600 275724,388298\
+ 265045,387996 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v (revision 264)
@@ -0,0 +1,102 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// rxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: rxStatusMonitor.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:53 sfielding
+// Created
+//
+//
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ connectionEventOut <= 1'b1;
+ else
+ connectionEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js (revision 264)
@@ -0,0 +1,249 @@
+
+// styles definition
+
+document.writeln ('');
+
+// paths
+
+if ((ie) || (nn))
+{
+ var TreePath = "./images/tree/";
+ var ExtPath = "./images/ext/";
+ var DocPath = "./../src/";
+}
+if ((!ie) && (!nn))
+{
+ var TreePath = "./../images/tree/";
+ var ExtPath = "./../images/ext/";
+ var DocPath = "./../src/";
+}
+
+
+// preloading images
+
+Empty = new Image ();
+
+Join = new Image ();
+JoinBottom = new Image ();
+JoinTop = new Image ();
+JoinLeft = new Image ();
+
+Line = new Image ();
+
+Minus = new Image ();
+MinusBottom = new Image ();
+MinusOnly = new Image ();
+MinusTop = new Image ();
+
+Plus = new Image ();
+PlusBottom = new Image ();
+PlusOnly = new Image ();
+PlusTop = new Image ();
+
+FolderOpened = new Image ();
+FolderClosed = new Image ();
+
+Project = new Image ();
+
+VHD = new Image ();VHDL = new Image ();//VHDL Source cod
+V = new Image (); //Verilog Source cod
+EDN = new Image (); //edif...
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image (); //"State diagram"
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+SDF = new Image (); //"SDF File"
+
+XNF = new Image (); //"XNF Netlist"
+VLS = new Image (); //"ViewLogic Schematic"
+VTB = new Image (); //"VHDL Test bench" || "Verilog Test bench"
+HTM = new Image ();HTML = new Image (); //"HTML Document"
+BAS = new Image ();
+UND = new Image (); //undefined || "External File"
+
+CONF = new Image (); //"Configuration file"
+DRW = new Image (); //"Drawing" ????
+SYMB = new Image (); //"Symbol Sheet" ????
+
+ACP = new Image (); //Active-CAD Project
+AHW = new Image (); //Active-HDL Workspace
+
+///////////////////////////////////////////
+Empty.src = TreePath + "empty.gif";
+
+Join.src = TreePath + "join.gif";
+JoinBottom.src = TreePath + "join_b.gif";
+JoinTop.src = TreePath + "join_t.gif";
+JoinLeft.src = TreePath + "join_l.gif";
+
+Line.src = TreePath + "line.gif";
+
+Minus.src = TreePath + "minus.gif";
+MinusBottom.src = TreePath + "minus_b.gif";
+MinusOnly.src = TreePath + "minus_o.gif";
+MinusTop.src = TreePath + "minus_t.gif";
+
+Plus.src = TreePath + "plus.gif";
+PlusBottom.src = TreePath + "plus_b.gif";
+PlusOnly.src = TreePath + "plus_o.gif";
+
+FolderOpened.src = TreePath + "folder_o.gif";
+FolderClosed.src = TreePath + "folder_c.gif";
+///////////////////////////////////////////
+Project.src = TreePath + "project.gif";
+///////////////////////////////////////////
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+SDF.src = ExtPath + "sdf.gif";
+
+XNF.src = ExtPath + "xnf.gif";
+VLS.src = ExtPath + "vls.gif";
+VTB.src = ExtPath + "vtb.gif";
+HTM.src = ExtPath + "htm.gif"; HTML.src = HTM.src;
+BAS.src = ExtPath + "bas.gif";
+UND.src = ExtPath + "und.gif";
+
+CONF.src = ExtPath + "conf.gif";
+DRW.src = ExtPath + "drw.gif";
+SYMB.src = ExtPath + "symb.gif";
+
+ACP.src = ExtPath + "acp.gif";
+AHW.src = ExtPath + "ahw.gif";
+
+// working with tree
+
+function BeginTree ()
+ {
+ return '';
+ }
+
+function EndTree ()
+ {
+ return '
';
+ }
+
+function FirstCreateTree()
+{
+ window.frames["Map"].document.writeln(DrawMapTree());
+}
+
+function CreateTree ()
+ {
+ if (!ie)
+ {
+ window.frames["Map"].document.open();
+ window.frames["Map"].document.writeln("");
+ window.frames["Map"].document.writeln ('');
+ window.frames["Map"].document.writeln("");
+ window.frames["Map"].document.writeln("");
+ window.frames["Map"].document.writeln(DrawMapTree());
+ window.frames["Map"].document.writeln("");
+ window.frames["Map"].document.writeln("");
+ window.frames["Map"].document.close();
+ }
+ else
+ window.frames["Map"].document.body.innerHTML = DrawMapTree ();
+ }
+
+ function CollapseIt ()
+ {
+ for(i=0;i';
+ }
+
+function ER ()
+ {
+ return ' ' + Name + ' ';
+
+ if ((Type!="project")&&(URL==""))
+ return ' '+Name;
+ else
+ return ' ' + Name + ' ';
+ }
+ return Name;
+ }
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.project.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.project.hdb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,133 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifo.v,v 1.2 2004-12-18 14:36:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module RxFifo(
+ clk,
+ rst,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk;
+wire rst;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v (revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMem.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ .rclk(clk),
+ .rrst(1'b0),
+ .rce(1'b1),
+ .oe(readEn),
+ .raddr(addrOut),
+ .do(dataOut),
+ .wclk(clk),
+ .wrst(1'b0),
+ .wce(1'b1),
+ .we(writeEn),
+ .waddr(addrIn),
+ .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
+ .addrIn(addrIn),
+ .addrOut(addrOut),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(writeEn),
+ .readEn(readEn),
+ .dataOut(dataOut));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,267 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBHostControlBI.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
+// Created
+//
+//
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+ TxTransTypeReg, TxSOFEnableReg,
+ TxAddrReg, TxEndPReg, frameNumIn,
+ RxPktStatusIn, RxPIDIn,
+ connectStateIn,
+ SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+ hostControlSelect,
+ clrTransReq,
+ preambleEn,
+ SOFSync,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ transReq
+ );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+ clrSOFReq <= 1'b0;
+ clrConnEvtReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ setTransReq <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+ begin
+ case (address)
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn[2];
+ SOFSync <= dataIn[1];
+ setTransReq <= dataIn[0];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+ `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+ `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn[3];
+ clrConnEvtReq <= dataIn[2];
+ clrResInReq <= dataIn[1];
+ clrTransDoneReq <= dataIn[0];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (SOFSentIn == 1'b1)
+ SOFSentInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFSentInt <= 1'b0;
+
+ if (connEventIn == 1'b1)
+ connEventInt <= 1'b1;
+ else if (clrConnEvtReq == 1'b1)
+ connEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end
+
+//transaction request set/clear
+always @(posedge clk)
+begin
+ if (setTransReq == 1'b1)
+ transReq <= 1'b1;
+ else if (clrTransReq == 1'b1)
+ transReq <= 1'b0;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+ TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+ fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq)
+begin
+ case (address)
+ `TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+ `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+ `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+ `FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
+ `FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn;
+ `RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm (revision 264)
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info (revision 264)
@@ -0,0 +1,3 @@
+Quartus_Version = Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
+Version_Index = 53250
+Creation_Time = Sat Oct 02 05:36:22 2004
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws (revision 264)
@@ -0,0 +1,23 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+ptn_Child2=Workmode
+ptn_Child3=ActionPoints
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
+InCompileMode=True
+InSimulateMode=False
+InFirmwareMode=False
+WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPGBAAAAAANBAAAAAACGCAAAAAGHBAAAAA
+IsActiveChildFrame=True
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
+[ProjectWorkspace.Workmode]
+CurrentWorkmode=0
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v (revision 264)
@@ -0,0 +1,126 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifoBI.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ clk, rst, fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ fifoFull,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v (revision 264)
@@ -0,0 +1,254 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBI.v,v 1.2 2004-12-18 14:36:08 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+
+module wishBoneBI (
+ address, dataIn, dataOut, writeEn,
+ strobe_i,
+ ack_o,
+ clk, rst,
+ hostControlSel,
+ hostRxFifoSel, hostTxFifoSel,
+ slaveControlSel,
+ slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
+ slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
+ hostSlaveMuxSel,
+ dataFromHostControl,
+ dataFromHostRxFifo,
+ dataFromHostTxFifo,
+ dataFromSlaveControl,
+ dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+ dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+ dataFromHostSlaveMux
+ );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+ dataFromHostControl or
+ dataFromHostRxFifo or
+ dataFromHostTxFifo or
+ dataFromSlaveControl or
+ dataFromEP0RxFifo or
+ dataFromEP1RxFifo or
+ dataFromEP2RxFifo or
+ dataFromEP3RxFifo or
+ dataFromHostSlaveMux or
+ dataFromEP0TxFifo or
+ dataFromEP1TxFifo or
+ dataFromEP2TxFifo or
+ dataFromEP3TxFifo)
+begin
+ hostControlSel <= 1'b0;
+ hostRxFifoSel <= 1'b0;
+ hostTxFifoSel <= 1'b0;
+ slaveControlSel <= 1'b0;
+ slaveEP0RxFifoSel <= 1'b0;
+ slaveEP0TxFifoSel <= 1'b0;
+ slaveEP1RxFifoSel <= 1'b0;
+ slaveEP1TxFifoSel <= 1'b0;
+ slaveEP2RxFifoSel <= 1'b0;
+ slaveEP2TxFifoSel <= 1'b0;
+ slaveEP3RxFifoSel <= 1'b0;
+ slaveEP3TxFifoSel <= 1'b0;
+ hostSlaveMuxSel <= 1'b0;
+ case (address & `ADDRESS_DECODE_MASK)
+ `HCREG_BASE : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HCREG_BASE_PLUS_0X10 : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HOST_RX_FIFO_BASE : begin
+ hostRxFifoSel <= 1'b1;
+ dataOut <= dataFromHostRxFifo;
+ end
+ `HOST_TX_FIFO_BASE : begin
+ hostTxFifoSel <= 1'b1;
+ dataOut <= dataFromHostTxFifo;
+ end
+ `SCREG_BASE : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `SCREG_BASE_PLUS_0X10 : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `EP0_RX_FIFO_BASE : begin
+ slaveEP0RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0RxFifo;
+ end
+ `EP0_TX_FIFO_BASE : begin
+ slaveEP0TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0TxFifo;
+ end
+ `EP1_RX_FIFO_BASE : begin
+ slaveEP1RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1RxFifo;
+ end
+ `EP1_TX_FIFO_BASE : begin
+ slaveEP1TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1TxFifo;
+ end
+ `EP2_RX_FIFO_BASE : begin
+ slaveEP2RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2RxFifo;
+ end
+ `EP2_TX_FIFO_BASE : begin
+ slaveEP2TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2TxFifo;
+ end
+ `EP3_RX_FIFO_BASE : begin
+ slaveEP3RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3RxFifo;
+ end
+ `EP3_TX_FIFO_BASE : begin
+ slaveEP3TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3TxFifo;
+ end
+ `HOST_SLAVE_CONTROL_BASE : begin
+ hostSlaveMuxSel <= 1'b1;
+ dataOut <= dataFromHostSlaveMux;
+ end
+ default:
+ dataOut <= 8'h00;
+ endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+ ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+ ack_immediate <= strobe_i;
+end
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+ if (writeEn == 1'b0 &&
+ (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+ begin
+ ack_o <= ack_delayed;
+ end
+ else
+ begin
+ ack_o <= ack_immediate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf (revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: getpacket.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 58
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 112
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 245
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+ 88541,112746 87971,105860 87641,93102 87312,80344\
+ 87761,70127 92565,59363 97370,48599 95270,45542\
+ 101102,30966
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus = { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+ 57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf (revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=432
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: hostcontroller.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
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+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+ 170250,145750 137550,145450 128737,144962 119925,144475\
+ 117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+C 321 320 0 TEXT "Conditions" | 124852,185328 1 0 0 "sendPacketRdy == 1'b1"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 331 BEZIER "Transitions" | 82714,126587 85717,114267 91541,91328 94544,79008
+C 333 332 0 TEXT "Conditions" | 48120,123470 1 0 0 "sendPacketRdy == 1'b1"
+A 334 332 16 TEXT "Actions" | 87236,105298 1 0 0 "getPacketREn <= 1'b1;"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+ 110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+ 88026,17883 53248,36150 43780,48625 34312,61101\
+ 33772,117285 37441,132224 41110,147164 52980,154980\
+ 61012,157537 69044,160095 94076,164012 106263,166770
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+ 129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 2 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+ 40160,89849 37728,77233 37462,69633 37196,62033\
+ 38564,44249 44378,36953 50192,29657 72080,18257\
+ 79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 368 362 4 TEXT "Actions" | 121320,126002 1 0 0 "sendPacketWEn <= 1'b0;"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+ 134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 231 220 4 TEXT "Actions" | 102966,127564 1 0 0 "sendPacketWEn <= 1'b0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v (revision 264)
@@ -0,0 +1,355 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacket.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input [3:0]PID;
+input rst;
+input sendPacketWEn;
+input [6:0]TxAddr;
+input [3:0]TxEndP;
+output fifoReadEn;
+output [10:0]frameNum;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+reg [10:0]frameNum, next_frameNum;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire [3:0]PID;
+wire rst;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+wire [6:0]TxAddr;
+wire [3:0]TxEndP;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+ NextState_sndPkt <= CurrState_sndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ next_frameNum <= frameNum;
+ case (CurrState_sndPkt) // synopsys parallel_case full_case
+ `START_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ end
+ `WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_sndPkt <= `SP_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `SP_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_HCTxPortReq <= 1'b0;
+ end
+ `SEND_PID_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= PIDNotPID;
+ next_HCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SEND_PID_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ else if (PID == `SOF)
+ begin
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+ end
+ else if (PID == `OUT ||
+ PID == `IN ||
+ PID == `SETUP)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sndPkt <= `FIN_SP;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY1:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY2:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `OUT_IN_SETUP_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+ end
+ `SEND_SOF_FIN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_frameNum <= frameNum + 1'b1;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `SEND_SOF_WAIT_RDY3:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= frameNum[7:0];
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_WAIT_RDY4:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_FIN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+ end
+ `DATA0_DATA1_READ_FIFO:
+ begin
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= fifoData;
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+ end
+ `DATA0_DATA1_WAIT_READ_FIFO:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `DATA0_DATA1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+ end
+ end
+ `DATA0_DATA1_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `DATA0_DATA1_TERM_BYTE:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `DATA0_DATA1_CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ `DATA0_DATA1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sndPkt <= `START_SP;
+ else
+ CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ HCTxPortData <= 8'h00;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ frameNum <= 11'h000;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ frameNum <= next_frameNum;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v (revision 264)
@@ -0,0 +1,183 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketarbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacketarbiter.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input clk;
+input [3:0]HC_PID;
+input HC_SP_WEn;
+input HCTxReq;
+input rst;
+input SOF_SP_WEn;
+input SOFTxReq;
+output HCTxGnt;
+output [3:0]sendPacketPID;
+output sendPacketWEnable;
+output SOFTxGnt;
+
+wire clk;
+wire [3:0]HC_PID;
+wire HC_SP_WEn;
+reg HCTxGnt, next_HCTxGnt;
+wire HCTxReq;
+wire rst;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+reg sendPacketWEnable, next_sendPacketWEnable;
+wire SOF_SP_WEn;
+reg SOFTxGnt, next_SOFTxGnt;
+wire SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+ NextState_sendPktArb <= CurrState_sendPktArb;
+ // Set default values for outputs and signals
+ next_HCTxGnt <= HCTxGnt;
+ next_SOFTxGnt <= SOFTxGnt;
+ next_muxSOFNotHC <= muxSOFNotHC;
+ case (CurrState_sendPktArb) // synopsys parallel_case full_case
+ `HC_ACT:
+ begin
+ if (HCTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_HCTxGnt <= 1'b0;
+ end
+ end
+ `SOF_ACT:
+ begin
+ if (SOFTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_SOFTxGnt <= 1'b0;
+ end
+ end
+ `SARB_WAIT_REQ:
+ begin
+ if (SOFTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `SOF_ACT;
+ next_SOFTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b1;
+ end
+ else if (HCTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `HC_ACT;
+ next_HCTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktArb <= `START_SARB;
+ else
+ CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxGnt <= 1'b0;
+ SOFTxGnt <= 1'b0;
+ muxSOFNotHC <= 1'b0;
+ end
+ else
+ begin
+ HCTxGnt <= next_HCTxGnt;
+ SOFTxGnt <= next_SOFTxGnt;
+ muxSOFNotHC <= next_muxSOFNotHC;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v (revision 264)
@@ -0,0 +1,184 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sofcontroller
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sofcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input clk;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+input SOFEnable;
+input SOFTimerClr;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output [15:0]SOFTimer;
+
+wire clk;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+wire SOFEnable;
+reg [15:0]SOFTimer, next_SOFTimer;
+wire SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+ NextState_sofCntl <= CurrState_sofCntl;
+ // Set default values for outputs and signals
+ next_SOFTimer <= SOFTimer;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_sofCntl) // synopsys parallel_case full_case
+ `START_SC:
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ end
+ `WAIT_SOF_EN:
+ begin
+ if (SOFEnable == 1'b1)
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `WAIT_SEND_RESUME:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sofCntl <= `CLR_WEN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_RESUME_START;
+ end
+ end
+ `INC_TIMER:
+ begin
+ next_HCTxPortReq <= 1'b0;
+ if (SOFTimerClr == 1'b1)
+ next_SOFTimer <= 16'h0000;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1;
+ if (SOFEnable == 1'b0)
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ next_SOFTimer <= 16'h0000;
+ end
+ end
+ `SC_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sofCntl <= `WAIT_SEND_RESUME;
+ end
+ end
+ `CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sofCntl <= `INC_TIMER;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sofCntl <= `START_SC;
+ else
+ CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFTimer <= 16'h0000;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm (revision 264)
@@ -0,0 +1 @@
+Appropriate file was not exported
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini (revision 264)
@@ -0,0 +1 @@
+35
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf (revision 264)
@@ -0,0 +1,93 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+# The default values for assignments are stored in the file
+# usbHostSlave_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "05:36:22 OCTOBER 02, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name VERILOG_FILE ../../RTL/wrapper/usbHostSlave.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/USBSlaveControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/endpMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/fifoMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/sctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slavecontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveDirectcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveGetpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveRxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveSendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/usbSlaveControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/writeUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/lineControlUpdate.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxBit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processTxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/readUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/siereceiver.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/SIETransmitter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC5.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC16.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMuxBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/USBHostControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/directcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/getpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hostcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/rxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketcheckpreamble.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sofcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/softransmit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/speedCtrlMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/usbHostControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/busInterface/wishBoneBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoRTL.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifo.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/simFifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifo.v
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlave
+set_global_assignment -name USER_LIBRARIES "c:\\projects\\usbhostslaveforoc\\rtl\\include/"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C20F400C6
Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v (revision 264)
@@ -0,0 +1,131 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifo.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module TxFifo(
+ clk,
+ rst,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk;
+wire rst;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoFull(fifoFull),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v (revision 264)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// simFifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: simFifoMem.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module simFifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+ dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+ if (writeEn == 1'b1)
+ buffer[addrIn] <= dataIn;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v (revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// directControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: directcontrol.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+ NextState_drctCntl <= CurrState_drctCntl;
+ // Set default values for outputs and signals
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_drctCntl) // synopsys parallel_case full_case
+ `START_DC:
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ next_HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {6'b000000, directControlLineState};
+ next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_HCTxPortReq <= 1'b0;
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_drctCntl <= `START_DC;
+ else
+ CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v (revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hctxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+input [7:0]SOFCntlCntl;
+input [7:0]SOFCntlData;
+input SOFCntlReq;
+input SOFCntlWEn;
+output directCntlGnt;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortWEnable;
+output sendPacketGnt;
+output SOFCntlGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+reg HCTxPortWEnable, next_HCTxPortWEnable;
+wire rst;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [7:0]SOFCntlCntl;
+wire [7:0]SOFCntlData;
+reg SOFCntlGnt, next_SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+ NextState_HCTxArb = CurrState_HCTxArb;
+ // Set default values for outputs and signals
+ next_SOFCntlGnt <= SOFCntlGnt;
+ next_sendPacketGnt <= sendPacketGnt;
+ next_directCntlGnt <= directCntlGnt;
+ next_muxCntl <= muxCntl;
+ case (CurrState_HCTxArb) // synopsys parallel_case full_case
+ `START_HARB:
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ end
+ `WAIT_REQ:
+ begin
+ if (SOFCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_SOF;
+ next_SOFCntlGnt <= 1'b1;
+ next_muxCntl <= `SOF_CTRL_MUX;
+ end
+ else if (sendPacketReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxCntl <= `SEND_PACKET_MUX;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `DIRECT_CONTROL;
+ next_directCntlGnt <= 1'b1;
+ next_muxCntl <= `DIRECT_CTRL_MUX;
+ end
+ end
+ `SEND_SOF:
+ begin
+ if (SOFCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_SOFCntlGnt <= 1'b0;
+ end
+ end
+ `SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `DIRECT_CONTROL:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_HCTxArb = `START_HARB;
+ else
+ CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFCntlGnt = 1'b0;
+ sendPacketGnt = 1'b0;
+ directCntlGnt = 1'b0;
+ muxCntl = 2'b00;
+ end
+ else
+ begin
+ SOFCntlGnt = next_SOFCntlGnt;
+ sendPacketGnt = next_sendPacketGnt;
+ directCntlGnt = next_directCntlGnt;
+ muxCntl = next_muxCntl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf (revision 264)
@@ -0,0 +1,243 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=225
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacket.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
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+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+ 48213,88528 42471,75064 41184,67490 39897,59917\
+ 40491,43087 47668,36800 54846,30514 82962,22198\
+ 91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+ 200128,135446 205472,144130 205681,151728 205890,159327\
+ 201380,181037 194241,189595 187102,198154 163054,210680\
+ 152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v (revision 264)
@@ -0,0 +1,234 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketcheckpreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacketcheckpreamble.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input clk;
+input preAmbleEnable;
+input rst;
+input [3:0]sendPacketCPPID;
+input sendPacketCPWEn;
+input sendPacketRdy;
+output fullSpeedBitRate;
+output fullSpeedPolarity;
+output grabLineControl; // mux select
+output sendPacketCPReady;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+
+wire clk;
+reg fullSpeedBitRate, next_fullSpeedBitRate;
+reg fullSpeedPolarity, next_fullSpeedPolarity;
+reg grabLineControl, next_grabLineControl;
+wire preAmbleEnable;
+wire rst;
+wire [3:0]sendPacketCPPID;
+reg sendPacketCPReady, next_sendPacketCPReady;
+wire sendPacketCPWEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin
+ NextState_sendPktCP <= CurrState_sendPktCP;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_fullSpeedBitRate <= fullSpeedBitRate;
+ next_fullSpeedPolarity <= fullSpeedPolarity;
+ next_grabLineControl <= grabLineControl;
+ case (CurrState_sendPktCP) // synopsys parallel_case full_case
+ `SPC_WAIT_EN:
+ begin
+ if (sendPacketCPWEn == 1'b1)
+ begin
+ NextState_sendPktCP <= `CHK_PREAM;
+ next_sendPacketCPReady <= 1'b0;
+ end
+ end
+ `START_SPC:
+ begin
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `CHK_PREAM:
+ begin
+ if (preAmbleEnable == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+ end
+ end
+ `READY:
+ begin
+ next_sendPacketCPReady <= 1'b1;
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `PREAM_PKT_SND_PREAM:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `PREAMBLE;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+ next_sendPacketWEn <= 1'b0;
+ end
+ `PREAM_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+ next_fullSpeedBitRate <= 1'b1;
+ next_fullSpeedPolarity <= 1'b1;
+ next_grabLineControl <= 1'b1;
+ end
+ end
+ `PREAM_PKT_WAIT_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+ next_fullSpeedBitRate <= 1'b1;
+ end
+ end
+ `PREAM_PKT_SND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+ next_sendPacketWEn <= 1'b0;
+ end
+ `PREAM_PKT_WAIT_RDY3:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `READY;
+ next_grabLineControl <= 1'b0;
+ end
+ end
+ `REG_PKT_SEND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+ end
+ `REG_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `REG_PKT_SEND_PID;
+ end
+ end
+ `REG_PKT_WAIT_RDY:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `READY;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktCP <= `START_SPC;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketCPReady <= 1'b1;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ fullSpeedBitRate <= 1'b0;
+ fullSpeedPolarity <= 1'b0;
+ grabLineControl <= 1'b0;
+ end
+ else
+ begin
+ sendPacketCPReady <= next_sendPacketCPReady;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ fullSpeedBitRate <= next_fullSpeedBitRate;
+ fullSpeedPolarity <= next_fullSpeedPolarity;
+ grabLineControl <= next_grabLineControl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v (revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// softransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: softransmit.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input clk;
+input rst;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn;
+input [15:0]SOFTimer;
+output sendPacketArbiterReq;
+output sendPacketWEn;
+output SOFSent; // single cycle pulse
+output SOFTimerClr; // Single cycle pulse
+
+wire clk;
+wire rst;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+wire SOFEnable;
+reg SOFSent, next_SOFSent;
+wire SOFSyncEn;
+wire [15:0]SOFTimer;
+reg SOFTimerClr, next_SOFTimerClr;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+ NextState_SOFTx <= CurrState_SOFTx;
+ // Set default values for outputs and signals
+ next_SOFSent <= SOFSent;
+ next_SOFTimerClr <= SOFTimerClr;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_SOFTx) // synopsys parallel_case full_case
+ `START_STX:
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ `WAIT_SOF_NEAR:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `WAIT_SP_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NOW;
+ end
+ end
+ `WAIT_SOF_NOW:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_sendPacketWEn <= 1'b1;
+ next_SOFTimerClr <= 1'b1;
+ next_SOFSent <= 1'b1;
+ end
+ else if (SOFEnable == 1'b0)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_SOFTimerClr <= 1'b1;
+ end
+ end
+ `SOF_FIN:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ next_SOFTimerClr <= 1'b0;
+ next_SOFSent <= 1'b0;
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ next_sendPacketArbiterReq <= 1'b0;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SOFTx <= `START_STX;
+ else
+ CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFSent <= 1'b0;
+ SOFTimerClr <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent;
+ SOFTimerClr <= next_SOFTimerClr;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMuxBI.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
+// Created
+//
+//
+
+ module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
+ hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ hostMode <= 1'b0;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
+ hostMode <= dataIn[0];
+ end
+end
+
+
+// async read mux
+always @(hostMode)
+begin
+ dataOut <= {7'h0, hostMode};
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v (revision 264)
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v
+//
+// $Id: usbSlaveControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+`endif //usbSlaveControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (revision 264)
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: lineControlUpdate.v,v 1.2 2004-12-18 14:36:15 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+ if (fullSpeedPolarity == 1'b1)
+ begin
+ JBit = `ONE_ZERO;
+ KBit = `ZERO_ONE;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE;
+ KBit = `ONE_ZERO;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v (revision 264)
@@ -0,0 +1,504 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processRxByte.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input processRxDataInWEn;
+input rst;
+input [7:0]RxByteIn;
+input [7:0]RxCtrlIn;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processRxByteRdy;
+output rstCRC;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+output RxDataOutWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+reg processRxByteRdy, next_processRxByteRdy;
+wire processRxDataInWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]RxByteIn;
+wire [7:0]RxCtrlIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+reg RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RxByte, next_RxByte;
+reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg [7:0]RxCtrl, next_RxCtrl;
+reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+ NextState_prRxByte <= CurrState_prRxByte;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte;
+ next_RxCtrl <= RxCtrl;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RxOverflow <= RxOverflow;
+ next_RxTimeOut <= RxTimeOut;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_RxDataOut <= RxDataOut;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOutWEn <= RxDataOutWEn;
+ next_rstCRC <= rstCRC;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_RXDataByteCnt <= RXDataByteCnt;
+ next_processRxByteRdy <= processRxByteRdy;
+ case (CurrState_prRxByte) // synopsys parallel_case full_case
+ `CHK_ST:
+ begin
+ if (RXByteStMachCurrState == `HS_BYTE_ST)
+ begin
+ NextState_prRxByte <= `HSHAKE_CHK;
+ end
+ else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+ begin
+ NextState_prRxByte <= `TOKEN_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+ begin
+ NextState_prRxByte <= `DATA_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+ begin
+ NextState_prRxByte <= `IDLE_CHK_START;
+ end
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+ begin
+ NextState_prRxByte <= `CHK_SYNC_DO;
+ end
+ else if (RXByteStMachCurrState == `CHECK_PID_ST)
+ begin
+ NextState_prRxByte <= `CHK_PID_DO_CHK;
+ end
+ end
+ `START_PRBY:
+ begin
+ next_RxByte <= 8'h00;
+ next_RxCtrl <= 8'h00;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxDataOut <= 8'h00;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOutWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_RXDataByteCnt <= 10'h00;
+ next_processRxByteRdy <= 1'b1;
+ NextState_prRxByte <= `WAIT_BYTE;
+ end
+ `WAIT_BYTE:
+ begin
+ if (processRxDataInWEn == 1'b1)
+ begin
+ NextState_prRxByte <= `CHK_ST;
+ next_RxByte <= RxByteIn;
+ next_RxCtrl <= RxCtrlIn;
+ next_processRxByteRdy <= 1'b0;
+ end
+ end
+ `HSHAKE_FIN:
+ begin
+ next_RxDataOutWEn <= 1'b0;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `HSHAKE_CHK:
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN;
+ if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RxDataOutWEn <= 1'b1;
+ end
+ `CHK_PID_DO_CHK:
+ begin
+ if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+ begin
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_processRxByteRdy <= 1'b1;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_RXDataByteCnt <= 0;
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_START;
+ next_RxDataOutWEn <= 1'b1;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `CHK_PID_FIRST_BYTE_PROC:
+ begin
+ next_rstCRC <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ case (RxByte[1:0] )
+ `SPECIAL: //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ `TOKEN: //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ `HANDSHAKE: //Handshake PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_ACKRxed <= 1'b1;
+ 2'b10:
+ next_NAKRxed <= 1'b1;
+ 2'b11:
+ next_stallRxed <= 1'b1;
+ default:
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST;
+ end
+ `DATA: //Data PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_dataSequence <= 1'b0;
+ 2'b10:
+ next_dataSequence <= 1'b1;
+ default:
+ $display ("Invalid DATA PID detected in ProcessRXByte\n");
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_FIN:
+ begin
+ next_CRC16En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC16Result != 16'hb001)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC16En <= 1'b1;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `DATA_FIN;
+ end
+ `DATA_WAIT_CRC:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `DATA_CHK_STRM;
+ end
+ end
+ `TOKEN_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC5Result != 5'h6)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ if (RXDataByteCnt > 10'h2)
+ begin
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `TOKEN_FIN;
+ end
+ `TOKEN_FIN:
+ begin
+ next_CRC5En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `TOKEN_WAIT_CRC:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `TOKEN_CHK_STRM;
+ end
+ end
+ `CHK_SYNC_DO:
+ begin
+ if (RxByte == `SYNC_BYTE)
+ next_RXByteStMachCurrState <= `CHECK_PID_ST;
+ else
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `IDLE_CHK_START:
+ begin
+ if (RxCtrl == `DATA_START)
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxByte <= `START_PRBY;
+ else
+ CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RxDataOut <= 8'h00;
+ RxCtrlOut <= 8'h00;
+ RxDataOutWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ processRxByteRdy <= 1'b1;
+ RxByte <= 8'h00;
+ RxCtrl <= 8'h00;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RxOverflow <= 1'b0;
+ RxTimeOut <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ RXDataByteCnt <= 10'h00;
+ end
+ else
+ begin
+ RxDataOut <= next_RxDataOut;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOutWEn <= next_RxDataOutWEn;
+ rstCRC <= next_rstCRC;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ processRxByteRdy <= next_processRxByteRdy;
+ RxByte <= next_RxByte;
+ RxCtrl <= next_RxCtrl;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RxOverflow <= next_RxOverflow;
+ RxTimeOut <= next_RxTimeOut;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ RXDataByteCnt <= next_RXDataByteCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf (revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIEReceiver\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: siereceiver.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+W 205 99 0 196 199 BEZIER "Transitions" | 95249,53980 101387,46223 111486,30323 117624,22566
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+I 219 0 130 Builtin Signal | 20132,253454 "" ""
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+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
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+I 233 0 130 Builtin Signal | 19714,243194 "" ""
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+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;\nRxBitsOut <= 2'b00;\nprocessRxBitsWEn <= 1'b0;\nSIERxRdyOut <= 1'b1;"
+I 225 0 130 Builtin OutPort | 129743,246614 "" ""
+L 224 225 0 TEXT "Labels" | 135743,246614 1 0 0 "RxBitsOut[1:0]"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 77844 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 61406,142366 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+C 254 194 0 TEXT "Conditions" | 81005,160052 1 0 0 "processRxBitRdyIn == 1'b1"
+C 253 204 0 TEXT "Conditions" | 76690,153596 1 0 0 "processRxBitRdyIn == 1'b1"
+A 252 204 16 TEXT "Actions" | 57026,138798 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+A 250 160 16 TEXT "Actions" | 151210,187452 1 0 0 "SIERxRdyOut <= 1'b1;"
+I 249 0 2 Builtin OutPort | 74763,249425 "" ""
+L 248 249 0 TEXT "Labels" | 80763,249425 1 0 0 "SIERxRdyOut"
+I 247 0 2 Builtin InPort | 132223,251370 "" ""
+L 246 247 0 TEXT "Labels" | 138223,251370 1 0 0 "processRxBitRdyIn"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 81940 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 64097,138640 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;"
+A 258 183 16 TEXT "Actions" | 78587,143608 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;\nSIERxRdyOut <= 1'b1; //early indication of ready"
+C 257 169 0 TEXT "Conditions" | 57276,154345 1 0 0 "processRxBitRdyIn == 1'b1"
+C 256 183 0 TEXT "Conditions" | 63784,161795 1 0 0 "processRxBitRdyIn == 1'b1"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (revision 264)
@@ -0,0 +1,378 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:04 sfielding
+// Created
+//
+//
+
+module usbSerialInterfaceEngine(
+ clk, rst,
+ //readUSBWireData
+ USBWireDataIn,
+ USBWireDataInTick,
+ //writeUSBWireData
+ USBWireDataOut,
+ USBWireCtrlOut,
+ USBWireDataOutTick,
+ //SIEReceiver
+ connectState,
+ //processRxBit
+ resumeDetected,
+ //processRxByte
+ RxCtrlOut,
+ RxDataOutWEn,
+ RxDataOut,
+ //SIETransmitter
+ SIEPortCtrlIn,
+ SIEPortDataIn,
+ SIEPortTxRdy,
+ SIEPortWEn,
+ //lineControlUpdate
+ fullSpeedPolarity,
+ fullSpeedBitRate,
+ noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut;
+output RxDataOutWEn;
+output [7:0] RxDataOut;
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy;
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut;
+wire RxDataOutWEn;
+wire [7:0] RxDataOut;
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy;
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire [1:0] RxBitsFromSIERxToPrRxBit;
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRxToSIERx;
+wire RxWireDataWEn;
+wire SIERxRdyOut;
+wire disableWireRead;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En;
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En;
+wire [4:0] RxCRC5Result;
+wire RxCRC5_8Bit;
+wire [7:0] RxCRCData;
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En;
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En;
+wire [4:0] TxCRC5Result;
+wire TxCRC5_8Bit;
+wire [7:0] TxCRCData;
+wire TxRstCRC;
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy;
+wire processTxByteWEn;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity(fullSpeedPolarity),
+ .fullSpeedBitRate(fullSpeedBitRate),
+ .JBit(JBit),
+ .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+ (.RxBitsOut(RxBitsFromSIERxToPrRxBit),
+ .RxWireDataIn(RxWireDataFromWireRxToSIERx),
+ .RxWireDataWEn(RxWireDataWEn),
+ .SIERxRdyOut(SIERxRdyOut),
+ .clk(clk),
+ .connectState(connectState),
+ .processRxBitRdyIn(processRxBitRdy),
+ .processRxBitsWEn(processRxBitsWEn),
+ .rst(rst) );
+
+processRxBit u_processRxBit
+ (.JBit(JBit),
+ .KBit(KBit),
+ .RxBitsIn(RxBitsFromSIERxToPrRxBit),
+ .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
+ .clk(clk),
+ .processRxBitRdy(processRxBitRdy),
+ .processRxBitsWEn(processRxBitsWEn),
+ .processRxByteWEn(processRxByteWEn),
+ .resumeDetected(resumeDetected),
+ .rst(rst),
+ .processRxByteRdy(processRxByteRdy) );
+
+processRxByte u_processRxByte
+ (.CRC16En(RxCRC16En),
+ .CRC16Result(RxCRC16Result),
+ .CRC16UpdateRdy(RxCRC16UpdateRdy),
+ .CRC5En(RxCRC5En),
+ .CRC5Result(RxCRC5Result),
+ .CRC5_8Bit(RxCRC5_8Bit),
+ .CRC5UpdateRdy(RxCRC5UpdateRdy),
+ .CRCData(RxCRCData),
+ .RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
+ .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataOut),
+ .clk(clk),
+ .processRxDataInWEn(processRxByteWEn),
+ .rst(rst),
+ .rstCRC(RxRstCRC),
+ .processRxByteRdy(processRxByteRdy) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC5Result),
+ .CRCEn(RxCRC5En),
+ .CRC5_8BitIn(RxCRC5_8Bit),
+ .dataIn(RxCRCData),
+ .ready(RxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC16Result),
+ .CRCEn(RxCRC16En),
+ .dataIn(RxCRCData),
+ .ready(RxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En(TxCRC16En),
+ .CRC16Result(TxCRC16Result),
+ .CRC5En(TxCRC5En),
+ .CRC5Result(TxCRC5Result),
+ .CRC5_8Bit(TxCRC5_8Bit),
+ .CRCData(TxCRCData),
+ .CRC5UpdateRdy(TxCRC5UpdateRdy),
+ .CRC16UpdateRdy(TxCRC16UpdateRdy),
+ .JBit(JBit),
+ .KBit(KBit),
+ .SIEPortCtrlIn(SIEPortCtrlIn),
+ .SIEPortDataIn(SIEPortDataIn),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEn),
+ .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
+ .TxByteOut(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(SIETxCtrl),
+ .USBWireData(SIETxData),
+ .USBWireGnt(SIETxGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(SIETxReq),
+ .USBWireWEn(SIETxWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .rstCRC(TxRstCRC) );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC5Result),
+ .CRCEn(TxCRC5En),
+ .CRC5_8BitIn(TxCRC5_8Bit),
+ .dataIn(TxCRCData),
+ .ready(TxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC16Result),
+ .CRCEn(TxCRC16En),
+ .dataIn(TxCRCData),
+ .ready(TxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+processTxByte u_processTxByte
+ (.JBit(JBit),
+ .KBit(KBit),
+ .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
+ .TxByteIn(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(prcTxByteCtrl),
+ .USBWireData(prcTxByteData),
+ .USBWireGnt(prcTxByteGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(prcTxByteReq),
+ .USBWireWEn(prcTxByteWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst) );
+
+USBTxWireArbiter u_USBTxWireArbiter
+ (.SIETxCtrl(SIETxCtrl),
+ .SIETxData(SIETxData),
+ .SIETxGnt(SIETxGnt),
+ .SIETxReq(SIETxReq),
+ .SIETxWEn(SIETxWEn),
+ .TxBits(TxBitsFromArbToWire),
+ .TxCtl(TxCtrlFromArbToWire),
+ .USBWireRdyIn(USBWireRdy),
+ .USBWireRdyOut(USBWireReadyFromTxArb),
+ .USBWireWEn(USBWireWEn),
+ .clk(clk),
+ .prcTxByteCtrl(prcTxByteCtrl),
+ .prcTxByteData(prcTxByteData),
+ .prcTxByteGnt(prcTxByteGnt),
+ .prcTxByteReq(prcTxByteReq),
+ .prcTxByteWEn(prcTxByteWEn),
+ .rst(rst) );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn(TxBitsFromArbToWire),
+ .TxBitsOut(USBWireDataOut),
+ .TxDataOutTick(USBWireDataOutTick),
+ .TxCtrlIn(TxCtrlFromArbToWire),
+ .TxCtrlOut(USBWireCtrlOut),
+ .USBWireRdy(USBWireRdy),
+ .USBWireWEn(USBWireWEn),
+ .disableWireReadOut(disableWireRead),
+ .fullSpeedRate(fullSpeedBitRate),
+ .clk(clk),
+ .rst(rst),
+ .noActivityTimeOut(noActivityTimeOut) );
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn(USBWireDataIn),
+ .RxDataInTick(USBWireDataInTick),
+ .RxBitsOut(RxWireDataFromWireRxToSIERx),
+ .SIERxRdyIn(SIERxRdyOut),
+ .SIERxWEn(RxWireDataWEn),
+ .fullSpeedRate(fullSpeedBitRate),
+ .disableWireRead(disableWireRead),
+ .clk(clk),
+ .rst(rst) );
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v (revision 264)
@@ -0,0 +1,401 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// getpacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: getpacket.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXPacketRdy;
+output [3:0]RxPID;
+output [7:0]RXPktStatus;
+
+wire clk;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+reg [7:0]RXPktStatus;
+wire [7:0]RXStreamStatusIn;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+ NextState_getPkt <= CurrState_getPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_getPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_getPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_getPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_getPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+ next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_getPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_getPkt <= `START_GP;
+ else
+ CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RxPID <= 4'h0;
+ RXOverflow <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXByteOld <= 8'h00;
+ RXTimeOut <= 1'b0;
+ end
+ else
+ begin
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RxPID <= next_RxPID;
+ RXOverflow <= next_RXOverflow;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXByteOld <= next_RXByteOld;
+ RXTimeOut <= next_RXTimeOut;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v (revision 264)
@@ -0,0 +1,426 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input clk;
+input getPacketRdy;
+input rst;
+input [7:0]RXStatus;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input transReq;
+input [1:0]transType;
+output clearTXReq;
+output getPacketREn;
+output sendPacketArbiterReq;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output transDone;
+
+reg clearTXReq, next_clearTXReq;
+wire clk;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+wire rst;
+wire [7:0]RXStatus;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg transDone, next_transDone;
+wire transReq;
+wire [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+ NextState_hstCntrl <= CurrState_hstCntrl;
+ // Set default values for outputs and signals
+ next_transDone <= transDone;
+ next_clearTXReq <= clearTXReq;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketPID <= sendPacketPID;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_hstCntrl) // synopsys parallel_case full_case
+ `START_HC:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `TX_REQ:
+ begin
+ if (transReq == 1'b1)
+ begin
+ NextState_hstCntrl <= `WAIT_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `CHK_TYPE:
+ begin
+ if (transType == `OUTDATA0_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+ end
+ else if (transType == `IN_TRANS)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+ end
+ else if (transType == `SETUP_TRANS)
+ begin
+ NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+ end
+ else if (transType == `OUTDATA1_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+ end
+ end
+ `FLAG:
+ begin
+ next_transDone <= 1'b1;
+ next_clearTXReq <= 1'b1;
+ next_sendPacketArbiterReq <= 1'b0;
+ NextState_hstCntrl <= `FIN;
+ end
+ `FIN:
+ begin
+ next_transDone <= 1'b0;
+ next_clearTXReq <= 1'b0;
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `WAIT_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1)
+ begin
+ NextState_hstCntrl <= `CHK_TYPE;
+ end
+ end
+ `SETUP_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+ end
+ `SETUP_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+ end
+ `SETUP_WAIT_PKT_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `SETUP_HC_WAIT_RDY:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `SETUP;
+ end
+ end
+ `SETUP_WAIT_SETUP_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `SETUP_WAIT_DATA_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_DATA_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+ end
+ end
+ `IN_CHK_FOR_ERROR:
+ begin
+ if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+ RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `IN_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+ end
+ `IN_WAIT_IN_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `IN;
+ end
+ end
+ `IN_WAIT_SP_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `IN_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+ end
+ `IN_WAIT_ACK_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_DATA0_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT0_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `OUT0_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT0_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+ end
+ `OUT0_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+ end
+ `OUT1_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `OUT1_WAIT_DATA1_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT1_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT1_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+ end
+ `OUT1_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_hstCntrl <= `START_HC;
+ else
+ CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ transDone <= 1'b0;
+ clearTXReq <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ transDone <= next_transDone;
+ clearTXReq <= next_clearTXReq;
+ getPacketREn <= next_getPacketREn;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacketarbiter.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/"
+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "SARB_WAIT_REQ\n/2/"
+S 9 6 12288 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "sendPktArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: sendPacketArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;"
+C 30 23 0 TEXT "Conditions" | 141765,76523 1 0 0 "HCTxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 88369,77278 1 0 0 "SOFTxReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 114611,125692 123896,121919
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 134973,143961 1 0 0 "SOFTxGnt <= 1'b0;\nHCTxGnt <= 1'b0; \nmuxSOFNotHC <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;"
+L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt"
+I 41 0 2 Builtin OutPort | 36274,157869 "" ""
+L 42 43 0 TEXT "Labels" | 168738,158202 1 0 0 "sendPacketWEnable"
+I 43 0 2 Builtin OutPort | 162738,158202 "" ""
+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
+I 45 0 130 Builtin OutPort | 162661,153684 "" ""
+L 46 47 0 TEXT "Labels" | 95651,157673 1 0 0 "SOFTxGnt"
+I 47 0 2 Builtin OutPort | 89651,157673 "" ""
+L 48 49 0 TEXT "Labels" | 98038,153080 1 0 0 "SOFTxReq"
+I 49 0 2 Builtin InPort | 92038,153080 "" ""
+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]"
+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 108713,128484 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+ 200193,83454 202194,93721 199799,97969 197405,102218\
+ 189371,107780 182843,108050 176316,108321 158239,103840\
+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) \nbegin\n if (muxSOFNotHC == 1'b1) \n begin\n sendPacketWEnable <= SOF_SP_WEn;\n sendPacketPID <= `SOF;\n end\n else\n begin\n sendPacketWEnable <= HC_SP_WEn;\n sendPacketPID <= HC_PID;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sofcontroller.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk"
+W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787
+I 13 6 0 Builtin Reset | 56682,217090
+W 12 6 0 9 11 BEZIER "Transitions" | 101472,200547 101472,195422 101786,186460 101786,181335
+S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500
+L 10 11 0 TEXT "State Labels" | 102510,174880 1 0 0 "WAIT_SOF_EN\n/1/"
+S 9 6 0 ELLIPSE "States" | 101706,207040 6500 6500
+L 8 9 0 TEXT "State Labels" | 101706,207040 1 0 0 "START_SC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
+A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;"
+C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1"
+C 26 22 0 TEXT "Conditions" | 109587,169712 1 0 0 "SOFEnable == 1'b1"
+W 25 6 0 21 62 BEZIER "Transitions" | 104501,138249 108970,126031 113441,113813 117910,101595
+S 24 6 12288 ELLIPSE "States" | 107147,54820 6500 6500
+L 23 24 0 TEXT "State Labels" | 107147,54820 1 0 0 "INC_TIMER\n/3/"
+W 22 6 0 11 50 BEZIER "Transitions" | 102807,168391 103209,163969 153274,157911 158500,157308
+S 21 6 8192 ELLIPSE "States" | 104118,144730 6500 6500
+L 20 21 0 TEXT "State Labels" | 104118,144730 1 0 0 "WAIT_SEND_RESUME\n/2/"
+C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 179694,255682 "" ""
+L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst"
+I 16 0 3 Builtin InPort | 180096,262516 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 46 0 130 Builtin OutPort | 81312,256878 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 44 0 130 Builtin OutPort | 81915,250446 "" ""
+L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn"
+I 42 0 2 Builtin OutPort | 81638,244416 "" ""
+I 41 0 2 Builtin InPort | 84018,239200 "" ""
+L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy"
+I 39 0 2 Builtin InPort | 22914,244024 "" ""
+L 38 39 0 TEXT "Labels" | 28914,244024 1 0 0 "SOFEnable"
+I 37 0 130 Builtin OutPort | 20502,239200 "" ""
+L 36 37 0 TEXT "Labels" | 26502,239200 1 0 0 "SOFTimer[15:0]"
+C 35 33 0 TEXT "Conditions" | 56071,65104 1 0 0 "SOFEnable == 1'b0"
+W 33 6 0 24 11 BEZIER "Transitions" | 101788,58497 95658,55482 71624,73399 68189,77671\
+ 64755,81944 65727,99405 63767,113072 61807,126740\
+ 62411,169554 65777,180659 69144,191764 82008,193372\
+ 86530,192015 91053,190659 96125,183689 98738,180172
+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n SOFTimer <= 16'h0000;\nelse\n SOFTimer <= SOFTimer + 1'b1;"
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v (revision 264)
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: speedCtrlMux.v,v 1.2 2004-12-18 14:36:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:55 sfielding
+// Created
+//
+//
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input directCtrlRate;
+input directCtrlPol;
+input sendPacketRate;
+input sendPacketPol;
+input sendPacketSel;
+output fullSpeedRate;
+output fullSpeedPol;
+
+wire directCtrlRate;
+wire directCtrlPol;
+wire sendPacketRate;
+wire sendPacketPol;
+wire sendPacketSel;
+reg fullSpeedRate;
+reg fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+ if (sendPacketSel == 1'b1)
+ begin
+ fullSpeedRate <= sendPacketRate;
+ fullSpeedPol <= sendPacketPol;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate;
+ fullSpeedPol <= directCtrlPol;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v (revision 264)
@@ -0,0 +1,40 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v
+//
+// $Id: usbConstants_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v (revision 264)
@@ -0,0 +1,42 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v
+// $Id: wishBoneBus_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf (revision 264)
@@ -0,0 +1,313 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=256
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processRxBit.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+I 38 41 0 Builtin Entry | 86360,167640
+I 37 41 0 Builtin Exit | 129540,111760
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+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
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+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
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+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
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+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h1; \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
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+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
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+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
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+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+I 85 32 0 Builtin Entry | 37613,245373
+I 86 32 0 Builtin Exit | 178157,29567
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
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+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
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+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+I 105 101 0 Builtin Entry | 97220,125648
+I 106 101 0 Builtin Exit | 140400,69768
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+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
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+ 182570,51409 180962,29567
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+ 151482,86440 167580,47791 175352,29567
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+I 138 122 0 Builtin Entry | 32350,235287
+I 139 122 0 Builtin Exit | 103994,120181
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 0; \nend"
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+I 154 129 0 Builtin Exit | 115081,122515
+I 155 129 0 Builtin Entry | 43437,237621
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+ 145117,36964 157043,31068 161599,29627 166155,28187\
+ 172203,29500 175352,29567
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+ 107061,21822 137747,20482 148467,20415 159187,20348\
+ 171381,21420 174463,22458 177545,23497 178090,26035\
+ 178157,27576
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit) //can only be a resume if line remains in Kbit state\n RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n resumeWaitCnt <= resumeWaitCnt + 1'b1; \n //if we've waited long enough, then\n if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n begin \n RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n resumeDetected <= 1'b1; //report resume detected\n end\nend"
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+I 165 50 0 Builtin Exit | 139214,89780
+I 166 50 0 Builtin Entry | 96034,145660
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+I 222 220 0 Builtin Exit | 129540,111760
+I 221 220 0 Builtin Entry | 86360,167640
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+I 216 214 0 Builtin Exit | 129540,111760
+I 215 214 0 Builtin Entry | 86360,167640
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+A 237 102 2 TEXT "Actions" | 35548,248222 1 0 0 "if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n RXSameBitCount <= RXSameBitCount + 1'b1; //inc 'RXSameBitCount'\n if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error\n bitStuffError <= 1'b1; //flag 'bitStuffError'\n else //else no bit stuffing error\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= { 1'b1, RXByte[7:1]}; //RZ bit = 1 (ie no change in 'RxBits')\n end\nend\nelse //else current 'RxBits' are different from old 'RxBits'\nbegin\n if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= {1'b0, RXByte[7:1]}; //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n end\n RXSameBitCount <= 4'h1; //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+I 230 228 0 Builtin Exit | 129540,111760
+I 229 228 0 Builtin Entry | 86360,167640
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf (revision 264)
@@ -0,0 +1,218 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1000
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processTxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processTxByte.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 887
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 994
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+ 25630,50244 23766,53274 22950,67894 22135,82515\
+ 20737,137969 21261,153813 21785,169657 25281,177579\
+ 27028,179792 28775,182006 32271,182938 33727,182355\
+ 35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1) //If this bit is 1, then\n TXOneCount <= TXOneCount + 1'b1; //increment 'TXOneCount'\nelse //else this is a zero bit\nbegin\n TXOneCount <= 4'h1; //reset 'TXOneCount'\n if (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\n else \n TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == 4'h6"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h1; //reset 'TXOneCount'\nif (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\nelse \n TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+ 113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+ 40522,42856 31562,47464 29098,65320 26634,83176\
+ 25738,149992 26858,168968 27978,187944 33354,197032\
+ 36938,198888 40522,200744 49226,198568 51498,198152\
+ 53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 1; \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 874 BEZIER "Transitions" | 142661,111545 128565,105371 68178,94636 54082,88462
+C 941 940 0 TEXT "Conditions" | 111729,100310 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+ 90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+ 104561,139388 153745,139620 168013,138576 182281,137532\
+ 190169,133124 192141,121582 194113,110040 194113,68280\
+ 192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+ 41124,121640 36948,124424 36020,132602 35092,140780\
+ 35556,170708 38166,179350 40776,187992 50140,192687\
+ 55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+ 30972,218732 29812,212468 29638,189094 29464,165720\
+ 29928,78488 31900,55230 33872,31972 41296,26172\
+ 49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v (revision 264)
@@ -0,0 +1,362 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: siereceiver.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);
+input clk;
+input processRxBitRdyIn;
+input rst;
+input [1:0]RxWireDataIn;
+input RxWireDataWEn;
+output [1:0]connectState;
+output processRxBitsWEn;
+output [1:0]RxBitsOut;
+output SIERxRdyOut;
+
+wire clk;
+reg [1:0]connectState, next_connectState;
+wire processRxBitRdyIn;
+reg processRxBitsWEn, next_processRxBitsWEn;
+wire rst;
+reg [1:0]RxBitsOut, next_RxBitsOut;
+wire [1:0]RxWireDataIn;
+wire RxWireDataWEn;
+reg SIERxRdyOut, next_SIERxRdyOut;
+
+// diagram signals declarations
+reg [1:0]RxBits, next_RxBits;
+reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define LS_CONN_PROC_RX_BITS 4'b0110
+`define FS_CONN_CHK_RX_BITS1 4'b0111
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
+`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
+`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
+`define FS_CONN_PROC_RX_BITS1 4'b1100
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)
+begin
+ NextState_rcvr <= CurrState_rcvr;
+ // Set default values for outputs and signals
+ next_RXWaitCount <= RXWaitCount;
+ next_connectState <= connectState;
+ next_RXStMachCurrState <= RXStMachCurrState;
+ next_processRxBitsWEn <= processRxBitsWEn;
+ next_RxBitsOut <= RxBitsOut;
+ next_RxBits <= RxBits;
+ next_SIERxRdyOut <= SIERxRdyOut;
+ case (CurrState_rcvr) // synopsys parallel_case full_case
+ `WAIT_BIT:
+ begin
+ if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+ next_RxBits <= RxWireDataIn;
+ next_SIERxRdyOut <= 1'b0;
+ end
+ end
+ `START_SRX:
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_RXWaitCount <= 8'h00;
+ next_connectState <= `DISCONNECT;
+ next_RxBits <= 2'b00;
+ next_RxBitsOut <= 2'b00;
+ next_processRxBitsWEn <= 1'b0;
+ next_SIERxRdyOut <= 1'b1;
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `DISCNCT_CHK_RXBITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ else if (RxBits == `ONE_ZERO)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ONE_ZERO)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `LS_CONN_CHK_RX_BITS:
+ begin
+ if (processRxBitRdyIn == 1'b1)
+ begin
+ NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ next_processRxBitsWEn <= 1'b1;
+ next_RxBitsOut <= RxBits;
+ end
+ end
+ `LS_CONN_PROC_RX_BITS:
+ begin
+ next_processRxBitsWEn <= 1'b0;
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `FS_CONN_CHK_RX_BITS1:
+ begin
+ if (processRxBitRdyIn == 1'b1)
+ begin
+ NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ next_processRxBitsWEn <= 1'b1;
+ next_RxBitsOut <= RxBits;
+ next_SIERxRdyOut <= 1'b1;
+ //early indication of ready
+ end
+ end
+ `FS_CONN_PROC_RX_BITS1:
+ begin
+ next_processRxBitsWEn <= 1'b0;
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS:
+ begin
+ if (processRxBitRdyIn == 1'b1)
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ next_processRxBitsWEn <= 1'b1;
+ end
+ end
+ `WAIT_LS_DIS_PROC_RX_BITS:
+ begin
+ next_processRxBitsWEn <= 1'b0;
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `WAIT_FS_DIS_PROC_RX_BITS2:
+ begin
+ next_processRxBitsWEn <= 1'b0;
+ NextState_rcvr <= `WAIT_BIT;
+ next_SIERxRdyOut <= 1'b1;
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2:
+ begin
+ if (processRxBitRdyIn == 1'b1)
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ next_processRxBitsWEn <= 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_rcvr <= `START_SRX;
+ else
+ CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ connectState <= `DISCONNECT;
+ processRxBitsWEn <= 1'b0;
+ RxBitsOut <= 2'b00;
+ SIERxRdyOut <= 1'b1;
+ RXWaitCount <= 8'h00;
+ RXStMachCurrState <= `DISCONNECT_ST;
+ RxBits <= 2'b00;
+ end
+ else
+ begin
+ connectState <= next_connectState;
+ processRxBitsWEn <= next_processRxBitsWEn;
+ RxBitsOut <= next_RxBitsOut;
+ SIERxRdyOut <= next_SIERxRdyOut;
+ RXWaitCount <= next_RXWaitCount;
+ RXStMachCurrState <= next_RXStMachCurrState;
+ RxBits <= next_RxBits;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (revision 264)
@@ -0,0 +1,105 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=128
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: usbTxWireArbiter.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
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+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
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+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
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+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 153906,181456 "" ""
+L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 156447,157894 "" ""
+L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 156216,186076 "" ""
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+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
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+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 155985,199705 "" ""
+L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 155985,195316 "" ""
+L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 155985,190696 "" ""
+L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 156447,171985 "" ""
+L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 156447,167596 "" ""
+L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v (revision 264)
@@ -0,0 +1,268 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: endpMux.v,v 1.2 2004-12-18 14:36:18 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:05 sfielding
+// Created
+//
+//
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveDirectcontrol.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
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+END
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Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v (revision 264)
@@ -0,0 +1,406 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl.v,v 1.2 2004-12-18 14:36:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
+// Created
+//
+//
+module usbHostControl(
+ clk, rst,
+ //sendPacket
+ TxFifoRE, TxFifoData, TxFifoEmpty,
+ //getPacket
+ RxFifoWE, RxFifoData, RxFifoFull,
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //HCTxPortArbiter
+ HCTxPortEn, HCTxPortRdy,
+ HCTxPortData, HCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFSentIntOut,
+ connEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ hostControlSelect
+ );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [3:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut;
+wire connEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFSentIntOut(SOFSentIntOut),
+ .connEventIntOut(connEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .TxTransTypeReg(transType),
+ .TxSOFEnableReg(SOFEnable),
+ .TxAddrReg(TxAddr),
+ .TxEndPReg(TxEndP),
+ .frameNumIn(frameNum),
+ .RxPktStatusIn(RxPktStatus),
+ .RxPIDIn(RxPID),
+ .connectStateIn(connectStateOut),
+ .SOFSentIn(SOFSent),
+ .connEventIn(connectionEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .hostControlSelect(hostControlSelect),
+ .clrTransReq(clrTxReq),
+ .preambleEn(preAmbleEnable),
+ .SOFSync(SOFSyncEn),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(directCtrlPol),
+ .fullSpeedRate(directCtrlRate),
+ .transReq(transReq)
+
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus(RxPktStatus),
+ .clearTXReq(clrTxReq),
+ .clk(clk),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketArbiterGnt(HCTxGnt),
+ .sendPacketArbiterReq(HCTxReq),
+ .sendPacketPID(HC_PID),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(HC_SP_WEn),
+ .transDone(transDone),
+ .transReq(transReq),
+ .transType(transType) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl(SOFCntlCntl),
+ .HCTxPortData(SOFCntlData),
+ .HCTxPortGnt(SOFCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(SOFCntlReq),
+ .HCTxPortWEn(SOFCntlWEn),
+ .SOFEnable(SOFEnable),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable(SOFEnable),
+ .SOFSent(SOFSent),
+ .SOFSyncEn(SOFSyncEn),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketArbiterGnt(SOFTxGnt),
+ .sendPacketArbiterReq(SOFTxReq),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(SOF_SP_WEn) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt(HCTxGnt),
+ .HCTxReq(HCTxReq),
+ .HC_PID(HC_PID),
+ .HC_SP_WEn(HC_SP_WEn),
+ .SOFTxGnt(SOFTxGnt),
+ .SOFTxReq(SOFTxReq),
+ .SOF_SP_WEn(SOF_SP_WEn),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketPID(sendPacketCPPIDIn),
+ .sendPacketWEnable(sendPacketCPWEnIn) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID(sendPacketCPPIDIn),
+ .clk(clk),
+ .fullSpeedBitRate(sendPacketCPFSRate),
+ .fullSpeedPolarity(sendPacketCPFSPol),
+ .grabLineControl(sendPacketCPGrabLine),
+ .preAmbleEnable(preAmbleEnable),
+ .rst(rst),
+ .sendPacketCPReady(sendPacketCPReadyOut),
+ .sendPacketCPWEn(sendPacketCPWEnIn),
+ .sendPacketPID(sendPacketCPPIDOut),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl(sendPacketCntl),
+ .HCTxPortData(sendPacketData),
+ .HCTxPortGnt(sendPacketGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(sendPacketReq),
+ .HCTxPortWEn(sendPacketWEn),
+ .PID(sendPacketCPPIDOut),
+ .TxAddr(TxAddr),
+ .TxEndP(TxEndP),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .frameNum(frameNum),
+ .rst(rst),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+directControl u_directControl
+ (.HCTxPortCntl(directCntlCntl),
+ .HCTxPortData(directCntlData),
+ .HCTxPortGnt(directCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(directCntlReq),
+ .HCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl(HCTxPortCtrl),
+ .HCTxPortData(HCTxPortData),
+ .HCTxPortWEnable(HCTxPortEn),
+ .SOFCntlCntl(SOFCntlCntl),
+ .SOFCntlData(SOFCntlData),
+ .SOFCntlGnt(SOFCntlGnt),
+ .SOFCntlReq(SOFCntlReq),
+ .SOFCntlWEn(SOFCntlWEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+getPacket u_getPacket
+ (.RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXPktStatus(RxPktStatus),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+speedCtrlMux u_speedCtrlMux
+ (.directCtrlRate(directCtrlRate),
+ .directCtrlPol(directCtrlPol),
+ .sendPacketRate(sendPacketCPFSRate),
+ .sendPacketPol(sendPacketCPFSPol),
+ .sendPacketSel(sendPacketCPGrabLine),
+ .fullSpeedRate(fullSpeedRate),
+ .fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .connectionEventOut(connectionEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v (revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v
+// $Id: usbHostControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+`define SOF_TX_TIME 16'hbb80 //Correct SOF interval for 48MHz clock
+//`define SOF_TX_MARGIN 2
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (revision 264)
@@ -0,0 +1,614 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=955
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIETransmitter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: SIETransmitter.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+A 835 9 4 TEXT "Actions" | 153876,205564 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 5'h0;"
+W 574 458 0 567 543 BEZIER "Transitions" | 44298,153135 48358,141709 56556,119871 60616,108445
+A 563 530 4 TEXT "Actions" | 161517,83673 1 0 0 "USBWireWEn <= 1'b0;"
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+I 572 458 0 Builtin Entry | 44780,253519
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/5/"
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/37/"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+A 562 532 4 TEXT "Actions" | 37965,60741 1 0 0 "USBWireWEn <= 1'b0;"
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+I 872 360 0 Builtin Exit | 188676,86316
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 92777,123293 108857,123025
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+I 599 489 0 Builtin Entry | 81144,219546
+I 606 489 0 Builtin Exit | 138120,51311
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+ 77086,119473 72191,126878 71751,132901 71312,138925\
+ 74451,155618 76866,160637 79282,165657 85808,169046\
+ 89165,169297 92522,169548 98692,166980 102143,165788
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/2/"
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 890 885 0 TEXT "State Labels" | 60832,129059 1 0 0 "CHK_FIN\n/1/"
+C 889 888 0 TEXT "Conditions" | 62558,122269 1 0 0 "i == 5'h7"
+W 888 217 8193 885 221 BEZIER "Transitions" | 60935,122562 61052,115893 61713,104679 61830,98010
+W 887 217 8194 885 883 BEZIER "Transitions" | 54752,126763 48791,125383 38452,124409 34248,125570\
+ 30044,126731 25149,134136 24709,140159 24270,146183\
+ 27409,162876 29824,167895 32240,172915 38766,176304\
+ 42123,176555 45480,176806 51650,174238 55101,173046
+A 886 885 4 TEXT "Actions" | 76742,138579 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 885 217 0 ELLIPSE "States" | 60832,129059 6500 6500
+L 884 883 0 TEXT "State Labels" | 60901,170112 1 0 0 "STX_WAIT_RDY\n/26/"
+S 883 217 0 ELLIPSE "States" | 60901,170112 6500 6500
+C 882 880 0 TEXT "Conditions" | 61330,163577 1 0 0 "USBWireRdy == 1'b1"
+A 881 880 16 TEXT "Actions" | 49805,157344 1 0 0 "USBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 880 217 0 883 885 BEZIER "Transitions" | 60836,163644 60774,157457 60714,141730 60652,135543
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+ 161730,108850 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+I 909 224 0 Builtin Exit | 108872,88817
+I 908 224 0 Builtin Entry | 85162,237767
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/33/"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/43/"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+ 43361,99065 46384,95576 54928,94878 63472,94181\
+ 94207,96080 109784,96428
+I 363 360 0 Builtin Entry | 47792,257148
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 636 610 0 Builtin Entry | 71380,236621
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+W 927 360 0 933 929 BEZIER "Transitions" | 144010,222256 143885,215969 143879,198227 143754,191940
+C 924 922 0 TEXT "Conditions" | 97818,190135 1 0 0 "USBWireRdy == 1'b1"
+A 923 922 16 TEXT "Actions" | 93859,209922 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit; \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 922 360 0 929 453 BEZIER "Transitions" | 138043,187612 109537,196045 81451,206574 52945,215007
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+A 920 888 16 TEXT "Actions" | 54464,112031 1 0 0 "USBWireReq <= 1'b0;"
+A 917 371 4 TEXT "Actions" | 71825,218040 1 0 0 "i <= 5'h0;"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+C 378 377 0 TEXT "Conditions" | 56860,208360 1 0 0 "USBWireGnt == 1'b1"
+W 377 217 0 371 883 BEZIER "Transitions" | 52975,210241 55849,199016 58723,187790 61597,176565
+A 374 373 16 TEXT "Actions" | 43761,237148 1 0 0 "USBWireReq <= 1'b1;"
+W 373 217 0 220 371 BEZIER "Transitions" | 41882,245025 44900,239618 46527,227520 49545,222113
+S 371 217 0 ELLIPSE "States" | 53178,216725 6500 6500
+L 370 371 0 TEXT "State Labels" | 53178,216725 1 0 0 "STX_WAIT_GNT\n/25/"
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/7/"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/40/"
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 645 610 0 Builtin Exit | 114540,97930
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/29/"
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 913 912 0 Builtin Entry | 86360,167640
+I 914 912 0 Builtin Exit | 129540,111760
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+A 937 453 4 TEXT "Actions" | 60460,224205 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+L 934 933 0 TEXT "State Labels" | 144285,228746 1 0 0 "WAIT_GNT\n/49/"
+S 933 360 12288 ELLIPSE "States" | 144285,228746 6500 6500
+A 932 931 16 TEXT "Actions" | 105661,247407 1 0 0 "USBWireReq <= 1'b1;"
+W 931 360 0 363 933 BEZIER "Transitions" | 51554,257148 80200,248283 109429,239528 138075,230663
+L 930 929 0 TEXT "State Labels" | 144175,185833 1 0 0 "WAIT_RDY_WIRE\n/48/"
+S 929 360 8192 ELLIPSE "States" | 144175,185458 6500 6500
+C 928 927 0 TEXT "Conditions" | 145669,221771 1 0 0 "USBWireGnt == 1'b1"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/31/"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 663 624 0 Builtin Entry | 59190,254840
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+ 104039,47385 110550,45085 113597,43935
+I 671 624 0 Builtin Exit | 116402,43935
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/50/"
+S 939 633 16384 ELLIPSE "States" | 39277,179580 6500 6500
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1; \ni <= i + 1'b1;"
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/38/"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/42/"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/27/"
+I 682 633 0 Builtin Exit | 119917,39891
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/51/"
+S 947 734 20480 ELLIPSE "States" | 160390,197270 6500 6500
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/52/"
+S 952 624 24576 ELLIPSE "States" | 35474,185224 6500 6500
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/34/"
+I 417 17 0 Builtin Entry | 44586,243455
+I 418 17 0 Builtin Exit | 145044,30588
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+ 28677,128486 23782,135891 23342,141914 22903,147938\
+ 26042,164631 28457,169650 30873,174670 37399,178059\
+ 40756,178310 44113,178561 50283,175993 53734,174801
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/6/"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/41/"
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/35/"
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/10/"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+I 711 480 0 Builtin Entry | 43257,253243
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 713 480 0 Builtin Exit | 85376,122104
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 715 471 0 Builtin Exit | 140592,59380
+I 716 471 0 Builtin Entry | 83616,227615
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/46/"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 731 727 0 Builtin Entry | 71380,236621
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/28/"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+I 738 727 0 Builtin Exit | 114540,97930
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/36/"
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+I 744 734 0 Builtin Exit | 116402,43935
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+I 750 734 0 Builtin Entry | 59190,254840
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/3/"
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 220 217 0 Builtin Entry | 38120,245025
+I 221 217 0 Builtin Exit | 61830,96075
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/32/"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+I 762 733 0 Builtin Exit | 119917,39891
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+ 48829,42592 51359,37532 61605,36267 71852,35002\
+ 109061,35775 128289,35775
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+ 48196,74723 50474,70169 60657,69030 70840,67892\
+ 108432,68626 127660,68626
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+ 46931,109511 49715,104703 60024,103501 70334,102300\
+ 108774,103037 128002,103037
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+ 46299,139871 48829,136075 59202,135063 69575,134052\
+ 106314,125693 125795,125567
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/8/"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/39/"
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/45/"
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+I 787 733 0 Builtin Entry | 62705,250796
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/4/"
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+ 31250,150650 32250,89650 34750,72525 37250,55400\
+ 46250,47900 56000,46150 65750,44400 95896,46012\
+ 103573,44899 111250,43786 113107,43935 113607,43935
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+ 128857,67252 162473,65260 171997,66691 181521,68123\
+ 186003,75843 187123,97692 188244,119542 188244,199222\
+ 184384,221196 180525,243170 165087,251388 155563,253628\
+ 146039,255869 123379,256617 115100,254625 106821,252633\
+ 98206,243956 92977,239599
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+I 540 458 0 Builtin Exit | 68103,43333
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/44/"
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v (revision 264)
@@ -0,0 +1,416 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processrxbit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processRxBit.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processRxBitsWEn;
+input processRxByteRdy;
+input rst;
+input [1:0]RxBitsIn;
+output processRxBitRdy;
+output processRxByteWEn;
+output resumeDetected;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processRxBitRdy, next_processRxBitRdy;
+wire processRxBitsWEn;
+wire processRxByteRdy;
+reg processRxByteWEn, next_processRxByteWEn;
+reg resumeDetected, next_resumeDetected;
+wire rst;
+wire [1:0]RxBitsIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg [1:0]oldRXBits, next_oldRXBits;
+reg [3:0]resumeWaitCnt, next_resumeWaitCnt;
+reg [3:0]RXBitCount, next_RXBitCount;
+reg [1:0]RxBits, next_RxBits;
+reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg [7:0]RXByte, next_RXByte;
+reg [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+ NextState_prRxBit <= CurrState_prRxBit;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOut <= RxDataOut;
+ next_resumeDetected <= resumeDetected;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState;
+ next_RxBits <= RxBits;
+ next_RXSameBitCount <= RXSameBitCount;
+ next_RXBitCount <= RXBitCount;
+ next_oldRXBits <= oldRXBits;
+ next_RXByte <= RXByte;
+ next_bitStuffError <= bitStuffError;
+ next_resumeWaitCnt <= resumeWaitCnt;
+ next_processRxBitRdy <= processRxBitRdy;
+ case (CurrState_prRxBit) // synopsys parallel_case full_case
+ `START:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOut <= 8'h00;
+ next_resumeDetected <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_RxBits <= 2'b00;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h0;
+ next_oldRXBits <= 2'b00;
+ next_RXByte <= 8'h00;
+ next_bitStuffError <= 1'b0;
+ next_resumeWaitCnt <= 4'h0;
+ next_processRxBitRdy <= 1'b1;
+ NextState_prRxBit <= `WAIT_BITS;
+ end
+ `WAIT_BITS:
+ begin
+ if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ end
+ `IDLE_FIRST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+ next_RXSameBitCount <= 4'h1;
+ next_RXBitCount <= 4'h1;
+ next_oldRXBits <= RxBits;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `IDLE_CHK_KBIT:
+ begin
+ if (RxBits == KBit)
+ begin
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `IDLE_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START;
+ //start of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_LAST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_CHK_SE0:
+ begin
+ next_bitStuffError <= 1'b0;
+ if (RxBits == `SE0)
+ begin
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+ if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
+ next_bitStuffError <= 1'b1;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1, RXByte[7:1]};
+ //RZ bit <= 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0, RXByte[7:1]};
+ //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h1;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP;
+ //end of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_DATA_DESTUFF:
+ begin
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+ end
+ else if (bitStuffError == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `DATA_RX_BYTE_SEND2:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_BYTE_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+ next_RXBitCount <= 4'h0;
+ next_RxDataOut <= RXByte;
+ next_RxCtrlOut <= `DATA_STREAM;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_ERROR_CHK_RES:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ if (RxBits == JBit) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+ //check for resume
+ next_resumeWaitCnt <= 0;
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_ERROR_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `RES_RX_CHK:
+ begin
+ if (RxBits != KBit) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+ next_resumeDetected <= 1'b1;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `RES_END_CHK1:
+ begin
+ if (RxBits != KBit) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_resumeDetected <= 1'b0;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxBit <= `START;
+ else
+ CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processRxByteWEn <= 1'b0;
+ RxCtrlOut <= 8'h00;
+ RxDataOut <= 8'h00;
+ resumeDetected <= 1'b0;
+ processRxBitRdy <= 1'b1;
+ RXBitStMachCurrState <= `IDLE_BIT_ST;
+ RxBits <= 2'b00;
+ RXSameBitCount <= 4'h0;
+ RXBitCount <= 4'h0;
+ oldRXBits <= 2'b00;
+ RXByte <= 8'h00;
+ bitStuffError <= 1'b0;
+ resumeWaitCnt <= 4'h0;
+ end
+ else
+ begin
+ processRxByteWEn <= next_processRxByteWEn;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOut <= next_RxDataOut;
+ resumeDetected <= next_resumeDetected;
+ processRxBitRdy <= next_processRxBitRdy;
+ RXBitStMachCurrState <= next_RXBitStMachCurrState;
+ RxBits <= next_RxBits;
+ RXSameBitCount <= next_RXSameBitCount;
+ RXBitCount <= next_RXBitCount;
+ oldRXBits <= next_oldRXBits;
+ RXByte <= next_RXByte;
+ bitStuffError <= next_bitStuffError;
+ resumeWaitCnt <= next_resumeWaitCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v (revision 264)
@@ -0,0 +1,358 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processTxByte.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteWEn;
+input rst;
+input [7:0]TxByteCtrlIn;
+input [7:0]TxByteIn;
+input USBWireGnt;
+input USBWireRdy;
+output processTxByteRdy;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processTxByteRdy, next_processTxByteRdy;
+wire processTxByteWEn;
+wire rst;
+wire [7:0]TxByteCtrlIn;
+wire [7:0]TxByteIn;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [3:0]i, next_i;
+reg [7:0]TxByte, next_TxByte;
+reg [7:0]TxByteCtrl, next_TxByteCtrl;
+reg [1:0]TXLineState, next_TXLineState;
+reg [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 4'b0000
+`define PTBY_WAIT_EN 4'b0001
+`define SEND_BYTE_UPDATE_BYTE 4'b0010
+`define SEND_BYTE_WAIT_RDY 4'b0011
+`define SEND_BYTE_CHK 4'b0100
+`define SEND_BYTE_BIT_STUFF 4'b0101
+`define SEND_BYTE_WAIT_RDY2 4'b0110
+`define SEND_BYTE_CHK_FIN 4'b0111
+`define PTBY_WAIT_GNT 4'b1000
+`define STOP_SND_SE0_2 4'b1001
+`define STOP_SND_SE0_1 4'b1010
+`define STOP_CHK 4'b1011
+`define STOP_SND_J 4'b1100
+`define STOP_SND_IDLE 4'b1101
+`define STOP_FIN 4'b1110
+
+reg [3:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin
+ NextState_prcTxB <= CurrState_prcTxB;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_USBWireReq <= USBWireReq;
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_TxByte <= TxByte;
+ next_TxByteCtrl <= TxByteCtrl;
+ next_TXLineState <= TXLineState;
+ next_TXOneCount <= TXOneCount;
+ case (CurrState_prcTxB) // synopsys parallel_case full_case
+ `START_PTBY:
+ begin
+ next_processTxByteRdy <= 1'b0;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_i <= 4'h0;
+ next_TxByte <= 8'h00;
+ next_TxByteCtrl <= 8'h00;
+ next_TXLineState <= 2'b0;
+ next_TXOneCount <= 4'h0;
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `PTBY_WAIT_EN:
+ begin
+ next_processTxByteRdy <= 1'b1;
+ if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TXOneCount <= 1;
+ next_TXLineState <= JBit;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (processTxByteWEn == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_i <= 4'h0;
+ end
+ end
+ `PTBY_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ end
+ `SEND_BYTE_UPDATE_BYTE:
+ begin
+ next_i <= i + 1'b1;
+ next_TxByte <= {1'b0, TxByte[7:1] };
+ if (TxByte[0] == 1'b1) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h1;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+ end
+ `SEND_BYTE_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (TXOneCount == 4'h6)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+ end
+ else if (i != 4'h8)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ else
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ end
+ `SEND_BYTE_BIT_STUFF:
+ begin
+ next_TXOneCount <= 4'h1;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+ end
+ `SEND_BYTE_WAIT_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == 4'h8)
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ else
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ end
+ `STOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_J;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_SND_SE0_1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_CHK:
+ begin
+ if (TxByteCtrl == `DATA_STOP)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_1;
+ end
+ else
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ end
+ `STOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_SND_IDLE:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `STOP_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prcTxB <= `START_PTBY;
+ else
+ CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processTxByteRdy <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ USBWireReq <= 1'b0;
+ USBWireWEn <= 1'b0;
+ i <= 4'h0;
+ TxByte <= 8'h00;
+ TxByteCtrl <= 8'h00;
+ TXLineState <= 2'b0;
+ TXOneCount <= 4'h0;
+ end
+ else
+ begin
+ processTxByteRdy <= next_processTxByteRdy;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ USBWireReq <= next_USBWireReq;
+ USBWireWEn <= next_USBWireWEn;
+ i <= next_i;
+ TxByte <= next_TxByte;
+ TxByteCtrl <= next_TxByteCtrl;
+ TXLineState <= next_TXLineState;
+ TXOneCount <= next_TXOneCount;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v (revision 264)
@@ -0,0 +1,113 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC16.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:04 sfielding
+// Created
+//
+//
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [15:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [15:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 16'hffff;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0)
+ begin
+ if (CRCEn == 1'b1) begin
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ ready <= 1'b0;
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[15:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == 4'h7)
+ begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (revision 264)
@@ -0,0 +1,205 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbTxWireArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbTxWireArbiter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input clk;
+input prcTxByteCtrl;
+input [1:0]prcTxByteData;
+input prcTxByteReq;
+input prcTxByteWEn;
+input rst;
+input SIETxCtrl;
+input [1:0]SIETxData;
+input SIETxReq;
+input SIETxWEn;
+input USBWireRdyIn;
+output prcTxByteGnt;
+output SIETxGnt;
+output [1:0]TxBits;
+output TxCtl;
+output USBWireRdyOut;
+output USBWireWEn;
+
+wire clk;
+wire prcTxByteCtrl;
+wire [1:0]prcTxByteData;
+reg prcTxByteGnt, next_prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire rst;
+wire SIETxCtrl;
+wire [1:0]SIETxData;
+reg SIETxGnt, next_SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+reg [1:0]TxBits, next_TxBits;
+reg TxCtl, next_TxCtl;
+wire USBWireRdyIn;
+reg USBWireRdyOut, next_USBWireRdyOut;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+if (muxSIENotPTXB == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+ NextState_txWireArb <= CurrState_txWireArb;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt;
+ next_SIETxGnt <= SIETxGnt;
+ next_muxSIENotPTXB <= muxSIENotPTXB;
+ case (CurrState_txWireArb) // synopsys parallel_case full_case
+ `START_TARB:
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ end
+ `TARB_WAIT_REQ:
+ begin
+ if (prcTxByteReq == 1'b1)
+ begin
+ NextState_txWireArb <= `PTXB_ACT;
+ next_prcTxByteGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b0;
+ end
+ else if (SIETxReq == 1'b1)
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT;
+ next_SIETxGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b1;
+ end
+ end
+ `PTXB_ACT:
+ begin
+ if (prcTxByteReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_prcTxByteGnt <= 1'b0;
+ end
+ end
+ `SIE_TX_ACT:
+ begin
+ if (SIETxReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_SIETxGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_txWireArb <= `START_TARB;
+ else
+ CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ prcTxByteGnt <= 1'b0;
+ SIETxGnt <= 1'b0;
+ muxSIENotPTXB <= 1'b0;
+ end
+ else
+ begin
+ prcTxByteGnt <= next_prcTxByteGnt;
+ SIETxGnt <= next_SIETxGnt;
+ muxSIENotPTXB <= next_muxSIENotPTXB;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v (revision 264)
@@ -0,0 +1,220 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMux.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:05 sfielding
+// Created
+//
+//
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v (revision 264)
@@ -0,0 +1,207 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveDirectcontrol.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+ `START_SDC:
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf (revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveSendpacket.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
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+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
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+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
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+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
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+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
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+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
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+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
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+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
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+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
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+I 173 0 130 Builtin InPort | 35299,213676 "" ""
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+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
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+ 139792,40658 161594,38692 165369,38074 169145,37457\
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+ 57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
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+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
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+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
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+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
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+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
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+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v (revision 264)
@@ -0,0 +1,397 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBSlaveControlBI.v,v 1.2 2004-12-18 14:36:17 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:10 sfielding
+// Created
+//
+//
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0SendStall <= dataIn[3];
+ EP0DataSequence <= dataIn[2];
+ EP0SetReady <= dataIn[1];
+ EP0Enable <= dataIn[0];
+ end
+ `EP1_CTRL_REG : begin
+ EP1SendStall <= dataIn[3];
+ EP1DataSequence <= dataIn[2];
+ EP1SetReady <= dataIn[1];
+ EP1Enable <= dataIn[0];
+ end
+ `EP2_CTRL_REG : begin
+ EP2SendStall <= dataIn[3];
+ EP2DataSequence <= dataIn[2];
+ EP2SetReady <= dataIn[1];
+ EP2Enable <= dataIn[0];
+ end
+ `EP3_CTRL_REG : begin
+ EP3SendStall <= dataIn[3];
+ EP3DataSequence <= dataIn[2];
+ EP3SetReady <= dataIn[1];
+ EP3Enable <= dataIn[0];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn[4];
+ clrSOFReq <= dataIn[3];
+ clrResetReq <= dataIn[2];
+ clrResInReq <= dataIn[1];
+ clrTransDoneReq <= dataIn[0];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (NAKSentIn == 1'b1)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedIn == 1'b1)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventIn == 1'b1)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0Ready == 1'b1)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1Ready == 1'b1)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2Ready == 1'b1)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3Ready == 1'b1)
+ EP3Ready <= 1'b0;
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
+begin
+ endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+ // async read mux
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+ endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+ endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
+ endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNum)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+ `EP0_STS_REG : dataOut <= EP0StatusReg;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+ `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+ `EP1_STS_REG : dataOut <= EP1StatusReg;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+ `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+ `EP2_STS_REG : dataOut <= EP2StatusReg;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+ `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+ `EP3_STS_REG : dataOut <= EP3StatusReg;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
+ `SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v (revision 264)
@@ -0,0 +1,203 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sctxportarbiter.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input SCTxPortRdyIn;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output directCntlGnt;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output sendPacketGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ:
+ begin
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ end
+ `SARB_SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `SARB_DC:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxDCEn <= 1'b0;
+ end
+ else
+ begin
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxDCEn <= next_muxDCEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveGetpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output ACKRxed;
+output bitStuffError;
+output CRCError;
+output dataSequence;
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output [3:0]RxPID;
+output RXTimeOut;
+
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+wire [7:0]RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXOverflow <= 1'b0;
+ ACKRxed <= 1'b0;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXTimeOut <= 1'b0;
+ RxPID <= 4'h0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByteOld <= 8'h00;
+ end
+ else
+ begin
+ RXOverflow <= next_RXOverflow;
+ ACKRxed <= next_ACKRxed;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXTimeOut <= next_RXTimeOut;
+ RxPID <= next_RxPID;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ RXByteOld <= next_RXByteOld;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf (revision 264)
@@ -0,0 +1,358 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=789
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slavecontroller.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 376
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 420
+PAGE 25400,0 215900,279400
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+END
+INSTHEADER 551
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+END
+INSTHEADER 580
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 617
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+END
+INSTHEADER 698
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+UPPERLEFT 0,0
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+END
+INSTHEADER 15
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+ 30330,86104 25492,143212 35905,156667 46318,170122\
+ 96612,168665 117496,167729
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+ 192923,24221 173766,19421 163644,19865 153522,20309\
+ 122483,20608 111915,23020 101347,25432 81761,37919\
+ 69710,37919
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+S 15 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,252232 1 0 0 "Module: slavecontroller"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 588 589 0 Builtin Entry | 89368,239805
+I 587 589 0 Builtin Exit | 192962,45432
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+C 607 601 0 TEXT "Conditions" | 114440,220845 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 606 589 0 588 605 BEZIER "Transitions" | 89368,237478 89903,233730 89797,226993 90332,223245
+S 605 589 53248 ELLIPSE "States" | 91340,216824 6500 6500
+L 604 605 0 TEXT "State Labels" | 91340,216824 1 0 0 "CHK_RDY\n/10/"
+A 603 596 4 TEXT "Actions" | 174409,172080 1 0 0 "sendPacketWEn <= 1'b0;"
+W 601 589 8193 605 596 BEZIER "Transitions" | 97839,216722 109714,216534 162558,220059 167812,183210
+W 600 589 8192 596 587 BEZIER "Transitions" | 168405,170293 203966,131503 199503,89144 196184,45432
+A 599 601 16 TEXT "Actions" | 124386,212388 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+C 598 600 0 TEXT "Conditions" | 159138,161356 1 0 0 "sendPacketRdy == 1'b1"
+L 597 596 0 TEXT "State Labels" | 169718,177574 1 0 0 "NAK_STALL\n/9/"
+S 596 589 49152 ELLIPSE "States" | 168684,176772 6500 6500
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 620 618 0 Builtin Exit | 144780,101600
+I 619 618 0 Builtin Entry | 96520,152400
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+A 615 612 16 TEXT "Actions" | 110702,185120 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 614 612 0 TEXT "Conditions" | 69153,194735 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+W 613 589 8195 605 617 BEZIER "Transitions" | 86536,212447 76974,203420 61686,186612 53042,177585
+W 612 589 8194 605 596 BEZIER "Transitions" | 91984,210359 90899,202871 142592,172810 163035,179986
+L 639 640 0 TEXT "State Labels" | 125814,48840 1 0 0 "GET_RESP\n/12/"
+A 638 631 16 TEXT "Actions" | 118603,107061 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 637 630 16 TEXT "Actions" | 36344,101376 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 636 630 0 TEXT "Conditions" | 29568,129096 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+W 631 589 8194 617 629 BEZIER "Transitions" | 54075,173680 59927,171524 83885,163128 122946,146882\
+ 162008,130636 145376,121704 139603,106244 133831,90784\
+ 72380,75586 70378,71274
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+ 35574,160974 35266,154506 35651,142263 36036,130020\
+ 37884,87516 41041,76736 44198,65956 54978,65340\
+ 57981,65109 60984,64878 60379,64505 60995,64351
+S 629 589 61440 ELLIPSE "States" | 67392,65502 6500 6500
+L 628 629 0 TEXT "State Labels" | 67392,65502 1 0 0 "DATA\n/11/"
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/13/"
+S 654 559 69632 ELLIPSE "States" | 92422,152802 6500 6500
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+I 650 559 0 Builtin Exit | 194044,45058
+I 649 559 0 Builtin Entry | 37971,243103
+C 647 646 0 TEXT "Conditions" | 140247,52755 1 0 0 "getPacketRdy == 1'b1"
+W 646 589 0 640 587 BEZIER "Transitions" | 132288,49411 139757,47794 182271,47049 189740,45432
+A 645 640 4 TEXT "Actions" | 108652,38924 1 0 0 "getPacketREn <= 1'b0;"
+A 644 641 16 TEXT "Actions" | 75293,54584 1 0 0 "getPacketREn <= 1'b1;"
+C 643 641 0 TEXT "Conditions" | 73811,60869 1 0 0 "sendPacketRdy == 1'b1"
+A 642 629 4 TEXT "Actions" | 76076,71808 1 0 0 "sendPacketWEn <= 1'b0;"
+W 641 589 0 629 640 BEZIER "Transitions" | 73191,62566 81815,59948 110822,52759 119446,50141
+S 640 589 65536 ELLIPSE "States" | 125814,48840 6500 6500
+I 381 377 0 Builtin Exit | 206487,14249
+I 380 377 0 Builtin Entry | 48940,236580
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 376 6 94212 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+I 96 722 0 Builtin Reset | 76296,129336
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/14/"
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+S 656 559 73728 ELLIPSE "States" | 109789,85208 5889 6500
+I 399 377 0 Builtin Link | 54419,17564
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+S 786 377 98304 ELLIPSE "States" | 123152,53144 6500 6500
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/17/"
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+ 60717,97705 62441,84600 62616,78575
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+ 53866,34676 56339,23332 57169,17564
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+ 209214,43082 209522,23062 208983,17094 208444,11127\
+ 205980,7277 191773,6353 177567,5429 123205,5583\
+ 106804,9317 90403,13052 79161,27836 75696,31763\
+ 72231,35690 70888,36159 69579,36621
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v (revision 264)
@@ -0,0 +1,501 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl.v,v 1.2 2004-12-18 14:36:21 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:10 sfielding
+// Created
+//
+//
+
+module usbSlaveControl(
+ clk, rst,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(clk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone)
+ );
+
+
+endpMux u_endpMux (
+ .clk(clk),
+ .rst(rst),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rst),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (revision 264)
@@ -0,0 +1,276 @@
+
+
+USBHostControlBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address , dataIn , dataOut , writeEn ,
+ strobe_i ,
+ clk , rst ,
+ SOFSentIntOut , connEventIntOut , resumeIntOut , transDoneIntOut ,
+ TxTransTypeReg , TxSOFEnableReg ,
+ TxAddrReg , TxEndPReg , frameNumIn ,
+ RxPktStatusIn , RxPIDIn ,
+ connectStateIn ,
+ SOFSentIn , connEventIn , resumeIntIn , transDoneIn ,
+ hostControlSelect ,
+ clrTransReq ,
+ preambleEn ,
+ SOFSync ,
+ TxLineState ,
+ LineDirectControlEn ,
+ fullSpeedPol ,
+ fullSpeedRate ,
+ transReq
+ );
+input [3 :0 ] address ;
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+output SOFSentIntOut ;
+output connEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+
+output [1 :0 ] TxTransTypeReg ;
+output TxSOFEnableReg ;
+output [6 :0 ] TxAddrReg ;
+output [3 :0 ] TxEndPReg ;
+input [10 :0 ] frameNumIn ;
+input [7 :0 ] RxPktStatusIn ;
+input [3 :0 ] RxPIDIn ;
+input [1 :0 ] connectStateIn ;
+input SOFSentIn ;
+input connEventIn ;
+input resumeIntIn ;
+input transDoneIn ;
+input hostControlSelect ;
+input clrTransReq ;
+output preambleEn ;
+output SOFSync ;
+output [1 :0 ] TxLineState ;
+output LineDirectControlEn ;
+output fullSpeedPol ;
+output fullSpeedRate ;
+output transReq ;
+
+wire [3 :0 ] address ;
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+
+reg SOFSentIntOut ;
+reg connEventIntOut ;
+reg resumeIntOut ;
+reg transDoneIntOut ;
+
+reg [1 :0 ] TxTransTypeReg ;
+reg TxSOFEnableReg ;
+reg [6 :0 ] TxAddrReg ;
+reg [3 :0 ] TxEndPReg ;
+wire [10 :0 ] frameNumIn ;
+wire [7 :0 ] RxPktStatusIn ;
+wire [3 :0 ] RxPIDIn ;
+wire [1 :0 ] connectStateIn ;
+
+wire SOFSentIn ;
+wire connEventIn ;
+wire resumeIntIn ;
+wire transDoneIn ;
+wire hostControlSelect ;
+wire clrTransReq ;
+reg preambleEn ;
+reg SOFSync ;
+reg [1 :0 ] TxLineState ;
+reg LineDirectControlEn ;
+reg fullSpeedPol ;
+reg fullSpeedRate ;
+reg transReq ;
+
+//internal wire and regs
+reg [1 :0 ] TxControlReg ;
+reg [4 :0 ] TxLineControlReg ;
+reg clrSOFReq ;
+reg clrConnEvtReq ;
+reg clrResInReq ;
+reg clrTransDoneReq ;
+reg SOFSentInt ;
+reg connEventInt ;
+reg resumeInt ;
+reg transDoneInt ;
+reg [3 :0 ] interruptMaskReg ;
+reg setTransReq ;
+
+//sync write demux
+always @(posedge clk )
+begin
+ clrSOFReq <= 1'b0 ;
+ clrConnEvtReq <= 1'b0 ;
+ clrResInReq <= 1'b0 ;
+ clrTransDoneReq <= 1'b0 ;
+ setTransReq <= 1'b0 ;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1 )
+ begin
+ case (address )
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn [2 ];
+ SOFSync <= dataIn [1 ];
+ setTransReq <= dataIn [0 ];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn [1 :0 ];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn [4 :0 ];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn [0 ];
+ `TX_ADDR_REG : TxAddrReg <= dataIn [6 :0 ];
+ `TX_ENDP_REG : TxEndPReg <= dataIn [3 :0 ];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn [3 ];
+ clrConnEvtReq <= dataIn [2 ];
+ clrResInReq <= dataIn [1 ];
+ clrTransDoneReq <= dataIn [0 ];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn [3 :0 ];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk )
+begin
+ if (SOFSentIn == 1'b1 )
+ SOFSentInt <= 1'b1 ;
+ else if (clrSOFReq == 1'b1 )
+ SOFSentInt <= 1'b0 ;
+
+ if (connEventIn == 1'b1 )
+ connEventInt <= 1'b1 ;
+ else if (clrConnEvtReq == 1'b1 )
+ connEventInt <= 1'b0 ;
+
+ if (resumeIntIn == 1'b1 )
+ resumeInt <= 1'b1 ;
+ else if (clrResInReq == 1'b1 )
+ resumeInt <= 1'b0 ;
+
+ if (transDoneIn == 1'b1 )
+ transDoneInt <= 1'b1 ;
+ else if (clrTransDoneReq == 1'b1 )
+ transDoneInt <= 1'b0 ;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt ) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg [`TRANS_DONE_BIT ];
+ resumeIntOut <= resumeInt & interruptMaskReg [`RESUME_INT_BIT ];
+ connEventIntOut <= connEventInt & interruptMaskReg [`CONNECTION_EVENT_BIT ];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg [`SOF_SENT_BIT ];
+end
+
+//transaction request set/clear
+always @(posedge clk )
+begin
+ if (setTransReq == 1'b1 )
+ transReq <= 1'b1 ;
+ else if (clrTransReq == 1'b1 )
+ transReq <= 1'b0 ;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg ) begin
+ TxLineState <= TxLineControlReg [`TX_LINE_STATE_MSBIT :`TX_LINE_STATE_LSBIT ];
+ LineDirectControlEn <= TxLineControlReg [`DIRECT_CONTROL_BIT ];
+ fullSpeedPol <= TxLineControlReg [`FULL_SPEED_LINE_POLARITY_BIT ];
+ fullSpeedRate <= TxLineControlReg [`FULL_SPEED_LINE_RATE_BIT ];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq )
+begin
+ case (address )
+ `TX_CONTROL_REG : dataOut <= {5'b00000 , preambleEn , SOFSync , transReq } ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000 , TxTransTypeReg };
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000 , TxLineControlReg };
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000 , TxSOFEnableReg };
+ `TX_ADDR_REG : dataOut <= {1'b0 , TxAddrReg };
+ `TX_ENDP_REG : dataOut <= {4'h0 , TxEndPReg };
+ `FRAME_NUM_MSB_REG : dataOut <= frameNumIn [10 :3 ];
+ `FRAME_NUM_LSB_REG : dataOut <= {5'b00000 , frameNumIn [2 :0 ]};
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0 , SOFSentInt , connEventInt , resumeInt , transDoneInt };
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0 , interruptMaskReg };
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn ;
+ `RX_PID_REG : dataOut <= {4'b0000 , RxPIDIn };
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000 , connectStateIn };
+ default : dataOut <= 8'h00 ;
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v (revision 264)
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+ clk,
+ rst,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk;
+wire rst;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoFull(fifoFull),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v (revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// simFifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module simFifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+ dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+ if (writeEn == 1'b1)
+ buffer[addrIn] <= dataIn;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v (revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveRxStatusMonitor.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:09 sfielding
+// Created
+//
+//
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v (revision 264)
@@ -0,0 +1,478 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slavecontroller.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input bitStuffError;
+input clk;
+input CRCError;
+input getPacketRdy;
+input rst;
+input [7:0]RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0]RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input sendPacketRdy;
+input [3:0]USBEndPControlReg;
+input [6:0]USBTgtAddress;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output [10:0]frameNum;
+output getPacketREn;
+output NAKSent;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output SOFRxed;
+output stallSent;
+output transDone;
+output [3:0]USBEndP;
+output [1:0]USBEndPNakTransTypeReg;
+output [1:0]USBEndPTransTypeReg;
+
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+wire CRCError;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg [10:0]frameNum, next_frameNum;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+reg NAKSent, next_NAKSent;
+wire rst;
+wire [7:0]RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0]RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg SOFRxed, next_SOFRxed;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+reg [3:0]USBEndP, next_USBEndP;
+wire [3:0]USBEndPControlReg;
+reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [7:0]PIDByte, next_PIDByte;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_getPacketREn <= getPacketREn;
+ case (CurrState_slvCntrl) // synopsys parallel_case full_case
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ begin
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `PID_ERROR;
+ end
+ end
+ `PID_ERROR:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ end
+ end
+ `SETUP_OUT_CHK:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ end
+ else if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `IN_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `START_S1:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `GET_TOKEN_WAIT_CRC:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_ADDR:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_STOP:
+ begin
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ end
+ else if (RxDataWEn == 1'b1)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_CHK_SOF:
+ begin
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ end
+ `GET_TOKEN_CHK_ADDR:
+ begin
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ stallSent <= 1'b0;
+ NAKSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ transDone <= 1'b0;
+ clrEPRdy <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ getPacketREn <= 1'b0;
+ PIDByte <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ addrEndPTemp <= 8'h00;
+ tempUSBEndPTransTypeReg <= 2'b00;
+ USBAddress <= 7'b0000000;
+ end
+ else
+ begin
+ stallSent <= next_stallSent;
+ NAKSent <= next_NAKSent;
+ SOFRxed <= next_SOFRxed;
+ transDone <= next_transDone;
+ clrEPRdy <= next_clrEPRdy;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ getPacketREn <= next_getPacketREn;
+ PIDByte <= next_PIDByte;
+ endpCRCTemp <= next_endpCRCTemp;
+ addrEndPTemp <= next_addrEndPTemp;
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ USBAddress <= next_USBAddress;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf (revision 264)
@@ -0,0 +1,150 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=153
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacketcheckpreamble.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
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+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+A 45 44 16 TEXT "Actions" | 74811,210616 1 0 0 "fullSpeedBitRate <= 1'b1;\nfullSpeedPolarity <= 1'b1;\ngrabLineControl <= 1'b1;"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 68 37 BEZIER "Transitions" | 95534,53084 101453,45264 180021,53114 185941,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 93181,145786 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 55 60 BEZIER "Transitions" | 89225,146684 89301,143318 91477,99456 91230,95807
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88382,164186 88295,159636
+S 55 33 20480 ELLIPSE "States" | 88650,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88650,153150 1 0 0 "WAIT_RDY2\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "WAIT_RDY3\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+A 64 62 16 TEXT "Actions" | 78524,125856 1 0 0 "fullSpeedBitRate <= 1'b1;"
+A 72 39 16 TEXT "Actions" | 141267,52580 1 0 0 "grabLineControl <= 1'b0;"
+C 73 39 0 TEXT "Conditions" | 97529,56755 1 0 0 "sendPacketRdy == 1'b1"
+L 74 75 0 TEXT "Labels" | 35624,223586 1 0 0 "grabLineControl"
+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
+L 76 77 0 TEXT "Labels" | 37072,218796 1 0 0 "fullSpeedPolarity"
+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
+L 78 79 0 TEXT "Labels" | 35397,214093 1 0 0 "fullSpeedBitRate"
+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+ 94907,51569 61918,50756 52575,52503 43232,54250\
+ 38843,62050 37706,72734 36569,83418 36406,118357\
+ 40062,129609 43718,140862 58507,150938 67687,153172\
+ 76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf (revision 264)
@@ -0,0 +1,98 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=73
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: softransmit.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+ 119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+W 51 6 0 26 11 BEZIER "Transitions" | 117404,14128 103585,14128 76675,12449 68441,16586\
+ 60208,20724 54912,37274 53629,49148 52346,61023\
+ 52495,91978 54333,104221 56172,116465 66907,131666\
+ 73940,137333 80974,143001 92272,144264 98160,144352\
+ 104049,144440 109926,143957 113732,143626
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+ 105450,47318 105450,38252 107207,34228 108965,30205\
+ 115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v (revision 264)
@@ -0,0 +1,171 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMux.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
+// Created
+//
+//
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE,
+ SIEPortCtrlInFromHost,
+ SIEPortCtrlInFromSlave,
+ SIEPortDataInToSIE,
+ SIEPortDataInFromHost,
+ SIEPortDataInFromSlave,
+ SIEPortWEnToSIE,
+ SIEPortWEnFromHost,
+ SIEPortWEnFromSlave,
+ fullSpeedPolarityToSIE,
+ fullSpeedPolarityFromHost,
+ fullSpeedPolarityFromSlave,
+ fullSpeedBitRateToSIE,
+ fullSpeedBitRateFromHost,
+ fullSpeedBitRateFromSlave,
+ dataIn,
+ dataOut,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ hostSlaveMuxSel );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE;
+input [7:0] SIEPortDataInFromHost;
+input [7:0] SIEPortDataInFromSlave;
+output SIEPortWEnToSIE;
+input SIEPortWEnFromHost;
+input SIEPortWEnFromSlave;
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+reg SIEPortWEnToSIE;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave)
+begin
+ if (hostMode == 1'b1)
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn(dataIn),
+ .dataOut(dataOut),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostMode(hostMode),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v (revision 264)
@@ -0,0 +1,100 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v
+//
+// $Id: usbSerialInterfaceEngine_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
+`define OVER_SAMPLE_RATE 4
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 6
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (revision 264)
@@ -0,0 +1,768 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: SIETransmitter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteRdy;
+input rst;
+input [7:0]SIEPortCtrlIn;
+input [7:0]SIEPortDataIn;
+input SIEPortWEn;
+input USBWireGnt;
+input USBWireRdy;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processTxByteWEn;
+output rstCRC;
+output SIEPortTxRdy;
+output [7:0]TxByteOut;
+output [7:0]TxByteOutCtrl;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+wire [1:0]JBit;
+wire [1:0]KBit;
+wire processTxByteRdy;
+reg processTxByteWEn, next_processTxByteWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]SIEPortCtrlIn;
+wire [7:0]SIEPortDataIn;
+reg SIEPortTxRdy, next_SIEPortTxRdy;
+wire SIEPortWEn;
+reg [7:0]TxByteOut, next_TxByteOut;
+reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [4:0]i, next_i;
+reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define IDLE_CHK_FIN 6'b000001
+`define DIR_CTL_CHK_FIN 6'b000010
+`define PKT_ST_CHK_PID 6'b000011
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
+`define PKT_ST_SPCL_PKT_SENT 6'b000101
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
+`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
+`define PKT_ST_HS_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define IDLE_STX_WAIT_GNT 6'b011001
+`define IDLE_STX_WAIT_RDY 6'b011010
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
+`define DIR_CTL_WAIT_GNT 6'b100001
+`define RES_ST_WAIT_GNT 6'b100010
+`define PKT_ST_HS_WAIT_RDY 6'b100011
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
+`define PKT_ST_SPCL_WAIT_RDY 6'b100101
+`define RES_ST_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
+`define DIR_CTL_WAIT_RDY 6'b101011
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
+`define PKT_ST_WAIT_RDY_PKT 6'b101110
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
+`define PKT_ST_WAIT_RDY_WIRE 6'b110000
+`define PKT_ST_WAIT_GNT 6'b110001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or KBit or CRC5Result or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin
+ NextState_SIETx <= CurrState_SIETx;
+ // Set default values for outputs and signals
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_USBWireReq <= USBWireReq;
+ next_processTxByteWEn <= processTxByteWEn;
+ next_rstCRC <= rstCRC;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_TxByteOut <= TxByteOut;
+ next_TxByteOutCtrl <= TxByteOutCtrl;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_SIEPortTxRdy <= SIEPortTxRdy;
+ next_SIEPortData <= SIEPortData;
+ next_SIEPortCtrl <= SIEPortCtrl;
+ case (CurrState_SIETx) // synopsys parallel_case full_case
+ `START_SIETX:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_TxByteOut <= 8'h00;
+ next_TxByteOutCtrl <= 8'h00;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_SIEPortTxRdy <= 1'b0;
+ next_SIEPortData <= 8'h00;
+ next_SIEPortCtrl <= 8'h00;
+ next_i <= 5'h0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `STX_CHK_ST:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_START)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_IDLE)
+ begin
+ NextState_SIETx <= `IDLE_STX_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ next_i <= 5'h0;
+ end
+ end
+ `STX_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `STX_CHK_ST;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `DIR_CTL_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 5'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_GNT:
+ begin
+ next_i <= 5'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN;
+ next_USBWireData <= SIEPortData[1:0];
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `IDLE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 5'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+ end
+ end
+ `IDLE_STX_WAIT_GNT:
+ begin
+ next_i <= 5'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+ end
+ end
+ `IDLE_STX_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `IDLE_CHK_FIN;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_CHK_PID:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ if (SIEPortData[1:0] == `HANDSHAKE)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `TOKEN)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `SPECIAL)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `DATA)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+ end
+ end
+ `PKT_ST_WAIT_RDY_PKT:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= `SYNC_BYTE;
+ next_TxByteOutCtrl <= `DATA_START;
+ end
+ end
+ `PKT_ST_WAIT_RDY_WIRE:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ //actively drive the first J bit
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
+ end
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[7:0];
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[15:8];
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_STOP)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+ end
+ end
+ `PKT_ST_DATA_DATA_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC16En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY:
+ begin
+ next_CRC16En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+ end
+ end
+ `PKT_ST_DATA_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `PKT_ST_HS_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_HS_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+ end
+ `PKT_ST_SPCL_SEND_IDLE1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_SPCL_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_WAIT_WIRE:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_CRC_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `RES_ST_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == `RESUME_LEN)
+ begin
+ NextState_SIETx <= `RES_ST_S1;
+ end
+ else
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_S1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S3;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S4;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S4:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S5;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S5:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S6;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S6:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `RES_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN;
+ next_USBWireData <= KBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ next_i <= i + 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SIETx <= `START_SIETX;
+ else
+ CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ USBWireWEn <= 1'b0;
+ USBWireReq <= 1'b0;
+ processTxByteWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ TxByteOut <= 8'h00;
+ TxByteOutCtrl <= 8'h00;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ SIEPortTxRdy <= 1'b0;
+ i <= 5'h0;
+ SIEPortData <= 8'h00;
+ SIEPortCtrl <= 8'h00;
+ end
+ else
+ begin
+ USBWireWEn <= next_USBWireWEn;
+ USBWireReq <= next_USBWireReq;
+ processTxByteWEn <= next_processTxByteWEn;
+ rstCRC <= next_rstCRC;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ TxByteOut <= next_TxByteOut;
+ TxByteOutCtrl <= next_TxByteOutCtrl;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ SIEPortTxRdy <= next_SIEPortTxRdy;
+ i <= next_i;
+ SIEPortData <= next_SIEPortData;
+ SIEPortCtrl <= next_SIEPortCtrl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf (revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processRxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processRxByte.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+ 162060,109038 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+ 41868,138924 51896,113272 59871,108777 67846,104282\
+ 74724,97474 86324,92674
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC5Result != 5'h6)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n if (RXDataByteCnt > 10'h2) \n begin\n RxOverflow <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n else \n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC5_8Bit <= 1'b1;\n CRC5En <= 1'b1;\n end\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n `SPECIAL: //Special PID.\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n `TOKEN: //Token PID\n begin\n RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n RXDataByteCnt <= 0;\n end\n `HANDSHAKE: //Handshake PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n ACKRxed <= 1'b1;\n 2'b10:\n NAKRxed <= 1'b1;\n 2'b11:\n stallRxed <= 1'b1;\n default:\n begin\n $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n end\n endcase\n RXByteStMachCurrState <= `HS_BYTE_ST;\n end\n `DATA: //Data PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n dataSequence <= 1'b0;\n 2'b10:\n dataSequence <= 1'b1;\n default:\n $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n endcase\n RXByteStMachCurrState <= `DATA_BYTE_ST;\n RXDataByteCnt <= 0;\n end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+ 110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+ 89364,102368 89220,95212 89220,94846
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (revision 264)
@@ -0,0 +1,203 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: readUSBWireData.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:01 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
+input [1:0] RxBitsIn;
+output RxDataInTick;
+input SIERxRdyIn;
+input clk;
+input fullSpeedRate;
+input rst;
+input disableWireRead;
+output [1:0] RxBitsOut;
+output SIERxWEn;
+
+wire [1:0] RxBitsIn;
+reg RxDataInTick;
+wire SIERxRdyIn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg [1:0] RxBitsOut;
+reg SIERxWEn;
+
+// local registers
+reg [1:0]buffer0;
+reg [1:0]buffer1;
+reg [1:0]buffer2;
+reg [1:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 2'b00;
+ buffer1 <= 2'b00;
+ buffer2 <= 2'b00;
+ buffer3 <= 2'b00;
+ RxDataInTick <= 1'b0;
+ end
+ else begin
+ RxBitsInReg <= RxBitsIn; //sync to local clock to avoid metastability issues
+ incBufferCnt <= 1'b0; //default value
+ oldRxBitsIn <= RxBitsInReg;
+ if (oldRxBitsIn != RxBitsInReg) //if edge detected then
+ i <= 5'b00000; //reset the counter
+ else
+ i <= i + 1'b1;
+ if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+ begin
+ RxDataInTick <= !RxDataInTick;
+ if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= RxBitsInReg;
+ 2'b01 : buffer1 <= RxBitsInReg;
+ 2'b10 : buffer2 <= RxBitsInReg;
+ 2'b11 : buffer3 <= RxBitsInReg;
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutIndex <= 2'b00;
+ RxBitsOut <= 2'b00;
+ SIERxWEn <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ else begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_NOT_EMPTY:
+ begin
+ if (bufferCnt != 3'b000)
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+ end
+ `WAIT_SIE_RX_READY:
+ begin
+ if (SIERxRdyIn == 1'b1)
+ begin
+ SIERxWEn <= 1'b1;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 : RxBitsOut <= buffer0;
+ 2'b01 : RxBitsOut <= buffer1;
+ 2'b10 : RxBitsOut <= buffer2;
+ 2'b11 : RxBitsOut <= buffer3;
+ endcase
+ end
+ end
+ `SIE_RX_WRITE:
+ begin
+ SIERxWEn <= 1'b0;
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ endcase
+ end
+end
+
+
+
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v (revision 264)
@@ -0,0 +1,120 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC5.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:04 sfielding
+// Created
+//
+//
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input CRC5_8BitIn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [4:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire CRC5_8BitIn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 5'h1f;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0) begin
+ if (CRCEn == 1'b1) begin
+ ready <= 1'b0;
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ if (CRC5_8BitIn == 1'b1) begin
+ loopEnd <= 4'h7;
+ end
+ else begin
+ loopEnd <= 4'h2;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[4:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == loopEnd) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (revision 264)
@@ -0,0 +1,311 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: writeUSBWireData.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:05 sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn,
+ TxBitsOut,
+ TxDataOutTick,
+ TxCtrlIn,
+ TxCtrlOut,
+ USBWireRdy,
+ USBWireWEn,
+ disableWireReadOut,
+ fullSpeedRate,
+ clk,
+ rst,
+ noActivityTimeOut );
+
+input [1:0] TxBitsIn;
+input TxCtrlIn;
+input USBWireWEn;
+input clk;
+input fullSpeedRate;
+input rst;
+output [1:0] TxBitsOut;
+output TxDataOutTick;
+output TxCtrlOut;
+output USBWireRdy;
+output disableWireReadOut;
+output noActivityTimeOut;
+
+wire [1:0] TxBitsIn;
+reg [1:0] TxBitsOut;
+reg TxDataOutTick;
+wire TxCtrlIn;
+reg TxCtrlOut;
+reg USBWireRdy;
+wire USBWireWEn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg disableWireReadOut;
+reg noActivityTimeOut;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+reg [15:0] timeOutCnt;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk) begin
+ if (rst == 1'b1) begin
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ USBWireRdy <= 1'b0;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ else begin
+ case (bufferInStMachCurrState)
+ `WAIT_BUFFER_NOT_FULL:
+ begin
+ if (bufferCnt != `BUFFER_FULL)
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ end
+ `WAIT_WRITE_REQ:
+ begin
+ if (USBWireWEn == 1'b1)
+ begin
+ incBufferCnt <= 1'b1;
+ USBWireRdy <= 1'b0;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+ 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+ 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+ 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+ end
+ end
+ `CLR_INC_BUFFER_CNT:
+ begin
+ incBufferCnt <= 1'b0;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ fullSpeedTick <= 1'b0;
+ lowSpeedTick <= 1'b0;
+ end
+ else
+ begin
+ i <= i + 1'b1;
+ if (i[1:0] == 2'b00)
+ fullSpeedTick <= 1'b1;
+ else
+ fullSpeedTick <= 1'b0;
+ if (i == 5'b00000)
+ lowSpeedTick <= 1'b1;
+ else
+ lowSpeedTick <= 1'b0;
+ end
+end
+
+//buffer output state machine
+//After reset, waits for the output buffer to become full.
+//Once the buffer is full then it is constantly emptied at either
+//the full or low speed rate with no under run protection
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferOutIndex <= 2'b00;
+ decBufferCnt <= 1'b0;
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ TxDataOutTick <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_FULL:
+ begin
+ if (bufferCnt == `BUFFER_FULL)
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ `WAIT_LINE_WRITE:
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+ begin
+ TxDataOutTick <= !TxDataOutTick;
+ bufferOutStMachCurrState <= `LINE_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0[2:1];
+ TxCtrlOut <= buffer0[0];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1[2:1];
+ TxCtrlOut <= buffer1[0];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2[2:1];
+ TxCtrlOut <= buffer2[0];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3[2:1];
+ TxCtrlOut <= buffer3[0];
+ end
+ endcase
+ end
+ end
+ `LINE_WRITE:
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ endcase
+ end
+end
+
+// control 'disableWireReadOut'
+always @(TxCtrlOut)
+begin
+ if (TxCtrlOut == `DRIVE)
+ disableWireReadOut <= 1'b1;
+ else
+ disableWireReadOut <= 1'b0;
+end
+
+//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
+always @(posedge clk) begin
+ if (rst) begin
+ timeOutCnt <= 16'h0000;
+ noActivityTimeOut <= 1'b0;
+ end
+ else begin
+ if (TxCtrlOut == `DRIVE)
+ timeOutCnt <= 16'h0000;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1;
+ //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+ if (timeOutCnt == 16'h200) //temporary fix
+ noActivityTimeOut <= 1'b1;
+ else
+ noActivityTimeOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf (revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sctxportarbiter.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n"
+END
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+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf (revision 264)
@@ -0,0 +1,275 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=280
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveGetpacket.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+L 277 278 0 TEXT "State Labels" | 44712,168924 1 0 0 "DELAY\n/17/"
+S 278 120 90112 ELLIPSE "States" | 44712,168924 6500 6500
+W 279 120 0 278 137 BEZIER "Transitions" | 45244,175402 46602,184714 48694,202964 53786,209657\
+ 58879,216350 75631,224113 84458,228187
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v (revision 264)
@@ -0,0 +1,270 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveSendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveSendpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input [3:0]PID;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+input sendPacketWEn;
+output fifoReadEn;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+wire [3:0]PID;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+ NextState_slvSndPkt <= CurrState_slvSndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+ `START_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ end
+ `SP_WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP1_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `SP1_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_SCTxPortReq <= 1'b0;
+ end
+ `SP_NOT_DATA:
+ begin
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_SEND_PID_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= PIDNotPID;
+ next_SCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SP_SEND_PID_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_NOT_DATA;
+ end
+ end
+ `SP_D0_D1_READ_FIFO:
+ begin
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= fifoData;
+ next_SCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+ end
+ `SP_D0_D1_WAIT_READ_FIFO:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `SP_D0_D1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+ end
+ end
+ `SP_D0_D1_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_D0_D1_TERM_BYTE:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `SP_D0_D1_CLR_WEN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ `SP_D0_D1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvSndPkt <= `START_SP1;
+ else
+ CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ SCTxPortData <= 8'h00;
+ SCTxPortCntl <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v (revision 264)
@@ -0,0 +1,518 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlave.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlave.v,v 1.2 2004-12-18 14:36:23 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/10/11 04:01:11 sfielding
+// Created
+//
+//
+
+module usbHostSlave(
+ clk,
+ rst,
+ address_i,
+ data_i,
+ data_o,
+ writeEn,
+ strobe_i,
+ ack_o,
+ hostSOFSentIntOut,
+ hostConnEventIntOut,
+ hostResumeIntOut,
+ hostTransDoneIntOut,
+ slaveNAKSentIntOut,
+ slaveSOFRxedIntOut,
+ slaveResetEventIntOut,
+ slaveResumeIntOut,
+ slaveTransDoneIntOut,
+ USBWireDataIn,
+ USBWireDataInTick,
+ USBWireDataOut,
+ USBWireDataOutTick,
+ USBWireCtrlOut
+ );
+ parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+ parameter HOST_FIFO_ADDR_WIDTH = 6;
+ parameter EP0_FIFO_DEPTH = 64;
+ parameter EP0_FIFO_ADDR_WIDTH = 6;
+ parameter EP1_FIFO_DEPTH = 64;
+ parameter EP1_FIFO_ADDR_WIDTH = 6;
+ parameter EP2_FIFO_DEPTH = 64;
+ parameter EP2_FIFO_ADDR_WIDTH = 6;
+ parameter EP3_FIFO_DEPTH = 64;
+ parameter EP3_FIFO_ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [7:0] address_i;
+input [7:0] data_i;
+output [7:0] data_o;
+input writeEn;
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut;
+output hostConnEventIntOut;
+output hostResumeIntOut;
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut;
+output slaveResetEventIntOut;
+output slaveResumeIntOut;
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+
+wire clk;
+wire rst;
+wire [7:0] address_i;
+wire [7:0] data_i;
+wire [7:0] data_o;
+wire writeEn;
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel;
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE;
+wire [7:0] hostTxFifoData;
+wire hostTxFifoEmpty;
+wire hostRxFifoWE;
+wire [7:0] hostRxFifoData;
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut;
+wire [7:0] RxDataFromSIE;
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState;
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+usbHostControl u_usbHostControl(
+ .clk(clk),
+ .rst(rst),
+ .TxFifoRE(hostTxFifoRE),
+ .TxFifoData(hostTxFifoData),
+ .TxFifoEmpty(hostTxFifoEmpty),
+ .RxFifoWE(hostRxFifoWE),
+ .RxFifoData(hostRxFifoData),
+ .RxFifoFull(hostRxFifoFull),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .fullSpeedRate(fullSpeedBitRateFromHost),
+ .fullSpeedPol(fullSpeedPolarityFromHost),
+ .HCTxPortEn(SIEPortWEnFromHost),
+ .HCTxPortRdy(SIEPortTxRdy),
+ .HCTxPortData(SIEPortDataInFromHost),
+ .HCTxPortCtrl(SIEPortCtrlInFromHost),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[3:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFSentIntOut(hostSOFSentIntOut),
+ .connEventIntOut(hostConnEventIntOut),
+ .resumeIntOut(hostResumeIntOut),
+ .transDoneIntOut(hostTransDoneIntOut),
+ .hostControlSelect(hostControlSel) );
+
+
+usbSlaveControl u_usbSlaveControl(
+ .clk(clk),
+ .rst(rst),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .RxFifoData(slaveRxFifoData),
+ .fullSpeedRate(fullSpeedBitRateFromSlave),
+ .fullSpeedPol(fullSpeedPolarityFromSlave),
+ .SCTxPortEn(SIEPortWEnFromSlave),
+ .SCTxPortRdy(SIEPortTxRdy),
+ .SCTxPortData(SIEPortDataInFromSlave),
+ .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[4:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromSlaveControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFRxedIntOut(slaveSOFRxedIntOut),
+ .resetEventIntOut(slaveResetEventIntOut),
+ .resumeIntOut(slaveResumeIntOut),
+ .transDoneIntOut(slaveTransDoneIntOut),
+ .NAKSentIntOut(slaveNAKSentIntOut),
+ .slaveControlSelect(slaveControlSel),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+wishBoneBI u_wishBoneBI (
+ .address(address_i),
+ .dataIn(data_i),
+ .dataOut(data_o),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .clk(clk),
+ .rst(rst),
+ .hostControlSel(hostControlSel),
+ .hostRxFifoSel(hostRxFifoSel),
+ .hostTxFifoSel(hostTxFifoSel),
+ .slaveControlSel(slaveControlSel),
+ .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
+ .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
+ .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
+ .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
+ .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
+ .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
+ .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
+ .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .dataFromHostControl(dataFromHostControl),
+ .dataFromHostRxFifo(dataFromHostRxFifo),
+ .dataFromHostTxFifo(dataFromHostTxFifo),
+ .dataFromSlaveControl(dataFromSlaveControl),
+ .dataFromEP0RxFifo(dataFromEP0RxFifo),
+ .dataFromEP1RxFifo(dataFromEP1RxFifo),
+ .dataFromEP2RxFifo(dataFromEP2RxFifo),
+ .dataFromEP3RxFifo(dataFromEP3RxFifo),
+ .dataFromEP0TxFifo(dataFromEP0TxFifo),
+ .dataFromEP1TxFifo(dataFromEP1TxFifo),
+ .dataFromEP2TxFifo(dataFromEP2TxFifo),
+ .dataFromEP3TxFifo(dataFromEP3TxFifo),
+ .dataFromHostSlaveMux(dataFromHostSlaveMux)
+ );
+
+hostSlaveMux u_hostSlaveMux(
+ .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+ .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+ .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+ .SIEPortDataInToSIE(SIEPortDataInToSIE),
+ .SIEPortDataInFromHost(SIEPortDataInFromHost),
+ .SIEPortDataInFromSlave(SIEPortDataInFromSlave),
+ .SIEPortWEnToSIE(SIEPortWEnToSIE),
+ .SIEPortWEnFromHost(SIEPortWEnFromHost),
+ .SIEPortWEnFromSlave(SIEPortWEnFromSlave),
+ .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+ .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+ .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+ .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+ .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+ .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+ .dataIn(data_i),
+ .dataOut(dataFromHostSlaveMux),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+ .clk(clk),
+ .rst(rst),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .connectState(connectState),
+ .resumeDetected(resumeDetected),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataFromSIE),
+ .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+ .SIEPortDataIn(SIEPortDataInToSIE),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEnToSIE),
+ .fullSpeedPolarity(fullSpeedPolarityToSIE),
+ .fullSpeedBitRate(fullSpeedBitRateToSIE),
+ .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(hostTxFifoRE),
+ .fifoEmpty(hostTxFifoEmpty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostTxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostTxFifo),
+ .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(hostRxFifoWE),
+ .fifoFull(hostRxFifoFull),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostRxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostRxFifo),
+ .fifoDataIn(hostRxFifoData) );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP0REn),
+ .fifoEmpty(TxFifoEP0Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0TxFifo),
+ .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP1REn),
+ .fifoEmpty(TxFifoEP1Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1TxFifo),
+ .fifoDataOut(TxFifoEP1Data) );
+
+ TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP2REn),
+ .fifoEmpty(TxFifoEP2Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2TxFifo),
+ .fifoDataOut(TxFifoEP2Data) );
+
+ TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP3REn),
+ .fifoEmpty(TxFifoEP3Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3TxFifo),
+ .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP0WEn),
+ .fifoFull(RxFifoEP0Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP1WEn),
+ .fifoFull(RxFifoEP1Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP2WEn),
+ .fifoFull(RxFifoEP2Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP3WEn),
+ .fifoFull(RxFifoEP3Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v (revision 264)
@@ -0,0 +1,116 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ clk, rst, fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ fifoFull,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// directControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+ NextState_drctCntl <= CurrState_drctCntl;
+ // Set default values for outputs and signals
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_drctCntl) // synopsys parallel_case full_case
+ `START_DC:
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ next_HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {6'b000000, directControlLineState};
+ next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_HCTxPortReq <= 1'b0;
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_drctCntl <= `START_DC;
+ else
+ CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v (revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hctxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+input [7:0]SOFCntlCntl;
+input [7:0]SOFCntlData;
+input SOFCntlReq;
+input SOFCntlWEn;
+output directCntlGnt;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortWEnable;
+output sendPacketGnt;
+output SOFCntlGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+reg HCTxPortWEnable, next_HCTxPortWEnable;
+wire rst;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [7:0]SOFCntlCntl;
+wire [7:0]SOFCntlData;
+reg SOFCntlGnt, next_SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+ NextState_HCTxArb = CurrState_HCTxArb;
+ // Set default values for outputs and signals
+ next_SOFCntlGnt <= SOFCntlGnt;
+ next_sendPacketGnt <= sendPacketGnt;
+ next_directCntlGnt <= directCntlGnt;
+ next_muxCntl <= muxCntl;
+ case (CurrState_HCTxArb) // synopsys parallel_case full_case
+ `START_HARB:
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ end
+ `WAIT_REQ:
+ begin
+ if (SOFCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_SOF;
+ next_SOFCntlGnt <= 1'b1;
+ next_muxCntl <= `SOF_CTRL_MUX;
+ end
+ else if (sendPacketReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxCntl <= `SEND_PACKET_MUX;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `DIRECT_CONTROL;
+ next_directCntlGnt <= 1'b1;
+ next_muxCntl <= `DIRECT_CTRL_MUX;
+ end
+ end
+ `SEND_SOF:
+ begin
+ if (SOFCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_SOFCntlGnt <= 1'b0;
+ end
+ end
+ `SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `DIRECT_CONTROL:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_HCTxArb = `START_HARB;
+ else
+ CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFCntlGnt = 1'b0;
+ sendPacketGnt = 1'b0;
+ directCntlGnt = 1'b0;
+ muxCntl = 2'b00;
+ end
+ else
+ begin
+ SOFCntlGnt = next_SOFCntlGnt;
+ sendPacketGnt = next_sendPacketGnt;
+ directCntlGnt = next_directCntlGnt;
+ muxCntl = next_muxCntl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf (revision 264)
@@ -0,0 +1,243 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=225
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
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+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 43
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 114645,116706 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 113134,104869 113443,100466
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 136066,86256 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+ 48213,88528 42471,75064 41184,67490 39897,59917\
+ 40491,43087 47668,36800 54846,30514 82962,22198\
+ 91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+ 200128,135446 205472,144130 205681,151728 205890,159327\
+ 201380,181037 194241,189595 187102,198154 163054,210680\
+ 152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf (revision 264)
@@ -0,0 +1,150 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=153
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+A 45 44 16 TEXT "Actions" | 74811,210616 1 0 0 "fullSpeedBitRate <= 1'b1;\nfullSpeedPolarity <= 1'b1;\ngrabLineControl <= 1'b1;"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 68 37 BEZIER "Transitions" | 95534,53084 101453,45264 180021,53114 185941,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 93181,145786 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 55 60 BEZIER "Transitions" | 89225,146684 89301,143318 91477,99456 91230,95807
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88382,164186 88295,159636
+S 55 33 20480 ELLIPSE "States" | 88650,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88650,153150 1 0 0 "WAIT_RDY2\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "WAIT_RDY3\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+A 64 62 16 TEXT "Actions" | 78524,125856 1 0 0 "fullSpeedBitRate <= 1'b1;"
+A 72 39 16 TEXT "Actions" | 141267,52580 1 0 0 "grabLineControl <= 1'b0;"
+C 73 39 0 TEXT "Conditions" | 97529,56755 1 0 0 "sendPacketRdy == 1'b1"
+L 74 75 0 TEXT "Labels" | 35624,223586 1 0 0 "grabLineControl"
+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
+L 76 77 0 TEXT "Labels" | 37072,218796 1 0 0 "fullSpeedPolarity"
+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
+L 78 79 0 TEXT "Labels" | 35397,214093 1 0 0 "fullSpeedBitRate"
+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+ 94907,51569 61918,50756 52575,52503 43232,54250\
+ 38843,62050 37706,72734 36569,83418 36406,118357\
+ 40062,129609 43718,140862 58507,150938 67687,153172\
+ 76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v (revision 264)
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlaveWrap.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlaveWrap.v,v 1.1 2004-12-18 14:57:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+
+module usbHostSlaveWrap(
+ clk,
+ reset,
+ address,
+ writedata,
+ readdata,
+ write,
+ read,
+ waitrequest,
+ chipselect,
+ irq,
+ USBWireVPI,
+ USBWireVMI,
+ USBWireDataInTick,
+ USBWireVPO,
+ USBWireVMO,
+ USBWireDataOutTick,
+ USBWireOutEn_n,
+ USBFullSpeed,
+ DPlusPullUp,
+ DMinusPullUp
+ );
+
+input clk;
+input reset;
+input [7:0] address;
+input [7:0] writedata;
+output [7:0] readdata;
+input write;
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+output DPlusPullUp;
+output DMinusPullUp;
+
+wire clk;
+wire reset;
+wire [7:0] address;
+wire [7:0] writedata;
+wire [7:0] readdata;
+wire write;
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+wire DPlusPullUp;
+wire DMinusPullUp;
+
+//internal wiring
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+ hostResumeIntOut | hostTransDoneIntOut |
+ slaveSOFRxedIntOut | slaveResetEventIntOut |
+ slaveResumeIntOut | slaveTransDoneIntOut |
+ slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut;
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+assign USBFullSpeed = 1'b1;
+assign DPlusPullUp = 1'b1;
+assign DMinusPullUp = 1'bz;
+
+//Parameters declaration:
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+ .clk(clk),
+ .rst(reset),
+ .address_i(address),
+ .data_i(writedata),
+ .data_o(readdata),
+ .writeEn(write),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .hostSOFSentIntOut(hostSOFSentIntOut),
+ .hostConnEventIntOut(hostConnEventIntOut),
+ .hostResumeIntOut(hostResumeIntOut),
+ .hostTransDoneIntOut(hostTransDoneIntOut),
+ .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+ .slaveResetEventIntOut(slaveResetEventIntOut),
+ .slaveResumeIntOut(slaveResumeIntOut),
+ .slaveTransDoneIntOut(slaveTransDoneIntOut),
+ .slaveNAKSentIntOut(slaveNAKSentIntOut),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+ clk,
+ rst,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk;
+wire rst;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ .rclk(clk),
+ .rrst(1'b0),
+ .rce(1'b1),
+ .oe(readEn),
+ .raddr(addrOut),
+ .do(dataOut),
+ .wclk(clk),
+ .wrst(1'b0),
+ .wce(1'b1),
+ .we(writeEn),
+ .waddr(addrIn),
+ .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
+ .addrIn(addrIn),
+ .addrOut(addrOut),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(writeEn),
+ .readEn(readEn),
+ .dataOut(dataOut));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+ TxTransTypeReg, TxSOFEnableReg,
+ TxAddrReg, TxEndPReg, frameNumIn,
+ RxPktStatusIn, RxPIDIn,
+ connectStateIn,
+ SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+ hostControlSelect,
+ clrTransReq,
+ preambleEn,
+ SOFSync,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ transReq
+ );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+ clrSOFReq <= 1'b0;
+ clrConnEvtReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ setTransReq <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+ begin
+ case (address)
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn[2];
+ SOFSync <= dataIn[1];
+ setTransReq <= dataIn[0];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+ `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+ `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn[3];
+ clrConnEvtReq <= dataIn[2];
+ clrResInReq <= dataIn[1];
+ clrTransDoneReq <= dataIn[0];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (SOFSentIn == 1'b1)
+ SOFSentInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFSentInt <= 1'b0;
+
+ if (connEventIn == 1'b1)
+ connEventInt <= 1'b1;
+ else if (clrConnEvtReq == 1'b1)
+ connEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end
+
+//transaction request set/clear
+always @(posedge clk)
+begin
+ if (setTransReq == 1'b1)
+ transReq <= 1'b1;
+ else if (clrTransReq == 1'b1)
+ transReq <= 1'b0;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+ TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+ fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq)
+begin
+ case (address)
+ `TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+ `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+ `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+ `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumIn[10:8]};
+ `FRAME_NUM_LSB_REG : dataOut <= frameNumIn[7:0];
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn;
+ `RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v (revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// getpacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXPacketRdy;
+output [3:0]RxPID;
+output [7:0]RXPktStatus;
+
+wire clk;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+reg [7:0]RXPktStatus;
+wire [7:0]RXStreamStatusIn;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+ NextState_getPkt <= CurrState_getPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_getPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_getPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_getPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_getPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+ next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_getPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_getPkt <= `START_GP;
+ else
+ CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RxPID <= 4'h0;
+ RXOverflow <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXByteOld <= 8'h00;
+ RXTimeOut <= 1'b0;
+ end
+ else
+ begin
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RxPID <= next_RxPID;
+ RXOverflow <= next_RXOverflow;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXByteOld <= next_RXByteOld;
+ RXTimeOut <= next_RXTimeOut;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v (revision 264)
@@ -0,0 +1,418 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input clk;
+input getPacketRdy;
+input rst;
+input [7:0]RXStatus;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input transReq;
+input [1:0]transType;
+output clearTXReq;
+output getPacketREn;
+output sendPacketArbiterReq;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output transDone;
+
+reg clearTXReq, next_clearTXReq;
+wire clk;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+wire rst;
+wire [7:0]RXStatus;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg transDone, next_transDone;
+wire transReq;
+wire [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+ NextState_hstCntrl <= CurrState_hstCntrl;
+ // Set default values for outputs and signals
+ next_transDone <= transDone;
+ next_clearTXReq <= clearTXReq;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketPID <= sendPacketPID;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_hstCntrl) // synopsys parallel_case full_case
+ `START_HC:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `TX_REQ:
+ begin
+ if (transReq == 1'b1)
+ begin
+ NextState_hstCntrl <= `WAIT_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `CHK_TYPE:
+ begin
+ if (transType == `IN_TRANS)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+ end
+ else if (transType == `OUTDATA0_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+ end
+ else if (transType == `OUTDATA1_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+ end
+ else if (transType == `SETUP_TRANS)
+ begin
+ NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+ end
+ end
+ `FLAG:
+ begin
+ next_transDone <= 1'b1;
+ next_clearTXReq <= 1'b1;
+ next_sendPacketArbiterReq <= 1'b0;
+ NextState_hstCntrl <= `FIN;
+ end
+ `FIN:
+ begin
+ next_transDone <= 1'b0;
+ next_clearTXReq <= 1'b0;
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `WAIT_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1)
+ begin
+ NextState_hstCntrl <= `CHK_TYPE;
+ end
+ end
+ `SETUP_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+ end
+ `SETUP_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+ end
+ `SETUP_WAIT_PKT_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `SETUP_HC_WAIT_RDY:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `SETUP;
+ end
+ end
+ `SETUP_WAIT_SETUP_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `SETUP_WAIT_DATA_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_DATA_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+ end
+ end
+ `IN_CHK_FOR_ERROR:
+ begin
+ if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+ RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `IN_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+ end
+ `IN_WAIT_IN_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `IN;
+ end
+ end
+ `IN_WAIT_SP_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `IN_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+ end
+ `IN_WAIT_ACK_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_DATA0_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT0_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `OUT0_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT0_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+ end
+ `OUT0_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+ end
+ `OUT1_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `OUT1_WAIT_DATA1_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT1_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT1_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+ end
+ `OUT1_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_hstCntrl <= `START_HC;
+ else
+ CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ transDone <= 1'b0;
+ clearTXReq <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ transDone <= next_transDone;
+ clearTXReq <= next_clearTXReq;
+ getPacketREn <= next_getPacketREn;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
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+I 43 0 2 Builtin OutPort | 162738,158202 "" ""
+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
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+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]"
+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) \nbegin\n if (muxSOFNotHC == 1'b1) \n begin\n sendPacketWEnable <= SOF_SP_WEn;\n sendPacketPID <= `SOF;\n end\n else\n begin\n sendPacketWEnable <= HC_SP_WEn;\n sendPacketPID <= HC_PID;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
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+ 123371,91703
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+I 85 0 2 Builtin InPort | 38222,167883 "" ""
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+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf (revision 264)
@@ -0,0 +1,98 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=73
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
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+END
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+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+ 119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+W 51 6 0 26 11 BEZIER "Transitions" | 117404,14128 103585,14128 76675,12449 68441,16586\
+ 60208,20724 54912,37274 53629,49148 52346,61023\
+ 52495,91978 54333,104221 56172,116465 66907,131666\
+ 73940,137333 80974,143001 92272,144264 98160,144352\
+ 104049,144440 109926,143957 113732,143626
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+ 105450,47318 105450,38252 107207,34228 108965,30205\
+ 115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v (revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE,
+ SIEPortCtrlInFromHost,
+ SIEPortCtrlInFromSlave,
+ SIEPortDataInToSIE,
+ SIEPortDataInFromHost,
+ SIEPortDataInFromSlave,
+ SIEPortWEnToSIE,
+ SIEPortWEnFromHost,
+ SIEPortWEnFromSlave,
+ fullSpeedPolarityToSIE,
+ fullSpeedPolarityFromHost,
+ fullSpeedPolarityFromSlave,
+ fullSpeedBitRateToSIE,
+ fullSpeedBitRateFromHost,
+ fullSpeedBitRateFromSlave,
+ dataIn,
+ dataOut,
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ hostSlaveMuxSel );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE;
+input [7:0] SIEPortDataInFromHost;
+input [7:0] SIEPortDataInFromSlave;
+output SIEPortWEnToSIE;
+input SIEPortWEnFromHost;
+input SIEPortWEnFromSlave;
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+reg SIEPortWEnToSIE;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave)
+begin
+ if (hostMode == 1'b1)
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn(dataIn),
+ .dataOut(dataOut),
+ .address(address),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostMode(hostMode),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v (revision 264)
@@ -0,0 +1,18 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+`define USBHOSTSLAVE_VERSION_NUM 8'h06
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v (revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+
+module wishBoneBI (
+ address, dataIn, dataOut, writeEn,
+ strobe_i,
+ ack_o,
+ clk, rst,
+ hostControlSel,
+ hostRxFifoSel, hostTxFifoSel,
+ slaveControlSel,
+ slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
+ slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
+ hostSlaveMuxSel,
+ dataFromHostControl,
+ dataFromHostRxFifo,
+ dataFromHostTxFifo,
+ dataFromSlaveControl,
+ dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+ dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+ dataFromHostSlaveMux
+ );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+ dataFromHostControl or
+ dataFromHostRxFifo or
+ dataFromHostTxFifo or
+ dataFromSlaveControl or
+ dataFromEP0RxFifo or
+ dataFromEP1RxFifo or
+ dataFromEP2RxFifo or
+ dataFromEP3RxFifo or
+ dataFromHostSlaveMux or
+ dataFromEP0TxFifo or
+ dataFromEP1TxFifo or
+ dataFromEP2TxFifo or
+ dataFromEP3TxFifo)
+begin
+ hostControlSel <= 1'b0;
+ hostRxFifoSel <= 1'b0;
+ hostTxFifoSel <= 1'b0;
+ slaveControlSel <= 1'b0;
+ slaveEP0RxFifoSel <= 1'b0;
+ slaveEP0TxFifoSel <= 1'b0;
+ slaveEP1RxFifoSel <= 1'b0;
+ slaveEP1TxFifoSel <= 1'b0;
+ slaveEP2RxFifoSel <= 1'b0;
+ slaveEP2TxFifoSel <= 1'b0;
+ slaveEP3RxFifoSel <= 1'b0;
+ slaveEP3TxFifoSel <= 1'b0;
+ hostSlaveMuxSel <= 1'b0;
+ case (address & `ADDRESS_DECODE_MASK)
+ `HCREG_BASE : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HCREG_BASE_PLUS_0X10 : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HOST_RX_FIFO_BASE : begin
+ hostRxFifoSel <= 1'b1;
+ dataOut <= dataFromHostRxFifo;
+ end
+ `HOST_TX_FIFO_BASE : begin
+ hostTxFifoSel <= 1'b1;
+ dataOut <= dataFromHostTxFifo;
+ end
+ `SCREG_BASE : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `SCREG_BASE_PLUS_0X10 : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `EP0_RX_FIFO_BASE : begin
+ slaveEP0RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0RxFifo;
+ end
+ `EP0_TX_FIFO_BASE : begin
+ slaveEP0TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0TxFifo;
+ end
+ `EP1_RX_FIFO_BASE : begin
+ slaveEP1RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1RxFifo;
+ end
+ `EP1_TX_FIFO_BASE : begin
+ slaveEP1TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1TxFifo;
+ end
+ `EP2_RX_FIFO_BASE : begin
+ slaveEP2RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2RxFifo;
+ end
+ `EP2_TX_FIFO_BASE : begin
+ slaveEP2TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2TxFifo;
+ end
+ `EP3_RX_FIFO_BASE : begin
+ slaveEP3RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3RxFifo;
+ end
+ `EP3_TX_FIFO_BASE : begin
+ slaveEP3TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3TxFifo;
+ end
+ `HOST_SLAVE_CONTROL_BASE : begin
+ hostSlaveMuxSel <= 1'b1;
+ dataOut <= dataFromHostSlaveMux;
+ end
+ default:
+ dataOut <= 8'h00;
+ endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+ ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+ ack_immediate <= strobe_i;
+end
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+ if (writeEn == 1'b0 &&
+ (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+ begin
+ ack_o <= ack_delayed;
+ end
+ else
+ begin
+ ack_o <= ack_immediate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf (revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 58
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 112
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 245
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+ 88541,112746 87971,105860 87641,93102 87312,80344\
+ 87761,70127 92565,59363 97370,48599 95270,45542\
+ 101102,30966
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus = { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+ 57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf (revision 264)
@@ -0,0 +1,283 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=432
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+ 170250,145750 137550,145450 128737,144962 119925,144475\
+ 117963,142662 116688,141837
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+A 334 332 16 TEXT "Actions" | 87236,105298 1 0 0 "getPacketREn <= 1'b1;"
+C 333 332 0 TEXT "Conditions" | 48120,123470 1 0 0 "sendPacketRdy == 1'b1"
+W 332 66 0 220 331 BEZIER "Transitions" | 82714,126587 85717,114267 91541,91328 94544,79008
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+I 55 52 0 Builtin Entry | 88756,239499
+I 56 52 0 Builtin Exit | 155694,46048
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+C 321 320 0 TEXT "Conditions" | 124852,185328 1 0 0 "sendPacketRdy == 1'b1"
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+ 110726,37400 115182,37514 117348,37514
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+I 366 73 0 Builtin Entry | 66816,246531
+I 365 73 0 Builtin Exit | 138662,35952
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+ 129080,35838 133536,35952 135702,35952
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+ 88026,17883 53248,36150 43780,48625 34312,61101\
+ 33772,117285 37441,132224 41110,147164 52980,154980\
+ 61012,157537 69044,160095 94076,164012 106263,166770
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 6 0 Builtin Reset | 67359,192312
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+W 371 59 2 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+ 40160,89849 37728,77233 37462,69633 37196,62033\
+ 38564,44249 44378,36953 50192,29657 72080,18257\
+ 79528,15331 86976,12405 94012,13028 97964,12876
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+I 411 59 0 Builtin Exit | 100924,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+ 134254,207065 123583,209376 117848,210301
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+I 216 66 0 Builtin Exit | 120308,37514
+I 215 66 0 Builtin Entry | 50996,240683
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v (revision 264)
@@ -0,0 +1,349 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input [3:0]PID;
+input rst;
+input sendPacketWEn;
+input [6:0]TxAddr;
+input [3:0]TxEndP;
+output fifoReadEn;
+output [10:0]frameNum;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+reg [10:0]frameNum, next_frameNum;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire [3:0]PID;
+wire rst;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+wire [6:0]TxAddr;
+wire [3:0]TxEndP;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+ NextState_sndPkt <= CurrState_sndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ next_frameNum <= frameNum;
+ case (CurrState_sndPkt) // synopsys parallel_case full_case
+ `START_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ end
+ `WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_sndPkt <= `SP_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `SP_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_HCTxPortReq <= 1'b0;
+ end
+ `SEND_PID_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= PIDNotPID;
+ next_HCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SEND_PID_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ else if (PID == `SOF)
+ begin
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+ end
+ else if (PID == `OUT ||
+ PID == `IN ||
+ PID == `SETUP)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sndPkt <= `FIN_SP;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY1:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY2:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `OUT_IN_SETUP_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+ end
+ `SEND_SOF_FIN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_frameNum <= frameNum + 1'b1;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `SEND_SOF_WAIT_RDY3:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= frameNum[7:0];
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_WAIT_RDY4:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_FIN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+ end
+ `DATA0_DATA1_READ_FIFO:
+ begin
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= fifoData;
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+ end
+ `DATA0_DATA1_WAIT_READ_FIFO:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `DATA0_DATA1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+ end
+ end
+ `DATA0_DATA1_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `DATA0_DATA1_TERM_BYTE:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `DATA0_DATA1_CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ `DATA0_DATA1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sndPkt <= `START_SP;
+ else
+ CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ HCTxPortData <= 8'h00;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ frameNum <= 11'h000;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ frameNum <= next_frameNum;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v (revision 264)
@@ -0,0 +1,228 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketcheckpreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input clk;
+input preAmbleEnable;
+input rst;
+input [3:0]sendPacketCPPID;
+input sendPacketCPWEn;
+input sendPacketRdy;
+output fullSpeedBitRate;
+output fullSpeedPolarity;
+output grabLineControl; // mux select
+output sendPacketCPReady;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+
+wire clk;
+reg fullSpeedBitRate, next_fullSpeedBitRate;
+reg fullSpeedPolarity, next_fullSpeedPolarity;
+reg grabLineControl, next_grabLineControl;
+wire preAmbleEnable;
+wire rst;
+wire [3:0]sendPacketCPPID;
+reg sendPacketCPReady, next_sendPacketCPReady;
+wire sendPacketCPWEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin
+ NextState_sendPktCP <= CurrState_sendPktCP;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_fullSpeedBitRate <= fullSpeedBitRate;
+ next_fullSpeedPolarity <= fullSpeedPolarity;
+ next_grabLineControl <= grabLineControl;
+ case (CurrState_sendPktCP) // synopsys parallel_case full_case
+ `SPC_WAIT_EN:
+ begin
+ if (sendPacketCPWEn == 1'b1)
+ begin
+ NextState_sendPktCP <= `CHK_PREAM;
+ next_sendPacketCPReady <= 1'b0;
+ end
+ end
+ `START_SPC:
+ begin
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `CHK_PREAM:
+ begin
+ if (preAmbleEnable == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+ end
+ end
+ `READY:
+ begin
+ next_sendPacketCPReady <= 1'b1;
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `PREAM_PKT_SND_PREAM:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `PREAMBLE;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+ next_sendPacketWEn <= 1'b0;
+ end
+ `PREAM_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+ next_fullSpeedBitRate <= 1'b1;
+ next_fullSpeedPolarity <= 1'b1;
+ next_grabLineControl <= 1'b1;
+ end
+ end
+ `PREAM_PKT_WAIT_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+ next_fullSpeedBitRate <= 1'b1;
+ end
+ end
+ `PREAM_PKT_SND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+ next_sendPacketWEn <= 1'b0;
+ end
+ `PREAM_PKT_WAIT_RDY3:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `READY;
+ next_grabLineControl <= 1'b0;
+ end
+ end
+ `REG_PKT_SEND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+ end
+ `REG_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `REG_PKT_SEND_PID;
+ end
+ end
+ `REG_PKT_WAIT_RDY:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `READY;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktCP <= `START_SPC;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketCPReady <= 1'b1;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ fullSpeedBitRate <= 1'b0;
+ fullSpeedPolarity <= 1'b0;
+ grabLineControl <= 1'b0;
+ end
+ else
+ begin
+ sendPacketCPReady <= next_sendPacketCPReady;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ fullSpeedBitRate <= next_fullSpeedBitRate;
+ fullSpeedPolarity <= next_fullSpeedPolarity;
+ grabLineControl <= next_grabLineControl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v (revision 264)
@@ -0,0 +1,172 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// softransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input clk;
+input rst;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn;
+input [15:0]SOFTimer;
+output sendPacketArbiterReq;
+output sendPacketWEn;
+output SOFSent; // single cycle pulse
+output SOFTimerClr; // Single cycle pulse
+
+wire clk;
+wire rst;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+wire SOFEnable;
+reg SOFSent, next_SOFSent;
+wire SOFSyncEn;
+wire [15:0]SOFTimer;
+reg SOFTimerClr, next_SOFTimerClr;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+ NextState_SOFTx <= CurrState_SOFTx;
+ // Set default values for outputs and signals
+ next_SOFSent <= SOFSent;
+ next_SOFTimerClr <= SOFTimerClr;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_SOFTx) // synopsys parallel_case full_case
+ `START_STX:
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ `WAIT_SOF_NEAR:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `WAIT_SP_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NOW;
+ end
+ end
+ `WAIT_SOF_NOW:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_sendPacketWEn <= 1'b1;
+ next_SOFTimerClr <= 1'b1;
+ next_SOFSent <= 1'b1;
+ end
+ else if (SOFEnable == 1'b0)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_SOFTimerClr <= 1'b1;
+ end
+ end
+ `SOF_FIN:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ next_SOFTimerClr <= 1'b0;
+ next_SOFSent <= 1'b0;
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ next_sendPacketArbiterReq <= 1'b0;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SOFTx <= `START_STX;
+ else
+ CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFSent <= 1'b0;
+ SOFTimerClr <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent;
+ SOFTimerClr <= next_SOFTimerClr;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+ module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
+ hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ hostMode <= 1'b0;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+ hostMode <= dataIn[0];
+ end
+end
+
+
+// async read mux
+always @(address or hostMode)
+begin
+ case (address)
+ `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+ `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+ endcase
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v (revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (revision 264)
@@ -0,0 +1,708 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteRdy;
+input rst;
+input [7:0]SIEPortCtrlIn;
+input [7:0]SIEPortDataIn;
+input SIEPortWEn;
+input USBWireGnt;
+input USBWireRdy;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processTxByteWEn;
+output rstCRC;
+output SIEPortTxRdy;
+output [7:0]TxByteOut;
+output [7:0]TxByteOutCtrl;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+wire [1:0]JBit;
+wire [1:0]KBit;
+wire processTxByteRdy;
+reg processTxByteWEn, next_processTxByteWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]SIEPortCtrlIn;
+wire [7:0]SIEPortDataIn;
+reg SIEPortTxRdy, next_SIEPortTxRdy;
+wire SIEPortWEn;
+reg [7:0]TxByteOut, next_TxByteOut;
+reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [4:0]i, next_i;
+reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define DIR_CTL_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
+`define PKT_ST_HS_PKT_SENT 6'b000110
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
+`define PKT_ST_SPCL_PKT_SENT 6'b001001
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define RES_ST_WAIT_GNT 6'b011111
+`define DIR_CTL_WAIT_GNT 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define PKT_ST_SPCL_WAIT_RDY 6'b100011
+`define PKT_ST_HS_WAIT_RDY 6'b100100
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
+`define DIR_CTL_WAIT_RDY 6'b100111
+`define RES_ST_WAIT_RDY 6'b101000
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
+`define PKT_ST_WAIT_RDY_PKT 6'b101100
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin
+ NextState_SIETx <= CurrState_SIETx;
+ // Set default values for outputs and signals
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_USBWireReq <= USBWireReq;
+ next_processTxByteWEn <= processTxByteWEn;
+ next_rstCRC <= rstCRC;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_TxByteOut <= TxByteOut;
+ next_TxByteOutCtrl <= TxByteOutCtrl;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_SIEPortTxRdy <= SIEPortTxRdy;
+ next_SIEPortData <= SIEPortData;
+ next_SIEPortCtrl <= SIEPortCtrl;
+ case (CurrState_SIETx) // synopsys parallel_case full_case
+ `IDLE:
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `START_SIETX:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_TxByteOut <= 8'h00;
+ next_TxByteOutCtrl <= 8'h00;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_SIEPortTxRdy <= 1'b0;
+ next_SIEPortData <= 8'h00;
+ next_SIEPortCtrl <= 8'h00;
+ next_i <= 5'h0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `STX_CHK_ST:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_START)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_IDLE)
+ begin
+ NextState_SIETx <= `IDLE;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ next_i <= 5'h0;
+ end
+ end
+ `STX_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `STX_CHK_ST;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `DIR_CTL_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 5'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_GNT:
+ begin
+ next_i <= 5'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN;
+ next_USBWireData <= SIEPortData[1:0];
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_CHK_PID:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ if (SIEPortData[1:0] == `TOKEN)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `HANDSHAKE)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `DATA)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `SPECIAL)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+ end
+ end
+ `PKT_ST_WAIT_RDY_PKT:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= `SYNC_BYTE;
+ next_TxByteOutCtrl <= `DATA_START;
+ end
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[7:0];
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[15:8];
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_STOP)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+ end
+ end
+ `PKT_ST_DATA_DATA_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC16En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY:
+ begin
+ next_CRC16En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+ end
+ end
+ `PKT_ST_DATA_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `PKT_ST_HS_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_HS_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+ end
+ `PKT_ST_SPCL_SEND_IDLE1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_SPCL_SEND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_SPCL_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_WAIT_WIRE:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_CRC_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `RES_ST_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == `RESUME_LEN)
+ begin
+ NextState_SIETx <= `RES_ST_S1;
+ end
+ else
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_S1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S3;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S4;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S4:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S5;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S5:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_S6;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_S6:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `RES_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN;
+ next_USBWireData <= KBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ next_i <= i + 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SIETx <= `START_SIETX;
+ else
+ CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ USBWireWEn <= 1'b0;
+ USBWireReq <= 1'b0;
+ processTxByteWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ TxByteOut <= 8'h00;
+ TxByteOutCtrl <= 8'h00;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ SIEPortTxRdy <= 1'b0;
+ i <= 5'h0;
+ SIEPortData <= 8'h00;
+ SIEPortCtrl <= 8'h00;
+ end
+ else
+ begin
+ USBWireWEn <= next_USBWireWEn;
+ USBWireReq <= next_USBWireReq;
+ processTxByteWEn <= next_processTxByteWEn;
+ rstCRC <= next_rstCRC;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ TxByteOut <= next_TxByteOut;
+ TxByteOutCtrl <= next_TxByteOutCtrl;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ SIEPortTxRdy <= next_SIEPortTxRdy;
+ i <= next_i;
+ SIEPortData <= next_SIEPortData;
+ SIEPortCtrl <= next_SIEPortCtrl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (revision 264)
@@ -0,0 +1,572 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=957
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIETransmitter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+OBJECTS
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+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
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+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
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+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
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+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/23/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
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+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
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+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 138120,51311
+I 599 489 0 Builtin Entry | 81144,219546
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+ 161730,108850 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/1/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+ 77086,119473 72191,126878 71751,132901 71312,138925\
+ 74451,155618 76866,160637 79282,165657 85808,169046\
+ 89165,169297 92522,169548 98692,166980 102143,165788
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+ 43361,99065 46384,95576 54928,94878 63472,94181\
+ 94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/39/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/32/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/27/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/10/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/46/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+ 104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/29/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 453 BEZIER "Transitions" | 30788,244668 34532,239130 40619,228589 44363,223051
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/48/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/47/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/26/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/38/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/40/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1; \ni <= i + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/37/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/5/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+ 28677,128486 23782,135891 23342,141914 22903,147938\
+ 26042,164631 28457,169650 30873,174670 37399,178059\
+ 40756,178310 44113,178561 50283,175993 53734,174801
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 145044,30588
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/31/"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/6/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/36/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/25/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/44/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/8/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/28/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/43/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/41/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/7/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+ 46299,139871 48829,136075 59202,135063 69575,134052\
+ 106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+ 46931,109511 49715,104703 60024,103501 70334,102300\
+ 108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+ 48196,74723 50474,70169 60657,69030 70840,67892\
+ 108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+ 48829,42592 51359,37532 61605,36267 71852,35002\
+ 109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+ 128857,67252 162473,65260 171997,66691 181521,68123\
+ 186003,75843 187123,97692 188244,119542 188244,199222\
+ 184384,221196 180525,243170 165087,251388 155563,253628\
+ 146039,255869 123379,256617 115100,254625 106821,252633\
+ 98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+ 31250,150650 32250,89650 34750,72525 37250,55400\
+ 46250,47900 56000,46150 65750,44400 95896,46012\
+ 103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/42/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+I 540 458 0 Builtin Exit | 68103,43333
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v (revision 264)
@@ -0,0 +1,410 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processrxbit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processRxBitsWEn;
+input processRxByteRdy;
+input rst;
+input [1:0]RxBitsIn;
+output processRxBitRdy;
+output processRxByteWEn;
+output resumeDetected;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processRxBitRdy, next_processRxBitRdy;
+wire processRxBitsWEn;
+wire processRxByteRdy;
+reg processRxByteWEn, next_processRxByteWEn;
+reg resumeDetected, next_resumeDetected;
+wire rst;
+wire [1:0]RxBitsIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg [1:0]oldRXBits, next_oldRXBits;
+reg [3:0]resumeWaitCnt, next_resumeWaitCnt;
+reg [3:0]RXBitCount, next_RXBitCount;
+reg [1:0]RxBits, next_RxBits;
+reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg [7:0]RXByte, next_RXByte;
+reg [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+ NextState_prRxBit <= CurrState_prRxBit;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOut <= RxDataOut;
+ next_resumeDetected <= resumeDetected;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState;
+ next_RxBits <= RxBits;
+ next_RXSameBitCount <= RXSameBitCount;
+ next_RXBitCount <= RXBitCount;
+ next_oldRXBits <= oldRXBits;
+ next_RXByte <= RXByte;
+ next_bitStuffError <= bitStuffError;
+ next_resumeWaitCnt <= resumeWaitCnt;
+ next_processRxBitRdy <= processRxBitRdy;
+ case (CurrState_prRxBit) // synopsys parallel_case full_case
+ `START:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOut <= 8'h00;
+ next_resumeDetected <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_RxBits <= 2'b00;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h0;
+ next_oldRXBits <= 2'b00;
+ next_RXByte <= 8'h00;
+ next_bitStuffError <= 1'b0;
+ next_resumeWaitCnt <= 4'h0;
+ next_processRxBitRdy <= 1'b1;
+ NextState_prRxBit <= `WAIT_BITS;
+ end
+ `WAIT_BITS:
+ begin
+ if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ end
+ `IDLE_FIRST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h1;
+ next_oldRXBits <= RxBits;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `IDLE_CHK_KBIT:
+ begin
+ if (RxBits == KBit)
+ begin
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `IDLE_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START;
+ //start of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_LAST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_CHK_SE0:
+ begin
+ next_bitStuffError <= 1'b0;
+ if (RxBits == `SE0)
+ begin
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+ if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+ next_bitStuffError <= 1'b1;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1, RXByte[7:1]};
+ //RZ bit <= 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0, RXByte[7:1]};
+ //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h0;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP;
+ //end of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_DATA_DESTUFF:
+ begin
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+ end
+ else if (bitStuffError == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `DATA_RX_BYTE_SEND2:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_BYTE_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+ next_RXBitCount <= 4'h0;
+ next_RxDataOut <= RXByte;
+ next_RxCtrlOut <= `DATA_STREAM;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_ERROR_CHK_RES:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ if (RxBits == JBit) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+ //check for resume
+ next_resumeWaitCnt <= 0;
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_ERROR_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `RES_RX_CHK:
+ begin
+ if (RxBits != KBit) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+ next_resumeDetected <= 1'b1;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `RES_END_CHK1:
+ begin
+ if (RxBits != KBit) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_resumeDetected <= 1'b0;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxBit <= `START;
+ else
+ CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processRxByteWEn <= 1'b0;
+ RxCtrlOut <= 8'h00;
+ RxDataOut <= 8'h00;
+ resumeDetected <= 1'b0;
+ processRxBitRdy <= 1'b1;
+ RXBitStMachCurrState <= `IDLE_BIT_ST;
+ RxBits <= 2'b00;
+ RXSameBitCount <= 4'h0;
+ RXBitCount <= 4'h0;
+ oldRXBits <= 2'b00;
+ RXByte <= 8'h00;
+ bitStuffError <= 1'b0;
+ resumeWaitCnt <= 4'h0;
+ end
+ else
+ begin
+ processRxByteWEn <= next_processRxByteWEn;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOut <= next_RxDataOut;
+ resumeDetected <= next_resumeDetected;
+ processRxBitRdy <= next_processRxBitRdy;
+ RXBitStMachCurrState <= next_RXBitStMachCurrState;
+ RxBits <= next_RxBits;
+ RXSameBitCount <= next_RXSameBitCount;
+ RXBitCount <= next_RXBitCount;
+ oldRXBits <= next_oldRXBits;
+ RXByte <= next_RXByte;
+ bitStuffError <= next_bitStuffError;
+ resumeWaitCnt <= next_resumeWaitCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v (revision 264)
@@ -0,0 +1,431 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input fullSpeedRate;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteWEn;
+input rst;
+input [7:0]TxByteCtrlIn;
+input [7:0]TxByteIn;
+input USBWireGnt;
+input USBWireRdy;
+output processTxByteRdy;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+wire fullSpeedRate;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processTxByteRdy, next_processTxByteRdy;
+wire processTxByteWEn;
+wire rst;
+wire [7:0]TxByteCtrlIn;
+wire [7:0]TxByteIn;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [3:0]i, next_i;
+reg [7:0]TxByte, next_TxByte;
+reg [7:0]TxByteCtrl, next_TxByteCtrl;
+reg [1:0]TXLineState, next_TXLineState;
+reg [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin
+ NextState_prcTxB <= CurrState_prcTxB;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_USBWireReq <= USBWireReq;
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_TxByte <= TxByte;
+ next_TxByteCtrl <= TxByteCtrl;
+ next_TXLineState <= TXLineState;
+ next_TXOneCount <= TXOneCount;
+ case (CurrState_prcTxB) // synopsys parallel_case full_case
+ `START_PTBY:
+ begin
+ next_processTxByteRdy <= 1'b0;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_i <= 4'h0;
+ next_TxByte <= 8'h00;
+ next_TxByteCtrl <= 8'h00;
+ next_TXLineState <= 2'b0;
+ next_TXOneCount <= 4'h0;
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `PTBY_WAIT_EN:
+ begin
+ next_processTxByteRdy <= 1'b1;
+ if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TXOneCount <= 4'h0;
+ next_TXLineState <= JBit;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (processTxByteWEn == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_i <= 4'h0;
+ end
+ end
+ `PTBY_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_WIRE;
+ end
+ end
+ `WAIT_RDY_WIRE:
+ begin
+ if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE1;
+ end
+ else if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_PKT;
+ //actively drive the first J bit
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `WAIT_RDY_PKT:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `SEND_BYTE_UPDATE_BYTE:
+ begin
+ next_i <= i + 1'b1;
+ next_TxByte <= {1'b0, TxByte[7:1] };
+ if (TxByte[0] == 1'b1) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+ end
+ `SEND_BYTE_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+ end
+ else if (i != 4'h8)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ else
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ end
+ `SEND_BYTE_BIT_STUFF:
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+ end
+ `SEND_BYTE_WAIT_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == 4'h8)
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ else
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ end
+ `STOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_J;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_SND_SE0_1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_CHK:
+ begin
+ if (TxByteCtrl == `DATA_STOP)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_1;
+ end
+ else
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ end
+ `STOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_SND_IDLE:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `STOP_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `LS_START_SND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_J1;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_J1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_FIN;
+ //Drive the first JBit
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `LS_START_SND_IDLE1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE3;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prcTxB <= `START_PTBY;
+ else
+ CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processTxByteRdy <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ USBWireReq <= 1'b0;
+ USBWireWEn <= 1'b0;
+ i <= 4'h0;
+ TxByte <= 8'h00;
+ TxByteCtrl <= 8'h00;
+ TXLineState <= 2'b0;
+ TXOneCount <= 4'h0;
+ end
+ else
+ begin
+ processTxByteRdy <= next_processTxByteRdy;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ USBWireReq <= next_USBWireReq;
+ USBWireWEn <= next_USBWireWEn;
+ i <= next_i;
+ TxByte <= next_TxByte;
+ TxByteCtrl <= next_TxByteCtrl;
+ TXLineState <= next_TXLineState;
+ TXOneCount <= next_TXOneCount;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v (revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [15:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [15:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 16'hffff;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0)
+ begin
+ if (CRCEn == 1'b1) begin
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ ready <= 1'b0;
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[15:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == 4'h7)
+ begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (revision 264)
@@ -0,0 +1,199 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbTxWireArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input clk;
+input prcTxByteCtrl;
+input [1:0]prcTxByteData;
+input prcTxByteReq;
+input prcTxByteWEn;
+input rst;
+input SIETxCtrl;
+input [1:0]SIETxData;
+input SIETxReq;
+input SIETxWEn;
+input USBWireRdyIn;
+output prcTxByteGnt;
+output SIETxGnt;
+output [1:0]TxBits;
+output TxCtl;
+output USBWireRdyOut;
+output USBWireWEn;
+
+wire clk;
+wire prcTxByteCtrl;
+wire [1:0]prcTxByteData;
+reg prcTxByteGnt, next_prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire rst;
+wire SIETxCtrl;
+wire [1:0]SIETxData;
+reg SIETxGnt, next_SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+reg [1:0]TxBits, next_TxBits;
+reg TxCtl, next_TxCtl;
+wire USBWireRdyIn;
+reg USBWireRdyOut, next_USBWireRdyOut;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+if (muxSIENotPTXB == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+ NextState_txWireArb <= CurrState_txWireArb;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt;
+ next_SIETxGnt <= SIETxGnt;
+ next_muxSIENotPTXB <= muxSIENotPTXB;
+ case (CurrState_txWireArb) // synopsys parallel_case full_case
+ `START_TARB:
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ end
+ `TARB_WAIT_REQ:
+ begin
+ if (prcTxByteReq == 1'b1)
+ begin
+ NextState_txWireArb <= `PTXB_ACT;
+ next_prcTxByteGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b0;
+ end
+ else if (SIETxReq == 1'b1)
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT;
+ next_SIETxGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b1;
+ end
+ end
+ `PTXB_ACT:
+ begin
+ if (prcTxByteReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_prcTxByteGnt <= 1'b0;
+ end
+ end
+ `SIE_TX_ACT:
+ begin
+ if (SIETxReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_SIETxGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_txWireArb <= `START_TARB;
+ else
+ CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ prcTxByteGnt <= 1'b0;
+ SIETxGnt <= 1'b0;
+ muxSIENotPTXB <= 1'b0;
+ end
+ else
+ begin
+ prcTxByteGnt <= next_prcTxByteGnt;
+ SIETxGnt <= next_SIETxGnt;
+ muxSIENotPTXB <= next_muxSIENotPTXB;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v (revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ fifoEmpty,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v (revision 264)
@@ -0,0 +1,139 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH-1:0]bufferInIndex;
+reg [ADDR_WIDTH-1:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || forceEmpty == 1'b1)
+ begin
+ bufferCnt <= 0;
+ fifoFull <= 1'b0;
+ fifoEmpty <= 1'b1;
+ bufferInIndex <= 0;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ end
+ fifoREnDelayed <= fifoREn;
+ if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+ bufferCnt <= bufferCnt + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferCnt <= bufferCnt - 1;
+ bufferOutIndex <= bufferOutIndex + 1;
+ end
+ else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferOutIndex <= bufferOutIndex + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ if (bufferCnt[ADDR_WIDTH] == 1'b1)
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ if (|bufferCnt == 1'b0)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
+ .addrIn(bufferInIndex),
+ .addrOut(bufferOutIndex),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf (revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+GRIDSIZE 5000,5000 10000,10000
+END
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+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
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+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend"
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+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// rxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ connectionEventOut <= 1'b1;
+ else
+ connectionEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v (revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketarbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input clk;
+input [3:0]HC_PID;
+input HC_SP_WEn;
+input HCTxReq;
+input rst;
+input SOF_SP_WEn;
+input SOFTxReq;
+output HCTxGnt;
+output [3:0]sendPacketPID;
+output sendPacketWEnable;
+output SOFTxGnt;
+
+wire clk;
+wire [3:0]HC_PID;
+wire HC_SP_WEn;
+reg HCTxGnt, next_HCTxGnt;
+wire HCTxReq;
+wire rst;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+reg sendPacketWEnable, next_sendPacketWEnable;
+wire SOF_SP_WEn;
+reg SOFTxGnt, next_SOFTxGnt;
+wire SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+ NextState_sendPktArb <= CurrState_sendPktArb;
+ // Set default values for outputs and signals
+ next_HCTxGnt <= HCTxGnt;
+ next_SOFTxGnt <= SOFTxGnt;
+ next_muxSOFNotHC <= muxSOFNotHC;
+ case (CurrState_sendPktArb) // synopsys parallel_case full_case
+ `HC_ACT:
+ begin
+ if (HCTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_HCTxGnt <= 1'b0;
+ end
+ end
+ `SOF_ACT:
+ begin
+ if (SOFTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_SOFTxGnt <= 1'b0;
+ end
+ end
+ `SARB_WAIT_REQ:
+ begin
+ if (SOFTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `SOF_ACT;
+ next_SOFTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b1;
+ end
+ else if (HCTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `HC_ACT;
+ next_HCTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktArb <= `START_SARB;
+ else
+ CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxGnt <= 1'b0;
+ SOFTxGnt <= 1'b0;
+ muxSOFNotHC <= 1'b0;
+ end
+ else
+ begin
+ HCTxGnt <= next_HCTxGnt;
+ SOFTxGnt <= next_SOFTxGnt;
+ muxSOFNotHC <= next_muxSOFNotHC;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v (revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sofcontroller
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input clk;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+input SOFEnable;
+input SOFTimerClr;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output [15:0]SOFTimer;
+
+wire clk;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+wire SOFEnable;
+reg [15:0]SOFTimer, next_SOFTimer;
+wire SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+ NextState_sofCntl <= CurrState_sofCntl;
+ // Set default values for outputs and signals
+ next_SOFTimer <= SOFTimer;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_sofCntl) // synopsys parallel_case full_case
+ `START_SC:
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ end
+ `WAIT_SOF_EN:
+ begin
+ if (SOFEnable == 1'b1)
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `WAIT_SEND_RESUME:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sofCntl <= `CLR_WEN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_RESUME_START;
+ end
+ end
+ `INC_TIMER:
+ begin
+ next_HCTxPortReq <= 1'b0;
+ if (SOFTimerClr == 1'b1)
+ next_SOFTimer <= 16'h0000;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1;
+ if (SOFEnable == 1'b0)
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ next_SOFTimer <= 16'h0000;
+ end
+ end
+ `SC_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sofCntl <= `WAIT_SEND_RESUME;
+ end
+ end
+ `CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sofCntl <= `INC_TIMER;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sofCntl <= `START_SC;
+ else
+ CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFTimer <= 16'h0000;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v (revision 264)
@@ -0,0 +1,399 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+ clk, rst,
+ //sendPacket
+ TxFifoRE, TxFifoData, TxFifoEmpty,
+ //getPacket
+ RxFifoWE, RxFifoData, RxFifoFull,
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //HCTxPortArbiter
+ HCTxPortEn, HCTxPortRdy,
+ HCTxPortData, HCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFSentIntOut,
+ connEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ hostControlSelect
+ );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [3:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut;
+wire connEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFSentIntOut(SOFSentIntOut),
+ .connEventIntOut(connEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .TxTransTypeReg(transType),
+ .TxSOFEnableReg(SOFEnable),
+ .TxAddrReg(TxAddr),
+ .TxEndPReg(TxEndP),
+ .frameNumIn(frameNum),
+ .RxPktStatusIn(RxPktStatus),
+ .RxPIDIn(RxPID),
+ .connectStateIn(connectStateOut),
+ .SOFSentIn(SOFSent),
+ .connEventIn(connectionEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .hostControlSelect(hostControlSelect),
+ .clrTransReq(clrTxReq),
+ .preambleEn(preAmbleEnable),
+ .SOFSync(SOFSyncEn),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(directCtrlPol),
+ .fullSpeedRate(directCtrlRate),
+ .transReq(transReq)
+
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus(RxPktStatus),
+ .clearTXReq(clrTxReq),
+ .clk(clk),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketArbiterGnt(HCTxGnt),
+ .sendPacketArbiterReq(HCTxReq),
+ .sendPacketPID(HC_PID),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(HC_SP_WEn),
+ .transDone(transDone),
+ .transReq(transReq),
+ .transType(transType) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl(SOFCntlCntl),
+ .HCTxPortData(SOFCntlData),
+ .HCTxPortGnt(SOFCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(SOFCntlReq),
+ .HCTxPortWEn(SOFCntlWEn),
+ .SOFEnable(SOFEnable),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable(SOFEnable),
+ .SOFSent(SOFSent),
+ .SOFSyncEn(SOFSyncEn),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketArbiterGnt(SOFTxGnt),
+ .sendPacketArbiterReq(SOFTxReq),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(SOF_SP_WEn) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt(HCTxGnt),
+ .HCTxReq(HCTxReq),
+ .HC_PID(HC_PID),
+ .HC_SP_WEn(HC_SP_WEn),
+ .SOFTxGnt(SOFTxGnt),
+ .SOFTxReq(SOFTxReq),
+ .SOF_SP_WEn(SOF_SP_WEn),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketPID(sendPacketCPPIDIn),
+ .sendPacketWEnable(sendPacketCPWEnIn) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID(sendPacketCPPIDIn),
+ .clk(clk),
+ .fullSpeedBitRate(sendPacketCPFSRate),
+ .fullSpeedPolarity(sendPacketCPFSPol),
+ .grabLineControl(sendPacketCPGrabLine),
+ .preAmbleEnable(preAmbleEnable),
+ .rst(rst),
+ .sendPacketCPReady(sendPacketCPReadyOut),
+ .sendPacketCPWEn(sendPacketCPWEnIn),
+ .sendPacketPID(sendPacketCPPIDOut),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl(sendPacketCntl),
+ .HCTxPortData(sendPacketData),
+ .HCTxPortGnt(sendPacketGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(sendPacketReq),
+ .HCTxPortWEn(sendPacketWEn),
+ .PID(sendPacketCPPIDOut),
+ .TxAddr(TxAddr),
+ .TxEndP(TxEndP),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .frameNum(frameNum),
+ .rst(rst),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+directControl u_directControl
+ (.HCTxPortCntl(directCntlCntl),
+ .HCTxPortData(directCntlData),
+ .HCTxPortGnt(directCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(directCntlReq),
+ .HCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl(HCTxPortCtrl),
+ .HCTxPortData(HCTxPortData),
+ .HCTxPortWEnable(HCTxPortEn),
+ .SOFCntlCntl(SOFCntlCntl),
+ .SOFCntlData(SOFCntlData),
+ .SOFCntlGnt(SOFCntlGnt),
+ .SOFCntlReq(SOFCntlReq),
+ .SOFCntlWEn(SOFCntlWEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+getPacket u_getPacket
+ (.RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXPktStatus(RxPktStatus),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+speedCtrlMux u_speedCtrlMux
+ (.directCtrlRate(directCtrlRate),
+ .directCtrlPol(directCtrlPol),
+ .sendPacketRate(sendPacketCPFSRate),
+ .sendPacketPol(sendPacketCPFSPol),
+ .sendPacketSel(sendPacketCPGrabLine),
+ .fullSpeedRate(fullSpeedRate),
+ .fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .connectionEventOut(connectionEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v (revision 264)
@@ -0,0 +1,71 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+`define SOF_TX_TIME 16'hbb80 //Correct SOF interval for 48MHz clock
+//`define SOF_TX_MARGIN 2
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v (revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf (revision 264)
@@ -0,0 +1,313 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=256
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
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+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
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+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
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+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 128380,96970
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+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
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+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
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+I 38 41 0 Builtin Entry | 86360,167640
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+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
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+ 43038,129670 44914,125650 53423,124511 61932,123372\
+ 93489,123426 109569,123158
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+ 46388,39220 49604,34396 58247,33391 66890,32386\
+ 97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+ 188238,99472 188778,113512 186145,122422 183513,131332\
+ 167904,143587 159264,149864 150624,156142 133542,158851\
+ 125779,159931 118017,161011 123617,159646 119837,160051
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+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0; \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 130017,172236 121274,163054 112530,153872 103787,144690
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
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+ 113975,98130 125575,96970
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+ 151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+ 176540,156388 181096,131196 181431,113977 181766,96758\
+ 182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 0; \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit) //can only be a resume if line remains in Kbit state\n RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n resumeWaitCnt <= resumeWaitCnt + 1'b1; \n //if we've waited long enough, then\n if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n begin \n RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n resumeDetected <= 1'b1; //report resume detected\n end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+ 107061,21822 137747,20482 148467,20415 159187,20348\
+ 171381,21420 174463,22458 177545,23497 178090,26035\
+ 178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+ 145117,36964 157043,31068 161599,29627 166155,28187\
+ 172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
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+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n RXSameBitCount <= RXSameBitCount + 1'b1; //inc 'RXSameBitCount'\n if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n bitStuffError <= 1'b1; //flag 'bitStuffError'\n else //else no bit stuffing error\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= { 1'b1, RXByte[7:1]}; //RZ bit = 1 (ie no change in 'RxBits')\n end\nend\nelse //else current 'RxBits' are different from old 'RxBits'\nbegin\n if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= {1'b0, RXByte[7:1]}; //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n end\n RXSameBitCount <= 4'h0; //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf (revision 264)
@@ -0,0 +1,286 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1099
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processTxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 887
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 994
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1025
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1034
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 1098 1035 0 1095 1097 BEZIER "Transitions" | 108942,40143 114373,39761 124823,37993 130254,37611
+I 1097 1035 0 Builtin Exit | 133008,37611
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+A 1088 1087 16 TEXT "Actions" | 79282,165145 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1089 1087 0 TEXT "Conditions" | 44839,149287 1 0 0 "USBWireRdy == 1'b1"
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+ 157955,32952 139055,31533 132716,31415 126377,31297\
+ 121929,32154 118701,32626
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "fullSpeedRate == 1'b0"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67229,69836 53212,80703
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+ 25630,50244 23766,53274 22950,67894 22135,82515\
+ 20737,137969 21261,153813 21785,169657 25281,177579\
+ 27028,179792 28775,182006 32271,182938 33727,182355\
+ 35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1) //If this bit is 1, then\n TXOneCount <= TXOneCount + 1'b1; //increment 'TXOneCount'\nelse //else this is a zero bit\nbegin\n TXOneCount <= 4'h0; //reset 'TXOneCount'\n if (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\n else \n TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0; //reset 'TXOneCount'\nif (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\nelse \n TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+ 113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+ 40522,42856 31562,47464 29098,65320 26634,83176\
+ 25738,149992 26858,168968 27978,187944 33354,197032\
+ 36938,198888 40522,200744 49226,198568 51498,198152\
+ 53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0; \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+ 90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+ 104561,139388 153745,139620 168013,138576 182281,137532\
+ 190169,133124 192141,121582 194113,110040 194113,68280\
+ 192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+ 41124,121640 36948,124424 36020,132602 35092,140780\
+ 35556,170708 38166,179350 40776,187992 50140,192687\
+ 55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+ 30972,218732 29812,212468 29638,189094 29464,165720\
+ 29928,78488 31900,55230 33872,31972 41296,26172\
+ 49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
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+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit; \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
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+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
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+I 1022 0 2 Builtin InPort | 124600,229120 "" ""
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
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+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+I 1028 1027 0 Builtin Entry | 86360,167640
+I 1029 1027 0 Builtin Exit | 129540,111760
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+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
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+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
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+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+W 1060 1035 0 1068 1095 BEZIER "Transitions" | 119595,89987 115301,85752 96726,74583 101803,48306
+C 1061 1060 0 TEXT "Conditions" | 120455,89906 1 0 0 "USBWireRdy == 1'b1"
+A 1064 1060 16 TEXT "Actions" | 103427,83175 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 1066 1035 0 1046 1068 BEZIER "Transitions" | 119437,138596 120065,131303 120589,109860 121217,102567
+C 1067 1066 0 TEXT "Conditions" | 120608,137968 1 0 0 "USBWireRdy == 1'b1"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+A 1070 1066 16 TEXT "Actions" | 116166,125942 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+I 1075 1035 0 Builtin Entry | 75208,271435
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
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+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+W 1087 1035 0 1084 1046 BEZIER "Transitions" | 51535,157150 52163,149857 101582,150816 115890,150819
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v (revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input clk;
+input rst;
+input [1:0]RxWireDataIn;
+input RxWireDataWEn;
+output [1:0]connectState;
+
+wire clk;
+reg [1:0]connectState, next_connectState;
+wire rst;
+wire [1:0]RxWireDataIn;
+wire RxWireDataWEn;
+
+// diagram signals declarations
+reg [1:0]RxBits, next_RxBits;
+reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+ NextState_rcvr <= CurrState_rcvr;
+ // Set default values for outputs and signals
+ next_RXWaitCount <= RXWaitCount;
+ next_connectState <= connectState;
+ next_RXStMachCurrState <= RXStMachCurrState;
+ next_RxBits <= RxBits;
+ case (CurrState_rcvr) // synopsys parallel_case full_case
+ `WAIT_BIT:
+ begin
+ if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ end
+ `START_SRX:
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_RXWaitCount <= 8'h00;
+ next_connectState <= `DISCONNECT;
+ next_RxBits <= 2'b00;
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `DISCNCT_CHK_RXBITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else if (RxBits == `ONE_ZERO)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ONE_ZERO)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `LS_CONN_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `FS_CONN_CHK_RX_BITS1:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_rcvr <= `START_SRX;
+ else
+ CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ connectState <= `DISCONNECT;
+ RXWaitCount <= 8'h00;
+ RXStMachCurrState <= `DISCONNECT_ST;
+ RxBits <= 2'b00;
+ end
+ else
+ begin
+ connectState <= next_connectState;
+ RXWaitCount <= next_RXWaitCount;
+ RXStMachCurrState <= next_RXStMachCurrState;
+ RxBits <= next_RxBits;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (revision 264)
@@ -0,0 +1,105 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=128
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
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+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
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+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
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+I 20 6 0 Builtin Reset | 86247,136033
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+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
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+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
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+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 153906,181456 "" ""
+L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 156447,157894 "" ""
+L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 156216,186076 "" ""
+L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 154368,153274 "" ""
+L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 155985,199705 "" ""
+L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 155985,195316 "" ""
+L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 155985,190696 "" ""
+L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 156447,171985 "" ""
+L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 156447,167596 "" ""
+L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
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+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl"
+L 8 9 0 TEXT "State Labels" | 101706,207040 1 0 0 "START_SC\n/0/"
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+L 10 11 0 TEXT "State Labels" | 102510,174880 1 0 0 "WAIT_SOF_EN\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500
+W 12 6 0 9 11 BEZIER "Transitions" | 101472,200547 101472,195422 101786,186460 101786,181335
+I 13 6 0 Builtin Reset | 56682,217090
+W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787
+L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 180096,262516 "" ""
+L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 179694,255682 "" ""
+C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst"
+L 20 21 0 TEXT "State Labels" | 104118,144730 1 0 0 "WAIT_SEND_RESUME\n/2/"
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+C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1"
+A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;"
+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n SOFTimer <= 16'h0000;\nelse\n SOFTimer <= SOFTimer + 1'b1;"
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+I 37 0 130 Builtin OutPort | 20502,239200 "" ""
+L 38 39 0 TEXT "Labels" | 28914,244024 1 0 0 "SOFEnable"
+I 39 0 2 Builtin InPort | 22914,244024 "" ""
+L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy"
+I 41 0 2 Builtin InPort | 84018,239200 "" ""
+I 42 0 2 Builtin OutPort | 81638,244416 "" ""
+L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn"
+I 44 0 130 Builtin OutPort | 81915,250446 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 46 0 130 Builtin OutPort | 81312,256878 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
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+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v (revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input directCtrlRate;
+input directCtrlPol;
+input sendPacketRate;
+input sendPacketPol;
+input sendPacketSel;
+output fullSpeedRate;
+output fullSpeedPol;
+
+wire directCtrlRate;
+wire directCtrlPol;
+wire sendPacketRate;
+wire sendPacketPol;
+wire sendPacketSel;
+reg fullSpeedRate;
+reg fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+ if (sendPacketSel == 1'b1)
+ begin
+ fullSpeedRate <= sendPacketRate;
+ fullSpeedPol <= sendPacketPol;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate;
+ fullSpeedPol <= directCtrlPol;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v (revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v (revision 264)
@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+`endif //usbSlaveControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+ if (fullSpeedPolarity == 1'b1)
+ begin
+ JBit = `ONE_ZERO;
+ KBit = `ZERO_ONE;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE;
+ KBit = `ONE_ZERO;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v (revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input processRxDataInWEn;
+input rst;
+input [7:0]RxByteIn;
+input [7:0]RxCtrlIn;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processRxByteRdy;
+output rstCRC;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+output RxDataOutWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+reg processRxByteRdy, next_processRxByteRdy;
+wire processRxDataInWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]RxByteIn;
+wire [7:0]RxCtrlIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+reg RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RxByte, next_RxByte;
+reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg [7:0]RxCtrl, next_RxCtrl;
+reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+ NextState_prRxByte <= CurrState_prRxByte;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte;
+ next_RxCtrl <= RxCtrl;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RxOverflow <= RxOverflow;
+ next_RxTimeOut <= RxTimeOut;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_RxDataOut <= RxDataOut;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOutWEn <= RxDataOutWEn;
+ next_rstCRC <= rstCRC;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_RXDataByteCnt <= RXDataByteCnt;
+ next_processRxByteRdy <= processRxByteRdy;
+ case (CurrState_prRxByte) // synopsys parallel_case full_case
+ `CHK_ST:
+ begin
+ if (RXByteStMachCurrState == `HS_BYTE_ST)
+ begin
+ NextState_prRxByte <= `HSHAKE_CHK;
+ end
+ else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+ begin
+ NextState_prRxByte <= `TOKEN_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+ begin
+ NextState_prRxByte <= `DATA_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+ begin
+ NextState_prRxByte <= `IDLE_CHK_START;
+ end
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+ begin
+ NextState_prRxByte <= `CHK_SYNC_DO;
+ end
+ else if (RXByteStMachCurrState == `CHECK_PID_ST)
+ begin
+ NextState_prRxByte <= `CHK_PID_DO_CHK;
+ end
+ end
+ `START_PRBY:
+ begin
+ next_RxByte <= 8'h00;
+ next_RxCtrl <= 8'h00;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxDataOut <= 8'h00;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOutWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_RXDataByteCnt <= 10'h00;
+ next_processRxByteRdy <= 1'b1;
+ NextState_prRxByte <= `WAIT_BYTE;
+ end
+ `WAIT_BYTE:
+ begin
+ if (processRxDataInWEn == 1'b1)
+ begin
+ NextState_prRxByte <= `CHK_ST;
+ next_RxByte <= RxByteIn;
+ next_RxCtrl <= RxCtrlIn;
+ next_processRxByteRdy <= 1'b0;
+ end
+ end
+ `HSHAKE_FIN:
+ begin
+ next_RxDataOutWEn <= 1'b0;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `HSHAKE_CHK:
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN;
+ if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RxDataOutWEn <= 1'b1;
+ end
+ `CHK_PID_DO_CHK:
+ begin
+ if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+ begin
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_processRxByteRdy <= 1'b1;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_RXDataByteCnt <= 0;
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_START;
+ next_RxDataOutWEn <= 1'b1;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `CHK_PID_FIRST_BYTE_PROC:
+ begin
+ next_rstCRC <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ case (RxByte[1:0] )
+ `SPECIAL: //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ `TOKEN: //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ `HANDSHAKE: //Handshake PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_ACKRxed <= 1'b1;
+ 2'b10:
+ next_NAKRxed <= 1'b1;
+ 2'b11:
+ next_stallRxed <= 1'b1;
+ default:
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST;
+ end
+ `DATA: //Data PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_dataSequence <= 1'b0;
+ 2'b10:
+ next_dataSequence <= 1'b1;
+ default:
+ $display ("Invalid DATA PID detected in ProcessRXByte\n");
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_FIN:
+ begin
+ next_CRC16En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC16Result != 16'hb001)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC16En <= 1'b1;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `DATA_FIN;
+ end
+ `DATA_WAIT_CRC:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `DATA_CHK_STRM;
+ end
+ end
+ `TOKEN_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC5Result != 5'h6)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ if (RXDataByteCnt > 10'h2)
+ begin
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `TOKEN_FIN;
+ end
+ `TOKEN_FIN:
+ begin
+ next_CRC5En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `TOKEN_WAIT_CRC:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `TOKEN_CHK_STRM;
+ end
+ end
+ `CHK_SYNC_DO:
+ begin
+ if (RxByte == `SYNC_BYTE)
+ next_RXByteStMachCurrState <= `CHECK_PID_ST;
+ else
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `IDLE_CHK_START:
+ begin
+ if (RxCtrl == `DATA_START)
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxByte <= `START_PRBY;
+ else
+ CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RxDataOut <= 8'h00;
+ RxCtrlOut <= 8'h00;
+ RxDataOutWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ processRxByteRdy <= 1'b1;
+ RxByte <= 8'h00;
+ RxCtrl <= 8'h00;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RxOverflow <= 1'b0;
+ RxTimeOut <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ RXDataByteCnt <= 10'h00;
+ end
+ else
+ begin
+ RxDataOut <= next_RxDataOut;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOutWEn <= next_RxDataOutWEn;
+ rstCRC <= next_rstCRC;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ processRxByteRdy <= next_processRxByteRdy;
+ RxByte <= next_RxByte;
+ RxCtrl <= next_RxCtrl;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RxOverflow <= next_RxOverflow;
+ RxTimeOut <= next_RxTimeOut;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ RXDataByteCnt <= next_RXDataByteCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf (revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIEReceiver\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+I 59 63 0 Builtin Exit | 129540,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+I 51 54 0 Builtin Entry | 86360,167640
+I 50 54 0 Builtin Exit | 145248,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+I 69 72 0 Builtin Entry | 64536,194920
+I 68 72 0 Builtin Exit | 131860,37310
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+ 42587,49163 46360,45589 52513,44944 58666,44299\
+ 125961,48736 136382,49232
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+ 52215,60675 60863,63077 65955,63276 71048,63475\
+ 83004,63522 85042,64000 87080,64479 134402,67217\
+ 135100,67416
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+ 50130,82213 57873,81220 62984,81170 68095,81121\
+ 127305,85134 133657,85531
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+ 48543,109011 48344,105238 49038,103700 49733,102162\
+ 52773,100254 56507,99743 60241,99232 74292,101683\
+ 79033,101771 83774,101859 131499,104027 132998,104525
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+ 54597,124090 58369,121813 62636,121465 66904,121118\
+ 125138,124972 131490,125269
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+ 57971,146130 62339,145137 65812,144988 69286,144839\
+ 125497,147159 130261,147357
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+ 41595,29611 48940,28220 55540,28071 62140,27923\
+ 127685,31371 137213,31768
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+ 164206,62109 167707,83613 169507,92702
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/6/"
+S 174 81 53248 ELLIPSE "States" | 85374,175380 6500 6500
+W 169 72 0 71 68 BEZIER "Transitions" | 86442,160488 87123,152997 131179,46721 131860,39230
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `FULL_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `LOW_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+ 188903,162522 181196,168609 172535,178212 163875,187816\
+ 140506,197413 125270,198727 110035,200042 80303,196085\
+ 61192,193841
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+ 22117,178006 22117,149970 33211,139263 44305,128556\
+ 88681,113764 103817,110238 118953,106712 136069,108777\
+ 144153,109121
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+I 188 90 0 Builtin Exit | 126468,30181
+I 187 90 0 Builtin Entry | 59972,198555
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/7/"
+S 185 90 57344 ELLIPSE "States" | 81562,170615 6500 6500
+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+I 177 81 0 Builtin Exit | 137732,35774
+I 176 81 0 Builtin Entry | 63784,203320
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+I 200 99 0 Builtin Entry | 53777,190526
+I 199 99 0 Builtin Exit | 120480,22566
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+I 238 236 0 Builtin Exit | 129540,111760
+I 237 236 0 Builtin Entry | 86360,167640
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+I 244 242 0 Builtin Exit | 129540,111760
+I 243 242 0 Builtin Entry | 86360,167640
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (revision 264)
@@ -0,0 +1,370 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+ clk, rst,
+ //readUSBWireData
+ USBWireDataIn,
+ USBWireDataInTick,
+ //writeUSBWireData
+ USBWireDataOut,
+ USBWireCtrlOut,
+ USBWireDataOutTick,
+ //SIEReceiver
+ connectState,
+ //processRxBit
+ resumeDetected,
+ //processRxByte
+ RxCtrlOut,
+ RxDataOutWEn,
+ RxDataOut,
+ //SIETransmitter
+ SIEPortCtrlIn,
+ SIEPortDataIn,
+ SIEPortTxRdy,
+ SIEPortWEn,
+ //lineControlUpdate
+ fullSpeedPolarity,
+ fullSpeedBitRate,
+ noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut;
+output RxDataOutWEn;
+output [7:0] RxDataOut;
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy;
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut;
+wire RxDataOutWEn;
+wire [7:0] RxDataOut;
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy;
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En;
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En;
+wire [4:0] RxCRC5Result;
+wire RxCRC5_8Bit;
+wire [7:0] RxCRCData;
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En;
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En;
+wire [4:0] TxCRC5Result;
+wire TxCRC5_8Bit;
+wire [7:0] TxCRCData;
+wire TxRstCRC;
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy;
+wire processTxByteWEn;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity(fullSpeedPolarity),
+ .fullSpeedBitRate(fullSpeedBitRate),
+ .JBit(JBit),
+ .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+ (
+ .RxWireDataIn(RxWireDataFromWireRx),
+ .RxWireDataWEn(RxWireDataWEn),
+ .clk(clk),
+ .connectState(connectState),
+ .rst(rst) );
+
+
+processRxBit u_processRxBit
+ (.JBit(JBit),
+ .KBit(KBit),
+ .RxBitsIn(RxWireDataFromWireRx),
+ .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
+ .clk(clk),
+ .processRxBitRdy(processRxBitRdy),
+ .processRxBitsWEn(RxWireDataWEn),
+ .processRxByteWEn(processRxByteWEn),
+ .resumeDetected(resumeDetected),
+ .rst(rst),
+ .processRxByteRdy(processRxByteRdy) );
+
+processRxByte u_processRxByte
+ (.CRC16En(RxCRC16En),
+ .CRC16Result(RxCRC16Result),
+ .CRC16UpdateRdy(RxCRC16UpdateRdy),
+ .CRC5En(RxCRC5En),
+ .CRC5Result(RxCRC5Result),
+ .CRC5_8Bit(RxCRC5_8Bit),
+ .CRC5UpdateRdy(RxCRC5UpdateRdy),
+ .CRCData(RxCRCData),
+ .RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
+ .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataOut),
+ .clk(clk),
+ .processRxDataInWEn(processRxByteWEn),
+ .rst(rst),
+ .rstCRC(RxRstCRC),
+ .processRxByteRdy(processRxByteRdy) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC5Result),
+ .CRCEn(RxCRC5En),
+ .CRC5_8BitIn(RxCRC5_8Bit),
+ .dataIn(RxCRCData),
+ .ready(RxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC16Result),
+ .CRCEn(RxCRC16En),
+ .dataIn(RxCRCData),
+ .ready(RxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En(TxCRC16En),
+ .CRC16Result(TxCRC16Result),
+ .CRC5En(TxCRC5En),
+ .CRC5Result(TxCRC5Result),
+ .CRC5_8Bit(TxCRC5_8Bit),
+ .CRCData(TxCRCData),
+ .CRC5UpdateRdy(TxCRC5UpdateRdy),
+ .CRC16UpdateRdy(TxCRC16UpdateRdy),
+ .JBit(JBit),
+ .KBit(KBit),
+ .SIEPortCtrlIn(SIEPortCtrlIn),
+ .SIEPortDataIn(SIEPortDataIn),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEn),
+ .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
+ .TxByteOut(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(SIETxCtrl),
+ .USBWireData(SIETxData),
+ .USBWireGnt(SIETxGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(SIETxReq),
+ .USBWireWEn(SIETxWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .rstCRC(TxRstCRC) );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC5Result),
+ .CRCEn(TxCRC5En),
+ .CRC5_8BitIn(TxCRC5_8Bit),
+ .dataIn(TxCRCData),
+ .ready(TxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC16Result),
+ .CRCEn(TxCRC16En),
+ .dataIn(TxCRCData),
+ .ready(TxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+processTxByte u_processTxByte
+ (.JBit(JBit),
+ .KBit(KBit),
+ .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
+ .TxByteIn(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(prcTxByteCtrl),
+ .USBWireData(prcTxByteData),
+ .USBWireGnt(prcTxByteGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(prcTxByteReq),
+ .USBWireWEn(prcTxByteWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .fullSpeedRate(fullSpeedBitRate) );
+
+USBTxWireArbiter u_USBTxWireArbiter
+ (.SIETxCtrl(SIETxCtrl),
+ .SIETxData(SIETxData),
+ .SIETxGnt(SIETxGnt),
+ .SIETxReq(SIETxReq),
+ .SIETxWEn(SIETxWEn),
+ .TxBits(TxBitsFromArbToWire),
+ .TxCtl(TxCtrlFromArbToWire),
+ .USBWireRdyIn(USBWireRdy),
+ .USBWireRdyOut(USBWireReadyFromTxArb),
+ .USBWireWEn(USBWireWEn),
+ .clk(clk),
+ .prcTxByteCtrl(prcTxByteCtrl),
+ .prcTxByteData(prcTxByteData),
+ .prcTxByteGnt(prcTxByteGnt),
+ .prcTxByteReq(prcTxByteReq),
+ .prcTxByteWEn(prcTxByteWEn),
+ .rst(rst) );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn(TxBitsFromArbToWire),
+ .TxBitsOut(USBWireDataOut),
+ .TxDataOutTick(USBWireDataOutTick),
+ .TxCtrlIn(TxCtrlFromArbToWire),
+ .TxCtrlOut(USBWireCtrlOut),
+ .USBWireRdy(USBWireRdy),
+ .USBWireWEn(USBWireWEn),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .fullSpeedRate(fullSpeedBitRate),
+ .clk(clk),
+ .rst(rst)
+ );
+
+
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn(USBWireDataIn),
+ .RxDataInTick(USBWireDataInTick),
+ .RxBitsOut(RxWireDataFromWireRx),
+ .SIERxRdyIn(processRxBitRdy),
+ .SIERxWEn(RxWireDataWEn),
+ .fullSpeedRate(fullSpeedBitRate),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .clk(clk),
+ .rst(rst),
+ .noActivityTimeOut(noActivityTimeOut));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf (revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processRxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+S 286 50 73728 ELLIPSE "States" | 54701,94283 6500 6500
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+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC16Result != 16'hb001)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC16En <= 1'b1;\n end\nendcase\nRxDataOutWEn <= 1'b1;"
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+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
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+I 291 50 0 Builtin Exit | 90483,62922
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+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+I 20 17 0 Builtin Entry | 45216,248076
+I 21 17 0 Builtin Exit | 89220,92674
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,94696 6500 6500
+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
+A 296 0 1 TEXT "Actions" | 13933,264927 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin \n RxStatus <= \n {1'b0, next_dataSequence, \n next_ACKRxed, \n next_stallRxed, next_NAKRxed, \n next_RxOverflow, \n next_bitStuffError, next_CRCError };\nend"
+L 297 298 0 TEXT "Labels" | 82848,260279 1 0 0 "RxDataOut[7:0]"
+I 298 0 130 Builtin OutPort | 76848,260279 "" ""
+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 300 0 130 Builtin OutPort | 76848,255265 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
+I 302 0 2 Builtin OutPort | 76139,250245 "" ""
+L 303 304 0 TEXT "Labels" | 84462,243195 1 0 0 "RxByteIn[7:0]"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 117500,64680 1 0 0 "TOKEN"
+W 36 41 0 38 371 BEZIER "Transitions" | 34704,258592 38731,254357 47806,246433 31745,235718
+I 37 41 0 Builtin Exit | 85286,98575
+I 38 41 0 Builtin Entry | 30541,258592
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
+L 305 306 0 TEXT "Labels" | 84465,238172 1 0 0 "RxCtrlIn[7:0]"
+I 306 0 130 Builtin InPort | 78465,238172 "" ""
+L 307 308 0 TEXT "Labels" | 85176,232428 1 0 0 "processRxDataInWEn"
+I 308 0 2 Builtin InPort | 78462,232428 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
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+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
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+I 314 0 130 Builtin InPort | 125655,250603 "" ""
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+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
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+ 96662,35330 112340,35732
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
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+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
+L 327 328 0 TEXT "Labels" | 175074,260836 1 0 0 "RxOverflow"
+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
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+I 332 0 2 Builtin Signal | 171717,252268 "" ""
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+I 334 0 2 Builtin Signal | 172074,247627 "" ""
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+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
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+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
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+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
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+I 338 0 2 Builtin Signal | 172074,238702 "" ""
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+I 342 0 130 Builtin Signal | 171929,216623 "" ""
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+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
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+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
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+ 41868,138924 51896,113272 59871,108777 67846,104282\
+ 74724,97474 86324,92674
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+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC5Result != 5'h6)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n if (RXDataByteCnt > 10'h2) \n begin\n RxOverflow <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n else \n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC5_8Bit <= 1'b1;\n CRC5En <= 1'b1;\n end\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n `SPECIAL: //Special PID.\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n `TOKEN: //Token PID\n begin\n RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n RXDataByteCnt <= 0;\n end\n `HANDSHAKE: //Handshake PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n ACKRxed <= 1'b1;\n 2'b10:\n NAKRxed <= 1'b1;\n 2'b11:\n stallRxed <= 1'b1;\n default:\n begin\n $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n end\n endcase\n RXByteStMachCurrState <= `HS_BYTE_ST;\n end\n `DATA: //Data PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n dataSequence <= 1'b0;\n 2'b10:\n dataSequence <= 1'b1;\n default:\n $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n endcase\n RXByteStMachCurrState <= `DATA_BYTE_ST;\n RXDataByteCnt <= 0;\n end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+ 110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+ 89364,102368 89220,95212 89220,94846
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (revision 264)
@@ -0,0 +1,222 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut);
+input [1:0] RxBitsIn;
+output RxDataInTick;
+input SIERxRdyIn;
+input clk;
+input fullSpeedRate;
+input rst;
+input TxWireActiveDrive;
+output [1:0] RxBitsOut;
+output SIERxWEn;
+output noActivityTimeOut;
+
+wire [1:0] RxBitsIn;
+reg RxDataInTick;
+wire SIERxRdyIn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg [1:0] RxBitsOut;
+reg SIERxWEn;
+reg noActivityTimeOut;
+
+// local registers
+reg [1:0]buffer0;
+reg [1:0]buffer1;
+reg [1:0]buffer2;
+reg [1:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireActive;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 2'b00;
+ buffer1 <= 2'b00;
+ buffer2 <= 2'b00;
+ buffer3 <= 2'b00;
+ RxDataInTick <= 1'b0;
+ RxWireActive <= 1'b0;
+ end
+ else begin
+ RxBitsInReg <= RxBitsIn; //sync to local clock to avoid metastability issues
+ incBufferCnt <= 1'b0; //default value
+ oldRxBitsIn <= RxBitsInReg;
+ if (oldRxBitsIn != RxBitsInReg) begin //if edge detected then
+ i <= 5'b00000; //reset the counter
+ RxWireActive <= 1'b1; // flag receive activity
+ end
+ else begin
+ i <= i + 1'b1;
+ RxWireActive <= 1'b0;
+ end
+ if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+ begin
+ RxDataInTick <= !RxDataInTick;
+ if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= RxBitsInReg;
+ 2'b01 : buffer1 <= RxBitsInReg;
+ 2'b10 : buffer2 <= RxBitsInReg;
+ 2'b11 : buffer3 <= RxBitsInReg;
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutIndex <= 2'b00;
+ RxBitsOut <= 2'b00;
+ SIERxWEn <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ else begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_NOT_EMPTY:
+ begin
+ if (bufferCnt != 3'b000)
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+ end
+ `WAIT_SIE_RX_READY:
+ begin
+ if (SIERxRdyIn == 1'b1)
+ begin
+ SIERxWEn <= 1'b1;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 : RxBitsOut <= buffer0;
+ 2'b01 : RxBitsOut <= buffer1;
+ 2'b10 : RxBitsOut <= buffer2;
+ 2'b11 : RxBitsOut <= buffer3;
+ endcase
+ end
+ end
+ `SIE_RX_WRITE:
+ begin
+ SIERxWEn <= 1'b0;
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ endcase
+ end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+ if (rst) begin
+ timeOutCnt <= 16'h0000;
+ noActivityTimeOut <= 1'b0;
+ end
+ else begin
+ if (TxWireActiveDrive == 1'b1 || RxWireActive == 1'b1)
+ timeOutCnt <= 16'h0000;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1;
+ //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+ if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+ || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+ //if (timeOutCnt == 16'h200) //temporary hack
+ noActivityTimeOut <= 1'b1;
+ else
+ noActivityTimeOut <= 1'b0;
+ end
+end
+
+
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v (revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input CRC5_8BitIn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [4:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire CRC5_8BitIn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 5'h1f;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0) begin
+ if (CRCEn == 1'b1) begin
+ ready <= 1'b0;
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ if (CRC5_8BitIn == 1'b1) begin
+ loopEnd <= 4'h7;
+ end
+ else begin
+ loopEnd <= 4'h2;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[4:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == loopEnd) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v (revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v (revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+ `START_SDC:
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v (revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "SCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "SCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "SCTxPortCntl <= 8'h00;\nSCTxPortData <= 8'h00;\nSCTxPortWEn <= 1'b0; \nSCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "SCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "SCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "SCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v (revision 264)
@@ -0,0 +1,390 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0SendStall <= dataIn[3];
+ EP0DataSequence <= dataIn[2];
+ EP0SetReady <= dataIn[1];
+ EP0Enable <= dataIn[0];
+ end
+ `EP1_CTRL_REG : begin
+ EP1SendStall <= dataIn[3];
+ EP1DataSequence <= dataIn[2];
+ EP1SetReady <= dataIn[1];
+ EP1Enable <= dataIn[0];
+ end
+ `EP2_CTRL_REG : begin
+ EP2SendStall <= dataIn[3];
+ EP2DataSequence <= dataIn[2];
+ EP2SetReady <= dataIn[1];
+ EP2Enable <= dataIn[0];
+ end
+ `EP3_CTRL_REG : begin
+ EP3SendStall <= dataIn[3];
+ EP3DataSequence <= dataIn[2];
+ EP3SetReady <= dataIn[1];
+ EP3Enable <= dataIn[0];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn[4];
+ clrSOFReq <= dataIn[3];
+ clrResetReq <= dataIn[2];
+ clrResInReq <= dataIn[1];
+ clrTransDoneReq <= dataIn[0];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (NAKSentIn == 1'b1)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedIn == 1'b1)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventIn == 1'b1)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0Ready == 1'b1)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1Ready == 1'b1)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2Ready == 1'b1)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3Ready == 1'b1)
+ EP3Ready <= 1'b0;
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
+begin
+ endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+ // async read mux
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+ endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+ endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
+ endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNum)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+ `EP0_STS_REG : dataOut <= EP0StatusReg;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+ `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+ `EP1_STS_REG : dataOut <= EP1StatusReg;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+ `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+ `EP2_STS_REG : dataOut <= EP2StatusReg;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+ `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+ `EP3_STS_REG : dataOut <= EP3StatusReg;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNum[10:8]};
+ `SC_FRAME_NUM_LSP : dataOut <= frameNum[7:0];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v (revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input SCTxPortRdyIn;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output directCntlGnt;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output sendPacketGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ:
+ begin
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ end
+ `SARB_SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `SARB_DC:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxDCEn <= 1'b0;
+ end
+ else
+ begin
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxDCEn <= next_muxDCEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output ACKRxed;
+output bitStuffError;
+output CRCError;
+output dataSequence;
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output [3:0]RxPID;
+output RXTimeOut;
+
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+wire [7:0]RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXOverflow <= 1'b0;
+ ACKRxed <= 1'b0;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXTimeOut <= 1'b0;
+ RxPID <= 4'h0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByteOld <= 8'h00;
+ end
+ else
+ begin
+ RXOverflow <= next_RXOverflow;
+ ACKRxed <= next_ACKRxed;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXTimeOut <= next_RXTimeOut;
+ RxPID <= next_RxPID;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ RXByteOld <= next_RXByteOld;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf (revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 126 65 0 Builtin Entry | 68162,237252
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170187,37688 173773,37229
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+ 198775,133379 204604,144369 205686,152818 206768,161268\
+ 205269,184079 201481,192903 197694,201727 184040,214216\
+ 173218,217462 162396,220708 133810,221642 118992,221891
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v (revision 264)
@@ -0,0 +1,493 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+ clk, rst,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(clk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone)
+ );
+
+
+endpMux u_endpMux (
+ .clk(clk),
+ .rst(rst),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rst),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v (revision 264)
@@ -0,0 +1,472 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input bitStuffError;
+input clk;
+input CRCError;
+input getPacketRdy;
+input rst;
+input [7:0]RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0]RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input sendPacketRdy;
+input [3:0]USBEndPControlReg;
+input [6:0]USBTgtAddress;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output [10:0]frameNum;
+output getPacketREn;
+output NAKSent;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output SOFRxed;
+output stallSent;
+output transDone;
+output [3:0]USBEndP;
+output [1:0]USBEndPNakTransTypeReg;
+output [1:0]USBEndPTransTypeReg;
+
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+wire CRCError;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg [10:0]frameNum, next_frameNum;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+reg NAKSent, next_NAKSent;
+wire rst;
+wire [7:0]RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0]RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg SOFRxed, next_SOFRxed;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+reg [3:0]USBEndP, next_USBEndP;
+wire [3:0]USBEndPControlReg;
+reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [7:0]PIDByte, next_PIDByte;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_getPacketREn <= getPacketREn;
+ case (CurrState_slvCntrl) // synopsys parallel_case full_case
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ begin
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `PID_ERROR;
+ end
+ end
+ `PID_ERROR:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ end
+ end
+ `SETUP_OUT_CHK:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ end
+ else if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `IN_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `START_S1:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `GET_TOKEN_WAIT_CRC:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_ADDR:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_STOP:
+ begin
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ end
+ else if (RxDataWEn == 1'b1)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_CHK_SOF:
+ begin
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ end
+ `GET_TOKEN_CHK_ADDR:
+ begin
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ stallSent <= 1'b0;
+ NAKSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ transDone <= 1'b0;
+ clrEPRdy <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ getPacketREn <= 1'b0;
+ PIDByte <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ addrEndPTemp <= 8'h00;
+ tempUSBEndPTransTypeReg <= 2'b00;
+ USBAddress <= 7'b0000000;
+ end
+ else
+ begin
+ stallSent <= next_stallSent;
+ NAKSent <= next_NAKSent;
+ SOFRxed <= next_SOFRxed;
+ transDone <= next_transDone;
+ clrEPRdy <= next_clrEPRdy;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ getPacketREn <= next_getPacketREn;
+ PIDByte <= next_PIDByte;
+ endpCRCTemp <= next_endpCRCTemp;
+ addrEndPTemp <= next_addrEndPTemp;
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ USBAddress <= next_USBAddress;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt (revision 264)
@@ -0,0 +1,24 @@
+USBHostSlave has been successfully compiled using Quartus 4.1 with Servive Pack 2
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+For those who wish to use a pre-configured Quartus project, I have included two files;
+usbhostslaveQuartusProj.qar - Quartus project archive
+usbHostSlaveNiosIDEProj.zip - NIOS IDE project zip file. You can use NIOS IDE File>>import to open the file
+
+
+If you wish to replicate the hardware setup, then you will need to replace
+the standard 50MHz oscillator with a 48MHz oscillator (Digikey XC280-ND),
+and you will need a add a Santa Cruz daughter card with two USB transceivers.
+
+If there is enough interest, I will consider producing a Santa Cruz daughter card
+with the hardware required to support this core.
+Please email me at sfielding@base2designs.com if you are interested in this option.
+
+
+Release notes:
+Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+ control reads and writes to USB flash dongle
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+ clk,
+ rst,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk;
+wire rst;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ .rclk(clk),
+ .rrst(1'b0),
+ .rce(1'b1),
+ .oe(readEn),
+ .raddr(addrOut),
+ .do(dataOut),
+ .wclk(clk),
+ .wrst(1'b0),
+ .wce(1'b1),
+ .we(writeEn),
+ .waddr(addrIn),
+ .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
+ .addrIn(addrIn),
+ .addrOut(addrOut),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(writeEn),
+ .readEn(readEn),
+ .dataOut(dataOut));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,290 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+ TxTransTypeReg, TxSOFEnableReg,
+ TxAddrReg, TxEndPReg, frameNumIn,
+ RxPktStatusIn, RxPIDIn,
+ connectStateIn,
+ SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+ hostControlSelect,
+ clrTransReq,
+ preambleEn,
+ SOFSync,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ transReq,
+ isoEn
+ );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output transReq;
+output isoEn; //enable isochronous mode
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ isoEn <= 1'b0;
+ preambleEn <= 1'b0;
+ SOFSync <= 1'b0;
+ TxTransTypeReg <= 2'b00;
+ TxLineControlReg <= 5'h00;
+ TxSOFEnableReg <= 1'b0;
+ TxAddrReg <= 7'h00;
+ TxEndPReg <= 4'h0;
+ interruptMaskReg <= 4'h0;
+ end
+ else begin
+ clrSOFReq <= 1'b0;
+ clrConnEvtReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ setTransReq <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+ begin
+ case (address)
+ `TX_CONTROL_REG : begin
+ isoEn <= dataIn[`ISO_ENABLE_BIT];
+ preambleEn <= dataIn[`PREAMBLE_ENABLE_BIT];
+ SOFSync <= dataIn[`SOF_SYNC_BIT];
+ setTransReq <= dataIn[`TRANS_REQ_BIT];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[`SOF_EN_BIT];
+ `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+ `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn[`SOF_SENT_BIT];
+ clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ SOFSentInt <= 1'b0;
+ connEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (SOFSentIn == 1'b1)
+ SOFSentInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFSentInt <= 1'b0;
+
+ if (connEventIn == 1'b1)
+ connEventInt <= 1'b1;
+ else if (clrConnEvtReq == 1'b1)
+ connEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end
+
+//transaction request set/clear
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ transReq <= 1'b0;
+ end
+ else begin
+ if (setTransReq == 1'b1)
+ transReq <= 1'b1;
+ else if (clrTransReq == 1'b1)
+ transReq <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+ TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+ fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq or isoEn)
+begin
+ case (address)
+ `TX_CONTROL_REG : dataOut <= {4'b0000, isoEn, preambleEn, SOFSync, transReq} ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+ `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+ `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+ `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumIn[10:8]};
+ `FRAME_NUM_LSB_REG : dataOut <= frameNumIn[7:0];
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn;
+ `RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v (revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// getpacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXPacketRdy;
+output [3:0]RxPID;
+output [7:0]RXPktStatus;
+
+wire clk;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+reg [7:0]RXPktStatus;
+wire [7:0]RXStreamStatusIn;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+ NextState_getPkt <= CurrState_getPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_getPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_getPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_getPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_getPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+ next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_getPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_getPkt <= `START_GP;
+ else
+ CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RxPID <= 4'h0;
+ RXOverflow <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXByteOld <= 8'h00;
+ RXTimeOut <= 1'b0;
+ end
+ else
+ begin
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RxPID <= next_RxPID;
+ RXOverflow <= next_RXOverflow;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXByteOld <= next_RXByteOld;
+ RXTimeOut <= next_RXTimeOut;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v (revision 264)
@@ -0,0 +1,436 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input clk;
+input getPacketRdy;
+input isoEn;
+input rst;
+input [7:0]RXStatus;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input transReq;
+input [1:0]transType;
+output clearTXReq;
+output getPacketREn;
+output sendPacketArbiterReq;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output transDone;
+
+reg clearTXReq, next_clearTXReq;
+wire clk;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+wire isoEn;
+wire rst;
+wire [7:0]RXStatus;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg transDone, next_transDone;
+wire transReq;
+wire [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+ NextState_hstCntrl <= CurrState_hstCntrl;
+ // Set default values for outputs and signals
+ next_transDone <= transDone;
+ next_clearTXReq <= clearTXReq;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketPID <= sendPacketPID;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_hstCntrl) // synopsys parallel_case full_case
+ `START_HC:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `TX_REQ:
+ begin
+ if (transReq == 1'b1)
+ begin
+ NextState_hstCntrl <= `WAIT_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `CHK_TYPE:
+ begin
+ if (transType == `OUTDATA0_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+ end
+ else if (transType == `IN_TRANS)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+ end
+ else if (transType == `SETUP_TRANS)
+ begin
+ NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+ end
+ else if (transType == `OUTDATA1_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+ end
+ end
+ `FLAG:
+ begin
+ next_transDone <= 1'b1;
+ next_clearTXReq <= 1'b1;
+ next_sendPacketArbiterReq <= 1'b0;
+ NextState_hstCntrl <= `FIN;
+ end
+ `FIN:
+ begin
+ next_transDone <= 1'b0;
+ next_clearTXReq <= 1'b0;
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `WAIT_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1)
+ begin
+ NextState_hstCntrl <= `CHK_TYPE;
+ end
+ end
+ `SETUP_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+ end
+ `SETUP_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+ end
+ `SETUP_WAIT_PKT_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `SETUP_HC_WAIT_RDY:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `SETUP;
+ end
+ end
+ `SETUP_WAIT_SETUP_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `SETUP_WAIT_DATA_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_DATA_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+ end
+ end
+ `IN_CHK_FOR_ERROR:
+ begin
+ if (isoEn == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+ RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `IN_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+ end
+ `IN_WAIT_IN_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `IN;
+ end
+ end
+ `IN_WAIT_SP_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `IN_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+ end
+ `IN_WAIT_ACK_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_DATA0_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CHK_ISO;
+ end
+ end
+ `OUT0_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `OUT0_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT0_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+ end
+ `OUT0_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+ end
+ `OUT0_CHK_ISO:
+ begin
+ if (isoEn == 1'b0)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `OUT1_WAIT_DATA1_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT1_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT1_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+ end
+ `OUT1_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_hstCntrl <= `START_HC;
+ else
+ CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ transDone <= 1'b0;
+ clearTXReq <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ transDone <= next_transDone;
+ clearTXReq <= next_clearTXReq;
+ getPacketREn <= next_getPacketREn;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn,
+ TxBitsOut,
+ TxDataOutTick,
+ TxCtrlIn,
+ TxCtrlOut,
+ USBWireRdy,
+ USBWireWEn,
+ TxWireActiveDrive,
+ fullSpeedRate,
+ clk,
+ rst
+ );
+
+input [1:0] TxBitsIn;
+input TxCtrlIn;
+input USBWireWEn;
+input clk;
+input fullSpeedRate;
+input rst;
+output [1:0] TxBitsOut;
+output TxDataOutTick;
+output TxCtrlOut;
+output USBWireRdy;
+output TxWireActiveDrive;
+
+wire [1:0] TxBitsIn;
+reg [1:0] TxBitsOut;
+reg TxDataOutTick;
+wire TxCtrlIn;
+reg TxCtrlOut;
+reg USBWireRdy;
+wire USBWireWEn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg TxWireActiveDrive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk) begin
+ if (rst == 1'b1) begin
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ USBWireRdy <= 1'b0;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ else begin
+ case (bufferInStMachCurrState)
+ `WAIT_BUFFER_NOT_FULL:
+ begin
+ if (bufferCnt != `BUFFER_FULL)
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ end
+ `WAIT_WRITE_REQ:
+ begin
+ if (USBWireWEn == 1'b1)
+ begin
+ incBufferCnt <= 1'b1;
+ USBWireRdy <= 1'b0;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+ 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+ 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+ 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+ end
+ end
+ `CLR_INC_BUFFER_CNT:
+ begin
+ incBufferCnt <= 1'b0;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ fullSpeedTick <= 1'b0;
+ lowSpeedTick <= 1'b0;
+ end
+ else
+ begin
+ i <= i + 1'b1;
+ if (i[1:0] == 2'b00)
+ fullSpeedTick <= 1'b1;
+ else
+ fullSpeedTick <= 1'b0;
+ if (i == 5'b00000)
+ lowSpeedTick <= 1'b1;
+ else
+ lowSpeedTick <= 1'b0;
+ end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferOutIndex <= 2'b00;
+ decBufferCnt <= 1'b0;
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ TxDataOutTick <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState)
+ `WAIT_LINE_WRITE:
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+ begin
+ TxDataOutTick <= !TxDataOutTick;
+ if (bufferCnt == 0) begin
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ end
+ else begin
+ bufferOutStMachCurrState <= `LINE_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0[2:1];
+ TxCtrlOut <= buffer0[0];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1[2:1];
+ TxCtrlOut <= buffer1[0];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2[2:1];
+ TxCtrlOut <= buffer2[0];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3[2:1];
+ TxCtrlOut <= buffer3[0];
+ end
+ endcase
+ end
+ end
+ end
+ `LINE_WRITE:
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ endcase
+ end
+end
+
+// control 'TxWireActiveDrive'
+always @(TxCtrlOut)
+begin
+ if (TxCtrlOut == `DRIVE)
+ TxWireActiveDrive <= 1'b1;
+ else
+ TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf (revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
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+I 16 6 0 Builtin Reset | 178237,395710
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+I 39 0 2 Builtin InPort | 189447,542126 "" ""
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+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
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+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
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+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
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+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut = SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
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+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf (revision 264)
@@ -0,0 +1,277 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=284
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v (revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveSendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input [3:0]PID;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+input sendPacketWEn;
+output fifoReadEn;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+wire [3:0]PID;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+ NextState_slvSndPkt <= CurrState_slvSndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+ `START_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ end
+ `SP_WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP1_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `SP1_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_SCTxPortReq <= 1'b0;
+ end
+ `SP_NOT_DATA:
+ begin
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_SEND_PID_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= PIDNotPID;
+ next_SCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SP_SEND_PID_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_NOT_DATA;
+ end
+ end
+ `SP_D0_D1_READ_FIFO:
+ begin
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= fifoData;
+ next_SCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+ end
+ `SP_D0_D1_WAIT_READ_FIFO:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `SP_D0_D1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+ end
+ end
+ `SP_D0_D1_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_D0_D1_TERM_BYTE:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `SP_D0_D1_CLR_WEN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ `SP_D0_D1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvSndPkt <= `START_SP1;
+ else
+ CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ SCTxPortData <= 8'h00;
+ SCTxPortCntl <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v (revision 264)
@@ -0,0 +1,516 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlave.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+ clk,
+ rst,
+ address_i,
+ data_i,
+ data_o,
+ writeEn,
+ strobe_i,
+ ack_o,
+ hostSOFSentIntOut,
+ hostConnEventIntOut,
+ hostResumeIntOut,
+ hostTransDoneIntOut,
+ slaveNAKSentIntOut,
+ slaveSOFRxedIntOut,
+ slaveResetEventIntOut,
+ slaveResumeIntOut,
+ slaveTransDoneIntOut,
+ USBWireDataIn,
+ USBWireDataInTick,
+ USBWireDataOut,
+ USBWireDataOutTick,
+ USBWireCtrlOut,
+ USBFullSpeed
+ );
+ parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+ parameter HOST_FIFO_ADDR_WIDTH = 6;
+ parameter EP0_FIFO_DEPTH = 64;
+ parameter EP0_FIFO_ADDR_WIDTH = 6;
+ parameter EP1_FIFO_DEPTH = 64;
+ parameter EP1_FIFO_ADDR_WIDTH = 6;
+ parameter EP2_FIFO_DEPTH = 64;
+ parameter EP2_FIFO_ADDR_WIDTH = 6;
+ parameter EP3_FIFO_DEPTH = 64;
+ parameter EP3_FIFO_ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [7:0] address_i;
+input [7:0] data_i;
+output [7:0] data_o;
+input writeEn;
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut;
+output hostConnEventIntOut;
+output hostResumeIntOut;
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut;
+output slaveResetEventIntOut;
+output slaveResumeIntOut;
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk;
+wire rst;
+wire [7:0] address_i;
+wire [7:0] data_i;
+wire [7:0] data_o;
+wire writeEn;
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel;
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE;
+wire [7:0] hostTxFifoData;
+wire hostTxFifoEmpty;
+wire hostRxFifoWE;
+wire [7:0] hostRxFifoData;
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut;
+wire [7:0] RxDataFromSIE;
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState;
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;
+
+usbHostControl u_usbHostControl(
+ .clk(clk),
+ .rst(rst),
+ .TxFifoRE(hostTxFifoRE),
+ .TxFifoData(hostTxFifoData),
+ .TxFifoEmpty(hostTxFifoEmpty),
+ .RxFifoWE(hostRxFifoWE),
+ .RxFifoData(hostRxFifoData),
+ .RxFifoFull(hostRxFifoFull),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .fullSpeedRate(fullSpeedBitRateFromHost),
+ .fullSpeedPol(fullSpeedPolarityFromHost),
+ .HCTxPortEn(SIEPortWEnFromHost),
+ .HCTxPortRdy(SIEPortTxRdy),
+ .HCTxPortData(SIEPortDataInFromHost),
+ .HCTxPortCtrl(SIEPortCtrlInFromHost),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[3:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFSentIntOut(hostSOFSentIntOut),
+ .connEventIntOut(hostConnEventIntOut),
+ .resumeIntOut(hostResumeIntOut),
+ .transDoneIntOut(hostTransDoneIntOut),
+ .hostControlSelect(hostControlSel) );
+
+
+usbSlaveControl u_usbSlaveControl(
+ .clk(clk),
+ .rst(rst),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .RxFifoData(slaveRxFifoData),
+ .fullSpeedRate(fullSpeedBitRateFromSlave),
+ .fullSpeedPol(fullSpeedPolarityFromSlave),
+ .SCTxPortEn(SIEPortWEnFromSlave),
+ .SCTxPortRdy(SIEPortTxRdy),
+ .SCTxPortData(SIEPortDataInFromSlave),
+ .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[4:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromSlaveControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFRxedIntOut(slaveSOFRxedIntOut),
+ .resetEventIntOut(slaveResetEventIntOut),
+ .resumeIntOut(slaveResumeIntOut),
+ .transDoneIntOut(slaveTransDoneIntOut),
+ .NAKSentIntOut(slaveNAKSentIntOut),
+ .slaveControlSelect(slaveControlSel),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+wishBoneBI u_wishBoneBI (
+ .address(address_i),
+ .dataIn(data_i),
+ .dataOut(data_o),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .clk(clk),
+ .rst(rst),
+ .hostControlSel(hostControlSel),
+ .hostRxFifoSel(hostRxFifoSel),
+ .hostTxFifoSel(hostTxFifoSel),
+ .slaveControlSel(slaveControlSel),
+ .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
+ .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
+ .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
+ .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
+ .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
+ .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
+ .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
+ .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .dataFromHostControl(dataFromHostControl),
+ .dataFromHostRxFifo(dataFromHostRxFifo),
+ .dataFromHostTxFifo(dataFromHostTxFifo),
+ .dataFromSlaveControl(dataFromSlaveControl),
+ .dataFromEP0RxFifo(dataFromEP0RxFifo),
+ .dataFromEP1RxFifo(dataFromEP1RxFifo),
+ .dataFromEP2RxFifo(dataFromEP2RxFifo),
+ .dataFromEP3RxFifo(dataFromEP3RxFifo),
+ .dataFromEP0TxFifo(dataFromEP0TxFifo),
+ .dataFromEP1TxFifo(dataFromEP1TxFifo),
+ .dataFromEP2TxFifo(dataFromEP2TxFifo),
+ .dataFromEP3TxFifo(dataFromEP3TxFifo),
+ .dataFromHostSlaveMux(dataFromHostSlaveMux)
+ );
+
+hostSlaveMux u_hostSlaveMux(
+ .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+ .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+ .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+ .SIEPortDataInToSIE(SIEPortDataInToSIE),
+ .SIEPortDataInFromHost(SIEPortDataInFromHost),
+ .SIEPortDataInFromSlave(SIEPortDataInFromSlave),
+ .SIEPortWEnToSIE(SIEPortWEnToSIE),
+ .SIEPortWEnFromHost(SIEPortWEnFromHost),
+ .SIEPortWEnFromSlave(SIEPortWEnFromSlave),
+ .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+ .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+ .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+ .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+ .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+ .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+ .dataIn(data_i),
+ .dataOut(dataFromHostSlaveMux),
+ .address(address_i[0]),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+ .clk(clk),
+ .rst(rst),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .connectState(connectState),
+ .resumeDetected(resumeDetected),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataFromSIE),
+ .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+ .SIEPortDataIn(SIEPortDataInToSIE),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEnToSIE),
+ .fullSpeedPolarity(fullSpeedPolarityToSIE),
+ .fullSpeedBitRate(fullSpeedBitRateToSIE),
+ .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(hostTxFifoRE),
+ .fifoEmpty(hostTxFifoEmpty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostTxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostTxFifo),
+ .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(hostRxFifoWE),
+ .fifoFull(hostRxFifoFull),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostRxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostRxFifo),
+ .fifoDataIn(hostRxFifoData) );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP0REn),
+ .fifoEmpty(TxFifoEP0Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0TxFifo),
+ .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP1REn),
+ .fifoEmpty(TxFifoEP1Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1TxFifo),
+ .fifoDataOut(TxFifoEP1Data) );
+
+ TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP2REn),
+ .fifoEmpty(TxFifoEP2Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2TxFifo),
+ .fifoDataOut(TxFifoEP2Data) );
+
+ TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP3REn),
+ .fifoEmpty(TxFifoEP3Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3TxFifo),
+ .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP0WEn),
+ .fifoFull(RxFifoEP0Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP1WEn),
+ .fifoFull(RxFifoEP1Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP2WEn),
+ .fifoFull(RxFifoEP2Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP3WEn),
+ .fifoFull(RxFifoEP3Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (revision 264)
@@ -0,0 +1,276 @@
+
+
+USBHostControlBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address , dataIn , dataOut , writeEn ,
+ strobe_i ,
+ clk , rst ,
+ SOFSentIntOut , connEventIntOut , resumeIntOut , transDoneIntOut ,
+ TxTransTypeReg , TxSOFEnableReg ,
+ TxAddrReg , TxEndPReg , frameNumIn ,
+ RxPktStatusIn , RxPIDIn ,
+ connectStateIn ,
+ SOFSentIn , connEventIn , resumeIntIn , transDoneIn ,
+ hostControlSelect ,
+ clrTransReq ,
+ preambleEn ,
+ SOFSync ,
+ TxLineState ,
+ LineDirectControlEn ,
+ fullSpeedPol ,
+ fullSpeedRate ,
+ transReq
+ );
+input [3 :0 ] address ;
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+output SOFSentIntOut ;
+output connEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+
+output [1 :0 ] TxTransTypeReg ;
+output TxSOFEnableReg ;
+output [6 :0 ] TxAddrReg ;
+output [3 :0 ] TxEndPReg ;
+input [10 :0 ] frameNumIn ;
+input [7 :0 ] RxPktStatusIn ;
+input [3 :0 ] RxPIDIn ;
+input [1 :0 ] connectStateIn ;
+input SOFSentIn ;
+input connEventIn ;
+input resumeIntIn ;
+input transDoneIn ;
+input hostControlSelect ;
+input clrTransReq ;
+output preambleEn ;
+output SOFSync ;
+output [1 :0 ] TxLineState ;
+output LineDirectControlEn ;
+output fullSpeedPol ;
+output fullSpeedRate ;
+output transReq ;
+
+wire [3 :0 ] address ;
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+
+reg SOFSentIntOut ;
+reg connEventIntOut ;
+reg resumeIntOut ;
+reg transDoneIntOut ;
+
+reg [1 :0 ] TxTransTypeReg ;
+reg TxSOFEnableReg ;
+reg [6 :0 ] TxAddrReg ;
+reg [3 :0 ] TxEndPReg ;
+wire [10 :0 ] frameNumIn ;
+wire [7 :0 ] RxPktStatusIn ;
+wire [3 :0 ] RxPIDIn ;
+wire [1 :0 ] connectStateIn ;
+
+wire SOFSentIn ;
+wire connEventIn ;
+wire resumeIntIn ;
+wire transDoneIn ;
+wire hostControlSelect ;
+wire clrTransReq ;
+reg preambleEn ;
+reg SOFSync ;
+reg [1 :0 ] TxLineState ;
+reg LineDirectControlEn ;
+reg fullSpeedPol ;
+reg fullSpeedRate ;
+reg transReq ;
+
+//internal wire and regs
+reg [1 :0 ] TxControlReg ;
+reg [4 :0 ] TxLineControlReg ;
+reg clrSOFReq ;
+reg clrConnEvtReq ;
+reg clrResInReq ;
+reg clrTransDoneReq ;
+reg SOFSentInt ;
+reg connEventInt ;
+reg resumeInt ;
+reg transDoneInt ;
+reg [3 :0 ] interruptMaskReg ;
+reg setTransReq ;
+
+//sync write demux
+always @(posedge clk )
+begin
+ clrSOFReq <= 1'b0 ;
+ clrConnEvtReq <= 1'b0 ;
+ clrResInReq <= 1'b0 ;
+ clrTransDoneReq <= 1'b0 ;
+ setTransReq <= 1'b0 ;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1 )
+ begin
+ case (address )
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn [2 ];
+ SOFSync <= dataIn [1 ];
+ setTransReq <= dataIn [0 ];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn [1 :0 ];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn [4 :0 ];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn [0 ];
+ `TX_ADDR_REG : TxAddrReg <= dataIn [6 :0 ];
+ `TX_ENDP_REG : TxEndPReg <= dataIn [3 :0 ];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn [3 ];
+ clrConnEvtReq <= dataIn [2 ];
+ clrResInReq <= dataIn [1 ];
+ clrTransDoneReq <= dataIn [0 ];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn [3 :0 ];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk )
+begin
+ if (SOFSentIn == 1'b1 )
+ SOFSentInt <= 1'b1 ;
+ else if (clrSOFReq == 1'b1 )
+ SOFSentInt <= 1'b0 ;
+
+ if (connEventIn == 1'b1 )
+ connEventInt <= 1'b1 ;
+ else if (clrConnEvtReq == 1'b1 )
+ connEventInt <= 1'b0 ;
+
+ if (resumeIntIn == 1'b1 )
+ resumeInt <= 1'b1 ;
+ else if (clrResInReq == 1'b1 )
+ resumeInt <= 1'b0 ;
+
+ if (transDoneIn == 1'b1 )
+ transDoneInt <= 1'b1 ;
+ else if (clrTransDoneReq == 1'b1 )
+ transDoneInt <= 1'b0 ;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt ) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg [`TRANS_DONE_BIT ];
+ resumeIntOut <= resumeInt & interruptMaskReg [`RESUME_INT_BIT ];
+ connEventIntOut <= connEventInt & interruptMaskReg [`CONNECTION_EVENT_BIT ];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg [`SOF_SENT_BIT ];
+end
+
+//transaction request set/clear
+always @(posedge clk )
+begin
+ if (setTransReq == 1'b1 )
+ transReq <= 1'b1 ;
+ else if (clrTransReq == 1'b1 )
+ transReq <= 1'b0 ;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg ) begin
+ TxLineState <= TxLineControlReg [`TX_LINE_STATE_MSBIT :`TX_LINE_STATE_LSBIT ];
+ LineDirectControlEn <= TxLineControlReg [`DIRECT_CONTROL_BIT ];
+ fullSpeedPol <= TxLineControlReg [`FULL_SPEED_LINE_POLARITY_BIT ];
+ fullSpeedRate <= TxLineControlReg [`FULL_SPEED_LINE_RATE_BIT ];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq )
+begin
+ case (address )
+ `TX_CONTROL_REG : dataOut <= {5'b00000 , preambleEn , SOFSync , transReq } ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000 , TxTransTypeReg };
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000 , TxLineControlReg };
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000 , TxSOFEnableReg };
+ `TX_ADDR_REG : dataOut <= {1'b0 , TxAddrReg };
+ `TX_ENDP_REG : dataOut <= {4'h0 , TxEndPReg };
+ `FRAME_NUM_MSB_REG : dataOut <= frameNumIn [10 :3 ];
+ `FRAME_NUM_LSB_REG : dataOut <= {5'b00000 , frameNumIn [2 :0 ]};
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0 , SOFSentInt , connEventInt , resumeInt , transDoneInt };
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0 , interruptMaskReg };
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn ;
+ `RX_PID_REG : dataOut <= {4'b0000 , RxPIDIn };
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000 , connectStateIn };
+ default : dataOut <= 8'h00 ;
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v (revision 264)
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+ clk,
+ rst,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk;
+wire rst;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoFull(fifoFull),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v (revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// simFifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module simFifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+ dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+ if (writeEn == 1'b1)
+ buffer[addrIn] <= dataIn;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// directControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+ NextState_drctCntl <= CurrState_drctCntl;
+ // Set default values for outputs and signals
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_drctCntl) // synopsys parallel_case full_case
+ `START_DC:
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ next_HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {6'b000000, directControlLineState};
+ next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_HCTxPortReq <= 1'b0;
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_drctCntl <= `START_DC;
+ else
+ CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v (revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hctxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+input [7:0]SOFCntlCntl;
+input [7:0]SOFCntlData;
+input SOFCntlReq;
+input SOFCntlWEn;
+output directCntlGnt;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortWEnable;
+output sendPacketGnt;
+output SOFCntlGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+reg HCTxPortWEnable, next_HCTxPortWEnable;
+wire rst;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [7:0]SOFCntlCntl;
+wire [7:0]SOFCntlData;
+reg SOFCntlGnt, next_SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+ NextState_HCTxArb = CurrState_HCTxArb;
+ // Set default values for outputs and signals
+ next_SOFCntlGnt <= SOFCntlGnt;
+ next_sendPacketGnt <= sendPacketGnt;
+ next_directCntlGnt <= directCntlGnt;
+ next_muxCntl <= muxCntl;
+ case (CurrState_HCTxArb) // synopsys parallel_case full_case
+ `START_HARB:
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ end
+ `WAIT_REQ:
+ begin
+ if (SOFCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_SOF;
+ next_SOFCntlGnt <= 1'b1;
+ next_muxCntl <= `SOF_CTRL_MUX;
+ end
+ else if (sendPacketReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxCntl <= `SEND_PACKET_MUX;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `DIRECT_CONTROL;
+ next_directCntlGnt <= 1'b1;
+ next_muxCntl <= `DIRECT_CTRL_MUX;
+ end
+ end
+ `SEND_SOF:
+ begin
+ if (SOFCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_SOFCntlGnt <= 1'b0;
+ end
+ end
+ `SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `DIRECT_CONTROL:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_HCTxArb = `START_HARB;
+ else
+ CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFCntlGnt = 1'b0;
+ sendPacketGnt = 1'b0;
+ directCntlGnt = 1'b0;
+ muxCntl = 2'b00;
+ end
+ else
+ begin
+ SOFCntlGnt = next_SOFCntlGnt;
+ sendPacketGnt = next_sendPacketGnt;
+ directCntlGnt = next_directCntlGnt;
+ muxCntl = next_muxCntl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
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+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v (revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input directCtrlRate;
+input directCtrlPol;
+input sendPacketRate;
+input sendPacketPol;
+input sendPacketSel;
+output fullSpeedRate;
+output fullSpeedPol;
+
+wire directCtrlRate;
+wire directCtrlPol;
+wire sendPacketRate;
+wire sendPacketPol;
+wire sendPacketSel;
+reg fullSpeedRate;
+reg fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+ if (sendPacketSel == 1'b1)
+ begin
+ fullSpeedRate <= sendPacketRate;
+ fullSpeedPol <= sendPacketPol;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate;
+ fullSpeedPol <= directCtrlPol;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf (revision 264)
@@ -0,0 +1,358 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=790
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 698
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
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+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 15
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,252232 1 0 0 "Module: slavecontroller"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+S 15 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+ 192923,24221 173766,19421 163644,19865 153522,20309\
+ 122483,20608 111915,23020 101347,25432 81761,37919\
+ 69710,37919
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+ 30330,86104 25492,143212 35905,156667 46318,170122\
+ 96612,168665 117496,167729
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 89368,239805
+S 596 589 49152 ELLIPSE "States" | 168684,176772 6500 6500
+L 597 596 0 TEXT "State Labels" | 169718,177574 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 159138,161356 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 124386,212388 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 168405,170293 203966,131503 199503,89144 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 97839,216722 109714,216534 162558,220059 167812,183210
+A 603 596 4 TEXT "Actions" | 174409,172080 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 91340,216824 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 91340,216824 6500 6500
+W 606 589 0 588 605 BEZIER "Transitions" | 89368,237478 89903,233730 89797,226993 90332,223245
+C 607 601 0 TEXT "Conditions" | 114440,220845 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 91984,210359 90899,202871 142592,172810 163035,179986
+W 613 589 8195 605 617 BEZIER "Transitions" | 86536,212447 76974,203420 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 69153,194735 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 110702,185120 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+L 628 629 0 TEXT "State Labels" | 67392,65502 1 0 0 "DATA\n/11/"
+S 629 589 61440 ELLIPSE "States" | 67392,65502 6500 6500
+W 630 589 8193 617 629 BEZIER "Transitions" | 48383,172368 44995,170520 39116,166056 37345,163515\
+ 35574,160974 35266,154506 35651,142263 36036,130020\
+ 37884,87516 41041,76736 44198,65956 54978,65340\
+ 57981,65109 60984,64878 60379,64505 60995,64351
+W 631 589 8194 617 629 BEZIER "Transitions" | 54075,173680 59927,171524 83885,163128 122946,146882\
+ 162008,130636 145376,121704 139603,106244 133831,90784\
+ 72380,75586 70378,71274
+C 636 630 0 TEXT "Conditions" | 29568,129096 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 36344,101376 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 118603,107061 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+L 639 640 0 TEXT "State Labels" | 125814,48840 1 0 0 "GET_RESP\n/12/"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 94212 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+S 640 589 65536 ELLIPSE "States" | 125814,48840 6500 6500
+W 641 589 0 629 640 BEZIER "Transitions" | 73191,62566 81815,59948 110822,52759 119446,50141
+A 642 629 4 TEXT "Actions" | 76076,71808 1 0 0 "sendPacketWEn <= 1'b0;"
+C 643 641 0 TEXT "Conditions" | 73811,60869 1 0 0 "sendPacketRdy == 1'b1"
+A 644 641 16 TEXT "Actions" | 75293,54584 1 0 0 "getPacketREn <= 1'b1;"
+A 645 640 4 TEXT "Actions" | 108652,38924 1 0 0 "getPacketREn <= 1'b0;"
+W 646 589 0 640 587 BEZIER "Transitions" | 132288,49411 139757,47794 182271,47049 189740,45432
+C 647 646 0 TEXT "Conditions" | 140247,52755 1 0 0 "getPacketRdy == 1'b1"
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 69632 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/13/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 73728 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/14/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+ 209214,43082 209522,23062 208983,17094 208444,11127\
+ 205980,7277 191773,6353 177567,5429 123205,5583\
+ 106804,9317 90403,13052 79161,27836 75696,31763\
+ 72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+ 53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+ 60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/17/"
+S 786 377 98304 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v (revision 264)
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlaveWrap.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+ clk,
+ reset,
+ address,
+ writedata,
+ readdata,
+ write,
+ read,
+ waitrequest,
+ chipselect,
+ irq,
+ USBWireVPI,
+ USBWireVMI,
+ USBWireDataInTick,
+ USBWireVPO,
+ USBWireVMO,
+ USBWireDataOutTick,
+ USBWireOutEn_n,
+ USBFullSpeed
+ );
+
+input clk;
+input reset;
+input [7:0] address;
+input [7:0] writedata;
+output [7:0] readdata;
+input write;
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address;
+wire [7:0] writedata;
+wire [7:0] readdata;
+wire write;
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+ hostResumeIntOut | hostTransDoneIntOut |
+ slaveSOFRxedIntOut | slaveResetEventIntOut |
+ slaveResumeIntOut | slaveTransDoneIntOut |
+ slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut;
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration:
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+ .clk(clk),
+ .rst(reset),
+ .address_i(address),
+ .data_i(writedata),
+ .data_o(readdata),
+ .writeEn(write),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .hostSOFSentIntOut(hostSOFSentIntOut),
+ .hostConnEventIntOut(hostConnEventIntOut),
+ .hostResumeIntOut(hostResumeIntOut),
+ .hostTransDoneIntOut(hostTransDoneIntOut),
+ .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+ .slaveResetEventIntOut(slaveResetEventIntOut),
+ .slaveResumeIntOut(slaveResumeIntOut),
+ .slaveTransDoneIntOut(slaveTransDoneIntOut),
+ .slaveNAKSentIntOut(slaveNAKSentIntOut),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v (revision 264)
@@ -0,0 +1,116 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ clk, rst, fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ fifoFull,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v (revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+
+module wishBoneBI (
+ address, dataIn, dataOut, writeEn,
+ strobe_i,
+ ack_o,
+ clk, rst,
+ hostControlSel,
+ hostRxFifoSel, hostTxFifoSel,
+ slaveControlSel,
+ slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
+ slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
+ hostSlaveMuxSel,
+ dataFromHostControl,
+ dataFromHostRxFifo,
+ dataFromHostTxFifo,
+ dataFromSlaveControl,
+ dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+ dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+ dataFromHostSlaveMux
+ );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+ dataFromHostControl or
+ dataFromHostRxFifo or
+ dataFromHostTxFifo or
+ dataFromSlaveControl or
+ dataFromEP0RxFifo or
+ dataFromEP1RxFifo or
+ dataFromEP2RxFifo or
+ dataFromEP3RxFifo or
+ dataFromHostSlaveMux or
+ dataFromEP0TxFifo or
+ dataFromEP1TxFifo or
+ dataFromEP2TxFifo or
+ dataFromEP3TxFifo)
+begin
+ hostControlSel <= 1'b0;
+ hostRxFifoSel <= 1'b0;
+ hostTxFifoSel <= 1'b0;
+ slaveControlSel <= 1'b0;
+ slaveEP0RxFifoSel <= 1'b0;
+ slaveEP0TxFifoSel <= 1'b0;
+ slaveEP1RxFifoSel <= 1'b0;
+ slaveEP1TxFifoSel <= 1'b0;
+ slaveEP2RxFifoSel <= 1'b0;
+ slaveEP2TxFifoSel <= 1'b0;
+ slaveEP3RxFifoSel <= 1'b0;
+ slaveEP3TxFifoSel <= 1'b0;
+ hostSlaveMuxSel <= 1'b0;
+ case (address & `ADDRESS_DECODE_MASK)
+ `HCREG_BASE : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HCREG_BASE_PLUS_0X10 : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HOST_RX_FIFO_BASE : begin
+ hostRxFifoSel <= 1'b1;
+ dataOut <= dataFromHostRxFifo;
+ end
+ `HOST_TX_FIFO_BASE : begin
+ hostTxFifoSel <= 1'b1;
+ dataOut <= dataFromHostTxFifo;
+ end
+ `SCREG_BASE : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `SCREG_BASE_PLUS_0X10 : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `EP0_RX_FIFO_BASE : begin
+ slaveEP0RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0RxFifo;
+ end
+ `EP0_TX_FIFO_BASE : begin
+ slaveEP0TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0TxFifo;
+ end
+ `EP1_RX_FIFO_BASE : begin
+ slaveEP1RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1RxFifo;
+ end
+ `EP1_TX_FIFO_BASE : begin
+ slaveEP1TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1TxFifo;
+ end
+ `EP2_RX_FIFO_BASE : begin
+ slaveEP2RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2RxFifo;
+ end
+ `EP2_TX_FIFO_BASE : begin
+ slaveEP2TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2TxFifo;
+ end
+ `EP3_RX_FIFO_BASE : begin
+ slaveEP3RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3RxFifo;
+ end
+ `EP3_TX_FIFO_BASE : begin
+ slaveEP3TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3TxFifo;
+ end
+ `HOST_SLAVE_CONTROL_BASE : begin
+ hostSlaveMuxSel <= 1'b1;
+ dataOut <= dataFromHostSlaveMux;
+ end
+ default:
+ dataOut <= 8'h00;
+ endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+ ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+ ack_immediate <= strobe_i;
+end
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+ if (writeEn == 1'b0 &&
+ (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+ begin
+ ack_o <= ack_delayed;
+ end
+ else
+ begin
+ ack_o <= ack_immediate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf (revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 58
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 112
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 245
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+ 88541,112746 87971,105860 87641,93102 87312,80344\
+ 87761,70127 92565,59363 97370,48599 95270,45542\
+ 101102,30966
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus = { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+ 57686,214631 75382,223396 84426,228258
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf (revision 264)
@@ -0,0 +1,298 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=445
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
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+INSTHEADER 47
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+INSTHEADER 49
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+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+ 170250,145750 137550,145450 128737,144962 119925,144475\
+ 117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+ 110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+ 88026,17883 53248,36150 43780,48625 34312,61101\
+ 33772,117285 37441,132224 41110,147164 52980,154980\
+ 61012,157537 69044,160095 94076,164012 106263,166770
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+ 129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+ 40160,89849 37728,77233 37462,69633 37196,62033\
+ 38564,44249 44378,36953 50192,29657 72080,18257\
+ 79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+ 134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+ 58620,51804 60468,38868 64038,33660 67608,28452\
+ 80040,20556 84492,18330 88944,16104 95212,13380\
+ 97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+ 41567,48930 50502,39578 58559,36864 66617,34151\
+ 89914,32647 97658,32793 105403,32939 113545,36471\
+ 117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input fullSpeedPolarity;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input [3:0]PID;
+input rst;
+input sendPacketWEn;
+input [6:0]TxAddr;
+input [3:0]TxEndP;
+output fifoReadEn;
+output [10:0]frameNum;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+reg [10:0]frameNum, next_frameNum;
+wire fullSpeedPolarity;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire [3:0]PID;
+wire rst;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+wire [6:0]TxAddr;
+wire [3:0]TxEndP;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+ NextState_sndPkt <= CurrState_sndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ next_frameNum <= frameNum;
+ case (CurrState_sndPkt) // synopsys parallel_case full_case
+ `START_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ end
+ `WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_sndPkt <= `SP_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `SP_WAIT_GNT:
+ begin
+ if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+ begin
+ NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+ end
+ else if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_HCTxPortReq <= 1'b0;
+ end
+ `SEND_PID_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= PIDNotPID;
+ next_HCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SEND_PID_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ else if (PID == `SOF)
+ begin
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+ end
+ else if (PID == `OUT ||
+ PID == `IN ||
+ PID == `SETUP)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sndPkt <= `FIN_SP;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY1:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY2:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `OUT_IN_SETUP_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+ end
+ `SEND_SOF_FIN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_frameNum <= frameNum + 1'b1;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `SEND_SOF_WAIT_RDY3:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= frameNum[7:0];
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_WAIT_RDY4:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_FIN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+ end
+ `DATA0_DATA1_READ_FIFO:
+ begin
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= fifoData;
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+ end
+ `DATA0_DATA1_WAIT_READ_FIFO:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `DATA0_DATA1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+ end
+ end
+ `DATA0_DATA1_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `DATA0_DATA1_TERM_BYTE:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `DATA0_DATA1_CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ `DATA0_DATA1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+ end
+ `LS_EOP_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `LS_EOP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+ end
+ end
+ `LS_EOP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sndPkt <= `START_SP;
+ else
+ CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ HCTxPortData <= 8'h00;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ frameNum <= 11'h000;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ frameNum <= next_frameNum;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v (revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketcheckpreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input clk;
+input preAmbleEnable;
+input rst;
+input [3:0]sendPacketCPPID;
+input sendPacketCPWEn;
+input sendPacketRdy;
+output sendPacketCPReady;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+
+wire clk;
+wire preAmbleEnable;
+wire rst;
+wire [3:0]sendPacketCPPID;
+reg sendPacketCPReady, next_sendPacketCPReady;
+wire sendPacketCPWEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+ NextState_sendPktCP <= CurrState_sendPktCP;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ case (CurrState_sendPktCP) // synopsys parallel_case full_case
+ `SPC_WAIT_EN:
+ begin
+ if (sendPacketCPWEn == 1'b1)
+ begin
+ NextState_sendPktCP <= `CHK_PREAM;
+ next_sendPacketCPReady <= 1'b0;
+ end
+ end
+ `START_SPC:
+ begin
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `CHK_PREAM:
+ begin
+ if (preAmbleEnable == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+ end
+ end
+ `READY:
+ begin
+ next_sendPacketCPReady <= 1'b1;
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `PREAM_PKT_SND_PREAM:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `PREAMBLE;
+ NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+ end
+ `PREAM_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+ end
+ end
+ `PREAM_PKT_PREAM_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+ end
+ `PREAM_PKT_SND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+ end
+ `PREAM_PKT_PID_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+ end
+ `PREAM_PKT_WAIT_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+ end
+ end
+ `PREAM_PKT_WAIT_RDY3:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `READY;
+ end
+ end
+ `REG_PKT_SEND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+ end
+ `REG_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `REG_PKT_SEND_PID;
+ end
+ end
+ `REG_PKT_WAIT_RDY:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `READY;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktCP <= `START_SPC;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketCPReady <= 1'b1;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ end
+ else
+ begin
+ sendPacketCPReady <= next_sendPacketCPReady;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// softransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input clk;
+input rst;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn;
+input [15:0]SOFTimer;
+output sendPacketArbiterReq;
+output sendPacketWEn;
+output SOFSent; // single cycle pulse
+output SOFTimerClr; // Single cycle pulse
+
+wire clk;
+wire rst;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+wire SOFEnable;
+reg SOFSent, next_SOFSent;
+wire SOFSyncEn;
+wire [15:0]SOFTimer;
+reg SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+ NextState_SOFTx <= CurrState_SOFTx;
+ // Set default values for outputs and signals
+ next_SOFSent <= SOFSent;
+ next_SOFTimerClr <= SOFTimerClr;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_i <= i;
+ case (CurrState_SOFTx) // synopsys parallel_case full_case
+ `START_STX:
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ `WAIT_SOF_NEAR:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `WAIT_SP_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NOW;
+ end
+ end
+ `WAIT_SOF_NOW:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_sendPacketWEn <= 1'b1;
+ next_SOFTimerClr <= 1'b1;
+ next_SOFSent <= 1'b1;
+ end
+ else if (SOFEnable == 1'b0)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_SOFTimerClr <= 1'b1;
+ end
+ end
+ `SOF_FIN:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ next_SOFTimerClr <= 1'b0;
+ next_SOFSent <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK1;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK1:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK2;
+ next_sendPacketArbiterReq <= 1'b0;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK2:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SOFTx <= `START_STX;
+ else
+ CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFSent <= 1'b0;
+ SOFTimerClr <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketWEn <= 1'b0;
+ i <= 8'h00;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent;
+ SOFTimerClr <= next_SOFTimerClr;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketWEn <= next_sendPacketWEn;
+ i <= next_i;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v (revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ fifoEmpty,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v (revision 264)
@@ -0,0 +1,139 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH-1:0]bufferInIndex;
+reg [ADDR_WIDTH-1:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || forceEmpty == 1'b1)
+ begin
+ bufferCnt <= 0;
+ fifoFull <= 1'b0;
+ fifoEmpty <= 1'b1;
+ bufferInIndex <= 0;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ end
+ fifoREnDelayed <= fifoREn;
+ if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+ bufferCnt <= bufferCnt + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferCnt <= bufferCnt - 1;
+ bufferOutIndex <= bufferOutIndex + 1;
+ end
+ else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferOutIndex <= bufferOutIndex + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ if (bufferCnt[ADDR_WIDTH] == 1'b1)
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ if (|bufferCnt == 1'b0)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
+ .addrIn(bufferInIndex),
+ .addrOut(bufferOutIndex),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
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+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
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+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
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+ 120424,175336 108976,175654
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+I 150 128 0 Builtin Entry | 67068,204814
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+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
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+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
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+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
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+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf (revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+INSTHEADER 1
+PAGE 12700,12700 431800,558800
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
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+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
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+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend"
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+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
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+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
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+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
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+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
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+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
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+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// rxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ connectionEventOut <= 1'b1;
+ else
+ connectionEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v (revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketarbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input clk;
+input [3:0]HC_PID;
+input HC_SP_WEn;
+input HCTxReq;
+input rst;
+input SOF_SP_WEn;
+input SOFTxReq;
+output HCTxGnt;
+output [3:0]sendPacketPID;
+output sendPacketWEnable;
+output SOFTxGnt;
+
+wire clk;
+wire [3:0]HC_PID;
+wire HC_SP_WEn;
+reg HCTxGnt, next_HCTxGnt;
+wire HCTxReq;
+wire rst;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+reg sendPacketWEnable, next_sendPacketWEnable;
+wire SOF_SP_WEn;
+reg SOFTxGnt, next_SOFTxGnt;
+wire SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+ NextState_sendPktArb <= CurrState_sendPktArb;
+ // Set default values for outputs and signals
+ next_HCTxGnt <= HCTxGnt;
+ next_SOFTxGnt <= SOFTxGnt;
+ next_muxSOFNotHC <= muxSOFNotHC;
+ case (CurrState_sendPktArb) // synopsys parallel_case full_case
+ `HC_ACT:
+ begin
+ if (HCTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_HCTxGnt <= 1'b0;
+ end
+ end
+ `SOF_ACT:
+ begin
+ if (SOFTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_SOFTxGnt <= 1'b0;
+ end
+ end
+ `SARB_WAIT_REQ:
+ begin
+ if (SOFTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `SOF_ACT;
+ next_SOFTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b1;
+ end
+ else if (HCTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `HC_ACT;
+ next_HCTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktArb <= `START_SARB;
+ else
+ CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxGnt <= 1'b0;
+ SOFTxGnt <= 1'b0;
+ muxSOFNotHC <= 1'b0;
+ end
+ else
+ begin
+ HCTxGnt <= next_HCTxGnt;
+ SOFTxGnt <= next_SOFTxGnt;
+ muxSOFNotHC <= next_muxSOFNotHC;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v (revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sofcontroller
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input clk;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+input SOFEnable;
+input SOFTimerClr;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output [15:0]SOFTimer;
+
+wire clk;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+wire SOFEnable;
+reg [15:0]SOFTimer, next_SOFTimer;
+wire SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+ NextState_sofCntl <= CurrState_sofCntl;
+ // Set default values for outputs and signals
+ next_SOFTimer <= SOFTimer;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_sofCntl) // synopsys parallel_case full_case
+ `START_SC:
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ end
+ `WAIT_SOF_EN:
+ begin
+ if (SOFEnable == 1'b1)
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `WAIT_SEND_RESUME:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sofCntl <= `CLR_WEN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_RESUME_START;
+ end
+ end
+ `INC_TIMER:
+ begin
+ next_HCTxPortReq <= 1'b0;
+ if (SOFTimerClr == 1'b1)
+ next_SOFTimer <= 16'h0000;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1;
+ if (SOFEnable == 1'b0)
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ next_SOFTimer <= 16'h0000;
+ end
+ end
+ `SC_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sofCntl <= `WAIT_SEND_RESUME;
+ end
+ end
+ `CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sofCntl <= `INC_TIMER;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sofCntl <= `START_SC;
+ else
+ CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFTimer <= 16'h0000;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v (revision 264)
@@ -0,0 +1,386 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+ clk, rst,
+ //sendPacket
+ TxFifoRE, TxFifoData, TxFifoEmpty,
+ //getPacket
+ RxFifoWE, RxFifoData, RxFifoFull,
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //HCTxPortArbiter
+ HCTxPortEn, HCTxPortRdy,
+ HCTxPortData, HCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFSentIntOut,
+ connEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ hostControlSelect
+ );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [3:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut;
+wire connEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFSentIntOut(SOFSentIntOut),
+ .connEventIntOut(connEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .TxTransTypeReg(transType),
+ .TxSOFEnableReg(SOFEnable),
+ .TxAddrReg(TxAddr),
+ .TxEndPReg(TxEndP),
+ .frameNumIn(frameNum),
+ .RxPktStatusIn(RxPktStatus),
+ .RxPIDIn(RxPID),
+ .connectStateIn(connectStateOut),
+ .SOFSentIn(SOFSent),
+ .connEventIn(connectionEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .hostControlSelect(hostControlSelect),
+ .clrTransReq(clrTxReq),
+ .preambleEn(preAmbleEnable),
+ .SOFSync(SOFSyncEn),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .transReq(transReq),
+ .isoEn(isoEn)
+
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus(RxPktStatus),
+ .clearTXReq(clrTxReq),
+ .clk(clk),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketArbiterGnt(HCTxGnt),
+ .sendPacketArbiterReq(HCTxReq),
+ .sendPacketPID(HC_PID),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(HC_SP_WEn),
+ .transDone(transDone),
+ .transReq(transReq),
+ .transType(transType),
+ .isoEn(isoEn) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl(SOFCntlCntl),
+ .HCTxPortData(SOFCntlData),
+ .HCTxPortGnt(SOFCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(SOFCntlReq),
+ .HCTxPortWEn(SOFCntlWEn),
+ .SOFEnable(SOFEnable),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable(SOFEnable),
+ .SOFSent(SOFSent),
+ .SOFSyncEn(SOFSyncEn),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketArbiterGnt(SOFTxGnt),
+ .sendPacketArbiterReq(SOFTxReq),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(SOF_SP_WEn) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt(HCTxGnt),
+ .HCTxReq(HCTxReq),
+ .HC_PID(HC_PID),
+ .HC_SP_WEn(HC_SP_WEn),
+ .SOFTxGnt(SOFTxGnt),
+ .SOFTxReq(SOFTxReq),
+ .SOF_SP_WEn(SOF_SP_WEn),
+ .clk(clk),
+ .rst(rst),
+ .sendPacketPID(sendPacketCPPIDIn),
+ .sendPacketWEnable(sendPacketCPWEnIn) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID(sendPacketCPPIDIn),
+ .clk(clk),
+ .preAmbleEnable(preAmbleEnable),
+ .rst(rst),
+ .sendPacketCPReady(sendPacketCPReadyOut),
+ .sendPacketCPWEn(sendPacketCPWEnIn),
+ .sendPacketPID(sendPacketCPPIDOut),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl(sendPacketCntl),
+ .HCTxPortData(sendPacketData),
+ .HCTxPortGnt(sendPacketGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(sendPacketReq),
+ .HCTxPortWEn(sendPacketWEn),
+ .PID(sendPacketCPPIDOut),
+ .TxAddr(TxAddr),
+ .TxEndP(TxEndP),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .frameNum(frameNum),
+ .rst(rst),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut),
+ .fullSpeedPolarity(fullSpeedPol) );
+
+directControl u_directControl
+ (.HCTxPortCntl(directCntlCntl),
+ .HCTxPortData(directCntlData),
+ .HCTxPortGnt(directCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(directCntlReq),
+ .HCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl(HCTxPortCtrl),
+ .HCTxPortData(HCTxPortData),
+ .HCTxPortWEnable(HCTxPortEn),
+ .SOFCntlCntl(SOFCntlCntl),
+ .SOFCntlData(SOFCntlData),
+ .SOFCntlGnt(SOFCntlGnt),
+ .SOFCntlReq(SOFCntlReq),
+ .SOFCntlWEn(SOFCntlWEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+getPacket u_getPacket
+ (.RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXPktStatus(RxPktStatus),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .connectionEventOut(connectionEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v (revision 264)
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
+`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v (revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf (revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
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+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
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+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
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+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0; \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
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+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
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+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
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+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
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+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
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+ 182570,51409 180962,29567
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+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
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+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
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+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 5'h0; \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit) //can only be a resume if line remains in Kbit state\n RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n resumeWaitCnt <= resumeWaitCnt + 1'b1; \n //if we've waited long enough, then\n if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n begin \n RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n resumeDetected <= 1'b1; //report resume detected\n end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
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+ 178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+ 145117,36964 157043,31068 161599,29627 166155,28187\
+ 172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
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+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
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+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
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+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n RXSameBitCount <= RXSameBitCount + 1'b1; //inc 'RXSameBitCount'\n if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n bitStuffError <= 1'b1; //flag 'bitStuffError'\n else //else no bit stuffing error\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= { 1'b1, RXByte[7:1]}; //RZ bit = 1 (ie no change in 'RxBits')\n end\nend\nelse //else current 'RxBits' are different from old 'RxBits'\nbegin\n if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= {1'b0, RXByte[7:1]}; //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n end\n RXSameBitCount <= 4'h0; //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v (revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v (revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+`endif //usbSlaveControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v (revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+ if (fullSpeedPolarity == 1'b1)
+ begin
+ JBit = `ONE_ZERO;
+ KBit = `ZERO_ONE;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE;
+ KBit = `ONE_ZERO;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v (revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input processRxDataInWEn;
+input rst;
+input [7:0]RxByteIn;
+input [7:0]RxCtrlIn;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processRxByteRdy;
+output rstCRC;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+output RxDataOutWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+reg processRxByteRdy, next_processRxByteRdy;
+wire processRxDataInWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]RxByteIn;
+wire [7:0]RxCtrlIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+reg RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RxByte, next_RxByte;
+reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg [7:0]RxCtrl, next_RxCtrl;
+reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+ NextState_prRxByte <= CurrState_prRxByte;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte;
+ next_RxCtrl <= RxCtrl;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RxOverflow <= RxOverflow;
+ next_RxTimeOut <= RxTimeOut;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_RxDataOut <= RxDataOut;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOutWEn <= RxDataOutWEn;
+ next_rstCRC <= rstCRC;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_RXDataByteCnt <= RXDataByteCnt;
+ next_processRxByteRdy <= processRxByteRdy;
+ case (CurrState_prRxByte) // synopsys parallel_case full_case
+ `CHK_ST:
+ begin
+ if (RXByteStMachCurrState == `HS_BYTE_ST)
+ begin
+ NextState_prRxByte <= `HSHAKE_CHK;
+ end
+ else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+ begin
+ NextState_prRxByte <= `TOKEN_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+ begin
+ NextState_prRxByte <= `DATA_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+ begin
+ NextState_prRxByte <= `IDLE_CHK_START;
+ end
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+ begin
+ NextState_prRxByte <= `CHK_SYNC_DO;
+ end
+ else if (RXByteStMachCurrState == `CHECK_PID_ST)
+ begin
+ NextState_prRxByte <= `CHK_PID_DO_CHK;
+ end
+ end
+ `START_PRBY:
+ begin
+ next_RxByte <= 8'h00;
+ next_RxCtrl <= 8'h00;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxDataOut <= 8'h00;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOutWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_RXDataByteCnt <= 10'h00;
+ next_processRxByteRdy <= 1'b1;
+ NextState_prRxByte <= `WAIT_BYTE;
+ end
+ `WAIT_BYTE:
+ begin
+ if (processRxDataInWEn == 1'b1)
+ begin
+ NextState_prRxByte <= `CHK_ST;
+ next_RxByte <= RxByteIn;
+ next_RxCtrl <= RxCtrlIn;
+ next_processRxByteRdy <= 1'b0;
+ end
+ end
+ `HSHAKE_FIN:
+ begin
+ next_RxDataOutWEn <= 1'b0;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `HSHAKE_CHK:
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN;
+ if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RxDataOutWEn <= 1'b1;
+ end
+ `CHK_PID_DO_CHK:
+ begin
+ if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+ begin
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_processRxByteRdy <= 1'b1;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_RXDataByteCnt <= 0;
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_START;
+ next_RxDataOutWEn <= 1'b1;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `CHK_PID_FIRST_BYTE_PROC:
+ begin
+ next_rstCRC <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ case (RxByte[1:0] )
+ `SPECIAL: //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ `TOKEN: //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ `HANDSHAKE: //Handshake PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_ACKRxed <= 1'b1;
+ 2'b10:
+ next_NAKRxed <= 1'b1;
+ 2'b11:
+ next_stallRxed <= 1'b1;
+ default:
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST;
+ end
+ `DATA: //Data PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_dataSequence <= 1'b0;
+ 2'b10:
+ next_dataSequence <= 1'b1;
+ default:
+ $display ("Invalid DATA PID detected in ProcessRXByte\n");
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_FIN:
+ begin
+ next_CRC16En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC16Result != 16'hb001)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC16En <= 1'b1;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `DATA_FIN;
+ end
+ `DATA_WAIT_CRC:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `DATA_CHK_STRM;
+ end
+ end
+ `TOKEN_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC5Result != 5'h6)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ if (RXDataByteCnt > 10'h2)
+ begin
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `TOKEN_FIN;
+ end
+ `TOKEN_FIN:
+ begin
+ next_CRC5En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `TOKEN_WAIT_CRC:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `TOKEN_CHK_STRM;
+ end
+ end
+ `CHK_SYNC_DO:
+ begin
+ if (RxByte == `SYNC_BYTE)
+ next_RXByteStMachCurrState <= `CHECK_PID_ST;
+ else
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `IDLE_CHK_START:
+ begin
+ if (RxCtrl == `DATA_START)
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxByte <= `START_PRBY;
+ else
+ CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RxDataOut <= 8'h00;
+ RxCtrlOut <= 8'h00;
+ RxDataOutWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ processRxByteRdy <= 1'b1;
+ RxByte <= 8'h00;
+ RxCtrl <= 8'h00;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RxOverflow <= 1'b0;
+ RxTimeOut <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ RXDataByteCnt <= 10'h00;
+ end
+ else
+ begin
+ RxDataOut <= next_RxDataOut;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOutWEn <= next_RxDataOutWEn;
+ rstCRC <= next_rstCRC;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ processRxByteRdy <= next_processRxByteRdy;
+ RxByte <= next_RxByte;
+ RxCtrl <= next_RxCtrl;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RxOverflow <= next_RxOverflow;
+ RxTimeOut <= next_RxTimeOut;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ RXDataByteCnt <= next_RXDataByteCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf (revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIEReceiver\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+END
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+END
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+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
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+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
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+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+I 16 6 0 Builtin Reset | 25106,221421
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;"
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+I 42 39 0 Builtin Entry | 42918,241791
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+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+I 69 72 0 Builtin Entry | 64536,194920
+I 68 72 0 Builtin Exit | 131860,37310
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+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
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+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `FULL_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `LOW_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
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+I 188 90 0 Builtin Exit | 126468,30181
+I 187 90 0 Builtin Entry | 59972,198555
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+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+I 177 81 0 Builtin Exit | 137732,35774
+I 176 81 0 Builtin Entry | 63784,203320
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+I 200 99 0 Builtin Entry | 53777,190526
+I 199 99 0 Builtin Exit | 120480,22566
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+I 238 236 0 Builtin Exit | 129540,111760
+I 237 236 0 Builtin Entry | 86360,167640
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+I 244 242 0 Builtin Exit | 129540,111760
+I 243 242 0 Builtin Entry | 86360,167640
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf (revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 41
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 43
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 227
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 236
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+ 48213,88528 42471,75064 41184,67490 39897,59917\
+ 40491,43087 47668,36800 54846,30514 82962,22198\
+ 91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+ 200128,135446 205472,144130 205681,151728 205890,159327\
+ 201380,181037 194241,189595 187102,198154 163054,210680\
+ 152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+ 202640,35412 197280,23183 191376,19540 185472,15898\
+ 167213,13552 158043,13342 148873,13133 131482,15160\
+ 122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf (revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+ 94907,51569 61918,50756 52575,52503 43232,54250\
+ 38843,62050 37706,72734 36569,83418 36406,118357\
+ 40062,129609 43718,140862 58507,150938 67687,153172\
+ 76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf (revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+ 119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+ 70296,21816 59880,36936 57948,44622 56016,52308\
+ 59778,66554 61122,74366
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+ 105450,47318 105450,38252 107207,34228 108965,30205\
+ 115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v (revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE,
+ SIEPortCtrlInFromHost,
+ SIEPortCtrlInFromSlave,
+ SIEPortDataInToSIE,
+ SIEPortDataInFromHost,
+ SIEPortDataInFromSlave,
+ SIEPortWEnToSIE,
+ SIEPortWEnFromHost,
+ SIEPortWEnFromSlave,
+ fullSpeedPolarityToSIE,
+ fullSpeedPolarityFromHost,
+ fullSpeedPolarityFromSlave,
+ fullSpeedBitRateToSIE,
+ fullSpeedBitRateFromHost,
+ fullSpeedBitRateFromSlave,
+ dataIn,
+ dataOut,
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ hostSlaveMuxSel );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE;
+input [7:0] SIEPortDataInFromHost;
+input [7:0] SIEPortDataInFromSlave;
+output SIEPortWEnToSIE;
+input SIEPortWEnFromHost;
+input SIEPortWEnFromSlave;
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+reg SIEPortWEnToSIE;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave)
+begin
+ if (hostMode == 1'b1)
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn(dataIn),
+ .dataOut(dataOut),
+ .address(address),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostMode(hostMode),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v (revision 264)
@@ -0,0 +1,28 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+// Version 7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
+// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
+// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+// speed, and TX resume is always low speed.
+// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
+// in missing receive packets.
+// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+// by adding kludged delay to softranmit. This needs to be fixed properly.
+// This version has undergone limited testing
+// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+`define USBHOSTSLAVE_VERSION_NUM 8'h07
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf (revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processTxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
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+END
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+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+I 1097 1035 0 Builtin Exit | 133008,37611
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
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+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+W 1103 1035 0 1084 1100 BEZIER "Transitions" | 50775,157143 50927,152127 51227,143877 51379,138861
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
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+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
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+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
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+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
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+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47452,100861 48245,91628
+W 897 6 0 874 887 BEZIER "Transitions" | 48492,78681 48772,71498 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+ 25630,50244 23766,53274 22950,67894 22135,82515\
+ 20737,137969 21261,153813 21785,169657 25281,177579\
+ 27028,179792 28775,182006 32271,182938 33727,182355\
+ 35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1) //If this bit is 1, then\n TXOneCount <= TXOneCount + 1'b1; //increment 'TXOneCount'\nelse //else this is a zero bit\nbegin\n TXOneCount <= 4'h0; //reset 'TXOneCount'\n if (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\n else \n TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0; //reset 'TXOneCount'\nif (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\nelse \n TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+ 113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+ 40522,42856 31562,47464 29098,65320 26634,83176\
+ 25738,149992 26858,168968 27978,187944 33354,197032\
+ 36938,198888 40522,200744 49226,198568 51498,198152\
+ 53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0; \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+ 90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+ 104561,139388 153745,139620 168013,138576 182281,137532\
+ 190169,133124 192141,121582 194113,110040 194113,68280\
+ 192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+ 41124,121640 36948,124424 36020,132602 35092,140780\
+ 35556,170708 38166,179350 40776,187992 50140,192687\
+ 55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+ 30972,218732 29812,212468 29638,189094 29464,165720\
+ 29928,78488 31900,55230 33872,31972 41296,26172\
+ 49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit; \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+I 1028 1027 0 Builtin Entry | 86360,167640
+I 1029 1027 0 Builtin Exit | 129540,111760
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+I 1075 1035 0 Builtin Entry | 75208,271435
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v (revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input clk;
+input rst;
+input [1:0]RxWireDataIn;
+input RxWireDataWEn;
+output [1:0]connectState;
+
+wire clk;
+reg [1:0]connectState, next_connectState;
+wire rst;
+wire [1:0]RxWireDataIn;
+wire RxWireDataWEn;
+
+// diagram signals declarations
+reg [1:0]RxBits, next_RxBits;
+reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+ NextState_rcvr <= CurrState_rcvr;
+ // Set default values for outputs and signals
+ next_RXWaitCount <= RXWaitCount;
+ next_connectState <= connectState;
+ next_RXStMachCurrState <= RXStMachCurrState;
+ next_RxBits <= RxBits;
+ case (CurrState_rcvr) // synopsys parallel_case full_case
+ `WAIT_BIT:
+ begin
+ if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ end
+ `START_SRX:
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_RXWaitCount <= 8'h00;
+ next_connectState <= `DISCONNECT;
+ next_RxBits <= 2'b00;
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `DISCNCT_CHK_RXBITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else if (RxBits == `ONE_ZERO)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ONE_ZERO)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `LS_CONN_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `FS_CONN_CHK_RX_BITS1:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_rcvr <= `START_SRX;
+ else
+ CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ connectState <= `DISCONNECT;
+ RXWaitCount <= 8'h00;
+ RXStMachCurrState <= `DISCONNECT_ST;
+ RxBits <= 2'b00;
+ end
+ else
+ begin
+ connectState <= next_connectState;
+ RXWaitCount <= next_RXWaitCount;
+ RXStMachCurrState <= next_RXStMachCurrState;
+ RxBits <= next_RxBits;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v (revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+ module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
+ hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ hostMode <= 1'b0;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+ hostMode <= dataIn[0];
+ end
+end
+
+
+// async read mux
+always @(address or hostMode)
+begin
+ case (address)
+ `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+ `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+ endcase
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v (revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
+`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v (revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input fullSpeedRateIn;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteRdy;
+input rst;
+input [7:0]SIEPortCtrlIn;
+input [7:0]SIEPortDataIn;
+input SIEPortWEn;
+input USBWireGnt;
+input USBWireRdy;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processTxByteWEn;
+output rstCRC;
+output SIEPortTxRdy;
+output [7:0]TxByteOut;
+output [7:0]TxByteOutCtrl;
+output TxByteOutFullSpeedRate;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+wire fullSpeedRateIn;
+wire [1:0]JBit;
+wire [1:0]KBit;
+wire processTxByteRdy;
+reg processTxByteWEn, next_processTxByteWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]SIEPortCtrlIn;
+wire [7:0]SIEPortDataIn;
+reg SIEPortTxRdy, next_SIEPortTxRdy;
+wire SIEPortWEn;
+reg [7:0]TxByteOut, next_TxByteOut;
+reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [2:0]i, next_i;
+reg [15:0]resumeCnt, next_resumeCnt;
+reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+ NextState_SIETx <= CurrState_SIETx;
+ // Set default values for outputs and signals
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_USBWireReq <= USBWireReq;
+ next_processTxByteWEn <= processTxByteWEn;
+ next_rstCRC <= rstCRC;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteOut <= TxByteOut;
+ next_TxByteOutCtrl <= TxByteOutCtrl;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_SIEPortTxRdy <= SIEPortTxRdy;
+ next_SIEPortData <= SIEPortData;
+ next_SIEPortCtrl <= SIEPortCtrl;
+ next_resumeCnt <= resumeCnt;
+ next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+ case (CurrState_SIETx) // synopsys parallel_case full_case
+ `IDLE:
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `START_SIETX:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_TxByteOut <= 8'h00;
+ next_TxByteOutCtrl <= 8'h00;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_SIEPortTxRdy <= 1'b0;
+ next_SIEPortData <= 8'h00;
+ next_SIEPortCtrl <= 8'h00;
+ next_i <= 3'h0;
+ next_resumeCnt <= 16'h0000;
+ next_TxByteOutFullSpeedRate <= 1'b0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `STX_CHK_ST:
+ begin
+ if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ next_TxByteOutFullSpeedRate <= 1'b1;
+ //SOF and PRE always at full speed
+ end
+ else if (SIEPortCtrl == `TX_PACKET_START)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ end
+ else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_IDLE)
+ begin
+ NextState_SIETx <= `IDLE;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ next_resumeCnt <= 16'h0000;
+ next_USBWireFullSpeedRate <= 1'b0;
+ //resume always uses low speed timing
+ end
+ end
+ `STX_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `STX_CHK_ST;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ end
+ `DIR_CTL_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 3'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `DIR_CTL_DELAY;
+ end
+ end
+ `DIR_CTL_WAIT_GNT:
+ begin
+ next_i <= 3'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN;
+ next_USBWireData <= SIEPortData[1:0];
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `DIR_CTL_DELAY:
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ `PKT_ST_CHK_PID:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ if (SIEPortData[1:0] == `TOKEN)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `HANDSHAKE)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `DATA)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `SPECIAL)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+ end
+ end
+ `PKT_ST_WAIT_RDY_PKT:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= `SYNC_BYTE;
+ next_TxByteOutCtrl <= `DATA_START;
+ end
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[7:0];
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[15:8];
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_STOP)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+ end
+ end
+ `PKT_ST_DATA_DATA_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC16En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY:
+ begin
+ next_CRC16En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+ end
+ end
+ `PKT_ST_DATA_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `PKT_ST_HS_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_HS_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_SPCL_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_CRC_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `RES_ST_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (resumeCnt == `HOST_TX_RESUME_TIME)
+ begin
+ NextState_SIETx <= `RES_ST_W_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `RES_ST_DELAY;
+ end
+ end
+ `RES_ST_SND_J_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY4;
+ end
+ `RES_ST_SND_J_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ `RES_ST_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY2;
+ end
+ `RES_ST_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY3;
+ end
+ `RES_ST_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN;
+ next_USBWireData <= KBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ next_resumeCnt <= resumeCnt + 1'b1;
+ end
+ end
+ `RES_ST_DELAY:
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ `RES_ST_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_2;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_WAIT_GNT1:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+ end
+ end
+ `TX_LS_EOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+ end
+ `TX_LS_EOP_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+ end
+ `TX_LS_EOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `TX_LS_EOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_J;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SIETx <= `START_SIETX;
+ else
+ CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ USBWireWEn <= 1'b0;
+ USBWireReq <= 1'b0;
+ processTxByteWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ TxByteOut <= 8'h00;
+ TxByteOutCtrl <= 8'h00;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ SIEPortTxRdy <= 1'b0;
+ TxByteOutFullSpeedRate <= 1'b0;
+ i <= 3'h0;
+ SIEPortData <= 8'h00;
+ SIEPortCtrl <= 8'h00;
+ resumeCnt <= 16'h0000;
+ end
+ else
+ begin
+ USBWireWEn <= next_USBWireWEn;
+ USBWireReq <= next_USBWireReq;
+ processTxByteWEn <= next_processTxByteWEn;
+ rstCRC <= next_rstCRC;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ TxByteOut <= next_TxByteOut;
+ TxByteOutCtrl <= next_TxByteOutCtrl;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ SIEPortTxRdy <= next_SIEPortTxRdy;
+ TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+ i <= next_i;
+ SIEPortData <= next_SIEPortData;
+ SIEPortCtrl <= next_SIEPortCtrl;
+ resumeCnt <= next_resumeCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf (revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processRxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+L 279 280 0 TEXT "State Labels" | 49504,129936 1 0 0 "FIN\n/10/"
+A 278 257 4 TEXT "Actions" | 130366,127109 1 0 0 "RxDataOutWEn <= 1'b0;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prRxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processRxByte"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PRBY\n/1/"
+S 9 6 4096 ELLIPSE "States" | 41526,197822 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "CHK_ST\n/0/"
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+L 15 16 0 TEXT "State Labels" | 115714,125064 1 0 0 "CHK_PID"
+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC16Result != 16'hb001)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC16En <= 1'b1;\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
+I 292 50 0 Builtin Entry | 33692,252435
+I 291 50 0 Builtin Exit | 90483,62922
+L 289 286 0 TEXT "State Labels" | 54701,94283 1 0 0 "FIN\n/11/"
+W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
+S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,123462 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+I 20 17 0 Builtin Entry | 45216,248076
+I 21 17 0 Builtin Exit | 89220,92674
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,94696 6500 6500
+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
+A 296 0 1 TEXT "Actions" | 13933,264927 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin \n RxStatus <= \n {1'b0, next_dataSequence, \n next_ACKRxed, \n next_stallRxed, next_NAKRxed, \n next_RxOverflow, \n next_bitStuffError, next_CRCError };\nend"
+L 297 298 0 TEXT "Labels" | 82848,260279 1 0 0 "RxDataOut[7:0]"
+I 298 0 130 Builtin OutPort | 76848,260279 "" ""
+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 300 0 130 Builtin OutPort | 76848,255265 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
+I 302 0 2 Builtin OutPort | 76139,250245 "" ""
+L 303 304 0 TEXT "Labels" | 84462,243195 1 0 0 "RxByteIn[7:0]"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 117500,64680 1 0 0 "TOKEN"
+W 36 41 0 38 371 BEZIER "Transitions" | 34704,258592 38731,254357 47806,246433 31745,235718
+I 37 41 0 Builtin Exit | 85286,98575
+I 38 41 0 Builtin Entry | 30541,258592
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
+L 305 306 0 TEXT "Labels" | 84465,238172 1 0 0 "RxCtrlIn[7:0]"
+I 306 0 130 Builtin InPort | 78465,238172 "" ""
+L 307 308 0 TEXT "Labels" | 85176,232428 1 0 0 "processRxDataInWEn"
+I 308 0 2 Builtin InPort | 78462,232428 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 93136,123615 109216,123347
+W 52 6 0 11 24 BEZIER "Transitions" | 41273,169115 41809,155581 41924,114126 42929,106354\
+ 43934,98582 46882,94562 55190,93624 63498,92686\
+ 93782,92954 101420,93021 109058,93088 109445,93150\
+ 109579,93150
+W 53 6 0 11 33 BEZIER "Transitions" | 41642,169108 42044,146596 42058,88800 43264,77142\
+ 44470,65484 48490,63876 56999,63474 65508,63072\
+ 95524,63072 103095,63072 110666,63072 111053,63134\
+ 111187,63134
+W 54 6 0 11 42 BEZIER "Transitions" | 41669,169131 42607,140455 43130,70308 44403,54764\
+ 45676,39220 48892,34396 57535,33391 66178,32386\
+ 96662,35330 112340,35732
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
+L 327 328 0 TEXT "Labels" | 175074,260836 1 0 0 "RxOverflow"
+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
+L 331 332 0 TEXT "Labels" | 174717,252268 1 0 0 "NAKRxed"
+I 332 0 2 Builtin Signal | 171717,252268 "" ""
+L 333 334 0 TEXT "Labels" | 175074,247627 1 0 0 "stallRxed"
+I 334 0 2 Builtin Signal | 172074,247627 "" ""
+L 335 336 0 TEXT "Labels" | 175074,243343 1 0 0 "ACKRxed"
+W 64 6 0 9 63 BEZIER "Transitions" | 48012,197411 59579,195797 95649,181504 106856,175930
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59763,178747 47927,176730
+C 66 65 0 TEXT "Conditions" | 62843,168563 1 0 0 "processRxDataInWEn == 1'b1"
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+ 162060,109038 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+ 41868,138924 51896,113272 59871,108777 67846,104282\
+ 74724,97474 86324,92674
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC5Result != 5'h6)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n if (RXDataByteCnt > 10'h2) \n begin\n RxOverflow <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n else \n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC5_8Bit <= 1'b1;\n CRC5En <= 1'b1;\n end\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n `SPECIAL: //Special PID.\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n `TOKEN: //Token PID\n begin\n RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n RXDataByteCnt <= 0;\n end\n `HANDSHAKE: //Handshake PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n ACKRxed <= 1'b1;\n 2'b10:\n NAKRxed <= 1'b1;\n 2'b11:\n stallRxed <= 1'b1;\n default:\n begin\n $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n end\n endcase\n RXByteStMachCurrState <= `HS_BYTE_ST;\n end\n `DATA: //Data PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n dataSequence <= 1'b0;\n 2'b10:\n dataSequence <= 1'b1;\n default:\n $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n endcase\n RXByteStMachCurrState <= `DATA_BYTE_ST;\n RXDataByteCnt <= 0;\n end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+ 110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+ 89364,102368 89220,95212 89220,94846
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v (revision 264)
@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive);
+input [1:0] RxBitsIn;
+output RxDataInTick;
+input SIERxRdyIn;
+input clk;
+input fullSpeedRate;
+input rst;
+input TxWireActiveDrive;
+output [1:0] RxBitsOut;
+output SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+
+wire [1:0] RxBitsIn;
+reg RxDataInTick;
+wire SIERxRdyIn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg [1:0] RxBitsOut;
+reg SIERxWEn;
+reg noActivityTimeOut;
+reg RxWireActive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg1;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ RxDataInTick <= 1'b0;
+ RxWireEdgeDetect <= 1'b0;
+ RxWireActiveReg1 <= 1'b0;
+ RxWireActiveReg2 <= 1'b0;
+ end
+ else begin
+ RxWireActiveReg2 <= RxWireActiveReg1; //Delay RxWireActiveReg1 until after i has been reset
+ RxBitsInReg <= RxBitsIn; //sync incoming data to local clock to avoid metastability issues
+ incBufferCnt <= 1'b0; //default value
+ oldRxBitsIn <= RxBitsInReg;
+ if ( (TxWireActiveDrive == 1'b0) && (oldRxBitsIn != RxBitsInReg)) begin //if edge detected then
+ i <= 5'b00000; //reset the counter
+ RxWireEdgeDetect <= 1'b1; // flag receive activity
+ RxWireActiveReg1 <= 1'b1;
+ end
+ else begin
+ i <= i + 1'b1;
+ RxWireEdgeDetect <= 1'b0;
+ end
+ if (noActivityTimeOut == 1'b1)
+ RxWireActiveReg1 <= 1'b0;
+ if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+ begin
+ RxDataInTick <= !RxDataInTick;
+ if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b01 : buffer1 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b10 : buffer2 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b11 : buffer3 <= {RxWireActiveReg2, RxBitsInReg};
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutIndex <= 2'b00;
+ RxBitsOut <= 2'b00;
+ SIERxWEn <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ else begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_NOT_EMPTY:
+ begin
+ if (bufferCnt != 3'b000)
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+ end
+ `WAIT_SIE_RX_READY:
+ begin
+ if (SIERxRdyIn == 1'b1)
+ begin
+ SIERxWEn <= 1'b1;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+ 2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+ 2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+ 2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+ endcase
+ end
+ end
+ `SIE_RX_WRITE:
+ begin
+ SIERxWEn <= 1'b0;
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ endcase
+ end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+ if (rst) begin
+ timeOutCnt <= 16'h0000;
+ noActivityTimeOut <= 1'b0;
+ end
+ else begin
+ if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1)
+ timeOutCnt <= 16'h0000;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1;
+ if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+ || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+ noActivityTimeOut <= 1'b1;
+ else
+ noActivityTimeOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v (revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input CRC5_8BitIn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [4:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire CRC5_8BitIn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 5'h1f;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0) begin
+ if (CRCEn == 1'b1) begin
+ ready <= 1'b0;
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ if (CRC5_8BitIn == 1'b1) begin
+ loopEnd <= 4'h7;
+ end
+ else begin
+ loopEnd <= 4'h2;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[4:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == loopEnd) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v (revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn,
+ TxBitsOut,
+ TxDataOutTick,
+ TxCtrlIn,
+ TxCtrlOut,
+ USBWireRdy,
+ USBWireWEn,
+ TxWireActiveDrive,
+ fullSpeedRate,
+ clk,
+ rst
+ );
+
+input [1:0] TxBitsIn;
+input TxCtrlIn;
+input USBWireWEn;
+input clk;
+input fullSpeedRate;
+input rst;
+output [1:0] TxBitsOut;
+output TxDataOutTick;
+output TxCtrlOut;
+output USBWireRdy;
+output TxWireActiveDrive;
+
+wire [1:0] TxBitsIn;
+reg [1:0] TxBitsOut;
+reg TxDataOutTick;
+wire TxCtrlIn;
+reg TxCtrlOut;
+reg USBWireRdy;
+wire USBWireWEn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg TxWireActiveDrive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk) begin
+ if (rst == 1'b1) begin
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ USBWireRdy <= 1'b0;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ else begin
+ case (bufferInStMachCurrState)
+ `WAIT_BUFFER_NOT_FULL:
+ begin
+ if (bufferCnt != `BUFFER_FULL)
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ end
+ `WAIT_WRITE_REQ:
+ begin
+ if (USBWireWEn == 1'b1)
+ begin
+ incBufferCnt <= 1'b1;
+ USBWireRdy <= 1'b0;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+ 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+ 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+ 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+ end
+ end
+ `CLR_INC_BUFFER_CNT:
+ begin
+ incBufferCnt <= 1'b0;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ fullSpeedTick <= 1'b0;
+ lowSpeedTick <= 1'b0;
+ end
+ else
+ begin
+ i <= i + 1'b1;
+ if (i[1:0] == 2'b00)
+ fullSpeedTick <= 1'b1;
+ else
+ fullSpeedTick <= 1'b0;
+ if (i == 5'b00000)
+ lowSpeedTick <= 1'b1;
+ else
+ lowSpeedTick <= 1'b0;
+ end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferOutIndex <= 2'b00;
+ decBufferCnt <= 1'b0;
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ TxDataOutTick <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState)
+ `WAIT_LINE_WRITE:
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+ begin
+ TxDataOutTick <= !TxDataOutTick;
+ if (bufferCnt == 0) begin
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ end
+ else begin
+ bufferOutStMachCurrState <= `LINE_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0[2:1];
+ TxCtrlOut <= buffer0[0];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1[2:1];
+ TxCtrlOut <= buffer1[0];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2[2:1];
+ TxCtrlOut <= buffer2[0];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3[2:1];
+ TxCtrlOut <= buffer3[0];
+ end
+ endcase
+ end
+ end
+ end
+ `LINE_WRITE:
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ endcase
+ end
+end
+
+// control 'TxWireActiveDrive'
+always @(TxCtrlOut)
+begin
+ if (TxCtrlOut == `DRIVE)
+ TxWireActiveDrive <= 1'b1;
+ else
+ TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf (revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+PAGE 12700,12700 431800,558800
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut = SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "SCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+ 259846,282068 289467,282068 298484,284234 307501,286400\
+ 313949,295065 315460,307759 316972,320453 316568,362568\
+ 311430,375060 306292,387553 286142,395412 275462,395110\
+ 264783,394808 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+ 200193,83454 202194,93721 199799,97969 197405,102218\
+ 189371,107780 182843,108050 176316,108321 158239,103840\
+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n TxFSRate <= SIETxFSRate;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n TxFSRate <= prcTxByteFSRate;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v (revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v (revision 264)
@@ -0,0 +1,507 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input bitStuffError;
+input clk;
+input CRCError;
+input getPacketRdy;
+input rst;
+input [7:0]RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0]RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input sendPacketRdy;
+input [4:0]USBEndPControlReg;
+input [6:0]USBTgtAddress;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output [10:0]frameNum;
+output getPacketREn;
+output NAKSent;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output SOFRxed;
+output stallSent;
+output transDone;
+output [3:0]USBEndP;
+output [1:0]USBEndPNakTransTypeReg;
+output [1:0]USBEndPTransTypeReg;
+
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+wire CRCError;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg [10:0]frameNum, next_frameNum;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+reg NAKSent, next_NAKSent;
+wire rst;
+wire [7:0]RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0]RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg SOFRxed, next_SOFRxed;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+reg [3:0]USBEndP, next_USBEndP;
+wire [4:0]USBEndPControlReg;
+reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [7:0]PIDByte, next_PIDByte;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_getPacketREn <= getPacketREn;
+ case (CurrState_slvCntrl) // synopsys parallel_case full_case
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ begin
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else if (((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `PID_ERROR;
+ end
+ end
+ `PID_ERROR:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ end
+ end
+ `SETUP_OUT_CHK:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ end
+ else if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_CHK_RDY:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `IN_RESP_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_RESP_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+ end
+ end
+ `IN_RESP_CHK_ISO:
+ begin
+ if (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `START_S1:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `GET_TOKEN_WAIT_CRC:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_ADDR:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_STOP:
+ begin
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ end
+ else if (RxDataWEn == 1'b1)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_CHK_SOF:
+ begin
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ end
+ `GET_TOKEN_CHK_ADDR:
+ begin
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ stallSent <= 1'b0;
+ NAKSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ transDone <= 1'b0;
+ clrEPRdy <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ getPacketREn <= 1'b0;
+ PIDByte <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ addrEndPTemp <= 8'h00;
+ tempUSBEndPTransTypeReg <= 2'b00;
+ USBAddress <= 7'b0000000;
+ end
+ else
+ begin
+ stallSent <= next_stallSent;
+ NAKSent <= next_NAKSent;
+ SOFRxed <= next_SOFRxed;
+ transDone <= next_transDone;
+ clrEPRdy <= next_clrEPRdy;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ getPacketREn <= next_getPacketREn;
+ PIDByte <= next_PIDByte;
+ endpCRCTemp <= next_endpCRCTemp;
+ addrEndPTemp <= next_addrEndPTemp;
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ USBAddress <= next_USBAddress;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt (revision 264)
@@ -0,0 +1,24 @@
+USBHostSlave has been successfully compiled using Quartus 4.1 with Servive Pack 2
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+For those who wish to use a pre-configured Quartus project, I have included two files;
+usbhostslaveQuartusProj.qar - Quartus project archive
+usbHostSlaveNiosIDEProj.zip - NIOS IDE project zip file. You can use NIOS IDE File>>import to open the file
+
+
+If you wish to replicate the hardware setup, then you will need to replace
+the standard 50MHz oscillator with a 48MHz oscillator (Digikey XC280-ND),
+and you will need a add a Santa Cruz daughter card with two USB transceivers.
+
+If there is enough interest, I will consider producing a Santa Cruz daughter card
+with the hardware required to support this core.
+Please email me at sfielding@base2designs.com if you are interested in this option.
+
+
+Release notes:
+Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+ control reads and writes to USB flash dongle
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ rstSyncToUsbClk,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input rstSyncToUsbClk;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty; //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .wrClk(usbClk),
+ .rdClk(busClk),
+ .rstSyncToWrClk(rstSyncToUsbClk),
+ .rstSyncToRdClk(rstSyncToBusClk),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmptySyncToWrClk(forceEmptySyncToUsbClk),
+ .forceEmptySyncToRdClk(forceEmptySyncToBusClk),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (revision 264)
@@ -0,0 +1,391 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+ clk, rst,
+ //readUSBWireData
+ USBWireDataIn,
+ USBWireDataInTick,
+ //writeUSBWireData
+ USBWireDataOut,
+ USBWireCtrlOut,
+ USBWireDataOutTick,
+ //SIEReceiver
+ connectState,
+ //processRxBit
+ resumeDetected,
+ //processRxByte
+ RxCtrlOut,
+ RxDataOutWEn,
+ RxDataOut,
+ //SIETransmitter
+ SIEPortCtrlIn,
+ SIEPortDataIn,
+ SIEPortTxRdy,
+ SIEPortWEn,
+ //lineControlUpdate
+ fullSpeedPolarity,
+ fullSpeedBitRate,
+ noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut;
+output RxDataOutWEn;
+output [7:0] RxDataOut;
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy;
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut;
+wire RxDataOutWEn;
+wire [7:0] RxDataOut;
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy;
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En;
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En;
+wire [4:0] RxCRC5Result;
+wire RxCRC5_8Bit;
+wire [7:0] RxCRCData;
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En;
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En;
+wire [4:0] TxCRC5Result;
+wire TxCRC5_8Bit;
+wire [7:0] TxCRCData;
+wire TxRstCRC;
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy;
+wire processTxByteWEn;
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity(fullSpeedPolarity),
+ .fullSpeedBitRate(fullSpeedBitRate),
+ .JBit(JBit),
+ .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+ (
+ .RxWireDataIn(RxWireDataFromWireRx),
+ .RxWireDataWEn(RxWireDataWEn),
+ .clk(clk),
+ .connectState(connectState),
+ .rst(rst) );
+
+
+processRxBit u_processRxBit
+ (.JBit(JBit),
+ .KBit(KBit),
+ .RxBitsIn(RxWireDataFromWireRx),
+ .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
+ .clk(clk),
+ .processRxBitRdy(processRxBitRdy),
+ .processRxBitsWEn(RxWireDataWEn),
+ .processRxByteWEn(processRxByteWEn),
+ .resumeDetected(resumeDetected),
+ .rst(rst),
+ .processRxByteRdy(processRxByteRdy),
+ .RxWireActive(RxWireActive)
+ );
+
+processRxByte u_processRxByte
+ (.CRC16En(RxCRC16En),
+ .CRC16Result(RxCRC16Result),
+ .CRC16UpdateRdy(RxCRC16UpdateRdy),
+ .CRC5En(RxCRC5En),
+ .CRC5Result(RxCRC5Result),
+ .CRC5_8Bit(RxCRC5_8Bit),
+ .CRC5UpdateRdy(RxCRC5UpdateRdy),
+ .CRCData(RxCRCData),
+ .RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
+ .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataOut),
+ .clk(clk),
+ .processRxDataInWEn(processRxByteWEn),
+ .rst(rst),
+ .rstCRC(RxRstCRC),
+ .processRxByteRdy(processRxByteRdy) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC5Result),
+ .CRCEn(RxCRC5En),
+ .CRC5_8BitIn(RxCRC5_8Bit),
+ .dataIn(RxCRCData),
+ .ready(RxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC16Result),
+ .CRCEn(RxCRC16En),
+ .dataIn(RxCRCData),
+ .ready(RxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En(TxCRC16En),
+ .CRC16Result(TxCRC16Result),
+ .CRC5En(TxCRC5En),
+ .CRC5Result(TxCRC5Result),
+ .CRC5_8Bit(TxCRC5_8Bit),
+ .CRCData(TxCRCData),
+ .CRC5UpdateRdy(TxCRC5UpdateRdy),
+ .CRC16UpdateRdy(TxCRC16UpdateRdy),
+ .JBit(JBit),
+ .KBit(KBit),
+ .SIEPortCtrlIn(SIEPortCtrlIn),
+ .SIEPortDataIn(SIEPortDataIn),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEn),
+ .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
+ .TxByteOut(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(SIETxCtrl),
+ .USBWireData(SIETxData),
+ .USBWireGnt(SIETxGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(SIETxReq),
+ .USBWireWEn(SIETxWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .rstCRC(TxRstCRC),
+ .USBWireFullSpeedRate(SIEFsRate),
+ .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+ .fullSpeedRateIn(fullSpeedBitRate)
+ );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC5Result),
+ .CRCEn(TxCRC5En),
+ .CRC5_8BitIn(TxCRC5_8Bit),
+ .dataIn(TxCRCData),
+ .ready(TxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC16Result),
+ .CRCEn(TxCRC16En),
+ .dataIn(TxCRCData),
+ .ready(TxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+processTxByte u_processTxByte
+ (.JBit(JBit),
+ .KBit(KBit),
+ .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
+ .TxByteIn(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(prcTxByteCtrl),
+ .USBWireData(prcTxByteData),
+ .USBWireGnt(prcTxByteGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(prcTxByteReq),
+ .USBWireWEn(prcTxByteWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .USBWireFullSpeedRate(prcTxByteFSRate),
+ .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+ );
+
+USBTxWireArbiter u_USBTxWireArbiter
+ (.SIETxCtrl(SIETxCtrl),
+ .SIETxData(SIETxData),
+ .SIETxGnt(SIETxGnt),
+ .SIETxReq(SIETxReq),
+ .SIETxWEn(SIETxWEn),
+ .TxBits(TxBitsFromArbToWire),
+ .TxCtl(TxCtrlFromArbToWire),
+ .USBWireRdyIn(USBWireRdy),
+ .USBWireRdyOut(USBWireReadyFromTxArb),
+ .USBWireWEn(USBWireWEn),
+ .clk(clk),
+ .prcTxByteCtrl(prcTxByteCtrl),
+ .prcTxByteData(prcTxByteData),
+ .prcTxByteGnt(prcTxByteGnt),
+ .prcTxByteReq(prcTxByteReq),
+ .prcTxByteWEn(prcTxByteWEn),
+ .rst(rst),
+ .SIETxFSRate(SIEFsRate),
+ .prcTxByteFSRate(prcTxByteFSRate),
+ .TxFSRate(FSRateFromArbiterToWire)
+ );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn(TxBitsFromArbToWire),
+ .TxBitsOut(USBWireDataOut),
+ .TxDataOutTick(USBWireDataOutTick),
+ .TxCtrlIn(TxCtrlFromArbToWire),
+ .TxCtrlOut(USBWireCtrlOut),
+ .USBWireRdy(USBWireRdy),
+ .USBWireWEn(USBWireWEn),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .fullSpeedRate(FSRateFromArbiterToWire),
+ .clk(clk),
+ .rst(rst)
+ );
+
+
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn(USBWireDataIn),
+ .RxDataInTick(USBWireDataInTick),
+ .RxBitsOut(RxWireDataFromWireRx),
+ .SIERxRdyIn(processRxBitRdy),
+ .SIERxWEn(RxWireDataWEn),
+ .fullSpeedRate(fullSpeedBitRate),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .clk(clk),
+ .rst(rst),
+ .noActivityTimeOut(noActivityTimeOut),
+ .RxWireActive(RxWireActive)
+ );
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v (revision 264)
@@ -0,0 +1,438 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ clk, rst,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ EP0IsoEn <= 1'b0;
+ EP0SendStall <= 1'b0;
+ EP0DataSequence <= 1'b0;
+ EP0Enable <= 1'b0;
+ EP1IsoEn <= 1'b0;
+ EP1SendStall <= 1'b0;
+ EP1DataSequence <= 1'b0;
+ EP1Enable <= 1'b0;
+ EP2IsoEn <= 1'b0;
+ EP2SendStall <= 1'b0;
+ EP2DataSequence <= 1'b0;
+ EP2Enable <= 1'b0;
+ EP3IsoEn <= 1'b0;
+ EP3SendStall <= 1'b0;
+ EP3DataSequence <= 1'b0;
+ EP3Enable <= 1'b0;
+ SCControlReg <= 6'h00;
+ SCAddrReg <= 7'h00;
+ interruptMaskReg <= 5'h00;
+ end
+ else begin
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP1_CTRL_REG : begin
+ EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP2_CTRL_REG : begin
+ EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP3_CTRL_REG : begin
+ EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+ clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+ clrResetReq <= dataIn[`RESET_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ NAKSentInt <= 1'b0;
+ SOFRxedInt <= 1'b0;
+ resetEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (NAKSentIn == 1'b1)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedIn == 1'b1)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventIn == 1'b1)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntIn == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneIn == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+ if (rst == 1'b1) begin
+ EP0Ready <= 1'b0;
+ EP1Ready <= 1'b0;
+ EP2Ready <= 1'b0;
+ EP3Ready <= 1'b0;
+ end
+ else begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0Ready == 1'b1)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1Ready == 1'b1)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2Ready == 1'b1)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3Ready == 1'b1)
+ EP3Ready <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
+begin
+ endP0ControlReg <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlReg <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlReg <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlReg <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+ // async read mux
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+ endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+ endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
+ endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNum)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+ `EP0_STS_REG : dataOut <= EP0StatusReg;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+ `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+ `EP1_STS_REG : dataOut <= EP1StatusReg;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+ `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+ `EP2_STS_REG : dataOut <= EP2StatusReg;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+ `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+ `EP3_STS_REG : dataOut <= EP3StatusReg;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNum[10:8]};
+ `SC_FRAME_NUM_LSP : dataOut <= frameNum[7:0];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v (revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input SCTxPortRdyIn;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output directCntlGnt;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output sendPacketGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ:
+ begin
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ end
+ `SARB_SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `SARB_DC:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxDCEn <= 1'b0;
+ end
+ else
+ begin
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxDCEn <= next_muxDCEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output ACKRxed;
+output bitStuffError;
+output CRCError;
+output dataSequence;
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output [3:0]RxPID;
+output RXTimeOut;
+
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+wire [7:0]RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXOverflow <= 1'b0;
+ ACKRxed <= 1'b0;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXTimeOut <= 1'b0;
+ RxPID <= 4'h0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByteOld <= 8'h00;
+ end
+ else
+ begin
+ RXOverflow <= next_RXOverflow;
+ ACKRxed <= next_ACKRxed;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXTimeOut <= next_RXTimeOut;
+ RxPID <= next_RxPID;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ RXByteOld <= next_RXByteOld;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf (revision 264)
@@ -0,0 +1,403 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=857
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+I 832 821 0 Builtin Exit | 195662,92880
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+ 187314,234737 186141,226528 176133,223346 166125,220164\
+ 127582,215026 108152,212765
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+I 850 821 0 Builtin Entry | 49920,240120
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 588 589 0 Builtin Entry | 205195,243792
+I 587 589 0 Builtin Exit | 192962,45432
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 620 618 0 Builtin Exit | 144780,101600
+I 619 618 0 Builtin Entry | 96520,152400
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 614 612 0 TEXT "Conditions" | 70152,180662 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+ 162008,130636 151291,117855 140238,106874 129185,95894\
+ 77774,78896 71279,71294
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+ 41052,159480 41752,153900 40959,141711 40167,129522\
+ 46701,89176 50135,78506 53570,67837 54978,65340\
+ 57981,65109 60984,64878 60458,64813 61074,64659
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+I 650 559 0 Builtin Exit | 194044,45058
+I 649 559 0 Builtin Entry | 37971,243103
+I 381 377 0 Builtin Exit | 206487,14249
+I 380 377 0 Builtin Entry | 48940,236580
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+I 96 722 0 Builtin Reset | 76296,129336
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+I 399 377 0 Builtin Link | 54419,17564
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+ 197587,175015 201929,162657 202973,147251 204017,131846\
+ 203849,82580 202847,68719 201846,54859 198970,48147\
+ 197050,45058
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
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Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v (revision 264)
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlaveWrap.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+ clk,
+ reset,
+ address,
+ writedata,
+ readdata,
+ write,
+ read,
+ waitrequest,
+ chipselect,
+ irq,
+ USBWireVPI,
+ USBWireVMI,
+ USBWireDataInTick,
+ USBWireVPO,
+ USBWireVMO,
+ USBWireDataOutTick,
+ USBWireOutEn_n,
+ USBFullSpeed
+ );
+
+input clk;
+input reset;
+input [7:0] address;
+input [7:0] writedata;
+output [7:0] readdata;
+input write;
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address;
+wire [7:0] writedata;
+wire [7:0] readdata;
+wire write;
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+ hostResumeIntOut | hostTransDoneIntOut |
+ slaveSOFRxedIntOut | slaveResetEventIntOut |
+ slaveResumeIntOut | slaveTransDoneIntOut |
+ slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut;
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration:
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+ .clk(clk),
+ .rst(reset),
+ .address_i(address),
+ .data_i(writedata),
+ .data_o(readdata),
+ .writeEn(write),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .hostSOFSentIntOut(hostSOFSentIntOut),
+ .hostConnEventIntOut(hostConnEventIntOut),
+ .hostResumeIntOut(hostResumeIntOut),
+ .hostTransDoneIntOut(hostTransDoneIntOut),
+ .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+ .slaveResetEventIntOut(slaveResetEventIntOut),
+ .slaveResumeIntOut(slaveResumeIntOut),
+ .slaveTransDoneIntOut(slaveTransDoneIntOut),
+ .slaveNAKSentIntOut(slaveNAKSentIntOut),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v (revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ forceEmptySyncToUsbClk,
+ forceEmptySyncToBusClk,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+reg fifoWEn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstSyncToBusClk == 1'b1)
+ forceEmptyShift <= 6'b000000;
+ else begin
+ if (forceEmpty == 1'b1)
+ forceEmptyShift <= 6'b111111;
+ else
+ forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+ end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+ forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+// case (address)
+// `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+// `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+// `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+// default: busDataOut <= 8'h00;
+// endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
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\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf (revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIETransmitter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+ 161730,108850 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 144540,155815\
+ 141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+ 43361,99065 46384,95576 54928,94878 63472,94181\
+ 94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+ 104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1; \nresumeCnt <= resumeCnt + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+ 43973,74547 45899,68928 54485,67524 63072,66120\
+ 95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+ 34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+ 41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+ 46299,139871 48829,136075 59202,135063 69575,134052\
+ 106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+ 46931,109511 49715,104703 60024,103501 70334,102300\
+ 108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+ 48196,74723 50474,70169 60657,69030 70840,67892\
+ 108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+ 48829,42592 51359,37532 61605,36267 71852,35002\
+ 109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+ 128857,67252 162473,65260 171997,66691 181521,68123\
+ 186003,75843 187123,97692 188244,119542 188244,199222\
+ 184384,221196 180525,243170 165087,251388 155563,253628\
+ 146039,255869 123379,256617 115100,254625 106821,252633\
+ 98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+ 31250,150650 32250,89650 34750,72525 37250,55400\
+ 46250,47900 56000,46150 65750,44400 95896,46012\
+ 103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+ 124894,217487 107954,214253 97790,213829 87626,213406\
+ 65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v (revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processrxbit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processRxBitsWEn;
+input processRxByteRdy;
+input rst;
+input [1:0]RxBitsIn;
+input RxWireActive;
+output processRxBitRdy;
+output processRxByteWEn;
+output resumeDetected;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processRxBitRdy, next_processRxBitRdy;
+wire processRxBitsWEn;
+wire processRxByteRdy;
+reg processRxByteWEn, next_processRxByteWEn;
+reg resumeDetected, next_resumeDetected;
+wire rst;
+wire [1:0]RxBitsIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+wire RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg [1:0]oldRXBits, next_oldRXBits;
+reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg [3:0]RXBitCount, next_RXBitCount;
+reg [1:0]RxBits, next_RxBits;
+reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg [7:0]RXByte, next_RXByte;
+reg [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+ NextState_prRxBit <= CurrState_prRxBit;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOut <= RxDataOut;
+ next_resumeDetected <= resumeDetected;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState;
+ next_RxBits <= RxBits;
+ next_RXSameBitCount <= RXSameBitCount;
+ next_RXBitCount <= RXBitCount;
+ next_oldRXBits <= oldRXBits;
+ next_RXByte <= RXByte;
+ next_bitStuffError <= bitStuffError;
+ next_resumeWaitCnt <= resumeWaitCnt;
+ next_processRxBitRdy <= processRxBitRdy;
+ case (CurrState_prRxBit) // synopsys parallel_case full_case
+ `START:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOut <= 8'h00;
+ next_resumeDetected <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_RxBits <= 2'b00;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h0;
+ next_oldRXBits <= 2'b00;
+ next_RXByte <= 8'h00;
+ next_bitStuffError <= 1'b0;
+ next_resumeWaitCnt <= 5'h0;
+ next_processRxBitRdy <= 1'b1;
+ NextState_prRxBit <= `WAIT_BITS;
+ end
+ `WAIT_BITS:
+ begin
+ if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ end
+ `IDLE_FIRST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h1;
+ next_oldRXBits <= RxBits;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `IDLE_CHK_KBIT:
+ begin
+ if ((RxBits == KBit) && (RxWireActive == 1'b1))
+ begin
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `IDLE_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START;
+ //start of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_LAST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_CHK_SE0:
+ begin
+ next_bitStuffError <= 1'b0;
+ if (RxBits == `SE0)
+ begin
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+ if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+ next_bitStuffError <= 1'b1;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1, RXByte[7:1]};
+ //RZ bit <= 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0, RXByte[7:1]};
+ //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h0;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP;
+ //end of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_DATA_DESTUFF:
+ begin
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+ end
+ else if (bitStuffError == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `DATA_RX_BYTE_SEND2:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_BYTE_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+ next_RXBitCount <= 4'h0;
+ next_RxDataOut <= RXByte;
+ next_RxCtrlOut <= `DATA_STREAM;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_ERROR_CHK_RES:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ if (RxBits == JBit) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+ //check for resume
+ next_resumeWaitCnt <= 5'h0;
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_ERROR_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `RES_RX_CHK:
+ begin
+ if (RxBits != KBit) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+ next_resumeDetected <= 1'b1;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `RES_END_CHK1:
+ begin
+ if (RxBits != KBit) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_resumeDetected <= 1'b0;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxBit <= `START;
+ else
+ CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processRxByteWEn <= 1'b0;
+ RxCtrlOut <= 8'h00;
+ RxDataOut <= 8'h00;
+ resumeDetected <= 1'b0;
+ processRxBitRdy <= 1'b1;
+ RXBitStMachCurrState <= `IDLE_BIT_ST;
+ RxBits <= 2'b00;
+ RXSameBitCount <= 4'h0;
+ RXBitCount <= 4'h0;
+ oldRXBits <= 2'b00;
+ RXByte <= 8'h00;
+ bitStuffError <= 1'b0;
+ resumeWaitCnt <= 5'h0;
+ end
+ else
+ begin
+ processRxByteWEn <= next_processRxByteWEn;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOut <= next_RxDataOut;
+ resumeDetected <= next_resumeDetected;
+ processRxBitRdy <= next_processRxBitRdy;
+ RXBitStMachCurrState <= next_RXBitStMachCurrState;
+ RxBits <= next_RxBits;
+ RXSameBitCount <= next_RXSameBitCount;
+ RXBitCount <= next_RXBitCount;
+ oldRXBits <= next_oldRXBits;
+ RXByte <= next_RXByte;
+ bitStuffError <= next_bitStuffError;
+ resumeWaitCnt <= next_resumeWaitCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v (revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteWEn;
+input rst;
+input [7:0]TxByteCtrlIn;
+input TxByteFullSpeedRateIn;
+input [7:0]TxByteIn;
+input USBWireGnt;
+input USBWireRdy;
+output processTxByteRdy;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processTxByteRdy, next_processTxByteRdy;
+wire processTxByteWEn;
+wire rst;
+wire [7:0]TxByteCtrlIn;
+wire TxByteFullSpeedRateIn;
+wire [7:0]TxByteIn;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [3:0]i, next_i;
+reg [7:0]TxByte, next_TxByte;
+reg [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg [1:0]TXLineState, next_TXLineState;
+reg [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+ NextState_prcTxB <= CurrState_prcTxB;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_USBWireReq <= USBWireReq;
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_TxByte <= TxByte;
+ next_TxByteCtrl <= TxByteCtrl;
+ next_TXLineState <= TXLineState;
+ next_TXOneCount <= TXOneCount;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+ case (CurrState_prcTxB) // synopsys parallel_case full_case
+ `START_PTBY:
+ begin
+ next_processTxByteRdy <= 1'b0;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_i <= 4'h0;
+ next_TxByte <= 8'h00;
+ next_TxByteCtrl <= 8'h00;
+ next_TXLineState <= 2'b0;
+ next_TXOneCount <= 4'h0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ next_TxByteFullSpeedRate <= 1'b0;
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `PTBY_WAIT_EN:
+ begin
+ next_processTxByteRdy <= 1'b1;
+ if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_TXOneCount <= 4'h0;
+ next_TXLineState <= JBit;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (processTxByteWEn == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_i <= 4'h0;
+ end
+ end
+ `PTBY_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_WIRE;
+ end
+ end
+ `WAIT_RDY_WIRE:
+ begin
+ if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE1;
+ end
+ else if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_PKT;
+ //actively drive the first J bit
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `WAIT_RDY_PKT:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `SEND_BYTE_UPDATE_BYTE:
+ begin
+ next_i <= i + 1'b1;
+ next_TxByte <= {1'b0, TxByte[7:1] };
+ if (TxByte[0] == 1'b1) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+ end
+ `SEND_BYTE_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+ end
+ else if (i != 4'h8)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ else
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ end
+ `SEND_BYTE_BIT_STUFF:
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+ end
+ `SEND_BYTE_WAIT_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == 4'h8)
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ else
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ end
+ `STOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY2;
+ end
+ `STOP_SND_SE0_1:
+ begin
+ NextState_prcTxB <= `STOP_W_RDY1;
+ end
+ `STOP_CHK:
+ begin
+ if (TxByteCtrl == `DATA_STOP)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_1;
+ end
+ else
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ end
+ `STOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY3;
+ end
+ `STOP_SND_IDLE:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY4;
+ end
+ `STOP_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `STOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_J;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY2;
+ end
+ `LS_START_SND_J1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY3;
+ end
+ `LS_START_SND_IDLE1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY1;
+ end
+ `LS_START_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `LS_START_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE3;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_J1;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_FIN;
+ //Drive the first JBit
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prcTxB <= `START_PTBY;
+ else
+ CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processTxByteRdy <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ USBWireReq <= 1'b0;
+ USBWireWEn <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ i <= 4'h0;
+ TxByte <= 8'h00;
+ TxByteCtrl <= 8'h00;
+ TXLineState <= 2'b0;
+ TXOneCount <= 4'h0;
+ TxByteFullSpeedRate <= 1'b0;
+ end
+ else
+ begin
+ processTxByteRdy <= next_processTxByteRdy;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ USBWireReq <= next_USBWireReq;
+ USBWireWEn <= next_USBWireWEn;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ i <= next_i;
+ TxByte <= next_TxByte;
+ TxByteCtrl <= next_TxByteCtrl;
+ TXLineState <= next_TXLineState;
+ TXOneCount <= next_TXOneCount;
+ TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v (revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [15:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [15:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 16'hffff;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0)
+ begin
+ if (CRCEn == 1'b1) begin
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ ready <= 1'b0;
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[15:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == 4'h7)
+ begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v (revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbTxWireArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input clk;
+input prcTxByteCtrl;
+input [1:0]prcTxByteData;
+input prcTxByteFSRate;
+input prcTxByteReq;
+input prcTxByteWEn;
+input rst;
+input SIETxCtrl;
+input [1:0]SIETxData;
+input SIETxFSRate;
+input SIETxReq;
+input SIETxWEn;
+input USBWireRdyIn;
+output prcTxByteGnt;
+output SIETxGnt;
+output [1:0]TxBits;
+output TxCtl;
+output TxFSRate;
+output USBWireRdyOut;
+output USBWireWEn;
+
+wire clk;
+wire prcTxByteCtrl;
+wire [1:0]prcTxByteData;
+wire prcTxByteFSRate;
+reg prcTxByteGnt, next_prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire rst;
+wire SIETxCtrl;
+wire [1:0]SIETxData;
+wire SIETxFSRate;
+reg SIETxGnt, next_SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+reg [1:0]TxBits, next_TxBits;
+reg TxCtl, next_TxCtl;
+reg TxFSRate, next_TxFSRate;
+wire USBWireRdyIn;
+reg USBWireRdyOut, next_USBWireRdyOut;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+ NextState_txWireArb <= CurrState_txWireArb;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt;
+ next_SIETxGnt <= SIETxGnt;
+ next_muxSIENotPTXB <= muxSIENotPTXB;
+ case (CurrState_txWireArb) // synopsys parallel_case full_case
+ `START_TARB:
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ end
+ `TARB_WAIT_REQ:
+ begin
+ if (prcTxByteReq == 1'b1)
+ begin
+ NextState_txWireArb <= `PTXB_ACT;
+ next_prcTxByteGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b0;
+ end
+ else if (SIETxReq == 1'b1)
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT;
+ next_SIETxGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b1;
+ end
+ end
+ `PTXB_ACT:
+ begin
+ if (prcTxByteReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_prcTxByteGnt <= 1'b0;
+ end
+ end
+ `SIE_TX_ACT:
+ begin
+ if (SIETxReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_SIETxGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_txWireArb <= `START_TARB;
+ else
+ CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ prcTxByteGnt <= 1'b0;
+ SIETxGnt <= 1'b0;
+ muxSIENotPTXB <= 1'b0;
+ end
+ else
+ begin
+ prcTxByteGnt <= next_prcTxByteGnt;
+ SIETxGnt <= next_SIETxGnt;
+ muxSIENotPTXB <= next_muxSIENotPTXB;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v (revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v (revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+ `START_SDC:
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf (revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v (revision 264)
@@ -0,0 +1,493 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+ clk, rst,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(clk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rst),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone)
+ );
+
+
+endpMux u_endpMux (
+ .clk(clk),
+ .rst(rst),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(clk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rst),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(clk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rst) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(clk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rst),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(clk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rst) );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(clk),
+ .rst(rst) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v (revision 264)
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ forceEmptySyncToUsbClk,
+ forceEmptySyncToBusClk,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstSyncToBusClk == 1'b1)
+ forceEmptyShift <= 6'b000000;
+ else begin
+ if (forceEmpty == 1'b1)
+ forceEmptyShift <= 6'b111111;
+ else
+ forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+ end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+ forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v (revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dpMem_dc.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+ dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+ if (writeEn == 1'b1)
+ buffer[addrIn] <= dataIn;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 78
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 127
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+ 46421,89345 46021,97345 47471,100295 48921,103245\
+ 55748,105011 58848,106911
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "HCTxPortGnt == 1'b1"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+ 47285,153175 50048,167625 56316,171290 62585,174956\
+ 84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+ 171826,160150 159742,169266 150997,171704 142252,174142\
+ 120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf (revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+ 288786,359372 287077,371461 282417,376909 277757,382357\
+ 274547,381487 268775,381564 263003,381642 254872,381366\
+ 248267,378971 241663,376577 234289,371557 230118,369008
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+ 166944,348155 168507,364217 173450,370590 178394,376963\
+ 186275,384997 193806,383684 201338,382371 213515,373400\
+ 220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+ 259846,282068 289467,282068 298484,284234 307501,286400\
+ 313949,295065 315460,307759 316972,320453 316568,362568\
+ 311430,375060 306292,387553 286404,388600 275724,388298\
+ 265045,387996 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,380 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+ TxTransTypeReg, TxSOFEnableReg,
+ TxAddrReg, TxEndPReg, frameNumIn,
+ RxPktStatusIn, RxPIDIn,
+ connectStateIn,
+ SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+ hostControlSelect,
+ clrTransReq,
+ preambleEn,
+ SOFSync,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ transReq,
+ isoEn,
+ SOFTimer
+ );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output transReq;
+output isoEn; //enable isochronous mode
+input [15:0] SOFTimer;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+wire [15:0] SOFTimer;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [1:0] TxTransTypeRegSTB;
+reg TxSOFEnableRegSTB;
+reg [6:0] TxAddrRegSTB;
+reg [3:0] TxEndPRegSTB;
+reg preambleEnSTB;
+reg SOFSyncSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB;
+reg fullSpeedRateSTB;
+reg transReqSTB;
+reg isoEnSTB;
+reg [10:0] frameNumInSTB;
+reg [7:0] RxPktStatusInSTB;
+reg [3:0] RxPIDInSTB;
+reg [1:0] connectStateInSTB;
+reg SOFSentInSTB;
+reg connEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrTransReqSTB;
+reg [15:0] SOFTimerSTB;
+
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ isoEnSTB <= 1'b0;
+ preambleEnSTB <= 1'b0;
+ SOFSyncSTB <= 1'b0;
+ TxTransTypeRegSTB <= 2'b00;
+ TxLineControlReg <= 5'h00;
+ TxSOFEnableRegSTB <= 1'b0;
+ TxAddrRegSTB <= 7'h00;
+ TxEndPRegSTB <= 4'h0;
+ interruptMaskReg <= 4'h0;
+ end
+ else begin
+ clrSOFReq <= 1'b0;
+ clrConnEvtReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ setTransReq <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+ begin
+ case (address)
+ `TX_CONTROL_REG : begin
+ isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
+ preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
+ SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
+ setTransReq <= dataIn[`TRANS_REQ_BIT];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+ `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
+ `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
+ `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn[`SOF_SENT_BIT];
+ clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ SOFSentInt <= 1'b0;
+ connEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (SOFSentInSTB == 1'b1)
+ SOFSentInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFSentInt <= 1'b0;
+
+ if (connEventInSTB == 1'b1)
+ connEventInt <= 1'b1;
+ else if (clrConnEvtReq == 1'b1)
+ connEventInt <= 1'b0;
+
+ if (resumeIntInSTB == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneInSTB == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end
+
+//transaction request set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'setTransReq' must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the transaction request is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ transReqSTB <= 1'b0;
+ end
+ else begin
+ if (setTransReq == 1'b1)
+ transReqSTB <= 1'b1;
+ else if (clrTransReqSTB == 1'b1)
+ transReqSTB <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+ TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+ LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+ fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
+ TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
+ preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
+begin
+ case (address)
+ `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
+ `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
+ `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
+ `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
+ `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
+ `RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
+ `RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
+ `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+//re-sync from busClk to usbClk.
+always @(posedge usbClk) begin
+ if (rstSyncToUsbClk == 1'b1) begin
+ isoEn <= 1'b0;
+ preambleEn <= 1'b0;
+ SOFSync <= 1'b0;
+ TxTransTypeReg <= 2'b00;
+ TxSOFEnableReg <= 1'b0;
+ TxAddrReg <= 7'h00;
+ TxEndPReg <= 4'h0;
+ TxLineState <= 2'b00;
+ LineDirectControlEn <= 1'b0;
+ fullSpeedPol <= 1'b0;
+ fullSpeedRate <= 1'b0;
+ transReq <= 1'b0;
+ end
+ else begin
+ isoEn <= isoEnSTB;
+ preambleEn <= preambleEnSTB;
+ SOFSync <= SOFSyncSTB;
+ TxTransTypeReg <= TxTransTypeRegSTB;
+ TxSOFEnableReg <= TxSOFEnableRegSTB;
+ TxAddrReg <= TxAddrRegSTB;
+ TxEndPReg <= TxEndPRegSTB;
+ TxLineState <= TxLineStateSTB;
+ LineDirectControlEn <= LineDirectControlEnSTB;
+ fullSpeedPol <= fullSpeedPolSTB;
+ fullSpeedRate <= fullSpeedRateSTB;
+ transReq <= transReqSTB;
+ end
+end
+
+//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+ frameNumInSTB <= frameNumIn;
+ RxPktStatusInSTB <= RxPktStatusIn;
+ RxPIDInSTB <= RxPIDIn;
+ connectStateInSTB <= connectStateIn;
+ SOFSentInSTB <= SOFSentIn;
+ connEventInSTB <= connEventIn;
+ resumeIntInSTB <= resumeIntIn;
+ transDoneInSTB <= transDoneIn;
+ clrTransReqSTB <= clrTransReq;
+ SOFTimerSTB <= SOFTimer;
+end
+
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v (revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// getpacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXPacketRdy;
+output [3:0]RxPID;
+output [7:0]RXPktStatus;
+
+wire clk;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+reg [7:0]RXPktStatus;
+wire [7:0]RXStreamStatusIn;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+ NextState_getPkt <= CurrState_getPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_getPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_getPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_getPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_getPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+ next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_getPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_getPkt <= `START_GP;
+ else
+ CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RxPID <= 4'h0;
+ RXOverflow <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXByteOld <= 8'h00;
+ RXTimeOut <= 1'b0;
+ end
+ else
+ begin
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RxPID <= next_RxPID;
+ RXOverflow <= next_RXOverflow;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXByteOld <= next_RXByteOld;
+ RXTimeOut <= next_RXTimeOut;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf (revision 264)
@@ -0,0 +1,277 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=284
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+C 282 281 0 TEXT "Conditions" | 78641,126629 1 0 0 "SIERxTimeOut == 1'b1"
+W 281 6 0 11 40 BEZIER "Transitions" | 103032,141659 103834,114294 105382,61467 106184,34102
+W 279 120 0 278 137 BEZIER "Transitions" | 45244,175402 46602,184714 48694,202964 53786,209657\
+ 58879,216350 75631,224113 84458,228187
+S 278 120 90112 ELLIPSE "States" | 44712,168924 6500 6500
+L 277 278 0 TEXT "State Labels" | 44712,168924 1 0 0 "DELAY\n/17/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "slvGetPkt"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: slaveGetPacket"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
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+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
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+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
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+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
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+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
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+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
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+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
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+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
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+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
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+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
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+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v (revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveSendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input [3:0]PID;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+input sendPacketWEn;
+output fifoReadEn;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+wire [3:0]PID;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+ NextState_slvSndPkt <= CurrState_slvSndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+ `START_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ end
+ `SP_WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP1_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `SP1_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_SCTxPortReq <= 1'b0;
+ end
+ `SP_NOT_DATA:
+ begin
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_SEND_PID_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= PIDNotPID;
+ next_SCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SP_SEND_PID_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_NOT_DATA;
+ end
+ end
+ `SP_D0_D1_READ_FIFO:
+ begin
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= fifoData;
+ next_SCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+ end
+ `SP_D0_D1_WAIT_READ_FIFO:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `SP_D0_D1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+ end
+ end
+ `SP_D0_D1_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_D0_D1_TERM_BYTE:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `SP_D0_D1_CLR_WEN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ `SP_D0_D1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvSndPkt <= `START_SP1;
+ else
+ CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ SCTxPortData <= 8'h00;
+ SCTxPortCntl <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v (revision 264)
@@ -0,0 +1,516 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlave.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+ clk,
+ rst,
+ address_i,
+ data_i,
+ data_o,
+ writeEn,
+ strobe_i,
+ ack_o,
+ hostSOFSentIntOut,
+ hostConnEventIntOut,
+ hostResumeIntOut,
+ hostTransDoneIntOut,
+ slaveNAKSentIntOut,
+ slaveSOFRxedIntOut,
+ slaveResetEventIntOut,
+ slaveResumeIntOut,
+ slaveTransDoneIntOut,
+ USBWireDataIn,
+ USBWireDataInTick,
+ USBWireDataOut,
+ USBWireDataOutTick,
+ USBWireCtrlOut,
+ USBFullSpeed
+ );
+ parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+ parameter HOST_FIFO_ADDR_WIDTH = 6;
+ parameter EP0_FIFO_DEPTH = 64;
+ parameter EP0_FIFO_ADDR_WIDTH = 6;
+ parameter EP1_FIFO_DEPTH = 64;
+ parameter EP1_FIFO_ADDR_WIDTH = 6;
+ parameter EP2_FIFO_DEPTH = 64;
+ parameter EP2_FIFO_ADDR_WIDTH = 6;
+ parameter EP3_FIFO_DEPTH = 64;
+ parameter EP3_FIFO_ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [7:0] address_i;
+input [7:0] data_i;
+output [7:0] data_o;
+input writeEn;
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut;
+output hostConnEventIntOut;
+output hostResumeIntOut;
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut;
+output slaveResetEventIntOut;
+output slaveResumeIntOut;
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk;
+wire rst;
+wire [7:0] address_i;
+wire [7:0] data_i;
+wire [7:0] data_o;
+wire writeEn;
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel;
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE;
+wire [7:0] hostTxFifoData;
+wire hostTxFifoEmpty;
+wire hostRxFifoWE;
+wire [7:0] hostRxFifoData;
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut;
+wire [7:0] RxDataFromSIE;
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState;
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;
+
+usbHostControl u_usbHostControl(
+ .clk(clk),
+ .rst(rst),
+ .TxFifoRE(hostTxFifoRE),
+ .TxFifoData(hostTxFifoData),
+ .TxFifoEmpty(hostTxFifoEmpty),
+ .RxFifoWE(hostRxFifoWE),
+ .RxFifoData(hostRxFifoData),
+ .RxFifoFull(hostRxFifoFull),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .fullSpeedRate(fullSpeedBitRateFromHost),
+ .fullSpeedPol(fullSpeedPolarityFromHost),
+ .HCTxPortEn(SIEPortWEnFromHost),
+ .HCTxPortRdy(SIEPortTxRdy),
+ .HCTxPortData(SIEPortDataInFromHost),
+ .HCTxPortCtrl(SIEPortCtrlInFromHost),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[3:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFSentIntOut(hostSOFSentIntOut),
+ .connEventIntOut(hostConnEventIntOut),
+ .resumeIntOut(hostResumeIntOut),
+ .transDoneIntOut(hostTransDoneIntOut),
+ .hostControlSelect(hostControlSel) );
+
+
+usbSlaveControl u_usbSlaveControl(
+ .clk(clk),
+ .rst(rst),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .RxFifoData(slaveRxFifoData),
+ .fullSpeedRate(fullSpeedBitRateFromSlave),
+ .fullSpeedPol(fullSpeedPolarityFromSlave),
+ .SCTxPortEn(SIEPortWEnFromSlave),
+ .SCTxPortRdy(SIEPortTxRdy),
+ .SCTxPortData(SIEPortDataInFromSlave),
+ .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[4:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromSlaveControl),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .SOFRxedIntOut(slaveSOFRxedIntOut),
+ .resetEventIntOut(slaveResetEventIntOut),
+ .resumeIntOut(slaveResumeIntOut),
+ .transDoneIntOut(slaveTransDoneIntOut),
+ .NAKSentIntOut(slaveNAKSentIntOut),
+ .slaveControlSelect(slaveControlSel),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+wishBoneBI u_wishBoneBI (
+ .address(address_i),
+ .dataIn(data_i),
+ .dataOut(data_o),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .clk(clk),
+ .rst(rst),
+ .hostControlSel(hostControlSel),
+ .hostRxFifoSel(hostRxFifoSel),
+ .hostTxFifoSel(hostTxFifoSel),
+ .slaveControlSel(slaveControlSel),
+ .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
+ .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
+ .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
+ .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
+ .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
+ .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
+ .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
+ .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .dataFromHostControl(dataFromHostControl),
+ .dataFromHostRxFifo(dataFromHostRxFifo),
+ .dataFromHostTxFifo(dataFromHostTxFifo),
+ .dataFromSlaveControl(dataFromSlaveControl),
+ .dataFromEP0RxFifo(dataFromEP0RxFifo),
+ .dataFromEP1RxFifo(dataFromEP1RxFifo),
+ .dataFromEP2RxFifo(dataFromEP2RxFifo),
+ .dataFromEP3RxFifo(dataFromEP3RxFifo),
+ .dataFromEP0TxFifo(dataFromEP0TxFifo),
+ .dataFromEP1TxFifo(dataFromEP1TxFifo),
+ .dataFromEP2TxFifo(dataFromEP2TxFifo),
+ .dataFromEP3TxFifo(dataFromEP3TxFifo),
+ .dataFromHostSlaveMux(dataFromHostSlaveMux)
+ );
+
+hostSlaveMux u_hostSlaveMux(
+ .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+ .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+ .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+ .SIEPortDataInToSIE(SIEPortDataInToSIE),
+ .SIEPortDataInFromHost(SIEPortDataInFromHost),
+ .SIEPortDataInFromSlave(SIEPortDataInFromSlave),
+ .SIEPortWEnToSIE(SIEPortWEnToSIE),
+ .SIEPortWEnFromHost(SIEPortWEnFromHost),
+ .SIEPortWEnFromSlave(SIEPortWEnFromSlave),
+ .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+ .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+ .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+ .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+ .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+ .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+ .dataIn(data_i),
+ .dataOut(dataFromHostSlaveMux),
+ .address(address_i[0]),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .clk(clk),
+ .rst(rst),
+ .hostSlaveMuxSel(hostSlaveMuxSel) );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+ .clk(clk),
+ .rst(rst),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .connectState(connectState),
+ .resumeDetected(resumeDetected),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataFromSIE),
+ .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+ .SIEPortDataIn(SIEPortDataInToSIE),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEnToSIE),
+ .fullSpeedPolarity(fullSpeedPolarityToSIE),
+ .fullSpeedBitRate(fullSpeedBitRateToSIE),
+ .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(hostTxFifoRE),
+ .fifoEmpty(hostTxFifoEmpty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostTxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostTxFifo),
+ .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(hostRxFifoWE),
+ .fifoFull(hostRxFifoFull),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostRxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostRxFifo),
+ .fifoDataIn(hostRxFifoData) );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP0REn),
+ .fifoEmpty(TxFifoEP0Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0TxFifo),
+ .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP1REn),
+ .fifoEmpty(TxFifoEP1Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1TxFifo),
+ .fifoDataOut(TxFifoEP1Data) );
+
+ TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP2REn),
+ .fifoEmpty(TxFifoEP2Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2TxFifo),
+ .fifoDataOut(TxFifoEP2Data) );
+
+ TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+ .clk(clk),
+ .rst(rst),
+ .fifoREn(TxFifoEP3REn),
+ .fifoEmpty(TxFifoEP3Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3TxFifo),
+ .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP0WEn),
+ .fifoFull(RxFifoEP0Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP1WEn),
+ .fifoFull(RxFifoEP1Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP2WEn),
+ .fifoFull(RxFifoEP2Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+ .clk(clk),
+ .rst(rst),
+ .fifoWEn(RxFifoEP3WEn),
+ .fifoFull(RxFifoEP3Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(writeEn),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm (revision 264)
@@ -0,0 +1,276 @@
+
+
+USBHostControlBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address , dataIn , dataOut , writeEn ,
+ strobe_i ,
+ clk , rst ,
+ SOFSentIntOut , connEventIntOut , resumeIntOut , transDoneIntOut ,
+ TxTransTypeReg , TxSOFEnableReg ,
+ TxAddrReg , TxEndPReg , frameNumIn ,
+ RxPktStatusIn , RxPIDIn ,
+ connectStateIn ,
+ SOFSentIn , connEventIn , resumeIntIn , transDoneIn ,
+ hostControlSelect ,
+ clrTransReq ,
+ preambleEn ,
+ SOFSync ,
+ TxLineState ,
+ LineDirectControlEn ,
+ fullSpeedPol ,
+ fullSpeedRate ,
+ transReq
+ );
+input [3 :0 ] address ;
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+output SOFSentIntOut ;
+output connEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+
+output [1 :0 ] TxTransTypeReg ;
+output TxSOFEnableReg ;
+output [6 :0 ] TxAddrReg ;
+output [3 :0 ] TxEndPReg ;
+input [10 :0 ] frameNumIn ;
+input [7 :0 ] RxPktStatusIn ;
+input [3 :0 ] RxPIDIn ;
+input [1 :0 ] connectStateIn ;
+input SOFSentIn ;
+input connEventIn ;
+input resumeIntIn ;
+input transDoneIn ;
+input hostControlSelect ;
+input clrTransReq ;
+output preambleEn ;
+output SOFSync ;
+output [1 :0 ] TxLineState ;
+output LineDirectControlEn ;
+output fullSpeedPol ;
+output fullSpeedRate ;
+output transReq ;
+
+wire [3 :0 ] address ;
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+
+reg SOFSentIntOut ;
+reg connEventIntOut ;
+reg resumeIntOut ;
+reg transDoneIntOut ;
+
+reg [1 :0 ] TxTransTypeReg ;
+reg TxSOFEnableReg ;
+reg [6 :0 ] TxAddrReg ;
+reg [3 :0 ] TxEndPReg ;
+wire [10 :0 ] frameNumIn ;
+wire [7 :0 ] RxPktStatusIn ;
+wire [3 :0 ] RxPIDIn ;
+wire [1 :0 ] connectStateIn ;
+
+wire SOFSentIn ;
+wire connEventIn ;
+wire resumeIntIn ;
+wire transDoneIn ;
+wire hostControlSelect ;
+wire clrTransReq ;
+reg preambleEn ;
+reg SOFSync ;
+reg [1 :0 ] TxLineState ;
+reg LineDirectControlEn ;
+reg fullSpeedPol ;
+reg fullSpeedRate ;
+reg transReq ;
+
+//internal wire and regs
+reg [1 :0 ] TxControlReg ;
+reg [4 :0 ] TxLineControlReg ;
+reg clrSOFReq ;
+reg clrConnEvtReq ;
+reg clrResInReq ;
+reg clrTransDoneReq ;
+reg SOFSentInt ;
+reg connEventInt ;
+reg resumeInt ;
+reg transDoneInt ;
+reg [3 :0 ] interruptMaskReg ;
+reg setTransReq ;
+
+//sync write demux
+always @(posedge clk )
+begin
+ clrSOFReq <= 1'b0 ;
+ clrConnEvtReq <= 1'b0 ;
+ clrResInReq <= 1'b0 ;
+ clrTransDoneReq <= 1'b0 ;
+ setTransReq <= 1'b0 ;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1 )
+ begin
+ case (address )
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn [2 ];
+ SOFSync <= dataIn [1 ];
+ setTransReq <= dataIn [0 ];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn [1 :0 ];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn [4 :0 ];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn [0 ];
+ `TX_ADDR_REG : TxAddrReg <= dataIn [6 :0 ];
+ `TX_ENDP_REG : TxEndPReg <= dataIn [3 :0 ];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn [3 ];
+ clrConnEvtReq <= dataIn [2 ];
+ clrResInReq <= dataIn [1 ];
+ clrTransDoneReq <= dataIn [0 ];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn [3 :0 ];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk )
+begin
+ if (SOFSentIn == 1'b1 )
+ SOFSentInt <= 1'b1 ;
+ else if (clrSOFReq == 1'b1 )
+ SOFSentInt <= 1'b0 ;
+
+ if (connEventIn == 1'b1 )
+ connEventInt <= 1'b1 ;
+ else if (clrConnEvtReq == 1'b1 )
+ connEventInt <= 1'b0 ;
+
+ if (resumeIntIn == 1'b1 )
+ resumeInt <= 1'b1 ;
+ else if (clrResInReq == 1'b1 )
+ resumeInt <= 1'b0 ;
+
+ if (transDoneIn == 1'b1 )
+ transDoneInt <= 1'b1 ;
+ else if (clrTransDoneReq == 1'b1 )
+ transDoneInt <= 1'b0 ;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt ) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg [`TRANS_DONE_BIT ];
+ resumeIntOut <= resumeInt & interruptMaskReg [`RESUME_INT_BIT ];
+ connEventIntOut <= connEventInt & interruptMaskReg [`CONNECTION_EVENT_BIT ];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg [`SOF_SENT_BIT ];
+end
+
+//transaction request set/clear
+always @(posedge clk )
+begin
+ if (setTransReq == 1'b1 )
+ transReq <= 1'b1 ;
+ else if (clrTransReq == 1'b1 )
+ transReq <= 1'b0 ;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg ) begin
+ TxLineState <= TxLineControlReg [`TX_LINE_STATE_MSBIT :`TX_LINE_STATE_LSBIT ];
+ LineDirectControlEn <= TxLineControlReg [`DIRECT_CONTROL_BIT ];
+ fullSpeedPol <= TxLineControlReg [`FULL_SPEED_LINE_POLARITY_BIT ];
+ fullSpeedRate <= TxLineControlReg [`FULL_SPEED_LINE_RATE_BIT ];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq )
+begin
+ case (address )
+ `TX_CONTROL_REG : dataOut <= {5'b00000 , preambleEn , SOFSync , transReq } ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000 , TxTransTypeReg };
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000 , TxLineControlReg };
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000 , TxSOFEnableReg };
+ `TX_ADDR_REG : dataOut <= {1'b0 , TxAddrReg };
+ `TX_ENDP_REG : dataOut <= {4'h0 , TxEndPReg };
+ `FRAME_NUM_MSB_REG : dataOut <= frameNumIn [10 :3 ];
+ `FRAME_NUM_LSB_REG : dataOut <= {5'b00000 , frameNumIn [2 :0 ]};
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0 , SOFSentInt , connEventInt , resumeInt , transDoneInt };
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0 , interruptMaskReg };
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn ;
+ `RX_PID_REG : dataOut <= {4'b0000 , RxPIDIn };
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000 , connectStateIn };
+ default : dataOut <= 8'h00 ;
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v (revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ rstSyncToUsbClk,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input rstSyncToUsbClk;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .wrClk(busClk),
+ .rdClk(usbClk),
+ .rstSyncToWrClk(rstSyncToBusClk),
+ .rstSyncToRdClk(rstSyncToUsbClk),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmptySyncToWrClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToRdClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v (revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+
+module wishBoneBI (
+ address, dataIn, dataOut, writeEn,
+ strobe_i,
+ ack_o,
+ clk, rst,
+ hostControlSel,
+ hostRxFifoSel, hostTxFifoSel,
+ slaveControlSel,
+ slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
+ slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
+ hostSlaveMuxSel,
+ dataFromHostControl,
+ dataFromHostRxFifo,
+ dataFromHostTxFifo,
+ dataFromSlaveControl,
+ dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+ dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+ dataFromHostSlaveMux
+ );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+ dataFromHostControl or
+ dataFromHostRxFifo or
+ dataFromHostTxFifo or
+ dataFromSlaveControl or
+ dataFromEP0RxFifo or
+ dataFromEP1RxFifo or
+ dataFromEP2RxFifo or
+ dataFromEP3RxFifo or
+ dataFromHostSlaveMux or
+ dataFromEP0TxFifo or
+ dataFromEP1TxFifo or
+ dataFromEP2TxFifo or
+ dataFromEP3TxFifo)
+begin
+ hostControlSel <= 1'b0;
+ hostRxFifoSel <= 1'b0;
+ hostTxFifoSel <= 1'b0;
+ slaveControlSel <= 1'b0;
+ slaveEP0RxFifoSel <= 1'b0;
+ slaveEP0TxFifoSel <= 1'b0;
+ slaveEP1RxFifoSel <= 1'b0;
+ slaveEP1TxFifoSel <= 1'b0;
+ slaveEP2RxFifoSel <= 1'b0;
+ slaveEP2TxFifoSel <= 1'b0;
+ slaveEP3RxFifoSel <= 1'b0;
+ slaveEP3TxFifoSel <= 1'b0;
+ hostSlaveMuxSel <= 1'b0;
+ case (address & `ADDRESS_DECODE_MASK)
+ `HCREG_BASE : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HCREG_BASE_PLUS_0X10 : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HOST_RX_FIFO_BASE : begin
+ hostRxFifoSel <= 1'b1;
+ dataOut <= dataFromHostRxFifo;
+ end
+ `HOST_TX_FIFO_BASE : begin
+ hostTxFifoSel <= 1'b1;
+ dataOut <= dataFromHostTxFifo;
+ end
+ `SCREG_BASE : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `SCREG_BASE_PLUS_0X10 : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `EP0_RX_FIFO_BASE : begin
+ slaveEP0RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0RxFifo;
+ end
+ `EP0_TX_FIFO_BASE : begin
+ slaveEP0TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0TxFifo;
+ end
+ `EP1_RX_FIFO_BASE : begin
+ slaveEP1RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1RxFifo;
+ end
+ `EP1_TX_FIFO_BASE : begin
+ slaveEP1TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1TxFifo;
+ end
+ `EP2_RX_FIFO_BASE : begin
+ slaveEP2RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2RxFifo;
+ end
+ `EP2_TX_FIFO_BASE : begin
+ slaveEP2TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2TxFifo;
+ end
+ `EP3_RX_FIFO_BASE : begin
+ slaveEP3RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3RxFifo;
+ end
+ `EP3_TX_FIFO_BASE : begin
+ slaveEP3TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3TxFifo;
+ end
+ `HOST_SLAVE_CONTROL_BASE : begin
+ hostSlaveMuxSel <= 1'b1;
+ dataOut <= dataFromHostSlaveMux;
+ end
+ default:
+ dataOut <= 8'h00;
+ endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+ ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+ ack_immediate <= strobe_i;
+end
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+ if (writeEn == 1'b0 &&
+ (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+ begin
+ ack_o <= ack_delayed;
+ end
+ else
+ begin
+ ack_o <= ack_immediate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf (revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+PAGE 12700,12700 215900,279400
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+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus = { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+ 57686,214631 75382,223396 84426,228258
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// rxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ connectionEventOut <= 1'b1;
+ else
+ connectionEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v (revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketarbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input clk;
+input [3:0]HC_PID;
+input HC_SP_WEn;
+input HCTxReq;
+input rst;
+input SOF_SP_WEn;
+input SOFTxReq;
+output HCTxGnt;
+output [3:0]sendPacketPID;
+output sendPacketWEnable;
+output SOFTxGnt;
+
+wire clk;
+wire [3:0]HC_PID;
+wire HC_SP_WEn;
+reg HCTxGnt, next_HCTxGnt;
+wire HCTxReq;
+wire rst;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+reg sendPacketWEnable, next_sendPacketWEnable;
+wire SOF_SP_WEn;
+reg SOFTxGnt, next_SOFTxGnt;
+wire SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+ NextState_sendPktArb <= CurrState_sendPktArb;
+ // Set default values for outputs and signals
+ next_HCTxGnt <= HCTxGnt;
+ next_SOFTxGnt <= SOFTxGnt;
+ next_muxSOFNotHC <= muxSOFNotHC;
+ case (CurrState_sendPktArb) // synopsys parallel_case full_case
+ `HC_ACT:
+ begin
+ if (HCTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_HCTxGnt <= 1'b0;
+ end
+ end
+ `SOF_ACT:
+ begin
+ if (SOFTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_SOFTxGnt <= 1'b0;
+ end
+ end
+ `SARB_WAIT_REQ:
+ begin
+ if (SOFTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `SOF_ACT;
+ next_SOFTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b1;
+ end
+ else if (HCTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `HC_ACT;
+ next_HCTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktArb <= `START_SARB;
+ else
+ CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxGnt <= 1'b0;
+ SOFTxGnt <= 1'b0;
+ muxSOFNotHC <= 1'b0;
+ end
+ else
+ begin
+ HCTxGnt <= next_HCTxGnt;
+ SOFTxGnt <= next_SOFTxGnt;
+ muxSOFNotHC <= next_muxSOFNotHC;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v (revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sofcontroller
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input clk;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+input SOFEnable;
+input SOFTimerClr;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output [15:0]SOFTimer;
+
+wire clk;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+wire SOFEnable;
+reg [15:0]SOFTimer, next_SOFTimer;
+wire SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+ NextState_sofCntl <= CurrState_sofCntl;
+ // Set default values for outputs and signals
+ next_SOFTimer <= SOFTimer;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_sofCntl) // synopsys parallel_case full_case
+ `START_SC:
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ end
+ `WAIT_SOF_EN:
+ begin
+ if (SOFEnable == 1'b1)
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `WAIT_SEND_RESUME:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sofCntl <= `CLR_WEN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_RESUME_START;
+ end
+ end
+ `INC_TIMER:
+ begin
+ next_HCTxPortReq <= 1'b0;
+ if (SOFTimerClr == 1'b1)
+ next_SOFTimer <= 16'h0000;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1;
+ if (SOFEnable == 1'b0)
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ next_SOFTimer <= 16'h0000;
+ end
+ end
+ `SC_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sofCntl <= `WAIT_SEND_RESUME;
+ end
+ end
+ `CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sofCntl <= `INC_TIMER;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sofCntl <= `START_SC;
+ else
+ CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFTimer <= 16'h0000;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v (revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+ busClk, rstSyncToBusClk,
+ usbClk, rstSyncToUsbClk,
+ //sendPacket
+ TxFifoRE, TxFifoData, TxFifoEmpty,
+ //getPacket
+ RxFifoWE, RxFifoData, RxFifoFull,
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //HCTxPortArbiter
+ HCTxPortEn, HCTxPortRdy,
+ HCTxPortData, HCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFSentIntOut,
+ connEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ hostControlSelect
+ );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [3:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+input hostControlSelect;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut;
+wire connEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .SOFSentIntOut(SOFSentIntOut),
+ .connEventIntOut(connEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .TxTransTypeReg(transType),
+ .TxSOFEnableReg(SOFEnable),
+ .TxAddrReg(TxAddr),
+ .TxEndPReg(TxEndP),
+ .frameNumIn(frameNum),
+ .RxPktStatusIn(RxPktStatus),
+ .RxPIDIn(RxPID),
+ .connectStateIn(connectStateOut),
+ .SOFSentIn(SOFSent),
+ .connEventIn(connectionEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .hostControlSelect(hostControlSelect),
+ .clrTransReq(clrTxReq),
+ .preambleEn(preAmbleEnable),
+ .SOFSync(SOFSyncEn),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .transReq(transReq),
+ .isoEn(isoEn),
+ .SOFTimer(SOFTimer)
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus(RxPktStatus),
+ .clearTXReq(clrTxReq),
+ .clk(usbClk),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rstSyncToUsbClk),
+ .sendPacketArbiterGnt(HCTxGnt),
+ .sendPacketArbiterReq(HCTxReq),
+ .sendPacketPID(HC_PID),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(HC_SP_WEn),
+ .transDone(transDone),
+ .transReq(transReq),
+ .transType(transType),
+ .isoEn(isoEn) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl(SOFCntlCntl),
+ .HCTxPortData(SOFCntlData),
+ .HCTxPortGnt(SOFCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(SOFCntlReq),
+ .HCTxPortWEn(SOFCntlWEn),
+ .SOFEnable(SOFEnable),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable(SOFEnable),
+ .SOFSent(SOFSent),
+ .SOFSyncEn(SOFSyncEn),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .sendPacketArbiterGnt(SOFTxGnt),
+ .sendPacketArbiterReq(SOFTxReq),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(SOF_SP_WEn) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt(HCTxGnt),
+ .HCTxReq(HCTxReq),
+ .HC_PID(HC_PID),
+ .HC_SP_WEn(HC_SP_WEn),
+ .SOFTxGnt(SOFTxGnt),
+ .SOFTxReq(SOFTxReq),
+ .SOF_SP_WEn(SOF_SP_WEn),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .sendPacketPID(sendPacketCPPIDIn),
+ .sendPacketWEnable(sendPacketCPWEnIn) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID(sendPacketCPPIDIn),
+ .clk(usbClk),
+ .preAmbleEnable(preAmbleEnable),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCPReady(sendPacketCPReadyOut),
+ .sendPacketCPWEn(sendPacketCPWEnIn),
+ .sendPacketPID(sendPacketCPPIDOut),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl(sendPacketCntl),
+ .HCTxPortData(sendPacketData),
+ .HCTxPortGnt(sendPacketGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(sendPacketReq),
+ .HCTxPortWEn(sendPacketWEn),
+ .PID(sendPacketCPPIDOut),
+ .TxAddr(TxAddr),
+ .TxEndP(TxEndP),
+ .clk(usbClk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .frameNum(frameNum),
+ .rst(rstSyncToUsbClk),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut),
+ .fullSpeedPolarity(fullSpeedPol) );
+
+directControl u_directControl
+ (.HCTxPortCntl(directCntlCntl),
+ .HCTxPortData(directCntlData),
+ .HCTxPortGnt(directCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(directCntlReq),
+ .HCTxPortWEn(directCntlWEn),
+ .clk(usbClk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rstSyncToUsbClk) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl(HCTxPortCtrl),
+ .HCTxPortData(HCTxPortData),
+ .HCTxPortWEnable(HCTxPortEn),
+ .SOFCntlCntl(SOFCntlCntl),
+ .SOFCntlData(SOFCntlData),
+ .SOFCntlGnt(SOFCntlGnt),
+ .SOFCntlReq(SOFCntlReq),
+ .SOFCntlWEn(SOFCntlWEn),
+ .clk(usbClk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+getPacket u_getPacket
+ (.RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXPktStatus(RxPktStatus),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(usbClk),
+ .getPacketEn(getPacketREn),
+ .rst(rstSyncToUsbClk) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .connectionEventOut(connectionEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v (revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
+`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v (revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v (revision 264)
@@ -0,0 +1,447 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input clk;
+input getPacketRdy;
+input isoEn;
+input rst;
+input [7:0]RXStatus;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input transReq;
+input [1:0]transType;
+output clearTXReq;
+output getPacketREn;
+output sendPacketArbiterReq;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output transDone;
+
+reg clearTXReq, next_clearTXReq;
+wire clk;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+wire isoEn;
+wire rst;
+wire [7:0]RXStatus;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg transDone, next_transDone;
+wire transReq;
+wire [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+`define DEL1 6'b100001
+`define DEL2 6'b100010
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+ NextState_hstCntrl <= CurrState_hstCntrl;
+ // Set default values for outputs and signals
+ next_transDone <= transDone;
+ next_clearTXReq <= clearTXReq;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketPID <= sendPacketPID;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_hstCntrl) // synopsys parallel_case full_case
+ `START_HC:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `TX_REQ:
+ begin
+ if (transReq == 1'b1)
+ begin
+ NextState_hstCntrl <= `WAIT_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `CHK_TYPE:
+ begin
+ if (transType == `OUTDATA0_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+ end
+ else if (transType == `IN_TRANS)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+ end
+ else if (transType == `SETUP_TRANS)
+ begin
+ NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+ end
+ else if (transType == `OUTDATA1_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+ end
+ end
+ `FLAG:
+ begin
+ next_transDone <= 1'b1;
+ next_clearTXReq <= 1'b1;
+ next_sendPacketArbiterReq <= 1'b0;
+ NextState_hstCntrl <= `FIN;
+ end
+ `FIN:
+ begin
+ next_clearTXReq <= 1'b0;
+ next_transDone <= 1'b0;
+ //now wait for 'transReq' to clear
+ NextState_hstCntrl <= `DEL1;
+ end
+ `WAIT_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1)
+ begin
+ NextState_hstCntrl <= `CHK_TYPE;
+ end
+ end
+ `DEL1:
+ begin
+ NextState_hstCntrl <= `DEL2;
+ end
+ `DEL2:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `SETUP_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+ end
+ `SETUP_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+ end
+ `SETUP_WAIT_PKT_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `SETUP_HC_WAIT_RDY:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `SETUP;
+ end
+ end
+ `SETUP_WAIT_SETUP_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `SETUP_WAIT_DATA_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_DATA_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+ end
+ end
+ `IN_CHK_FOR_ERROR:
+ begin
+ if (isoEn == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+ RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `IN_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+ end
+ `IN_WAIT_IN_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `IN;
+ end
+ end
+ `IN_WAIT_SP_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `IN_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+ end
+ `IN_WAIT_ACK_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_DATA0_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CHK_ISO;
+ end
+ end
+ `OUT0_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `OUT0_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT0_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+ end
+ `OUT0_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+ end
+ `OUT0_CHK_ISO:
+ begin
+ if (isoEn == 1'b0)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `OUT1_WAIT_DATA1_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT1_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT1_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+ end
+ `OUT1_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_hstCntrl <= `START_HC;
+ else
+ CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ transDone <= 1'b0;
+ clearTXReq <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ transDone <= next_transDone;
+ clearTXReq <= next_clearTXReq;
+ getPacketREn <= next_getPacketREn;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
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+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) \nbegin\n if (muxSOFNotHC == 1'b1) \n begin\n sendPacketWEnable <= SOF_SP_WEn;\n sendPacketPID <= `SOF;\n end\n else\n begin\n sendPacketWEnable <= HC_SP_WEn;\n sendPacketPID <= HC_PID;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
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+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+I 13 6 0 Builtin Reset | 56682,217090
+W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787
+L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 180096,262516 "" ""
+L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 179694,255682 "" ""
+C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst"
+L 20 21 0 TEXT "State Labels" | 104118,144730 1 0 0 "WAIT_SEND_RESUME\n/2/"
+S 21 6 8192 ELLIPSE "States" | 104118,144730 6500 6500
+W 22 6 0 11 50 BEZIER "Transitions" | 102807,168391 103209,163969 153274,157911 158500,157308
+L 23 24 0 TEXT "State Labels" | 107147,54820 1 0 0 "INC_TIMER\n/3/"
+S 24 6 12288 ELLIPSE "States" | 107147,54820 6500 6500
+W 25 6 0 21 62 BEZIER "Transitions" | 104501,138249 108970,126031 113441,113813 117910,101595
+C 26 22 0 TEXT "Conditions" | 109587,169712 1 0 0 "SOFEnable == 1'b1"
+C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1"
+A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;"
+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n SOFTimer <= 16'h0000;\nelse\n SOFTimer <= SOFTimer + 1'b1;"
+W 33 6 0 24 11 BEZIER "Transitions" | 101788,58497 95658,55482 71624,73399 68189,77671\
+ 64755,81944 65727,99405 63767,113072 61807,126740\
+ 62411,169554 65777,180659 69144,191764 82008,193372\
+ 86530,192015 91053,190659 96125,183689 98738,180172
+C 35 33 0 TEXT "Conditions" | 56071,65104 1 0 0 "SOFEnable == 1'b0"
+L 36 37 0 TEXT "Labels" | 26502,239200 1 0 0 "SOFTimer[15:0]"
+I 37 0 130 Builtin OutPort | 20502,239200 "" ""
+L 38 39 0 TEXT "Labels" | 28914,244024 1 0 0 "SOFEnable"
+I 39 0 2 Builtin InPort | 22914,244024 "" ""
+L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy"
+I 41 0 2 Builtin InPort | 84018,239200 "" ""
+I 42 0 2 Builtin OutPort | 81638,244416 "" ""
+L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn"
+I 44 0 130 Builtin OutPort | 81915,250446 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 46 0 130 Builtin OutPort | 81312,256878 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v (revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input directCtrlRate;
+input directCtrlPol;
+input sendPacketRate;
+input sendPacketPol;
+input sendPacketSel;
+output fullSpeedRate;
+output fullSpeedPol;
+
+wire directCtrlRate;
+wire directCtrlPol;
+wire sendPacketRate;
+wire sendPacketPol;
+wire sendPacketSel;
+reg fullSpeedRate;
+reg fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+ if (sendPacketSel == 1'b1)
+ begin
+ fullSpeedRate <= sendPacketRate;
+ fullSpeedPol <= sendPacketPol;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate;
+ fullSpeedPol <= directCtrlPol;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v (revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v (revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+`endif //usbSlaveControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v (revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+ if (fullSpeedPolarity == 1'b1)
+ begin
+ JBit = `ONE_ZERO;
+ KBit = `ZERO_ONE;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE;
+ KBit = `ONE_ZERO;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v (revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn,
+ dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+ forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH:0]bufferInIndex;
+reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg [ADDR_WIDTH:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+ bufferOutIndexSyncToWrClk <= bufferOutIndex;
+ if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+ begin
+ fifoFull <= 1'b0;
+ bufferInIndex <= 0;
+ end
+ else
+ begin
+ if (fifoWEn == 1'b1) begin
+ bufferInIndex <= bufferInIndex + 1'b1;
+ end
+ if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+ (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex)
+ bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+ bufferInIndexSyncToRdClk <= bufferInIndex;
+ if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+ begin
+ fifoEmpty <= 1'b1;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ fifoREnDelayed <= fifoREn;
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ end
+ if (bufferInIndexSyncToRdClk == bufferOutIndex)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+ bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+ bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc (
+ .addrIn(bufferInIndexToMem),
+ .addrOut(bufferOutIndexToMem),
+ .wrClk(wrClk),
+ .rdClk(rdClk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// directControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+ NextState_drctCntl <= CurrState_drctCntl;
+ // Set default values for outputs and signals
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_drctCntl) // synopsys parallel_case full_case
+ `START_DC:
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ next_HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {6'b000000, directControlLineState};
+ next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_HCTxPortReq <= 1'b0;
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_drctCntl <= `START_DC;
+ else
+ CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v (revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hctxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+input [7:0]SOFCntlCntl;
+input [7:0]SOFCntlData;
+input SOFCntlReq;
+input SOFCntlWEn;
+output directCntlGnt;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortWEnable;
+output sendPacketGnt;
+output SOFCntlGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+reg HCTxPortWEnable, next_HCTxPortWEnable;
+wire rst;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [7:0]SOFCntlCntl;
+wire [7:0]SOFCntlData;
+reg SOFCntlGnt, next_SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+ NextState_HCTxArb = CurrState_HCTxArb;
+ // Set default values for outputs and signals
+ next_SOFCntlGnt <= SOFCntlGnt;
+ next_sendPacketGnt <= sendPacketGnt;
+ next_directCntlGnt <= directCntlGnt;
+ next_muxCntl <= muxCntl;
+ case (CurrState_HCTxArb) // synopsys parallel_case full_case
+ `START_HARB:
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ end
+ `WAIT_REQ:
+ begin
+ if (SOFCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_SOF;
+ next_SOFCntlGnt <= 1'b1;
+ next_muxCntl <= `SOF_CTRL_MUX;
+ end
+ else if (sendPacketReq == 1'b1)
+ begin
+ NextState_HCTxArb = `SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxCntl <= `SEND_PACKET_MUX;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb = `DIRECT_CONTROL;
+ next_directCntlGnt <= 1'b1;
+ next_muxCntl <= `DIRECT_CTRL_MUX;
+ end
+ end
+ `SEND_SOF:
+ begin
+ if (SOFCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_SOFCntlGnt <= 1'b0;
+ end
+ end
+ `SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `DIRECT_CONTROL:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb = `WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_HCTxArb = `START_HARB;
+ else
+ CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFCntlGnt = 1'b0;
+ sendPacketGnt = 1'b0;
+ directCntlGnt = 1'b0;
+ muxCntl = 2'b00;
+ end
+ else
+ begin
+ SOFCntlGnt = next_SOFCntlGnt;
+ sendPacketGnt = next_sendPacketGnt;
+ directCntlGnt = next_directCntlGnt;
+ muxCntl = next_muxCntl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf (revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
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+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+ 48213,88528 42471,75064 41184,67490 39897,59917\
+ 40491,43087 47668,36800 54846,30514 82962,22198\
+ 91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+ 200128,135446 205472,144130 205681,151728 205890,159327\
+ 201380,181037 194241,189595 187102,198154 163054,210680\
+ 152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+ 202640,35412 197280,23183 191376,19540 185472,15898\
+ 167213,13552 158043,13342 148873,13133 131482,15160\
+ 122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf (revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+ 94907,51569 61918,50756 52575,52503 43232,54250\
+ 38843,62050 37706,72734 36569,83418 36406,118357\
+ 40062,129609 43718,140862 58507,150938 67687,153172\
+ 76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf (revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
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+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 16 6 0 Builtin Reset | 76112,190530
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
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+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
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+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
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+ 105450,47318 105450,38252 107207,34228 108965,30205\
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+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
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+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
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+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v (revision 264)
@@ -0,0 +1,185 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE,
+ SIEPortCtrlInFromHost,
+ SIEPortCtrlInFromSlave,
+ SIEPortDataInToSIE,
+ SIEPortDataInFromHost,
+ SIEPortDataInFromSlave,
+ SIEPortWEnToSIE,
+ SIEPortWEnFromHost,
+ SIEPortWEnFromSlave,
+ fullSpeedPolarityToSIE,
+ fullSpeedPolarityFromHost,
+ fullSpeedPolarityFromSlave,
+ fullSpeedBitRateToSIE,
+ fullSpeedBitRateFromHost,
+ fullSpeedBitRateFromSlave,
+ dataIn,
+ dataOut,
+ address,
+ writeEn,
+ strobe_i,
+ busClk,
+ usbClk,
+ hostSlaveMuxSel,
+ rstFromWire,
+ rstSyncToBusClkOut,
+ rstSyncToUsbClkOut
+);
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE;
+input [7:0] SIEPortDataInFromHost;
+input [7:0] SIEPortDataInFromSlave;
+output SIEPortWEnToSIE;
+input SIEPortWEnFromHost;
+input SIEPortWEnFromSlave;
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+reg SIEPortWEnToSIE;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClkOut;
+wire rstSyncToUsbClkOut;
+wire rstFromWire;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave)
+begin
+ if (hostMode == 1'b1)
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn(dataIn),
+ .dataOut(dataOut),
+ .address(address),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .hostMode(hostMode),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .rstFromWire(rstFromWire),
+ .rstSyncToBusClkOut(rstSyncToBusClkOut),
+ .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v (revision 264)
@@ -0,0 +1,46 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
+// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
+// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+// speed, and TX resume is always low speed.
+// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
+// in missing receive packets.
+// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+// by adding kludged delay to softranmit. This needs to be fixed properly.
+// This version has undergone limited testing
+// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+// with uClinux, and is known to work with a full speed USB flash stick.
+// Moving Opencores project status from Beta to done.
+// TODO: Test isochronous mode, and low speed mode using uClinux driver
+// Create a seperate clock domain for the bus interface
+// Add frame period adjustment capability
+// Add compilation flags for slave only and host only versions
+// Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+// Removed TX and RX fifo status registers, and removed
+// TX fifo data count register.
+// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+// Fixed slave mode bug which caused receive fifo to be filled with
+// incoming data when the slave was responding with a NAK, and the
+// data should have been discarded.
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h10
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf (revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIETransmitter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 16
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 213
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+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 359
+PAGE 12700,12700 215900,279400
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+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 455
+PAGE 12700,12700 215900,279400
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+GRID=OFF
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+END
+INSTHEADER 465
+PAGE 12700,12700 215900,279400
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+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 474
+PAGE 12700,12700 215900,279400
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+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 483
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 609
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 617
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 626
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 718
+PAGE 12700,12700 215900,279400
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+INSTHEADER 720
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 911
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 958
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1073
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/19/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,209519
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/18/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 124599,219647 "" ""
+I 846 0 130 Builtin InPort | 125108,215006 "" ""
+L 845 846 0 TEXT "Labels" | 131108,215006 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[2:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 118825,194982 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/31/"
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+ 161730,108850 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 144540,155815\
+ 141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+ 43361,99065 46384,95576 54928,94878 63472,94181\
+ 94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+ 104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1; \nresumeCnt <= resumeCnt + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+ 43973,74547 45899,68928 54485,67524 63072,66120\
+ 95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+ 34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+ 41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+ 46299,139871 48829,136075 59202,135063 69575,134052\
+ 106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+ 46931,109511 49715,104703 60024,103501 70334,102300\
+ 108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+ 48196,74723 50474,70169 60657,69030 70840,67892\
+ 108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+ 48829,42592 51359,37532 61605,36267 71852,35002\
+ 109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+ 128857,67252 162473,65260 171997,66691 181521,68123\
+ 186003,75843 187123,97692 188244,119542 188244,199222\
+ 184384,221196 180525,243170 165087,251388 155563,253628\
+ 146039,255869 123379,256617 115100,254625 106821,252633\
+ 98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+ 31250,150650 32250,89650 34750,72525 37250,55400\
+ 46250,47900 56000,46150 65750,44400 95896,46012\
+ 103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+ 124894,217487 107954,214253 97790,213829 87626,213406\
+ 65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf (revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 16
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 24
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 33
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 42
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+UPPERLEFT 0,0
+GRID=OFF
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+END
+INSTHEADER 97
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+END
+INSTHEADER 227
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 99337,112266 6500 6500
+L 19 18 0 TEXT "State Labels" | 99337,112266 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 146563,24238
+W 23 17 0 18 21 BEZIER "Transitions" | 103975,107713 107885,100636 103154,45547 143864,24443
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+ 43038,129670 44914,125650 53423,124511 61932,123372\
+ 93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+ 44646,98582 47594,94562 55902,93624 64210,92686\
+ 94494,92954 102132,93021 109770,93088 110325,93078\
+ 110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+ 45182,65484 49202,63876 57711,63474 66220,63072\
+ 96236,63072 103807,63072 111378,63072 111758,63165\
+ 111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+ 46388,39220 49604,34396 58247,33391 66890,32386\
+ 97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+ 188238,99472 188778,113512 186145,122422 183513,131332\
+ 167904,143587 159264,149864 150624,156142 133542,158851\
+ 125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0; \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 152390,172884 131374,171355 101683,127861 94565,116677
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 72243,162260 51221,151750 45574,140719\
+ 39928,129688 39788,80170 47763,75675 55738,71180\
+ 102436,61038 148189,26024
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+ 151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+ 176540,156388 181096,131196 181431,113977 181766,96758\
+ 182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 5'h0; \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit) //can only be a resume if line remains in Kbit state\n RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n resumeWaitCnt <= resumeWaitCnt + 1'b1; \n //if we've waited long enough, then\n if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n begin \n RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n resumeDetected <= 1'b1; //report resume detected\n end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+ 107061,21822 137747,20482 148467,20415 159187,20348\
+ 171381,21420 174463,22458 177545,23497 178090,26035\
+ 178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+ 145117,36964 157043,31068 161599,29627 166155,28187\
+ 172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n RXSameBitCount <= RXSameBitCount + 1'b1; //inc 'RXSameBitCount'\n if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n bitStuffError <= 1'b1; //flag 'bitStuffError'\n else //else no bit stuffing error\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= { 1'b1, RXByte[7:1]}; //RZ bit = 1 (ie no change in 'RxBits')\n end\nend\nelse //else current 'RxBits' are different from old 'RxBits'\nbegin\n if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= {1'b0, RXByte[7:1]}; //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n end\n RXSameBitCount <= 4'h0; //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf (revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processTxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+END
+OBJECTS
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+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate == 1'b0"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+ 157955,32952 139055,31533 132716,31415 126377,31297\
+ 121929,32154 118701,32626
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+I 1097 1035 0 Builtin Exit | 133008,37611
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+L 1116 1117 0 TEXT "State Labels" | 157607,86664 1 0 0 "W_RDY4\n/28/"
+S 1115 895 131072 ELLIPSE "States" | 152471,133209 6500 6500
+L 1114 1115 0 TEXT "State Labels" | 152471,133209 1 0 0 "W_RDY3\n/27/"
+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
+S 1111 895 122880 ELLIPSE "States" | 129359,218595 6500 6500
+L 1110 1111 0 TEXT "State Labels" | 129359,218595 1 0 0 "W_RDY1\n/25/"
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+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
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+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
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+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
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+I 884 880 0 Builtin Exit | 178131,23271
+I 883 880 0 Builtin Entry | 38120,248040
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
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+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1) //If this bit is 1, then\n TXOneCount <= TXOneCount + 1'b1; //increment 'TXOneCount'\nelse //else this is a zero bit\nbegin\n TXOneCount <= 4'h0; //reset 'TXOneCount'\n if (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\n else \n TXLineState <= JBit;\nend"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
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+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0; //reset 'TXOneCount'\nif (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\nelse \n TXLineState <= JBit;"
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0; \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+ 40522,42856 31562,47464 29098,65320 26634,83176\
+ 25738,149992 26858,168968 27978,187944 33354,197032\
+ 36938,198888 40522,200744 49226,198568 51498,198152\
+ 53770,197736 54409,198230 54473,198230
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+ 113354,23912 154429,23527 174909,23271
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+ 90132,26172 93257,24084 94765,23272
+I 974 895 0 Builtin Exit | 97904,23272
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+I 977 895 0 Builtin Entry | 34452,259216
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+ 30972,218732 29812,212468 29638,189094 29464,165720\
+ 29928,78488 31900,55230 33872,31972 41296,26172\
+ 49358,24664 57420,23156 82353,23388 94765,23272
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+ 41124,121640 36948,124424 36020,132602 35092,140780\
+ 35556,170708 38166,179350 40776,187992 50140,192687\
+ 55128,195007
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+ 104561,139388 153745,139620 168013,138576 182281,137532\
+ 190169,133124 192141,121582 194113,110040 194113,68280\
+ 192025,55114 189937,41948 185529,28723 181353,23271
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit; \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 996 995 0 Builtin Entry | 86360,167640
+I 997 995 0 Builtin Exit | 129540,111760
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 1029 1027 0 Builtin Exit | 129540,111760
+I 1028 1027 0 Builtin Entry | 86360,167640
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+I 1075 1035 0 Builtin Entry | 75208,271435
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v (revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input clk;
+input rst;
+input [1:0]RxWireDataIn;
+input RxWireDataWEn;
+output [1:0]connectState;
+
+wire clk;
+reg [1:0]connectState, next_connectState;
+wire rst;
+wire [1:0]RxWireDataIn;
+wire RxWireDataWEn;
+
+// diagram signals declarations
+reg [1:0]RxBits, next_RxBits;
+reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+ NextState_rcvr <= CurrState_rcvr;
+ // Set default values for outputs and signals
+ next_RXWaitCount <= RXWaitCount;
+ next_connectState <= connectState;
+ next_RXStMachCurrState <= RXStMachCurrState;
+ next_RxBits <= RxBits;
+ case (CurrState_rcvr) // synopsys parallel_case full_case
+ `WAIT_BIT:
+ begin
+ if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+ next_RxBits <= RxWireDataIn;
+ end
+ end
+ `START_SRX:
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_RXWaitCount <= 8'h00;
+ next_connectState <= `DISCONNECT;
+ next_RxBits <= 2'b00;
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `DISCNCT_CHK_RXBITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else if (RxBits == `ONE_ZERO)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ONE_ZERO)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `LS_CONN_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `FS_CONN_CHK_RX_BITS1:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_rcvr <= `START_SRX;
+ else
+ CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ connectState <= `DISCONNECT;
+ RXWaitCount <= 8'h00;
+ RXStMachCurrState <= `DISCONNECT_ST;
+ RxBits <= 2'b00;
+ end
+ else
+ begin
+ connectState <= next_connectState;
+ RXWaitCount <= next_RXWaitCount;
+ RXStMachCurrState <= next_RXStMachCurrState;
+ RxBits <= next_RxBits;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v (revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input processRxDataInWEn;
+input rst;
+input [7:0]RxByteIn;
+input [7:0]RxCtrlIn;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processRxByteRdy;
+output rstCRC;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+output RxDataOutWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+reg processRxByteRdy, next_processRxByteRdy;
+wire processRxDataInWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]RxByteIn;
+wire [7:0]RxCtrlIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+reg RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RxByte, next_RxByte;
+reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg [7:0]RxCtrl, next_RxCtrl;
+reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+ NextState_prRxByte <= CurrState_prRxByte;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte;
+ next_RxCtrl <= RxCtrl;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RxOverflow <= RxOverflow;
+ next_RxTimeOut <= RxTimeOut;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_RxDataOut <= RxDataOut;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOutWEn <= RxDataOutWEn;
+ next_rstCRC <= rstCRC;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_RXDataByteCnt <= RXDataByteCnt;
+ next_processRxByteRdy <= processRxByteRdy;
+ case (CurrState_prRxByte) // synopsys parallel_case full_case
+ `CHK_ST:
+ begin
+ if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+ begin
+ NextState_prRxByte <= `TOKEN_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `HS_BYTE_ST)
+ begin
+ NextState_prRxByte <= `HSHAKE_CHK;
+ end
+ else if (RXByteStMachCurrState == `CHECK_PID_ST)
+ begin
+ NextState_prRxByte <= `CHK_PID_DO_CHK;
+ end
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+ begin
+ NextState_prRxByte <= `CHK_SYNC_DO;
+ end
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+ begin
+ NextState_prRxByte <= `IDLE_CHK_START;
+ end
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+ begin
+ NextState_prRxByte <= `DATA_WAIT_CRC;
+ end
+ end
+ `START_PRBY:
+ begin
+ next_RxByte <= 8'h00;
+ next_RxCtrl <= 8'h00;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxDataOut <= 8'h00;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOutWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_RXDataByteCnt <= 10'h00;
+ next_processRxByteRdy <= 1'b1;
+ NextState_prRxByte <= `WAIT_BYTE;
+ end
+ `WAIT_BYTE:
+ begin
+ if (processRxDataInWEn == 1'b1)
+ begin
+ NextState_prRxByte <= `CHK_ST;
+ next_RxByte <= RxByteIn;
+ next_RxCtrl <= RxCtrlIn;
+ next_processRxByteRdy <= 1'b0;
+ end
+ end
+ `HSHAKE_FIN:
+ begin
+ next_RxDataOutWEn <= 1'b0;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `HSHAKE_CHK:
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN;
+ if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RxDataOutWEn <= 1'b1;
+ end
+ `CHK_PID_DO_CHK:
+ begin
+ if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+ begin
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_processRxByteRdy <= 1'b1;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_RXDataByteCnt <= 0;
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_START;
+ next_RxDataOutWEn <= 1'b1;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `CHK_PID_FIRST_BYTE_PROC:
+ begin
+ next_rstCRC <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ case (RxByte[1:0] )
+ `SPECIAL: //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ `TOKEN: //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ `HANDSHAKE: //Handshake PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_ACKRxed <= 1'b1;
+ 2'b10:
+ next_NAKRxed <= 1'b1;
+ 2'b11:
+ next_stallRxed <= 1'b1;
+ default:
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST;
+ end
+ `DATA: //Data PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_dataSequence <= 1'b0;
+ 2'b10:
+ next_dataSequence <= 1'b1;
+ default:
+ $display ("Invalid DATA PID detected in ProcessRXByte\n");
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_FIN:
+ begin
+ next_CRC16En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC16Result != 16'hb001)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC16En <= 1'b1;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `DATA_FIN;
+ end
+ `DATA_WAIT_CRC:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `DATA_CHK_STRM;
+ end
+ end
+ `TOKEN_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC5Result != 5'h6)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ if (RXDataByteCnt > 10'h2)
+ begin
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `TOKEN_FIN;
+ end
+ `TOKEN_FIN:
+ begin
+ next_CRC5En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `TOKEN_WAIT_CRC:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `TOKEN_CHK_STRM;
+ end
+ end
+ `CHK_SYNC_DO:
+ begin
+ if (RxByte == `SYNC_BYTE)
+ next_RXByteStMachCurrState <= `CHECK_PID_ST;
+ else
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `IDLE_CHK_START:
+ begin
+ if (RxCtrl == `DATA_START)
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxByte <= `START_PRBY;
+ else
+ CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RxDataOut <= 8'h00;
+ RxCtrlOut <= 8'h00;
+ RxDataOutWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ processRxByteRdy <= 1'b1;
+ RxByte <= 8'h00;
+ RxCtrl <= 8'h00;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RxOverflow <= 1'b0;
+ RxTimeOut <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ RXDataByteCnt <= 10'h00;
+ end
+ else
+ begin
+ RxDataOut <= next_RxDataOut;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOutWEn <= next_RxDataOutWEn;
+ rstCRC <= next_rstCRC;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ processRxByteRdy <= next_processRxByteRdy;
+ RxByte <= next_RxByte;
+ RxCtrl <= next_RxCtrl;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RxOverflow <= next_RxOverflow;
+ RxTimeOut <= next_RxTimeOut;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ RXDataByteCnt <= next_RXDataByteCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf (revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIEReceiver\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 235
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 241
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+W 14 6 0 9 11 BEZIER "Transitions" | 53793,212320 54090,208657 54044,202830 54341,199167
+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
+L 10 11 0 TEXT "State Labels" | 54795,192690 1 0 0 "WAIT_BIT\n/4/"
+S 9 6 20480 ELLIPSE "States" | 54004,218793 6500 6500
+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SIEReceiver"
+F 6 0 671089152 228 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14253,12655 205887,234211
+L 7 6 0 TEXT "Labels" | 17253,231211 1 0 0 "rcvr"
+S 23 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 143681,32406 6500 6500
+L 22 23 0 TEXT "State Labels" | 143681,32406 1 0 0 "DISCNCT"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;"
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+I 16 6 0 Builtin Reset | 25106,221421
+H 39 23 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 40 39 12288 ELLIPSE "States" | 64508,213851 6500 6500
+L 41 40 0 TEXT "State Labels" | 64508,213851 1 0 0 "CHK_RXBITS\n/3/"
+I 42 39 0 Builtin Entry | 42918,241791
+I 43 39 0 Builtin Exit | 147281,109121
+W 44 39 0 42 40 BEZIER "Transitions" | 47426,241791 52025,234967 56275,226064 60875,219240
+S 46 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 142838,49983 6500 6500
+L 47 46 0 TEXT "State Labels" | 142838,49983 1 0 0 "WAIT_FS_CONN"
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 50 54 0 Builtin Exit | 145248,94624
+I 51 54 0 Builtin Entry | 86360,167640
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 59 63 0 Builtin Exit | 129540,111760
+I 60 63 0 Builtin Entry | 86360,167640
+L 61 62 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/1/"
+S 62 63 4096 ELLIPSE "States" | 107950,139700 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+I 68 72 0 Builtin Exit | 131860,37310
+I 69 72 0 Builtin Entry | 64536,194920
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+ 57971,146130 62339,145137 65812,144988 69286,144839\
+ 125497,147159 130261,147357
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+ 54597,124090 58369,121813 62636,121465 66904,121118\
+ 125138,124972 131490,125269
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+ 48543,109011 48344,105238 49038,103700 49733,102162\
+ 52773,100254 56507,99743 60241,99232 74292,101683\
+ 79033,101771 83774,101859 131499,104027 132998,104525
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+ 50130,82213 57873,81220 62984,81170 68095,81121\
+ 127305,85134 133657,85531
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+ 52215,60675 60863,63077 65955,63276 71048,63475\
+ 83004,63522 85042,64000 87080,64479 134402,67217\
+ 135100,67416
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+ 42587,49163 46360,45589 52513,44944 58666,44299\
+ 125961,48736 136382,49232
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+ 164206,62109 167707,83613 169507,92702
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+ 41595,29611 48940,28220 55540,28071 62140,27923\
+ 127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+ 22117,178006 22117,149970 33211,139263 44305,128556\
+ 88681,113764 103817,110238 118953,106712 136069,108777\
+ 144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+ 188903,162522 181196,168609 172535,178212 163875,187816\
+ 140506,197413 125270,198727 110035,200042 80303,196085\
+ 61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `LOW_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `FULL_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+W 169 72 0 71 68 BEZIER "Transitions" | 86442,160488 87123,152997 131179,46721 131860,39230
+S 174 81 53248 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/6/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+S 185 90 57344 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/7/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf (revision 264)
@@ -0,0 +1,304 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=455
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\n//now wait for 'transReq' to clear"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+ 170250,145750 137550,145450 128737,144962 119925,144475\
+ 117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+ 110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+ 129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+ 40160,89849 37728,77233 37462,69633 37196,62033\
+ 38564,44249 44378,36953 50192,29657 72080,18257\
+ 79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+ 134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+ 58620,51804 60468,38868 64038,33660 67608,28452\
+ 80040,20556 84492,18330 88944,16104 95212,13380\
+ 97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+ 41567,48930 50502,39578 58559,36864 66617,34151\
+ 89914,32647 97658,32793 105403,32939 113545,36471\
+ 117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+L 445 446 0 TEXT "State Labels" | 91983,29847 1 0 0 "DEL1\n/33/"
+S 446 6 151552 ELLIPSE "States" | 91983,29847 6500 6500
+L 447 448 0 TEXT "State Labels" | 71118,38835 1 0 0 "DEL2\n/34/"
+S 448 6 155648 ELLIPSE "States" | 71118,38835 6500 6500
+W 451 6 0 294 446 BEZIER "Transitions" | 113064,28940 108490,29421 103055,29490 98481,29971
+W 452 6 0 446 448 BEZIER "Transitions" | 86012,32413 83123,33616 79949,35000 77060,36203
+W 454 6 0 448 41 BEZIER "Transitions" | 67046,43901 63355,51524 38215,83856 36770,94047\
+ 35326,104238 36932,129759 42870,138987 48808,148215\
+ 70958,159612 79745,162701 88532,165790 99731,166612\
+ 106231,167093
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input fullSpeedPolarity;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input [3:0]PID;
+input rst;
+input sendPacketWEn;
+input [6:0]TxAddr;
+input [3:0]TxEndP;
+output fifoReadEn;
+output [10:0]frameNum;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+reg [10:0]frameNum, next_frameNum;
+wire fullSpeedPolarity;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire [3:0]PID;
+wire rst;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+wire [6:0]TxAddr;
+wire [3:0]TxEndP;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+ NextState_sndPkt <= CurrState_sndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ next_frameNum <= frameNum;
+ case (CurrState_sndPkt) // synopsys parallel_case full_case
+ `START_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ end
+ `WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_sndPkt <= `SP_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `SP_WAIT_GNT:
+ begin
+ if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+ begin
+ NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+ end
+ else if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_HCTxPortReq <= 1'b0;
+ end
+ `SEND_PID_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= PIDNotPID;
+ next_HCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SEND_PID_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ else if (PID == `SOF)
+ begin
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+ end
+ else if (PID == `OUT ||
+ PID == `IN ||
+ PID == `SETUP)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sndPkt <= `FIN_SP;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY1:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY2:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `OUT_IN_SETUP_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+ end
+ `SEND_SOF_FIN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_frameNum <= frameNum + 1'b1;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `SEND_SOF_WAIT_RDY3:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= frameNum[7:0];
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_WAIT_RDY4:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_FIN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+ end
+ `DATA0_DATA1_READ_FIFO:
+ begin
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= fifoData;
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+ end
+ `DATA0_DATA1_WAIT_READ_FIFO:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `DATA0_DATA1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+ end
+ end
+ `DATA0_DATA1_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `DATA0_DATA1_TERM_BYTE:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `DATA0_DATA1_CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ `DATA0_DATA1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+ end
+ `LS_EOP_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `LS_EOP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+ end
+ end
+ `LS_EOP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sndPkt <= `START_SP;
+ else
+ CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ HCTxPortData <= 8'h00;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ frameNum <= 11'h000;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ frameNum <= next_frameNum;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v (revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketcheckpreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input clk;
+input preAmbleEnable;
+input rst;
+input [3:0]sendPacketCPPID;
+input sendPacketCPWEn;
+input sendPacketRdy;
+output sendPacketCPReady;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+
+wire clk;
+wire preAmbleEnable;
+wire rst;
+wire [3:0]sendPacketCPPID;
+reg sendPacketCPReady, next_sendPacketCPReady;
+wire sendPacketCPWEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+ NextState_sendPktCP <= CurrState_sendPktCP;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ case (CurrState_sendPktCP) // synopsys parallel_case full_case
+ `SPC_WAIT_EN:
+ begin
+ if (sendPacketCPWEn == 1'b1)
+ begin
+ NextState_sendPktCP <= `CHK_PREAM;
+ next_sendPacketCPReady <= 1'b0;
+ end
+ end
+ `START_SPC:
+ begin
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `CHK_PREAM:
+ begin
+ if (preAmbleEnable == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+ end
+ end
+ `READY:
+ begin
+ next_sendPacketCPReady <= 1'b1;
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `PREAM_PKT_SND_PREAM:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `PREAMBLE;
+ NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+ end
+ `PREAM_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+ end
+ end
+ `PREAM_PKT_PREAM_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+ end
+ `PREAM_PKT_SND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+ end
+ `PREAM_PKT_PID_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+ end
+ `PREAM_PKT_WAIT_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+ end
+ end
+ `PREAM_PKT_WAIT_RDY3:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `READY;
+ end
+ end
+ `REG_PKT_SEND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+ end
+ `REG_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `REG_PKT_SEND_PID;
+ end
+ end
+ `REG_PKT_WAIT_RDY:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `READY;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktCP <= `START_SPC;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketCPReady <= 1'b1;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ end
+ else
+ begin
+ sendPacketCPReady <= next_sendPacketCPReady;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// softransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input clk;
+input rst;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn;
+input [15:0]SOFTimer;
+output sendPacketArbiterReq;
+output sendPacketWEn;
+output SOFSent; // single cycle pulse
+output SOFTimerClr; // Single cycle pulse
+
+wire clk;
+wire rst;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+wire SOFEnable;
+reg SOFSent, next_SOFSent;
+wire SOFSyncEn;
+wire [15:0]SOFTimer;
+reg SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+ NextState_SOFTx <= CurrState_SOFTx;
+ // Set default values for outputs and signals
+ next_SOFSent <= SOFSent;
+ next_SOFTimerClr <= SOFTimerClr;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_i <= i;
+ case (CurrState_SOFTx) // synopsys parallel_case full_case
+ `START_STX:
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ `WAIT_SOF_NEAR:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `WAIT_SP_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NOW;
+ end
+ end
+ `WAIT_SOF_NOW:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_sendPacketWEn <= 1'b1;
+ next_SOFTimerClr <= 1'b1;
+ next_SOFSent <= 1'b1;
+ end
+ else if (SOFEnable == 1'b0)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_SOFTimerClr <= 1'b1;
+ end
+ end
+ `SOF_FIN:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ next_SOFTimerClr <= 1'b0;
+ next_SOFSent <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK1;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK1:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK2;
+ next_sendPacketArbiterReq <= 1'b0;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK2:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SOFTx <= `START_STX;
+ else
+ CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFSent <= 1'b0;
+ SOFTimerClr <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketWEn <= 1'b0;
+ i <= 8'h00;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent;
+ SOFTimerClr <= next_SOFTimerClr;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketWEn <= next_sendPacketWEn;
+ i <= next_i;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v (revision 264)
@@ -0,0 +1,125 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+ hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClkOut == 1'b1)
+ hostMode <= 1'b0;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+ hostMode <= dataIn[0];
+ end
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+ rstFromBus <= 1'b1;
+ else
+ rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+ case (address)
+ `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+ `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+ endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
+ rstShift <= 6'b111111;
+ else
+ rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+ rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+ rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v (revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
+`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v (revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input fullSpeedRateIn;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteRdy;
+input rst;
+input [7:0]SIEPortCtrlIn;
+input [7:0]SIEPortDataIn;
+input SIEPortWEn;
+input USBWireGnt;
+input USBWireRdy;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processTxByteWEn;
+output rstCRC;
+output SIEPortTxRdy;
+output [7:0]TxByteOut;
+output [7:0]TxByteOutCtrl;
+output TxByteOutFullSpeedRate;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+wire fullSpeedRateIn;
+wire [1:0]JBit;
+wire [1:0]KBit;
+wire processTxByteRdy;
+reg processTxByteWEn, next_processTxByteWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]SIEPortCtrlIn;
+wire [7:0]SIEPortDataIn;
+reg SIEPortTxRdy, next_SIEPortTxRdy;
+wire SIEPortWEn;
+reg [7:0]TxByteOut, next_TxByteOut;
+reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [2:0]i, next_i;
+reg [15:0]resumeCnt, next_resumeCnt;
+reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+ NextState_SIETx <= CurrState_SIETx;
+ // Set default values for outputs and signals
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_USBWireReq <= USBWireReq;
+ next_processTxByteWEn <= processTxByteWEn;
+ next_rstCRC <= rstCRC;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteOut <= TxByteOut;
+ next_TxByteOutCtrl <= TxByteOutCtrl;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_SIEPortTxRdy <= SIEPortTxRdy;
+ next_SIEPortData <= SIEPortData;
+ next_SIEPortCtrl <= SIEPortCtrl;
+ next_resumeCnt <= resumeCnt;
+ next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+ case (CurrState_SIETx) // synopsys parallel_case full_case
+ `IDLE:
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `START_SIETX:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_TxByteOut <= 8'h00;
+ next_TxByteOutCtrl <= 8'h00;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_SIEPortTxRdy <= 1'b0;
+ next_SIEPortData <= 8'h00;
+ next_SIEPortCtrl <= 8'h00;
+ next_i <= 3'h0;
+ next_resumeCnt <= 16'h0000;
+ next_TxByteOutFullSpeedRate <= 1'b0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `STX_CHK_ST:
+ begin
+ if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ next_TxByteOutFullSpeedRate <= 1'b1;
+ //SOF and PRE always at full speed
+ end
+ else if (SIEPortCtrl == `TX_PACKET_START)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ end
+ else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_IDLE)
+ begin
+ NextState_SIETx <= `IDLE;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ next_resumeCnt <= 16'h0000;
+ next_USBWireFullSpeedRate <= 1'b0;
+ //resume always uses low speed timing
+ end
+ end
+ `STX_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `STX_CHK_ST;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ end
+ `DIR_CTL_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 3'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `DIR_CTL_DELAY;
+ end
+ end
+ `DIR_CTL_WAIT_GNT:
+ begin
+ next_i <= 3'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN;
+ next_USBWireData <= SIEPortData[1:0];
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `DIR_CTL_DELAY:
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ `PKT_ST_CHK_PID:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ if (SIEPortData[1:0] == `TOKEN)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `HANDSHAKE)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `DATA)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `SPECIAL)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+ end
+ end
+ `PKT_ST_WAIT_RDY_PKT:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= `SYNC_BYTE;
+ next_TxByteOutCtrl <= `DATA_START;
+ end
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[7:0];
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[15:8];
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_STOP)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+ end
+ end
+ `PKT_ST_DATA_DATA_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC16En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY:
+ begin
+ next_CRC16En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+ end
+ end
+ `PKT_ST_DATA_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `PKT_ST_HS_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_HS_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_SPCL_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_CRC_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `RES_ST_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (resumeCnt == `HOST_TX_RESUME_TIME)
+ begin
+ NextState_SIETx <= `RES_ST_W_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `RES_ST_DELAY;
+ end
+ end
+ `RES_ST_SND_J_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY4;
+ end
+ `RES_ST_SND_J_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ `RES_ST_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY2;
+ end
+ `RES_ST_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY3;
+ end
+ `RES_ST_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN;
+ next_USBWireData <= KBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ next_resumeCnt <= resumeCnt + 1'b1;
+ end
+ end
+ `RES_ST_DELAY:
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ `RES_ST_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_2;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_WAIT_GNT1:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+ end
+ end
+ `TX_LS_EOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+ end
+ `TX_LS_EOP_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+ end
+ `TX_LS_EOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `TX_LS_EOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_J;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SIETx <= `START_SIETX;
+ else
+ CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ USBWireWEn <= 1'b0;
+ USBWireReq <= 1'b0;
+ processTxByteWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ TxByteOut <= 8'h00;
+ TxByteOutCtrl <= 8'h00;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ SIEPortTxRdy <= 1'b0;
+ TxByteOutFullSpeedRate <= 1'b0;
+ i <= 3'h0;
+ SIEPortData <= 8'h00;
+ SIEPortCtrl <= 8'h00;
+ resumeCnt <= 16'h0000;
+ end
+ else
+ begin
+ USBWireWEn <= next_USBWireWEn;
+ USBWireReq <= next_USBWireReq;
+ processTxByteWEn <= next_processTxByteWEn;
+ rstCRC <= next_rstCRC;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ TxByteOut <= next_TxByteOut;
+ TxByteOutCtrl <= next_TxByteOutCtrl;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ SIEPortTxRdy <= next_SIEPortTxRdy;
+ TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+ i <= next_i;
+ SIEPortData <= next_SIEPortData;
+ SIEPortCtrl <= next_SIEPortCtrl;
+ resumeCnt <= next_resumeCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf (revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processRxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+I 298 0 130 Builtin OutPort | 76848,260279 "" ""
+L 297 298 0 TEXT "Labels" | 82848,260279 1 0 0 "RxDataOut[7:0]"
+A 296 0 1 TEXT "Actions" | 13933,264927 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin \n RxStatus <= \n {1'b0, next_dataSequence, \n next_ACKRxed, \n next_stallRxed, next_NAKRxed, \n next_RxOverflow, \n next_bitStuffError, next_CRCError };\nend"
+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,94696 6500 6500
+I 21 17 0 Builtin Exit | 89220,92674
+I 20 17 0 Builtin Entry | 45216,248076
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,123462 6500 6500
+W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
+L 289 286 0 TEXT "State Labels" | 54701,94283 1 0 0 "FIN\n/11/"
+I 291 50 0 Builtin Exit | 90483,62922
+I 292 50 0 Builtin Entry | 33692,252435
+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC16Result != 16'hb001)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC16En <= 1'b1;\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 308 0 2 Builtin InPort | 78462,232428 "" ""
+L 307 308 0 TEXT "Labels" | 85176,232428 1 0 0 "processRxDataInWEn"
+I 306 0 130 Builtin InPort | 78465,238172 "" ""
+L 305 306 0 TEXT "Labels" | 84465,238172 1 0 0 "RxCtrlIn[7:0]"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+I 38 41 0 Builtin Entry | 30541,258592
+I 37 41 0 Builtin Exit | 85286,98575
+W 36 41 0 38 371 BEZIER "Transitions" | 34704,258592 38731,254357 47806,246433 31745,235718
+L 34 33 0 TEXT "State Labels" | 117500,64680 1 0 0 "TOKEN"
+S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,64680 6500 6500
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
+L 335 336 0 TEXT "Labels" | 175074,243343 1 0 0 "ACKRxed"
+I 334 0 2 Builtin Signal | 172074,247627 "" ""
+L 333 334 0 TEXT "Labels" | 175074,247627 1 0 0 "stallRxed"
+I 332 0 2 Builtin Signal | 171717,252268 "" ""
+L 331 332 0 TEXT "Labels" | 174717,252268 1 0 0 "NAKRxed"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 327 328 0 TEXT "Labels" | 175074,260836 1 0 0 "RxOverflow"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+W 54 6 0 11 42 BEZIER "Transitions" | 41669,169131 42607,140455 43130,70308 44403,54764\
+ 45676,39220 48892,34396 57535,33391 66178,32386\
+ 96662,35330 112340,35732
+W 53 6 0 11 33 BEZIER "Transitions" | 41642,169108 42044,146596 42058,88800 43264,77142\
+ 44470,65484 48490,63876 56999,63474 65508,63072\
+ 95524,63072 103095,63072 110666,63072 111053,63134\
+ 111187,63134
+W 52 6 0 11 24 BEZIER "Transitions" | 41273,169115 41809,155581 41924,114126 42929,106354\
+ 43934,98582 46882,94562 55190,93624 63498,92686\
+ 93782,92954 101420,93021 109058,93088 109445,93150\
+ 109579,93150
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 93136,123615 109216,123347
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+ 162060,109038 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 135270,157360\
+ 132480,162850 129690,168340 122852,170455 118982,171355
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
+C 66 65 0 TEXT "Conditions" | 62843,168563 1 0 0 "processRxDataInWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59763,178747 47927,176730
+W 64 6 0 9 63 BEZIER "Transitions" | 48012,197411 59579,195797 95649,181504 106856,175930
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+ 41868,138924 51896,113272 59871,108777 67846,104282\
+ 74724,97474 86324,92674
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 359 358 0 Builtin Entry | 86360,167640
+I 360 358 0 Builtin Exit | 129540,111760
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC5Result != 5'h6)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n if (RXDataByteCnt > 10'h2) \n begin\n RxOverflow <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n else \n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC5_8Bit <= 1'b1;\n CRC5En <= 1'b1;\n end\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 221 217 0 Builtin Exit | 136710,89055
+I 220 217 0 Builtin Entry | 86360,167640
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 228 224 0 Builtin Exit | 129540,111760
+I 227 224 0 Builtin Entry | 86360,167640
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+I 253 248 0 Builtin Exit | 78564,173120
+I 252 248 0 Builtin Entry | 35384,229000
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n `SPECIAL: //Special PID.\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n `TOKEN: //Token PID\n begin\n RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n RXDataByteCnt <= 0;\n end\n `HANDSHAKE: //Handshake PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n ACKRxed <= 1'b1;\n 2'b10:\n NAKRxed <= 1'b1;\n 2'b11:\n stallRxed <= 1'b1;\n default:\n begin\n $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n end\n endcase\n RXByteStMachCurrState <= `HS_BYTE_ST;\n end\n `DATA: //Data PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n dataSequence <= 1'b0;\n 2'b10:\n dataSequence <= 1'b1;\n default:\n $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n endcase\n RXByteStMachCurrState <= `DATA_BYTE_ST;\n RXDataByteCnt <= 0;\n end\nendcase"
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n RXByteStMachCurrState = `IDLE_BYTE_ST;"
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+ 89364,102368 89220,95212 89220,94846
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+I 259 32 0 Builtin Entry | 66351,233704
+I 260 32 0 Builtin Exit | 110355,78302
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+ 110499,87996 110355,80840 110355,80474
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v (revision 264)
@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive);
+input [1:0] RxBitsIn;
+output RxDataInTick;
+input SIERxRdyIn;
+input clk;
+input fullSpeedRate;
+input rst;
+input TxWireActiveDrive;
+output [1:0] RxBitsOut;
+output SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+
+wire [1:0] RxBitsIn;
+reg RxDataInTick;
+wire SIERxRdyIn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg [1:0] RxBitsOut;
+reg SIERxWEn;
+reg noActivityTimeOut;
+reg RxWireActive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg1;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ RxDataInTick <= 1'b0;
+ RxWireEdgeDetect <= 1'b0;
+ RxWireActiveReg1 <= 1'b0;
+ RxWireActiveReg2 <= 1'b0;
+ end
+ else begin
+ RxWireActiveReg2 <= RxWireActiveReg1; //Delay RxWireActiveReg1 until after i has been reset
+ RxBitsInReg <= RxBitsIn; //sync incoming data to local clock to avoid metastability issues
+ incBufferCnt <= 1'b0; //default value
+ oldRxBitsIn <= RxBitsInReg;
+ if ( (TxWireActiveDrive == 1'b0) && (oldRxBitsIn != RxBitsInReg)) begin //if edge detected then
+ i <= 5'b00000; //reset the counter
+ RxWireEdgeDetect <= 1'b1; // flag receive activity
+ RxWireActiveReg1 <= 1'b1;
+ end
+ else begin
+ i <= i + 1'b1;
+ RxWireEdgeDetect <= 1'b0;
+ end
+ if (noActivityTimeOut == 1'b1)
+ RxWireActiveReg1 <= 1'b0;
+ if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+ begin
+ RxDataInTick <= !RxDataInTick;
+ if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b01 : buffer1 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b10 : buffer2 <= {RxWireActiveReg2, RxBitsInReg};
+ 2'b11 : buffer3 <= {RxWireActiveReg2, RxBitsInReg};
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutIndex <= 2'b00;
+ RxBitsOut <= 2'b00;
+ SIERxWEn <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ else begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_NOT_EMPTY:
+ begin
+ if (bufferCnt != 3'b000)
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+ end
+ `WAIT_SIE_RX_READY:
+ begin
+ if (SIERxRdyIn == 1'b1)
+ begin
+ SIERxWEn <= 1'b1;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+ 2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+ 2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+ 2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+ endcase
+ end
+ end
+ `SIE_RX_WRITE:
+ begin
+ SIERxWEn <= 1'b0;
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ endcase
+ end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+ if (rst) begin
+ timeOutCnt <= 16'h0000;
+ noActivityTimeOut <= 1'b0;
+ end
+ else begin
+ if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1)
+ timeOutCnt <= 16'h0000;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1;
+ if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+ || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+ noActivityTimeOut <= 1'b1;
+ else
+ noActivityTimeOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v (revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input CRC5_8BitIn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [4:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire CRC5_8BitIn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 5'h1f;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0) begin
+ if (CRCEn == 1'b1) begin
+ ready <= 1'b0;
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ if (CRC5_8BitIn == 1'b1) begin
+ loopEnd <= 4'h7;
+ end
+ else begin
+ loopEnd <= 4'h2;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[4:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == loopEnd) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+ 200193,83454 202194,93721 199799,97969 197405,102218\
+ 189371,107780 182843,108050 176316,108321 158239,103840\
+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n TxFSRate <= SIETxFSRate;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n TxFSRate <= prcTxByteFSRate;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v (revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+PAGE 12700,12700 215900,279400
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+END
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+END
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+GRID=OFF
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+END
+OBJECTS
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+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
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+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "SCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
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+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "SCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
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+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v (revision 264)
@@ -0,0 +1,518 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input bitStuffError;
+input clk;
+input CRCError;
+input getPacketRdy;
+input rst;
+input [7:0]RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0]RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input sendPacketRdy;
+input [4:0]USBEndPControlReg;
+input [6:0]USBTgtAddress;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output endPointReadyToGetPkt;
+output [10:0]frameNum;
+output getPacketREn;
+output NAKSent;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output SOFRxed;
+output stallSent;
+output transDone;
+output [3:0]USBEndP;
+output [1:0]USBEndPNakTransTypeReg;
+output [1:0]USBEndPTransTypeReg;
+
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+wire CRCError;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg [10:0]frameNum, next_frameNum;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+reg NAKSent, next_NAKSent;
+wire rst;
+wire [7:0]RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0]RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg SOFRxed, next_SOFRxed;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+reg [3:0]USBEndP, next_USBEndP;
+wire [4:0]USBEndPControlReg;
+reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [7:0]PIDByte, next_PIDByte;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg [6:0]USBAddress, next_USBAddress;
+reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_getPacketREn <= getPacketREn;
+ next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+ next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+ case (CurrState_slvCntrl) // synopsys parallel_case full_case
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ begin
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `PID_ERROR;
+ end
+ end
+ `PID_ERROR:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_RDY:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ end
+ end
+ `SETUP_OUT_CHK:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ end
+ else if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_CHK_RDY:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `IN_RESP_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_RESP_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+ end
+ end
+ `IN_RESP_CHK_ISO:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `START_S1:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `GET_TOKEN_WAIT_CRC:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_ADDR:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_STOP:
+ begin
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ end
+ else if (RxDataWEn == 1'b1)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_CHK_SOF:
+ begin
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ end
+ `GET_TOKEN_CHK_ADDR:
+ begin
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ next_USBEndPControlRegCopy <= USBEndPControlReg;
+ next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+ end
+ else
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ stallSent <= 1'b0;
+ NAKSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ transDone <= 1'b0;
+ clrEPRdy <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ getPacketREn <= 1'b0;
+ endPointReadyToGetPkt <= 1'b0;
+ PIDByte <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ addrEndPTemp <= 8'h00;
+ tempUSBEndPTransTypeReg <= 2'b00;
+ USBAddress <= 7'b0000000;
+ USBEndPControlRegCopy <= 5'b00000;
+ end
+ else
+ begin
+ stallSent <= next_stallSent;
+ NAKSent <= next_NAKSent;
+ SOFRxed <= next_SOFRxed;
+ transDone <= next_transDone;
+ clrEPRdy <= next_clrEPRdy;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ getPacketREn <= next_getPacketREn;
+ endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+ PIDByte <= next_PIDByte;
+ endpCRCTemp <= next_endpCRCTemp;
+ addrEndPTemp <= next_addrEndPTemp;
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ USBAddress <= next_USBAddress;
+ USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/doc/README.txt (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/doc/README.txt (revision 264)
@@ -0,0 +1,37 @@
+USBHostSlave has been successfully compiled using Quartus 4.2
+For some reason I have not been able to use SOPC Builder 4.2 to build the usb SOPC component
+However, SOPC Builder 4.1 generates a usable SOPC component. This may be an error on my part, I need to
+investigate further.
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+
+Release notes:
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
+// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
+// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+// speed, and TX resume is always low speed.
+// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
+// in missing receive packets.
+// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+// by adding kludged delay to softranmit. This needs to be fixed properly.
+// This version has undergone limited testing
+// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+// with uClinux, and is known to work with a full speed USB flash stick.
+// Moving Opencores project status from Beta to done.
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+// Modified RX and TX fifo status registers, and removed TX fifo data count
+// register. Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+// Fixed slave mode bug which caused receive fifo to
+// be filled with incoming data when the slave was
+// responding with a NAK, and the data should have been discarded.
+// TODO: Test isochronous mode, and low speed mode using uClinux driver
+// Add frame period adjustment capability
+// Add compilation flags for slave only and host only versions
+// Create data bus width options beyond 8-bit
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (revision 264)
@@ -0,0 +1,391 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+ clk, rst,
+ //readUSBWireData
+ USBWireDataIn,
+ USBWireDataInTick,
+ //writeUSBWireData
+ USBWireDataOut,
+ USBWireCtrlOut,
+ USBWireDataOutTick,
+ //SIEReceiver
+ connectState,
+ //processRxBit
+ resumeDetected,
+ //processRxByte
+ RxCtrlOut,
+ RxDataOutWEn,
+ RxDataOut,
+ //SIETransmitter
+ SIEPortCtrlIn,
+ SIEPortDataIn,
+ SIEPortTxRdy,
+ SIEPortWEn,
+ //lineControlUpdate
+ fullSpeedPolarity,
+ fullSpeedBitRate,
+ noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut;
+output RxDataOutWEn;
+output [7:0] RxDataOut;
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy;
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut;
+wire RxDataOutWEn;
+wire [7:0] RxDataOut;
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy;
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En;
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En;
+wire [4:0] RxCRC5Result;
+wire RxCRC5_8Bit;
+wire [7:0] RxCRCData;
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En;
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En;
+wire [4:0] TxCRC5Result;
+wire TxCRC5_8Bit;
+wire [7:0] TxCRCData;
+wire TxRstCRC;
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy;
+wire processTxByteWEn;
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity(fullSpeedPolarity),
+ .fullSpeedBitRate(fullSpeedBitRate),
+ .JBit(JBit),
+ .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+ (
+ .RxWireDataIn(RxWireDataFromWireRx),
+ .RxWireDataWEn(RxWireDataWEn),
+ .clk(clk),
+ .connectState(connectState),
+ .rst(rst) );
+
+
+processRxBit u_processRxBit
+ (.JBit(JBit),
+ .KBit(KBit),
+ .RxBitsIn(RxWireDataFromWireRx),
+ .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
+ .clk(clk),
+ .processRxBitRdy(processRxBitRdy),
+ .processRxBitsWEn(RxWireDataWEn),
+ .processRxByteWEn(processRxByteWEn),
+ .resumeDetected(resumeDetected),
+ .rst(rst),
+ .processRxByteRdy(processRxByteRdy),
+ .RxWireActive(RxWireActive)
+ );
+
+processRxByte u_processRxByte
+ (.CRC16En(RxCRC16En),
+ .CRC16Result(RxCRC16Result),
+ .CRC16UpdateRdy(RxCRC16UpdateRdy),
+ .CRC5En(RxCRC5En),
+ .CRC5Result(RxCRC5Result),
+ .CRC5_8Bit(RxCRC5_8Bit),
+ .CRC5UpdateRdy(RxCRC5UpdateRdy),
+ .CRCData(RxCRCData),
+ .RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
+ .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataOut),
+ .clk(clk),
+ .processRxDataInWEn(processRxByteWEn),
+ .rst(rst),
+ .rstCRC(RxRstCRC),
+ .processRxByteRdy(processRxByteRdy) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC5Result),
+ .CRCEn(RxCRC5En),
+ .CRC5_8BitIn(RxCRC5_8Bit),
+ .dataIn(RxCRCData),
+ .ready(RxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC16Result),
+ .CRCEn(RxCRC16En),
+ .dataIn(RxCRCData),
+ .ready(RxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En(TxCRC16En),
+ .CRC16Result(TxCRC16Result),
+ .CRC5En(TxCRC5En),
+ .CRC5Result(TxCRC5Result),
+ .CRC5_8Bit(TxCRC5_8Bit),
+ .CRCData(TxCRCData),
+ .CRC5UpdateRdy(TxCRC5UpdateRdy),
+ .CRC16UpdateRdy(TxCRC16UpdateRdy),
+ .JBit(JBit),
+ .KBit(KBit),
+ .SIEPortCtrlIn(SIEPortCtrlIn),
+ .SIEPortDataIn(SIEPortDataIn),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEn),
+ .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
+ .TxByteOut(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(SIETxCtrl),
+ .USBWireData(SIETxData),
+ .USBWireGnt(SIETxGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(SIETxReq),
+ .USBWireWEn(SIETxWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .rstCRC(TxRstCRC),
+ .USBWireFullSpeedRate(SIEFsRate),
+ .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+ .fullSpeedRateIn(fullSpeedBitRate)
+ );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC5Result),
+ .CRCEn(TxCRC5En),
+ .CRC5_8BitIn(TxCRC5_8Bit),
+ .dataIn(TxCRCData),
+ .ready(TxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC16Result),
+ .CRCEn(TxCRC16En),
+ .dataIn(TxCRCData),
+ .ready(TxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+processTxByte u_processTxByte
+ (.JBit(JBit),
+ .KBit(KBit),
+ .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
+ .TxByteIn(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(prcTxByteCtrl),
+ .USBWireData(prcTxByteData),
+ .USBWireGnt(prcTxByteGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(prcTxByteReq),
+ .USBWireWEn(prcTxByteWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .USBWireFullSpeedRate(prcTxByteFSRate),
+ .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+ );
+
+USBTxWireArbiter u_USBTxWireArbiter
+ (.SIETxCtrl(SIETxCtrl),
+ .SIETxData(SIETxData),
+ .SIETxGnt(SIETxGnt),
+ .SIETxReq(SIETxReq),
+ .SIETxWEn(SIETxWEn),
+ .TxBits(TxBitsFromArbToWire),
+ .TxCtl(TxCtrlFromArbToWire),
+ .USBWireRdyIn(USBWireRdy),
+ .USBWireRdyOut(USBWireReadyFromTxArb),
+ .USBWireWEn(USBWireWEn),
+ .clk(clk),
+ .prcTxByteCtrl(prcTxByteCtrl),
+ .prcTxByteData(prcTxByteData),
+ .prcTxByteGnt(prcTxByteGnt),
+ .prcTxByteReq(prcTxByteReq),
+ .prcTxByteWEn(prcTxByteWEn),
+ .rst(rst),
+ .SIETxFSRate(SIEFsRate),
+ .prcTxByteFSRate(prcTxByteFSRate),
+ .TxFSRate(FSRateFromArbiterToWire)
+ );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn(TxBitsFromArbToWire),
+ .TxBitsOut(USBWireDataOut),
+ .TxDataOutTick(USBWireDataOutTick),
+ .TxCtrlIn(TxCtrlFromArbToWire),
+ .TxCtrlOut(USBWireCtrlOut),
+ .USBWireRdy(USBWireRdy),
+ .USBWireWEn(USBWireWEn),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .fullSpeedRate(FSRateFromArbiterToWire),
+ .clk(clk),
+ .rst(rst)
+ );
+
+
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn(USBWireDataIn),
+ .RxDataInTick(USBWireDataInTick),
+ .RxBitsOut(RxWireDataFromWireRx),
+ .SIERxRdyIn(processRxBitRdy),
+ .SIERxWEn(RxWireDataWEn),
+ .fullSpeedRate(fullSpeedBitRate),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .clk(clk),
+ .rst(rst),
+ .noActivityTimeOut(noActivityTimeOut),
+ .RxWireActive(RxWireActive)
+ );
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v (revision 264)
@@ -0,0 +1,527 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg NAKSentInSTB;
+reg SOFRxedInSTB;
+reg resetEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrEP0ReadySTB;
+reg clrEP1ReadySTB;
+reg clrEP2ReadySTB;
+reg clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB;
+reg fullSpeedRateSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP3StatusRegSTB;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP1TransTypeRegSTB;
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP2TransTypeRegSTB;
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP3TransTypeRegSTB;
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [10:0] frameNumSTB;
+
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0IsoEn <= 1'b0;
+ EP0SendStall <= 1'b0;
+ EP0DataSequence <= 1'b0;
+ EP0Enable <= 1'b0;
+ EP1IsoEn <= 1'b0;
+ EP1SendStall <= 1'b0;
+ EP1DataSequence <= 1'b0;
+ EP1Enable <= 1'b0;
+ EP2IsoEn <= 1'b0;
+ EP2SendStall <= 1'b0;
+ EP2DataSequence <= 1'b0;
+ EP2Enable <= 1'b0;
+ EP3IsoEn <= 1'b0;
+ EP3SendStall <= 1'b0;
+ EP3DataSequence <= 1'b0;
+ EP3Enable <= 1'b0;
+ SCControlReg <= 6'h00;
+ SCAddrReg <= 7'h00;
+ interruptMaskReg <= 5'h00;
+ end
+ else begin
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP1_CTRL_REG : begin
+ EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP2_CTRL_REG : begin
+ EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP3_CTRL_REG : begin
+ EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+ clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+ clrResetReq <= dataIn[`RESET_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ NAKSentInt <= 1'b0;
+ SOFRxedInt <= 1'b0;
+ resetEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (NAKSentInSTB == 1'b1)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedInSTB == 1'b1)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventInSTB == 1'b1)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntInSTB == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneInSTB == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0Ready <= 1'b0;
+ EP1Ready <= 1'b0;
+ EP2Ready <= 1'b0;
+ EP3Ready <= 1'b0;
+ end
+ else begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0ReadySTB == 1'b1)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1ReadySTB == 1'b1)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2ReadySTB == 1'b1)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3ReadySTB == 1'b1)
+ EP3Ready <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
+begin
+ endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+// async read mux
+// FIX ME
+// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
+// some translation bug
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
+ endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
+ endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or
+ endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNumSTB)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+ `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+ `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+ `EP1_STS_REG : dataOut <= EP1StatusRegSTB;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+ `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+ `EP2_STS_REG : dataOut <= EP2StatusRegSTB;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+ `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+ `EP3_STS_REG : dataOut <= EP3StatusRegSTB;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+ `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+//re-sync from busClk to usbClk.
+always @(posedge usbClk) begin
+ endP0ControlReg <= endP0ControlRegSTB;
+ endP1ControlReg <= endP1ControlRegSTB;
+ endP2ControlReg <= endP2ControlRegSTB;
+ endP3ControlReg <= endP3ControlRegSTB;
+ SCGlobalEn <= SCGlobalEnSTB;
+ TxLineState <= TxLineStateSTB;
+ LineDirectControlEn <= LineDirectControlEnSTB;
+ fullSpeedPol <= fullSpeedPolSTB;
+ fullSpeedRate <= fullSpeedRateSTB;
+end
+
+//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+ NAKSentInSTB <= NAKSentIn;
+ SOFRxedInSTB <= SOFRxedIn;
+ resetEventInSTB <= resetEventIn;
+ resumeIntInSTB <= resumeIntIn;
+ transDoneInSTB <= transDoneIn;
+ clrEP0ReadySTB <= clrEP0Ready;
+ clrEP1ReadySTB <= clrEP1Ready;
+ clrEP2ReadySTB <= clrEP2Ready;
+ clrEP3ReadySTB <= clrEP3Ready;
+ EP0StatusRegSTB <= EP0StatusReg;
+ EP1StatusRegSTB <= EP1StatusReg;
+ EP2StatusRegSTB <= EP2StatusReg;
+ EP3StatusRegSTB <= EP3StatusReg;
+ endP0TransTypeRegSTB <= endP0TransTypeReg;
+ endP1TransTypeRegSTB <= endP1TransTypeReg;
+ endP2TransTypeRegSTB <= endP2TransTypeReg;
+ endP3TransTypeRegSTB <= endP3TransTypeReg;
+ endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
+ endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
+ endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
+ endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
+ frameNumSTB <= frameNum;
+end
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v (revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input SCTxPortRdyIn;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output directCntlGnt;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output sendPacketGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ:
+ begin
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ end
+ `SARB_SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `SARB_DC:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxDCEn <= 1'b0;
+ end
+ else
+ begin
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxDCEn <= next_muxDCEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v (revision 264)
@@ -0,0 +1,383 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input clk;
+input endPointReady;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output ACKRxed;
+output bitStuffError;
+output CRCError;
+output dataSequence;
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output [3:0]RxPID;
+output RXTimeOut;
+
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+wire endPointReady;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+wire [7:0]RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+wire SIERxTimeOut;
+
+// diagram signals declarations
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (endPointReady == 1'b0)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+ end
+ else if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ `PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXOverflow <= 1'b0;
+ ACKRxed <= 1'b0;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXTimeOut <= 1'b0;
+ RxPID <= 4'h0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByteOld <= 8'h00;
+ end
+ else
+ begin
+ RXOverflow <= next_RXOverflow;
+ ACKRxed <= next_ACKRxed;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXTimeOut <= next_RXTimeOut;
+ RxPID <= next_RxPID;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ RXByteOld <= next_RXByteOld;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf (revision 264)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 376
+PAGE 25400,0 215900,279400
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+PAGE 25400,0 215900,279400
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+INSTHEADER 551
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 580
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 617
+PAGE 25400,0 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 698
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+INSTHEADER 15
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 800
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 820
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 102610,273136 1 0 0 "Module: slavecontroller"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+S 15 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+ 192923,24221 173766,19421 163644,19865 153522,20309\
+ 122483,20608 111915,23020 101347,25432 81761,37919\
+ 69710,37919
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+ 30330,86104 25492,143212 35905,156667 46318,170122\
+ 96612,168665 117496,167729
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+L 819 820 0 TEXT "State Labels" | 67420,66064 1 0 0 "RESP"
+S 820 589 102404 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 67420,66064 6500 6500
+H 821 820 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 828 821 2 847 833 BEZIER "Transitions" | 143788,176826 110094,161523 73824,121282 61589,104841
+A 829 828 16 TEXT "Actions" | 74668,133998 1 0 0 "getPacketREn <= 1'b1;"
+W 830 821 1 847 832 BEZIER "Transitions" | 149052,177611 172803,163396 180803,116530 192775,92880
+C 831 830 0 TEXT "Conditions" | 112905,152704 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+I 832 821 0 Builtin Exit | 195662,92880
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+I 862 0 2 Builtin OutPort | 120122,261308 "" ""
+L 861 862 0 TEXT "Labels" | 126122,261308 1 0 0 "endPointReadyToGetPkt"
+A 860 457 16 TEXT "Actions" | 93778,19821 1 0 0 "USBEndPControlRegCopy <= USBEndPControlReg;\nendPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT] ;"
+I 859 0 130 Builtin Signal | 35412,208838 "" ""
+L 858 859 0 TEXT "Labels" | 38412,208838 1 0 0 "USBEndPControlRegCopy[4:0]"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 205195,243792
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 850 821 0 Builtin Entry | 49920,240120
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+ 187314,234737 186141,226528 176133,223346 166125,220164\
+ 127582,215026 108152,212765
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+ 41052,159480 41752,153900 40959,141711 40167,129522\
+ 46701,89176 50135,78506 53570,67837 54978,65340\
+ 57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+ 162008,130636 151291,117855 140238,106874 129185,95894\
+ 77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+ 209214,43082 209522,23062 208983,17094 208444,11127\
+ 205980,7277 191773,6353 177567,5429 123205,5583\
+ 106804,9317 90403,13052 79161,27836 75696,31763\
+ 72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+ 53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+ 60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 122196,51478 1 0 0 "Insert delay to allow USBEndP etc to update"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+ 197587,175015 201929,162657 202973,147251 204017,131846\
+ 203849,82580 202847,68719 201846,54859 198970,48147\
+ 197050,45058
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 69699,59883 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 803 805 0 Builtin Exit | 144780,101600
+I 804 805 0 Builtin Entry | 96520,152400
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+ 33432,172010 34721,79558 53522,54375 72324,29193\
+ 153226,30396 173104,33029 192983,35662 193169,40577\
+ 192962,43440
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v (revision 264)
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlaveWrap.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+ clk,
+ reset,
+ address,
+ writedata,
+ readdata,
+ write,
+ read,
+ waitrequest,
+ chipselect,
+ irq,
+ usbClk,
+ USBWireVPI,
+ USBWireVMI,
+ USBWireDataInTick,
+ USBWireVPO,
+ USBWireVMO,
+ USBWireDataOutTick,
+ USBWireOutEn_n,
+ USBFullSpeed
+ );
+
+input clk;
+input reset;
+input [7:0] address;
+input [7:0] writedata;
+output [7:0] readdata;
+input write;
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input usbClk;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address;
+wire [7:0] writedata;
+wire [7:0] readdata;
+wire write;
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire usbClk;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+ hostResumeIntOut | hostTransDoneIntOut |
+ slaveSOFRxedIntOut | slaveResetEventIntOut |
+ slaveResumeIntOut | slaveTransDoneIntOut |
+ slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut;
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration:
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+ .clk_i(clk),
+ .rst_i(reset),
+ .address_i(address),
+ .data_i(writedata),
+ .data_o(readdata),
+ .we_i(write),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .usbClk(usbClk),
+ .hostSOFSentIntOut(hostSOFSentIntOut),
+ .hostConnEventIntOut(hostConnEventIntOut),
+ .hostResumeIntOut(hostResumeIntOut),
+ .hostTransDoneIntOut(hostTransDoneIntOut),
+ .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+ .slaveResetEventIntOut(slaveResetEventIntOut),
+ .slaveResumeIntOut(slaveResumeIntOut),
+ .slaveTransDoneIntOut(slaveTransDoneIntOut),
+ .slaveNAKSentIntOut(slaveNAKSentIntOut),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v (revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processrxbit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processRxBitsWEn;
+input processRxByteRdy;
+input rst;
+input [1:0]RxBitsIn;
+input RxWireActive;
+output processRxBitRdy;
+output processRxByteWEn;
+output resumeDetected;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processRxBitRdy, next_processRxBitRdy;
+wire processRxBitsWEn;
+wire processRxByteRdy;
+reg processRxByteWEn, next_processRxByteWEn;
+reg resumeDetected, next_resumeDetected;
+wire rst;
+wire [1:0]RxBitsIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+wire RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg [1:0]oldRXBits, next_oldRXBits;
+reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg [3:0]RXBitCount, next_RXBitCount;
+reg [1:0]RxBits, next_RxBits;
+reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg [7:0]RXByte, next_RXByte;
+reg [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+ NextState_prRxBit <= CurrState_prRxBit;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOut <= RxDataOut;
+ next_resumeDetected <= resumeDetected;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState;
+ next_RxBits <= RxBits;
+ next_RXSameBitCount <= RXSameBitCount;
+ next_RXBitCount <= RXBitCount;
+ next_oldRXBits <= oldRXBits;
+ next_RXByte <= RXByte;
+ next_bitStuffError <= bitStuffError;
+ next_resumeWaitCnt <= resumeWaitCnt;
+ next_processRxBitRdy <= processRxBitRdy;
+ case (CurrState_prRxBit) // synopsys parallel_case full_case
+ `START:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOut <= 8'h00;
+ next_resumeDetected <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_RxBits <= 2'b00;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h0;
+ next_oldRXBits <= 2'b00;
+ next_RXByte <= 8'h00;
+ next_bitStuffError <= 1'b0;
+ next_resumeWaitCnt <= 5'h0;
+ next_processRxBitRdy <= 1'b1;
+ NextState_prRxBit <= `WAIT_BITS;
+ end
+ `WAIT_BITS:
+ begin
+ if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ end
+ `IDLE_FIRST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h1;
+ next_oldRXBits <= RxBits;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `IDLE_CHK_KBIT:
+ begin
+ if ((RxBits == KBit) && (RxWireActive == 1'b1))
+ begin
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `IDLE_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START;
+ //start of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_LAST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_CHK_SE0:
+ begin
+ next_bitStuffError <= 1'b0;
+ if (RxBits == `SE0)
+ begin
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+ if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+ next_bitStuffError <= 1'b1;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1, RXByte[7:1]};
+ //RZ bit <= 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0, RXByte[7:1]};
+ //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h0;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP;
+ //end of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_DATA_DESTUFF:
+ begin
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+ end
+ else if (bitStuffError == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `DATA_RX_BYTE_SEND2:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_BYTE_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+ next_RXBitCount <= 4'h0;
+ next_RxDataOut <= RXByte;
+ next_RxCtrlOut <= `DATA_STREAM;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_ERROR_CHK_RES:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ if (RxBits == JBit) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+ //check for resume
+ next_resumeWaitCnt <= 5'h0;
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_ERROR_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `RES_RX_CHK:
+ begin
+ if (RxBits != KBit) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+ next_resumeDetected <= 1'b1;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `RES_END_CHK1:
+ begin
+ if (RxBits != KBit) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_resumeDetected <= 1'b0;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxBit <= `START;
+ else
+ CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processRxByteWEn <= 1'b0;
+ RxCtrlOut <= 8'h00;
+ RxDataOut <= 8'h00;
+ resumeDetected <= 1'b0;
+ processRxBitRdy <= 1'b1;
+ RXBitStMachCurrState <= `IDLE_BIT_ST;
+ RxBits <= 2'b00;
+ RXSameBitCount <= 4'h0;
+ RXBitCount <= 4'h0;
+ oldRXBits <= 2'b00;
+ RXByte <= 8'h00;
+ bitStuffError <= 1'b0;
+ resumeWaitCnt <= 5'h0;
+ end
+ else
+ begin
+ processRxByteWEn <= next_processRxByteWEn;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOut <= next_RxDataOut;
+ resumeDetected <= next_resumeDetected;
+ processRxBitRdy <= next_processRxBitRdy;
+ RXBitStMachCurrState <= next_RXBitStMachCurrState;
+ RxBits <= next_RxBits;
+ RXSameBitCount <= next_RXSameBitCount;
+ RXBitCount <= next_RXBitCount;
+ oldRXBits <= next_oldRXBits;
+ RXByte <= next_RXByte;
+ bitStuffError <= next_bitStuffError;
+ resumeWaitCnt <= next_resumeWaitCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v (revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteWEn;
+input rst;
+input [7:0]TxByteCtrlIn;
+input TxByteFullSpeedRateIn;
+input [7:0]TxByteIn;
+input USBWireGnt;
+input USBWireRdy;
+output processTxByteRdy;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processTxByteRdy, next_processTxByteRdy;
+wire processTxByteWEn;
+wire rst;
+wire [7:0]TxByteCtrlIn;
+wire TxByteFullSpeedRateIn;
+wire [7:0]TxByteIn;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [3:0]i, next_i;
+reg [7:0]TxByte, next_TxByte;
+reg [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg [1:0]TXLineState, next_TXLineState;
+reg [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+ NextState_prcTxB <= CurrState_prcTxB;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_USBWireReq <= USBWireReq;
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_TxByte <= TxByte;
+ next_TxByteCtrl <= TxByteCtrl;
+ next_TXLineState <= TXLineState;
+ next_TXOneCount <= TXOneCount;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+ case (CurrState_prcTxB) // synopsys parallel_case full_case
+ `START_PTBY:
+ begin
+ next_processTxByteRdy <= 1'b0;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_i <= 4'h0;
+ next_TxByte <= 8'h00;
+ next_TxByteCtrl <= 8'h00;
+ next_TXLineState <= 2'b0;
+ next_TXOneCount <= 4'h0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ next_TxByteFullSpeedRate <= 1'b0;
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `PTBY_WAIT_EN:
+ begin
+ next_processTxByteRdy <= 1'b1;
+ if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_TXOneCount <= 4'h0;
+ next_TXLineState <= JBit;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (processTxByteWEn == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_i <= 4'h0;
+ end
+ end
+ `PTBY_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_WIRE;
+ end
+ end
+ `WAIT_RDY_WIRE:
+ begin
+ if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE1;
+ end
+ else if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_PKT;
+ //actively drive the first J bit
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `WAIT_RDY_PKT:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `SEND_BYTE_UPDATE_BYTE:
+ begin
+ next_i <= i + 1'b1;
+ next_TxByte <= {1'b0, TxByte[7:1] };
+ if (TxByte[0] == 1'b1) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+ end
+ `SEND_BYTE_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+ end
+ else if (i != 4'h8)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ else
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ end
+ `SEND_BYTE_BIT_STUFF:
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+ end
+ `SEND_BYTE_WAIT_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == 4'h8)
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ else
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ end
+ `STOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY2;
+ end
+ `STOP_SND_SE0_1:
+ begin
+ NextState_prcTxB <= `STOP_W_RDY1;
+ end
+ `STOP_CHK:
+ begin
+ if (TxByteCtrl == `DATA_STOP)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_1;
+ end
+ else
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ end
+ `STOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY3;
+ end
+ `STOP_SND_IDLE:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY4;
+ end
+ `STOP_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `STOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_J;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY2;
+ end
+ `LS_START_SND_J1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY3;
+ end
+ `LS_START_SND_IDLE1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY1;
+ end
+ `LS_START_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `LS_START_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE3;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_J1;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_FIN;
+ //Drive the first JBit
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prcTxB <= `START_PTBY;
+ else
+ CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processTxByteRdy <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ USBWireReq <= 1'b0;
+ USBWireWEn <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ i <= 4'h0;
+ TxByte <= 8'h00;
+ TxByteCtrl <= 8'h00;
+ TXLineState <= 2'b0;
+ TXOneCount <= 4'h0;
+ TxByteFullSpeedRate <= 1'b0;
+ end
+ else
+ begin
+ processTxByteRdy <= next_processTxByteRdy;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ USBWireReq <= next_USBWireReq;
+ USBWireWEn <= next_USBWireWEn;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ i <= next_i;
+ TxByte <= next_TxByte;
+ TxByteCtrl <= next_TxByteCtrl;
+ TXLineState <= next_TXLineState;
+ TXOneCount <= next_TXOneCount;
+ TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v (revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [15:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [15:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 16'hffff;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0)
+ begin
+ if (CRCEn == 1'b1) begin
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ ready <= 1'b0;
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[15:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == 4'h7)
+ begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v (revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbTxWireArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input clk;
+input prcTxByteCtrl;
+input [1:0]prcTxByteData;
+input prcTxByteFSRate;
+input prcTxByteReq;
+input prcTxByteWEn;
+input rst;
+input SIETxCtrl;
+input [1:0]SIETxData;
+input SIETxFSRate;
+input SIETxReq;
+input SIETxWEn;
+input USBWireRdyIn;
+output prcTxByteGnt;
+output SIETxGnt;
+output [1:0]TxBits;
+output TxCtl;
+output TxFSRate;
+output USBWireRdyOut;
+output USBWireWEn;
+
+wire clk;
+wire prcTxByteCtrl;
+wire [1:0]prcTxByteData;
+wire prcTxByteFSRate;
+reg prcTxByteGnt, next_prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire rst;
+wire SIETxCtrl;
+wire [1:0]SIETxData;
+wire SIETxFSRate;
+reg SIETxGnt, next_SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+reg [1:0]TxBits, next_TxBits;
+reg TxCtl, next_TxCtl;
+reg TxFSRate, next_TxFSRate;
+wire USBWireRdyIn;
+reg USBWireRdyOut, next_USBWireRdyOut;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+ NextState_txWireArb <= CurrState_txWireArb;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt;
+ next_SIETxGnt <= SIETxGnt;
+ next_muxSIENotPTXB <= muxSIENotPTXB;
+ case (CurrState_txWireArb) // synopsys parallel_case full_case
+ `START_TARB:
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ end
+ `TARB_WAIT_REQ:
+ begin
+ if (prcTxByteReq == 1'b1)
+ begin
+ NextState_txWireArb <= `PTXB_ACT;
+ next_prcTxByteGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b0;
+ end
+ else if (SIETxReq == 1'b1)
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT;
+ next_SIETxGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b1;
+ end
+ end
+ `PTXB_ACT:
+ begin
+ if (prcTxByteReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_prcTxByteGnt <= 1'b0;
+ end
+ end
+ `SIE_TX_ACT:
+ begin
+ if (SIETxReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_SIETxGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_txWireArb <= `START_TARB;
+ else
+ CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ prcTxByteGnt <= 1'b0;
+ SIETxGnt <= 1'b0;
+ muxSIENotPTXB <= 1'b0;
+ end
+ else
+ begin
+ prcTxByteGnt <= next_prcTxByteGnt;
+ SIETxGnt <= next_SIETxGnt;
+ muxSIENotPTXB <= next_muxSIENotPTXB;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v (revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v (revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+ `START_SDC:
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf (revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
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+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v (revision 264)
@@ -0,0 +1,507 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(usbClk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rstSyncToUsbClk),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone),
+ .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+
+endpMux u_endpMux (
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(usbClk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rstSyncToUsbClk),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(usbClk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rstSyncToUsbClk) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(usbClk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .clk(usbClk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rstSyncToUsbClk),
+ .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ rstSyncToUsbClk,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input rstSyncToUsbClk;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty; //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .wrClk(usbClk),
+ .rdClk(busClk),
+ .rstSyncToWrClk(rstSyncToUsbClk),
+ .rstSyncToRdClk(rstSyncToBusClk),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmptySyncToWrClk(forceEmptySyncToUsbClk),
+ .forceEmptySyncToRdClk(forceEmptySyncToBusClk),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v (revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dpMem_dc.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+ dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+ if (writeEn == 1'b1)
+ buffer[addrIn] <= dataIn;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+ 171826,160150 159742,169266 150997,171704 142252,174142\
+ 120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf (revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+ 288786,359372 287077,371461 282417,376909 277757,382357\
+ 274547,381487 268775,381564 263003,381642 254872,381366\
+ 248267,378971 241663,376577 234289,371557 230118,369008
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+ 166944,348155 168507,364217 173450,370590 178394,376963\
+ 186275,384997 193806,383684 201338,382371 213515,373400\
+ 220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+ 259846,282068 289467,282068 298484,284234 307501,286400\
+ 313949,295065 315460,307759 316972,320453 316568,362568\
+ 311430,375060 306292,387553 286404,388600 275724,388298\
+ 265045,387996 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v (revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn,
+ TxBitsOut,
+ TxDataOutTick,
+ TxCtrlIn,
+ TxCtrlOut,
+ USBWireRdy,
+ USBWireWEn,
+ TxWireActiveDrive,
+ fullSpeedRate,
+ clk,
+ rst
+ );
+
+input [1:0] TxBitsIn;
+input TxCtrlIn;
+input USBWireWEn;
+input clk;
+input fullSpeedRate;
+input rst;
+output [1:0] TxBitsOut;
+output TxDataOutTick;
+output TxCtrlOut;
+output USBWireRdy;
+output TxWireActiveDrive;
+
+wire [1:0] TxBitsIn;
+reg [1:0] TxBitsOut;
+reg TxDataOutTick;
+wire TxCtrlIn;
+reg TxCtrlOut;
+reg USBWireRdy;
+wire USBWireWEn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg TxWireActiveDrive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk) begin
+ if (rst == 1'b1) begin
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ USBWireRdy <= 1'b0;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ else begin
+ case (bufferInStMachCurrState)
+ `WAIT_BUFFER_NOT_FULL:
+ begin
+ if (bufferCnt != `BUFFER_FULL)
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ end
+ `WAIT_WRITE_REQ:
+ begin
+ if (USBWireWEn == 1'b1)
+ begin
+ incBufferCnt <= 1'b1;
+ USBWireRdy <= 1'b0;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+ 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+ 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+ 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+ end
+ end
+ `CLR_INC_BUFFER_CNT:
+ begin
+ incBufferCnt <= 1'b0;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ fullSpeedTick <= 1'b0;
+ lowSpeedTick <= 1'b0;
+ end
+ else
+ begin
+ i <= i + 1'b1;
+ if (i[1:0] == 2'b00)
+ fullSpeedTick <= 1'b1;
+ else
+ fullSpeedTick <= 1'b0;
+ if (i == 5'b00000)
+ lowSpeedTick <= 1'b1;
+ else
+ lowSpeedTick <= 1'b0;
+ end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferOutIndex <= 2'b00;
+ decBufferCnt <= 1'b0;
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ TxDataOutTick <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState)
+ `WAIT_LINE_WRITE:
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+ begin
+ TxDataOutTick <= !TxDataOutTick;
+ if (bufferCnt == 0) begin
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ end
+ else begin
+ bufferOutStMachCurrState <= `LINE_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0[2:1];
+ TxCtrlOut <= buffer0[0];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1[2:1];
+ TxCtrlOut <= buffer1[0];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2[2:1];
+ TxCtrlOut <= buffer2[0];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3[2:1];
+ TxCtrlOut <= buffer3[0];
+ end
+ endcase
+ end
+ end
+ end
+ `LINE_WRITE:
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ endcase
+ end
+end
+
+// control 'TxWireActiveDrive'
+always @(TxCtrlOut)
+begin
+ if (TxCtrlOut == `DRIVE)
+ TxWireActiveDrive <= 1'b1;
+ else
+ TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf (revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+ 288786,359372 287077,371461 282417,376909 277757,382357\
+ 274547,381487 268775,381564 263003,381642 254872,381366\
+ 248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210185,391478 219470,393186
+I 16 6 0 Builtin Reset | 178237,395710
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
+I 41 0 3 Builtin InPort | 190061,536582 "" ""
+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
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+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut = SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "SCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
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+ 259846,282068 289467,282068 298484,284234 307501,286400\
+ 313949,295065 315460,307759 316972,320453 316568,362568\
+ 311430,375060 306292,387553 286142,395412 275462,395110\
+ 264783,394808 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf (revision 264)
@@ -0,0 +1,290 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=292
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+END
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+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
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+S 287 120 94208 ELLIPSE "States" | 167860,243800 6500 6500
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+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
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+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
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+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
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+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v (revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveSendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input [3:0]PID;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+input sendPacketWEn;
+output fifoReadEn;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+wire [3:0]PID;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+ NextState_slvSndPkt <= CurrState_slvSndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+ `START_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ end
+ `SP_WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP1_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `SP1_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP1:
+ begin
+ NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_SCTxPortReq <= 1'b0;
+ end
+ `SP_NOT_DATA:
+ begin
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_SEND_PID_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= PIDNotPID;
+ next_SCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SP_SEND_PID_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_NOT_DATA;
+ end
+ end
+ `SP_D0_D1_READ_FIFO:
+ begin
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= fifoData;
+ next_SCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+ end
+ `SP_D0_D1_WAIT_READ_FIFO:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `SP_D0_D1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+ end
+ end
+ `SP_D0_D1_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `FIN_SP1;
+ end
+ `SP_D0_D1_TERM_BYTE:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvSndPkt <= `SP_D0_D1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `SP_D0_D1_CLR_WEN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+ end
+ `SP_D0_D1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvSndPkt <= `START_SP1;
+ else
+ CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ SCTxPortData <= 8'h00;
+ SCTxPortCntl <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v (revision 264)
@@ -0,0 +1,549 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlave.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+ clk_i,
+ rst_i,
+ address_i,
+ data_i,
+ data_o,
+ we_i,
+ strobe_i,
+ ack_o,
+ usbClk,
+ hostSOFSentIntOut,
+ hostConnEventIntOut,
+ hostResumeIntOut,
+ hostTransDoneIntOut,
+ slaveNAKSentIntOut,
+ slaveSOFRxedIntOut,
+ slaveResetEventIntOut,
+ slaveResumeIntOut,
+ slaveTransDoneIntOut,
+ USBWireDataIn,
+ USBWireDataInTick,
+ USBWireDataOut,
+ USBWireDataOutTick,
+ USBWireCtrlOut,
+ USBFullSpeed
+ );
+ parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+ parameter HOST_FIFO_ADDR_WIDTH = 6;
+ parameter EP0_FIFO_DEPTH = 64;
+ parameter EP0_FIFO_ADDR_WIDTH = 6;
+ parameter EP1_FIFO_DEPTH = 64;
+ parameter EP1_FIFO_ADDR_WIDTH = 6;
+ parameter EP2_FIFO_DEPTH = 64;
+ parameter EP2_FIFO_ADDR_WIDTH = 6;
+ parameter EP3_FIFO_DEPTH = 64;
+ parameter EP3_FIFO_ADDR_WIDTH = 6;
+
+input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i; //Wishbone bus address in
+input [7:0] data_i; //Wishbone bus data in
+output [7:0] data_o; //Wishbone bus data out
+input we_i; //Wishbone bus write enable in
+input strobe_i; //Wishbone bus strobe in
+output ack_o; //Wishbone bus acknowledge out
+input usbClk; //usb clock. 48Mhz +/-0.25%
+output hostSOFSentIntOut;
+output hostConnEventIntOut;
+output hostResumeIntOut;
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut;
+output slaveResetEventIntOut;
+output slaveResumeIntOut;
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i;
+wire [7:0] data_i;
+wire [7:0] data_o;
+wire we_i;
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel;
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE;
+wire [7:0] hostTxFifoData;
+wire hostTxFifoEmpty;
+wire hostRxFifoWE;
+wire [7:0] hostRxFifoData;
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut;
+wire [7:0] RxDataFromSIE;
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState;
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;
+
+usbHostControl u_usbHostControl(
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .TxFifoRE(hostTxFifoRE),
+ .TxFifoData(hostTxFifoData),
+ .TxFifoEmpty(hostTxFifoEmpty),
+ .RxFifoWE(hostRxFifoWE),
+ .RxFifoData(hostRxFifoData),
+ .RxFifoFull(hostRxFifoFull),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .fullSpeedRate(fullSpeedBitRateFromHost),
+ .fullSpeedPol(fullSpeedPolarityFromHost),
+ .HCTxPortEn(SIEPortWEnFromHost),
+ .HCTxPortRdy(SIEPortTxRdy),
+ .HCTxPortData(SIEPortDataInFromHost),
+ .HCTxPortCtrl(SIEPortCtrlInFromHost),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[3:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostControl),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .SOFSentIntOut(hostSOFSentIntOut),
+ .connEventIntOut(hostConnEventIntOut),
+ .resumeIntOut(hostResumeIntOut),
+ .transDoneIntOut(hostTransDoneIntOut),
+ .hostControlSelect(hostControlSel) );
+
+
+usbSlaveControl u_usbSlaveControl(
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .RxByteStatus(RxCtrlOut),
+ .RxData(RxDataFromSIE),
+ .RxDataValid(RxDataOutWEn),
+ .SIERxTimeOut(noActivityTimeOut),
+ .RxFifoData(slaveRxFifoData),
+ .fullSpeedRate(fullSpeedBitRateFromSlave),
+ .fullSpeedPol(fullSpeedPolarityFromSlave),
+ .SCTxPortEn(SIEPortWEnFromSlave),
+ .SCTxPortRdy(SIEPortTxRdy),
+ .SCTxPortData(SIEPortDataInFromSlave),
+ .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+ .connectStateIn(connectState),
+ .resumeDetectedIn(resumeDetected),
+ .busAddress(address_i[4:0]),
+ .busDataIn(data_i),
+ .busDataOut(dataFromSlaveControl),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .SOFRxedIntOut(slaveSOFRxedIntOut),
+ .resetEventIntOut(slaveResetEventIntOut),
+ .resumeIntOut(slaveResumeIntOut),
+ .transDoneIntOut(slaveTransDoneIntOut),
+ .NAKSentIntOut(slaveNAKSentIntOut),
+ .slaveControlSelect(slaveControlSel),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+wishBoneBI u_wishBoneBI (
+ .address(address_i),
+ .dataIn(data_i),
+ .dataOut(data_o),
+ .writeEn(we_i),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .clk(clk_i),
+ .rst(rstSyncToBusClk),
+ .hostControlSel(hostControlSel),
+ .hostRxFifoSel(hostRxFifoSel),
+ .hostTxFifoSel(hostTxFifoSel),
+ .slaveControlSel(slaveControlSel),
+ .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
+ .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
+ .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
+ .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
+ .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
+ .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
+ .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
+ .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .dataFromHostControl(dataFromHostControl),
+ .dataFromHostRxFifo(dataFromHostRxFifo),
+ .dataFromHostTxFifo(dataFromHostTxFifo),
+ .dataFromSlaveControl(dataFromSlaveControl),
+ .dataFromEP0RxFifo(dataFromEP0RxFifo),
+ .dataFromEP1RxFifo(dataFromEP1RxFifo),
+ .dataFromEP2RxFifo(dataFromEP2RxFifo),
+ .dataFromEP3RxFifo(dataFromEP3RxFifo),
+ .dataFromEP0TxFifo(dataFromEP0TxFifo),
+ .dataFromEP1TxFifo(dataFromEP1TxFifo),
+ .dataFromEP2TxFifo(dataFromEP2TxFifo),
+ .dataFromEP3TxFifo(dataFromEP3TxFifo),
+ .dataFromHostSlaveMux(dataFromHostSlaveMux)
+ );
+
+hostSlaveMux u_hostSlaveMux(
+ .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+ .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+ .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+ .SIEPortDataInToSIE(SIEPortDataInToSIE),
+ .SIEPortDataInFromHost(SIEPortDataInFromHost),
+ .SIEPortDataInFromSlave(SIEPortDataInFromSlave),
+ .SIEPortWEnToSIE(SIEPortWEnToSIE),
+ .SIEPortWEnFromHost(SIEPortWEnFromHost),
+ .SIEPortWEnFromSlave(SIEPortWEnFromSlave),
+ .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+ .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+ .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+ .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+ .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+ .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+ .dataIn(data_i),
+ .dataOut(dataFromHostSlaveMux),
+ .address(address_i[0]),
+ .writeEn(we_i),
+ .strobe_i(strobe_i),
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .rstFromWire(rst_i),
+ .rstSyncToBusClkOut(rstSyncToBusClk),
+ .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .connectState(connectState),
+ .resumeDetected(resumeDetected),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataFromSIE),
+ .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+ .SIEPortDataIn(SIEPortDataInToSIE),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEnToSIE),
+ .fullSpeedPolarity(fullSpeedPolarityToSIE),
+ .fullSpeedBitRate(fullSpeedBitRateToSIE),
+ .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoREn(hostTxFifoRE),
+ .fifoEmpty(hostTxFifoEmpty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostTxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostTxFifo),
+ .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoWEn(hostRxFifoWE),
+ .fifoFull(hostRxFifoFull),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(hostRxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromHostRxFifo),
+ .fifoDataIn(hostRxFifoData) );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoREn(TxFifoEP0REn),
+ .fifoEmpty(TxFifoEP0Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0TxFifo),
+ .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoREn(TxFifoEP1REn),
+ .fifoEmpty(TxFifoEP1Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1TxFifo),
+ .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoREn(TxFifoEP2REn),
+ .fifoEmpty(TxFifoEP2Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2TxFifo),
+ .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoREn(TxFifoEP3REn),
+ .fifoEmpty(TxFifoEP3Empty),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3TxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3TxFifo),
+ .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoWEn(RxFifoEP0WEn),
+ .fifoFull(RxFifoEP0Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP0RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP0RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoWEn(RxFifoEP1WEn),
+ .fifoFull(RxFifoEP1Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP1RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP1RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoWEn(RxFifoEP2WEn),
+ .fifoFull(RxFifoEP2Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP2RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP2RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+ .usbClk(usbClk),
+ .busClk(clk_i),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .fifoWEn(RxFifoEP3WEn),
+ .fifoFull(RxFifoEP3Full),
+ .busAddress(address_i[2:0]),
+ .busWriteEn(we_i),
+ .busStrobe_i(strobe_i),
+ .busFifoSelect(slaveEP3RxFifoSel),
+ .busDataIn(data_i),
+ .busDataOut(dataFromEP3RxFifo),
+ .fifoDataIn(slaveRxFifoData) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm (revision 264)
@@ -0,0 +1,276 @@
+
+
+USBHostControlBI.v
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//> ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from <http://www.opencores.org/lgpl.shtml> ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address , dataIn , dataOut , writeEn ,
+ strobe_i ,
+ clk , rst ,
+ SOFSentIntOut , connEventIntOut , resumeIntOut , transDoneIntOut ,
+ TxTransTypeReg , TxSOFEnableReg ,
+ TxAddrReg , TxEndPReg , frameNumIn ,
+ RxPktStatusIn , RxPIDIn ,
+ connectStateIn ,
+ SOFSentIn , connEventIn , resumeIntIn , transDoneIn ,
+ hostControlSelect ,
+ clrTransReq ,
+ preambleEn ,
+ SOFSync ,
+ TxLineState ,
+ LineDirectControlEn ,
+ fullSpeedPol ,
+ fullSpeedRate ,
+ transReq
+ );
+input [3 :0 ] address ;
+input [7 :0 ] dataIn ;
+input writeEn ;
+input strobe_i ;
+input clk ;
+input rst ;
+output [7 :0 ] dataOut ;
+output SOFSentIntOut ;
+output connEventIntOut ;
+output resumeIntOut ;
+output transDoneIntOut ;
+
+output [1 :0 ] TxTransTypeReg ;
+output TxSOFEnableReg ;
+output [6 :0 ] TxAddrReg ;
+output [3 :0 ] TxEndPReg ;
+input [10 :0 ] frameNumIn ;
+input [7 :0 ] RxPktStatusIn ;
+input [3 :0 ] RxPIDIn ;
+input [1 :0 ] connectStateIn ;
+input SOFSentIn ;
+input connEventIn ;
+input resumeIntIn ;
+input transDoneIn ;
+input hostControlSelect ;
+input clrTransReq ;
+output preambleEn ;
+output SOFSync ;
+output [1 :0 ] TxLineState ;
+output LineDirectControlEn ;
+output fullSpeedPol ;
+output fullSpeedRate ;
+output transReq ;
+
+wire [3 :0 ] address ;
+wire [7 :0 ] dataIn ;
+wire writeEn ;
+wire strobe_i ;
+wire clk ;
+wire rst ;
+reg [7 :0 ] dataOut ;
+
+reg SOFSentIntOut ;
+reg connEventIntOut ;
+reg resumeIntOut ;
+reg transDoneIntOut ;
+
+reg [1 :0 ] TxTransTypeReg ;
+reg TxSOFEnableReg ;
+reg [6 :0 ] TxAddrReg ;
+reg [3 :0 ] TxEndPReg ;
+wire [10 :0 ] frameNumIn ;
+wire [7 :0 ] RxPktStatusIn ;
+wire [3 :0 ] RxPIDIn ;
+wire [1 :0 ] connectStateIn ;
+
+wire SOFSentIn ;
+wire connEventIn ;
+wire resumeIntIn ;
+wire transDoneIn ;
+wire hostControlSelect ;
+wire clrTransReq ;
+reg preambleEn ;
+reg SOFSync ;
+reg [1 :0 ] TxLineState ;
+reg LineDirectControlEn ;
+reg fullSpeedPol ;
+reg fullSpeedRate ;
+reg transReq ;
+
+//internal wire and regs
+reg [1 :0 ] TxControlReg ;
+reg [4 :0 ] TxLineControlReg ;
+reg clrSOFReq ;
+reg clrConnEvtReq ;
+reg clrResInReq ;
+reg clrTransDoneReq ;
+reg SOFSentInt ;
+reg connEventInt ;
+reg resumeInt ;
+reg transDoneInt ;
+reg [3 :0 ] interruptMaskReg ;
+reg setTransReq ;
+
+//sync write demux
+always @(posedge clk )
+begin
+ clrSOFReq <= 1'b0 ;
+ clrConnEvtReq <= 1'b0 ;
+ clrResInReq <= 1'b0 ;
+ clrTransDoneReq <= 1'b0 ;
+ setTransReq <= 1'b0 ;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1 )
+ begin
+ case (address )
+ `TX_CONTROL_REG : begin
+ preambleEn <= dataIn [2 ];
+ SOFSync <= dataIn [1 ];
+ setTransReq <= dataIn [0 ];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn [1 :0 ];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn [4 :0 ];
+ `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn [0 ];
+ `TX_ADDR_REG : TxAddrReg <= dataIn [6 :0 ];
+ `TX_ENDP_REG : TxEndPReg <= dataIn [3 :0 ];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn [3 ];
+ clrConnEvtReq <= dataIn [2 ];
+ clrResInReq <= dataIn [1 ];
+ clrTransDoneReq <= dataIn [0 ];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn [3 :0 ];
+ endcase
+ end
+end
+
+//interrupt control
+always @(posedge clk )
+begin
+ if (SOFSentIn == 1'b1 )
+ SOFSentInt <= 1'b1 ;
+ else if (clrSOFReq == 1'b1 )
+ SOFSentInt <= 1'b0 ;
+
+ if (connEventIn == 1'b1 )
+ connEventInt <= 1'b1 ;
+ else if (clrConnEvtReq == 1'b1 )
+ connEventInt <= 1'b0 ;
+
+ if (resumeIntIn == 1'b1 )
+ resumeInt <= 1'b1 ;
+ else if (clrResInReq == 1'b1 )
+ resumeInt <= 1'b0 ;
+
+ if (transDoneIn == 1'b1 )
+ transDoneInt <= 1'b1 ;
+ else if (clrTransDoneReq == 1'b1 )
+ transDoneInt <= 1'b0 ;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt ) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg [`TRANS_DONE_BIT ];
+ resumeIntOut <= resumeInt & interruptMaskReg [`RESUME_INT_BIT ];
+ connEventIntOut <= connEventInt & interruptMaskReg [`CONNECTION_EVENT_BIT ];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg [`SOF_SENT_BIT ];
+end
+
+//transaction request set/clear
+always @(posedge clk )
+begin
+ if (setTransReq == 1'b1 )
+ transReq <= 1'b1 ;
+ else if (clrTransReq == 1'b1 )
+ transReq <= 1'b0 ;
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg ) begin
+ TxLineState <= TxLineControlReg [`TX_LINE_STATE_MSBIT :`TX_LINE_STATE_LSBIT ];
+ LineDirectControlEn <= TxLineControlReg [`DIRECT_CONTROL_BIT ];
+ fullSpeedPol <= TxLineControlReg [`FULL_SPEED_LINE_POLARITY_BIT ];
+ fullSpeedRate <= TxLineControlReg [`FULL_SPEED_LINE_RATE_BIT ];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+ TxAddrReg or TxEndPReg or frameNumIn or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+ preambleEn or SOFSync or transReq )
+begin
+ case (address )
+ `TX_CONTROL_REG : dataOut <= {5'b00000 , preambleEn , SOFSync , transReq } ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000 , TxTransTypeReg };
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000 , TxLineControlReg };
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000 , TxSOFEnableReg };
+ `TX_ADDR_REG : dataOut <= {1'b0 , TxAddrReg };
+ `TX_ENDP_REG : dataOut <= {4'h0 , TxEndPReg };
+ `FRAME_NUM_MSB_REG : dataOut <= frameNumIn [10 :3 ];
+ `FRAME_NUM_LSB_REG : dataOut <= {5'b00000 , frameNumIn [2 :0 ]};
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0 , SOFSentInt , connEventInt , resumeInt , transDoneInt };
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0 , interruptMaskReg };
+ `RX_STATUS_REG : dataOut <= RxPktStatusIn ;
+ `RX_PID_REG : dataOut <= {4'b0000 , RxPIDIn };
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000 , connectStateIn };
+ default : dataOut <= 8'h00 ;
+ endcase
+end
+
+
+endmodule
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v (revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ rstSyncToUsbClk,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input rstSyncToUsbClk;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .wrClk(busClk),
+ .rdClk(usbClk),
+ .rstSyncToWrClk(rstSyncToBusClk),
+ .rstSyncToRdClk(rstSyncToUsbClk),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmptySyncToWrClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToRdClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+ .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v (revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wishBoneBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+
+module wishBoneBI (
+ address, dataIn, dataOut, writeEn,
+ strobe_i,
+ ack_o,
+ clk, rst,
+ hostControlSel,
+ hostRxFifoSel, hostTxFifoSel,
+ slaveControlSel,
+ slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
+ slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
+ hostSlaveMuxSel,
+ dataFromHostControl,
+ dataFromHostRxFifo,
+ dataFromHostTxFifo,
+ dataFromSlaveControl,
+ dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+ dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+ dataFromHostSlaveMux
+ );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+ dataFromHostControl or
+ dataFromHostRxFifo or
+ dataFromHostTxFifo or
+ dataFromSlaveControl or
+ dataFromEP0RxFifo or
+ dataFromEP1RxFifo or
+ dataFromEP2RxFifo or
+ dataFromEP3RxFifo or
+ dataFromHostSlaveMux or
+ dataFromEP0TxFifo or
+ dataFromEP1TxFifo or
+ dataFromEP2TxFifo or
+ dataFromEP3TxFifo)
+begin
+ hostControlSel <= 1'b0;
+ hostRxFifoSel <= 1'b0;
+ hostTxFifoSel <= 1'b0;
+ slaveControlSel <= 1'b0;
+ slaveEP0RxFifoSel <= 1'b0;
+ slaveEP0TxFifoSel <= 1'b0;
+ slaveEP1RxFifoSel <= 1'b0;
+ slaveEP1TxFifoSel <= 1'b0;
+ slaveEP2RxFifoSel <= 1'b0;
+ slaveEP2TxFifoSel <= 1'b0;
+ slaveEP3RxFifoSel <= 1'b0;
+ slaveEP3TxFifoSel <= 1'b0;
+ hostSlaveMuxSel <= 1'b0;
+ case (address & `ADDRESS_DECODE_MASK)
+ `HCREG_BASE : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HCREG_BASE_PLUS_0X10 : begin
+ hostControlSel <= 1'b1;
+ dataOut <= dataFromHostControl;
+ end
+ `HOST_RX_FIFO_BASE : begin
+ hostRxFifoSel <= 1'b1;
+ dataOut <= dataFromHostRxFifo;
+ end
+ `HOST_TX_FIFO_BASE : begin
+ hostTxFifoSel <= 1'b1;
+ dataOut <= dataFromHostTxFifo;
+ end
+ `SCREG_BASE : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `SCREG_BASE_PLUS_0X10 : begin
+ slaveControlSel <= 1'b1;
+ dataOut <= dataFromSlaveControl;
+ end
+ `EP0_RX_FIFO_BASE : begin
+ slaveEP0RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0RxFifo;
+ end
+ `EP0_TX_FIFO_BASE : begin
+ slaveEP0TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP0TxFifo;
+ end
+ `EP1_RX_FIFO_BASE : begin
+ slaveEP1RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1RxFifo;
+ end
+ `EP1_TX_FIFO_BASE : begin
+ slaveEP1TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP1TxFifo;
+ end
+ `EP2_RX_FIFO_BASE : begin
+ slaveEP2RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2RxFifo;
+ end
+ `EP2_TX_FIFO_BASE : begin
+ slaveEP2TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP2TxFifo;
+ end
+ `EP3_RX_FIFO_BASE : begin
+ slaveEP3RxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3RxFifo;
+ end
+ `EP3_TX_FIFO_BASE : begin
+ slaveEP3TxFifoSel <= 1'b1;
+ dataOut <= dataFromEP3TxFifo;
+ end
+ `HOST_SLAVE_CONTROL_BASE : begin
+ hostSlaveMuxSel <= 1'b1;
+ dataOut <= dataFromHostSlaveMux;
+ end
+ default:
+ dataOut <= 8'h00;
+ endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+ ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+ ack_immediate <= strobe_i;
+end
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+ if (writeEn == 1'b0 &&
+ (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+ address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+ begin
+ ack_o <= ack_delayed;
+ end
+ else
+ begin
+ ack_o <= ack_immediate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf (revision 264)
@@ -0,0 +1,289 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=261
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+A 30 23 4 TEXT "Actions" | 120169,193701 1 0 0 "RXPacketRdy <= 1'b0;\nSIERxTimeOutEn <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+ 88541,112746 87971,105860 87641,93102 87312,80344\
+ 87761,70127 92565,59363 97370,48599 95270,45542\
+ 101102,30966
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,180996 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus = { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 260 0 2 Builtin OutPort | 77376,232444 "" ""
+L 259 260 0 TEXT "Labels" | 83376,232444 1 0 0 "SIERxTimeOutEn"
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+ 57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v (revision 264)
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ forceEmptySyncToUsbClk,
+ forceEmptySyncToBusClk,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstSyncToBusClk == 1'b1)
+ forceEmptyShift <= 6'b000000;
+ else begin
+ if (forceEmpty == 1'b1)
+ forceEmptyShift <= 6'b111111;
+ else
+ forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+ end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+ forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v (revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn,
+ dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+ forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH:0]bufferInIndex;
+reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg [ADDR_WIDTH:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+ bufferOutIndexSyncToWrClk <= bufferOutIndex;
+ if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+ begin
+ fifoFull <= 1'b0;
+ bufferInIndex <= 0;
+ end
+ else
+ begin
+ if (fifoWEn == 1'b1) begin
+ bufferInIndex <= bufferInIndex + 1'b1;
+ end
+ if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+ (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex)
+ bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+ bufferInIndexSyncToRdClk <= bufferInIndex;
+ if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+ begin
+ fifoEmpty <= 1'b1;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ fifoREnDelayed <= fifoREn;
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ end
+ if (bufferInIndexSyncToRdClk == bufferOutIndex)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+ bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+ bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc (
+ .addrIn(bufferInIndexToMem),
+ .addrOut(bufferOutIndexToMem),
+ .wrClk(wrClk),
+ .rdClk(rdClk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// directControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+ NextState_drctCntl <= CurrState_drctCntl;
+ // Set default values for outputs and signals
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_drctCntl) // synopsys parallel_case full_case
+ `START_DC:
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ next_HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {6'b000000, directControlLineState};
+ next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_HCTxPortReq <= 1'b0;
+ NextState_drctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_drctCntl <= `IDLE_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_drctCntl <= `START_DC;
+ else
+ CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v (revision 264)
@@ -0,0 +1,236 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hctxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+input [7:0]SOFCntlCntl;
+input [7:0]SOFCntlData;
+input SOFCntlReq;
+input SOFCntlWEn;
+output directCntlGnt;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortWEnable;
+output sendPacketGnt;
+output SOFCntlGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+reg HCTxPortWEnable, next_HCTxPortWEnable;
+wire rst;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [7:0]SOFCntlCntl;
+wire [7:0]SOFCntlData;
+reg SOFCntlGnt, next_SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+ NextState_HCTxArb <= CurrState_HCTxArb;
+ // Set default values for outputs and signals
+ next_SOFCntlGnt <= SOFCntlGnt;
+ next_sendPacketGnt <= sendPacketGnt;
+ next_directCntlGnt <= directCntlGnt;
+ next_muxCntl <= muxCntl;
+ case (CurrState_HCTxArb) // synopsys parallel_case full_case
+ `START_HARB:
+ begin
+ NextState_HCTxArb <= `WAIT_REQ;
+ end
+ `WAIT_REQ:
+ begin
+ if (SOFCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb <= `SEND_SOF;
+ next_SOFCntlGnt <= 1'b1;
+ next_muxCntl <= `SOF_CTRL_MUX;
+ end
+ else if (sendPacketReq == 1'b1)
+ begin
+ NextState_HCTxArb <= `SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxCntl <= `SEND_PACKET_MUX;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_HCTxArb <= `DIRECT_CONTROL;
+ next_directCntlGnt <= 1'b1;
+ next_muxCntl <= `DIRECT_CTRL_MUX;
+ end
+ end
+ `SEND_SOF:
+ begin
+ if (SOFCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb <= `WAIT_REQ;
+ next_SOFCntlGnt <= 1'b0;
+ end
+ end
+ `SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_HCTxArb <= `WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `DIRECT_CONTROL:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_HCTxArb <= `WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_HCTxArb <= `START_HARB;
+ else
+ CurrState_HCTxArb <= NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFCntlGnt <= 1'b0;
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxCntl <= 2'b00;
+ end
+ else
+ begin
+ SOFCntlGnt <= next_SOFCntlGnt;
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxCntl <= next_muxCntl;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// rxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ connectionEventOut <= 1'b1;
+ else
+ connectionEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v (revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketarbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input clk;
+input [3:0]HC_PID;
+input HC_SP_WEn;
+input HCTxReq;
+input rst;
+input SOF_SP_WEn;
+input SOFTxReq;
+output HCTxGnt;
+output [3:0]sendPacketPID;
+output sendPacketWEnable;
+output SOFTxGnt;
+
+wire clk;
+wire [3:0]HC_PID;
+wire HC_SP_WEn;
+reg HCTxGnt, next_HCTxGnt;
+wire HCTxReq;
+wire rst;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+reg sendPacketWEnable, next_sendPacketWEnable;
+wire SOF_SP_WEn;
+reg SOFTxGnt, next_SOFTxGnt;
+wire SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+ NextState_sendPktArb <= CurrState_sendPktArb;
+ // Set default values for outputs and signals
+ next_HCTxGnt <= HCTxGnt;
+ next_SOFTxGnt <= SOFTxGnt;
+ next_muxSOFNotHC <= muxSOFNotHC;
+ case (CurrState_sendPktArb) // synopsys parallel_case full_case
+ `HC_ACT:
+ begin
+ if (HCTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_HCTxGnt <= 1'b0;
+ end
+ end
+ `SOF_ACT:
+ begin
+ if (SOFTxReq == 1'b0)
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ next_SOFTxGnt <= 1'b0;
+ end
+ end
+ `SARB_WAIT_REQ:
+ begin
+ if (SOFTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `SOF_ACT;
+ next_SOFTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b1;
+ end
+ else if (HCTxReq == 1'b1)
+ begin
+ NextState_sendPktArb <= `HC_ACT;
+ next_HCTxGnt <= 1'b1;
+ next_muxSOFNotHC <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_sendPktArb <= `SARB_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktArb <= `START_SARB;
+ else
+ CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ HCTxGnt <= 1'b0;
+ SOFTxGnt <= 1'b0;
+ muxSOFNotHC <= 1'b0;
+ end
+ else
+ begin
+ HCTxGnt <= next_HCTxGnt;
+ SOFTxGnt <= next_SOFTxGnt;
+ muxSOFNotHC <= next_muxSOFNotHC;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v (revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sofcontroller
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input clk;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input rst;
+input SOFEnable;
+input SOFTimerClr;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output [15:0]SOFTimer;
+
+wire clk;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire rst;
+wire SOFEnable;
+reg [15:0]SOFTimer, next_SOFTimer;
+wire SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+ NextState_sofCntl <= CurrState_sofCntl;
+ // Set default values for outputs and signals
+ next_SOFTimer <= SOFTimer;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ case (CurrState_sofCntl) // synopsys parallel_case full_case
+ `START_SC:
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ end
+ `WAIT_SOF_EN:
+ begin
+ if (SOFEnable == 1'b1)
+ begin
+ NextState_sofCntl <= `SC_WAIT_GNT;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `WAIT_SEND_RESUME:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sofCntl <= `CLR_WEN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_RESUME_START;
+ end
+ end
+ `INC_TIMER:
+ begin
+ next_HCTxPortReq <= 1'b0;
+ if (SOFTimerClr == 1'b1)
+ next_SOFTimer <= 16'h0000;
+ else
+ next_SOFTimer <= SOFTimer + 1'b1;
+ if (SOFEnable == 1'b0)
+ begin
+ NextState_sofCntl <= `WAIT_SOF_EN;
+ next_SOFTimer <= 16'h0000;
+ end
+ end
+ `SC_WAIT_GNT:
+ begin
+ if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sofCntl <= `WAIT_SEND_RESUME;
+ end
+ end
+ `CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sofCntl <= `INC_TIMER;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sofCntl <= `START_SC;
+ else
+ CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFTimer <= 16'h0000;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortData <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SOFTimer <= next_SOFTimer;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v (revision 264)
@@ -0,0 +1,397 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+ busClk, rstSyncToBusClk,
+ usbClk, rstSyncToUsbClk,
+ //sendPacket
+ TxFifoRE, TxFifoData, TxFifoEmpty,
+ //getPacket
+ RxFifoWE, RxFifoData, RxFifoFull,
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, SIERxTimeOutEn,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //HCTxPortArbiter
+ HCTxPortEn, HCTxPortRdy,
+ HCTxPortData, HCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFSentIntOut,
+ connEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ hostControlSelect
+ );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output SIERxTimeOutEn;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [3:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+input hostControlSelect;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut;
+wire connEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .SOFSentIntOut(SOFSentIntOut),
+ .connEventIntOut(connEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .TxTransTypeReg(transType),
+ .TxSOFEnableReg(SOFEnable),
+ .TxAddrReg(TxAddr),
+ .TxEndPReg(TxEndP),
+ .frameNumIn(frameNum),
+ .RxPktStatusIn(RxPktStatus),
+ .RxPIDIn(RxPID),
+ .connectStateIn(connectStateOut),
+ .SOFSentIn(SOFSent),
+ .connEventIn(connectionEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .hostControlSelect(hostControlSelect),
+ .clrTransReq(clrTxReq),
+ .preambleEn(preAmbleEnable),
+ .SOFSync(SOFSyncEn),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .transReq(transReq),
+ .isoEn(isoEn),
+ .SOFTimer(SOFTimer)
+ );
+
+
+hostcontroller u_hostController
+ (.RXStatus(RxPktStatus),
+ .clearTXReq(clrTxReq),
+ .clk(usbClk),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rstSyncToUsbClk),
+ .sendPacketArbiterGnt(HCTxGnt),
+ .sendPacketArbiterReq(HCTxReq),
+ .sendPacketPID(HC_PID),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(HC_SP_WEn),
+ .transDone(transDone),
+ .transReq(transReq),
+ .transType(transType),
+ .isoEn(isoEn) );
+
+SOFController u_SOFController
+ (.HCTxPortCntl(SOFCntlCntl),
+ .HCTxPortData(SOFCntlData),
+ .HCTxPortGnt(SOFCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(SOFCntlReq),
+ .HCTxPortWEn(SOFCntlWEn),
+ .SOFEnable(SOFEnable),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+SOFTransmit u_SOFTransmit
+ (.SOFEnable(SOFEnable),
+ .SOFSent(SOFSent),
+ .SOFSyncEn(SOFSyncEn),
+ .SOFTimerClr(SOFTimerClr),
+ .SOFTimer(SOFTimer),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .sendPacketArbiterGnt(SOFTxGnt),
+ .sendPacketArbiterReq(SOFTxReq),
+ .sendPacketRdy(sendPacketCPReadyOut),
+ .sendPacketWEn(SOF_SP_WEn) );
+
+
+sendPacketArbiter u_sendPacketArbiter
+ (.HCTxGnt(HCTxGnt),
+ .HCTxReq(HCTxReq),
+ .HC_PID(HC_PID),
+ .HC_SP_WEn(HC_SP_WEn),
+ .SOFTxGnt(SOFTxGnt),
+ .SOFTxReq(SOFTxReq),
+ .SOF_SP_WEn(SOF_SP_WEn),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .sendPacketPID(sendPacketCPPIDIn),
+ .sendPacketWEnable(sendPacketCPWEnIn) );
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+ (.sendPacketCPPID(sendPacketCPPIDIn),
+ .clk(usbClk),
+ .preAmbleEnable(preAmbleEnable),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCPReady(sendPacketCPReadyOut),
+ .sendPacketCPWEn(sendPacketCPWEnIn),
+ .sendPacketPID(sendPacketCPPIDOut),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+ (.HCTxPortCntl(sendPacketCntl),
+ .HCTxPortData(sendPacketData),
+ .HCTxPortGnt(sendPacketGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(sendPacketReq),
+ .HCTxPortWEn(sendPacketWEn),
+ .PID(sendPacketCPPIDOut),
+ .TxAddr(TxAddr),
+ .TxEndP(TxEndP),
+ .clk(usbClk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .frameNum(frameNum),
+ .rst(rstSyncToUsbClk),
+ .sendPacketRdy(sendPacketCPReadyIn),
+ .sendPacketWEn(sendPacketCPWEnOut),
+ .fullSpeedPolarity(fullSpeedPol) );
+
+directControl u_directControl
+ (.HCTxPortCntl(directCntlCntl),
+ .HCTxPortData(directCntlData),
+ .HCTxPortGnt(directCntlGnt),
+ .HCTxPortRdy(HCTxPortRdy),
+ .HCTxPortReq(directCntlReq),
+ .HCTxPortWEn(directCntlWEn),
+ .clk(usbClk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rstSyncToUsbClk) );
+
+HCTxPortArbiter u_HCTxPortArbiter
+ (.HCTxPortCntl(HCTxPortCtrl),
+ .HCTxPortData(HCTxPortData),
+ .HCTxPortWEnable(HCTxPortEn),
+ .SOFCntlCntl(SOFCntlCntl),
+ .SOFCntlData(SOFCntlData),
+ .SOFCntlGnt(SOFCntlGnt),
+ .SOFCntlReq(SOFCntlReq),
+ .SOFCntlWEn(SOFCntlWEn),
+ .clk(usbClk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+getPacket u_getPacket
+ (.RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXPktStatus(RxPktStatus),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .SIERxTimeOutEn(SIERxTimeOutEn),
+ .clk(usbClk),
+ .getPacketEn(getPacketREn),
+ .rst(rstSyncToUsbClk) );
+
+rxStatusMonitor u_rxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .connectionEventOut(connectionEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v (revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ busClk,
+ usbClk,
+ rstSyncToBusClk,
+ fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ forceEmptySyncToUsbClk,
+ forceEmptySyncToBusClk,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+reg fifoWEn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstSyncToBusClk == 1'b1)
+ forceEmptyShift <= 6'b000000;
+ else begin
+ if (forceEmpty == 1'b1)
+ forceEmptyShift <= 6'b111111;
+ else
+ forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+ end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+ forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+// case (address)
+// `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+// `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+// `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+// default: busDataOut <= 8'h00;
+// endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,380 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+ TxTransTypeReg, TxSOFEnableReg,
+ TxAddrReg, TxEndPReg, frameNumIn,
+ RxPktStatusIn, RxPIDIn,
+ connectStateIn,
+ SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+ hostControlSelect,
+ clrTransReq,
+ preambleEn,
+ SOFSync,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ transReq,
+ isoEn,
+ SOFTimer
+ );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output transReq;
+output isoEn; //enable isochronous mode
+input [15:0] SOFTimer;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+wire [15:0] SOFTimer;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [1:0] TxTransTypeRegSTB;
+reg TxSOFEnableRegSTB;
+reg [6:0] TxAddrRegSTB;
+reg [3:0] TxEndPRegSTB;
+reg preambleEnSTB;
+reg SOFSyncSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB;
+reg fullSpeedRateSTB;
+reg transReqSTB;
+reg isoEnSTB;
+reg [10:0] frameNumInSTB;
+reg [7:0] RxPktStatusInSTB;
+reg [3:0] RxPIDInSTB;
+reg [1:0] connectStateInSTB;
+reg SOFSentInSTB;
+reg connEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrTransReqSTB;
+reg [15:0] SOFTimerSTB;
+
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ isoEnSTB <= 1'b0;
+ preambleEnSTB <= 1'b0;
+ SOFSyncSTB <= 1'b0;
+ TxTransTypeRegSTB <= 2'b00;
+ TxLineControlReg <= 5'h00;
+ TxSOFEnableRegSTB <= 1'b0;
+ TxAddrRegSTB <= 7'h00;
+ TxEndPRegSTB <= 4'h0;
+ interruptMaskReg <= 4'h0;
+ end
+ else begin
+ clrSOFReq <= 1'b0;
+ clrConnEvtReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ setTransReq <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+ begin
+ case (address)
+ `TX_CONTROL_REG : begin
+ isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
+ preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
+ SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
+ setTransReq <= dataIn[`TRANS_REQ_BIT];
+ end
+ `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
+ `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+ `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
+ `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
+ `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
+ `INTERRUPT_STATUS_REG : begin
+ clrSOFReq <= dataIn[`SOF_SENT_BIT];
+ clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ SOFSentInt <= 1'b0;
+ connEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (SOFSentInSTB == 1'b1)
+ SOFSentInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFSentInt <= 1'b0;
+
+ if (connEventInSTB == 1'b1)
+ connEventInt <= 1'b1;
+ else if (clrConnEvtReq == 1'b1)
+ connEventInt <= 1'b0;
+
+ if (resumeIntInSTB == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneInSTB == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+ SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end
+
+//transaction request set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'setTransReq' must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the transaction request is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ transReqSTB <= 1'b0;
+ end
+ else begin
+ if (setTransReq == 1'b1)
+ transReqSTB <= 1'b1;
+ else if (clrTransReqSTB == 1'b1)
+ transReqSTB <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+ TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+ LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+ fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+
+// async read mux
+always @(address or
+ TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
+ TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
+ SOFSentInt or connEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
+ preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
+begin
+ case (address)
+ `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
+ `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
+ `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+ `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
+ `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
+ `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
+ `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
+ `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
+ `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+ `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
+ `RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
+ `RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
+ `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
+ `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+//re-sync from busClk to usbClk.
+always @(posedge usbClk) begin
+ if (rstSyncToUsbClk == 1'b1) begin
+ isoEn <= 1'b0;
+ preambleEn <= 1'b0;
+ SOFSync <= 1'b0;
+ TxTransTypeReg <= 2'b00;
+ TxSOFEnableReg <= 1'b0;
+ TxAddrReg <= 7'h00;
+ TxEndPReg <= 4'h0;
+ TxLineState <= 2'b00;
+ LineDirectControlEn <= 1'b0;
+ fullSpeedPol <= 1'b0;
+ fullSpeedRate <= 1'b0;
+ transReq <= 1'b0;
+ end
+ else begin
+ isoEn <= isoEnSTB;
+ preambleEn <= preambleEnSTB;
+ SOFSync <= SOFSyncSTB;
+ TxTransTypeReg <= TxTransTypeRegSTB;
+ TxSOFEnableReg <= TxSOFEnableRegSTB;
+ TxAddrReg <= TxAddrRegSTB;
+ TxEndPReg <= TxEndPRegSTB;
+ TxLineState <= TxLineStateSTB;
+ LineDirectControlEn <= LineDirectControlEnSTB;
+ fullSpeedPol <= fullSpeedPolSTB;
+ fullSpeedRate <= fullSpeedRateSTB;
+ transReq <= transReqSTB;
+ end
+end
+
+//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+ frameNumInSTB <= frameNumIn;
+ RxPktStatusInSTB <= RxPktStatusIn;
+ RxPIDInSTB <= RxPIDIn;
+ connectStateInSTB <= connectStateIn;
+ SOFSentInSTB <= SOFSentIn;
+ connEventInSTB <= connEventIn;
+ resumeIntInSTB <= resumeIntIn;
+ transDoneInSTB <= transDoneIn;
+ clrTransReqSTB <= clrTransReq;
+ SOFTimerSTB <= SOFTimer;
+end
+
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v (revision 264)
@@ -0,0 +1,404 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// getpacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);
+input clk;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXPacketRdy;
+output [3:0]RxPID;
+output [7:0]RXPktStatus;
+output SIERxTimeOutEn;
+
+wire clk;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+reg [7:0]RXPktStatus;
+wire [7:0]RXStreamStatusIn;
+wire SIERxTimeOut;
+reg SIERxTimeOutEn, next_SIERxTimeOutEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)
+begin
+ NextState_getPkt <= CurrState_getPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ next_SIERxTimeOutEn <= SIERxTimeOutEn;
+ case (CurrState_getPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b1;
+ if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_getPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_getPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_getPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_getPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+ next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_getPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (RXFifoFull == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_getPkt <= `START_GP;
+ else
+ CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RxPID <= 4'h0;
+ SIERxTimeOutEn <= 1'b0;
+ RXOverflow <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXByteOld <= 8'h00;
+ RXTimeOut <= 1'b0;
+ end
+ else
+ begin
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RxPID <= next_RxPID;
+ SIERxTimeOutEn <= next_SIERxTimeOutEn;
+ RXOverflow <= next_RXOverflow;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXByteOld <= next_RXByteOld;
+ RXTimeOut <= next_RXTimeOut;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v (revision 264)
@@ -0,0 +1,447 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input clk;
+input getPacketRdy;
+input isoEn;
+input rst;
+input [7:0]RXStatus;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input transReq;
+input [1:0]transType;
+output clearTXReq;
+output getPacketREn;
+output sendPacketArbiterReq;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output transDone;
+
+reg clearTXReq, next_clearTXReq;
+wire clk;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+wire isoEn;
+wire rst;
+wire [7:0]RXStatus;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg transDone, next_transDone;
+wire transReq;
+wire [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+`define DEL1 6'b100001
+`define DEL2 6'b100010
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+ NextState_hstCntrl <= CurrState_hstCntrl;
+ // Set default values for outputs and signals
+ next_transDone <= transDone;
+ next_clearTXReq <= clearTXReq;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketPID <= sendPacketPID;
+ next_sendPacketWEn <= sendPacketWEn;
+ case (CurrState_hstCntrl) // synopsys parallel_case full_case
+ `START_HC:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `TX_REQ:
+ begin
+ if (transReq == 1'b1)
+ begin
+ NextState_hstCntrl <= `WAIT_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `CHK_TYPE:
+ begin
+ if (transType == `OUTDATA0_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+ end
+ else if (transType == `IN_TRANS)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+ end
+ else if (transType == `SETUP_TRANS)
+ begin
+ NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+ end
+ else if (transType == `OUTDATA1_TRANS)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+ end
+ end
+ `FLAG:
+ begin
+ next_transDone <= 1'b1;
+ next_clearTXReq <= 1'b1;
+ next_sendPacketArbiterReq <= 1'b0;
+ NextState_hstCntrl <= `FIN;
+ end
+ `FIN:
+ begin
+ next_clearTXReq <= 1'b0;
+ next_transDone <= 1'b0;
+ //now wait for 'transReq' to clear
+ NextState_hstCntrl <= `DEL1;
+ end
+ `WAIT_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1)
+ begin
+ NextState_hstCntrl <= `CHK_TYPE;
+ end
+ end
+ `DEL1:
+ begin
+ NextState_hstCntrl <= `DEL2;
+ end
+ `DEL2:
+ begin
+ NextState_hstCntrl <= `TX_REQ;
+ end
+ `SETUP_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+ end
+ `SETUP_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+ end
+ `SETUP_WAIT_PKT_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `SETUP_HC_WAIT_RDY:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `SETUP;
+ end
+ end
+ `SETUP_WAIT_SETUP_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `SETUP_WAIT_DATA_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_DATA_RXED:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+ end
+ end
+ `IN_CHK_FOR_ERROR:
+ begin
+ if (isoEn == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+ RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+ RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `IN_CLR_SP_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+ end
+ `IN_WAIT_IN_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `IN_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `IN;
+ end
+ end
+ `IN_WAIT_SP_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `IN_CLR_SP_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+ end
+ `IN_WAIT_ACK_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT0_WAIT_DATA0_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CHK_ISO;
+ end
+ end
+ `OUT0_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ end
+ `OUT0_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT0_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT0_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+ end
+ `OUT0_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+ end
+ `OUT0_CHK_ISO:
+ begin
+ if (isoEn == 1'b0)
+ begin
+ NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ else
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_RX_DATA:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `FLAG;
+ end
+ end
+ `OUT1_WAIT_OUT_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN2;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `OUT1_WAIT_DATA1_SENT:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `OUT1_WAIT_SP_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_hstCntrl <= `OUT1_CLR_WEN1;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `OUT;
+ end
+ end
+ `OUT1_CLR_WEN1:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+ end
+ `OUT1_CLR_WEN2:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_hstCntrl <= `START_HC;
+ else
+ CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ transDone <= 1'b0;
+ clearTXReq <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ end
+ else
+ begin
+ transDone <= next_transDone;
+ clearTXReq <= next_clearTXReq;
+ getPacketREn <= next_getPacketREn;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+I 61 0 2 Builtin InPort | 199418,251681 "" ""
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+ 200193,83454 202194,93721 199799,97969 197405,102218\
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+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) \nbegin\n if (muxSOFNotHC == 1'b1) \n begin\n sendPacketWEnable <= SOF_SP_WEn;\n sendPacketPID <= `SOF;\n end\n else\n begin\n sendPacketWEnable <= HC_SP_WEn;\n sendPacketPID <= HC_PID;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
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+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
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+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf (revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
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+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl"
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+S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500
+W 12 6 0 9 11 BEZIER "Transitions" | 101472,200547 101472,195422 101786,186460 101786,181335
+I 13 6 0 Builtin Reset | 56682,217090
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+I 16 0 3 Builtin InPort | 180096,262516 "" ""
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+I 18 0 2 Builtin InPort | 179694,255682 "" ""
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+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n SOFTimer <= 16'h0000;\nelse\n SOFTimer <= SOFTimer + 1'b1;"
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+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v (revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// speedCtrlMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input directCtrlRate;
+input directCtrlPol;
+input sendPacketRate;
+input sendPacketPol;
+input sendPacketSel;
+output fullSpeedRate;
+output fullSpeedPol;
+
+wire directCtrlRate;
+wire directCtrlPol;
+wire sendPacketRate;
+wire sendPacketPol;
+wire sendPacketSel;
+reg fullSpeedRate;
+reg fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+ if (sendPacketSel == 1'b1)
+ begin
+ fullSpeedRate <= sendPacketRate;
+ fullSpeedPol <= sendPacketPol;
+ end
+ else
+ begin
+ fullSpeedRate <= directCtrlRate;
+ fullSpeedPol <= directCtrlPol;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v (revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc
+
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v (revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants
+//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
+`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+
+//Host RXStatusRegIndices
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v (revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf (revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
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+OBJECTS
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 99337,112266 6500 6500
+L 19 18 0 TEXT "State Labels" | 99337,112266 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 146563,24238
+W 23 17 0 18 21 BEZIER "Transitions" | 103975,107713 107885,100636 103154,45547 143864,24443
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+ 43038,129670 44914,125650 53423,124511 61932,123372\
+ 93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+ 44646,98582 47594,94562 55902,93624 64210,92686\
+ 94494,92954 102132,93021 109770,93088 110325,93078\
+ 110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+ 45182,65484 49202,63876 57711,63474 66220,63072\
+ 96236,63072 103807,63072 111378,63072 111758,63165\
+ 111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+ 46388,39220 49604,34396 58247,33391 66890,32386\
+ 97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+ 188238,99472 188778,113512 186145,122422 183513,131332\
+ 167904,143587 159264,149864 150624,156142 133542,158851\
+ 125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0; \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 152390,172884 131374,171355 101683,127861 94565,116677
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 72243,162260 51221,151750 45574,140719\
+ 39928,129688 39788,80170 47763,75675 55738,71180\
+ 102436,61038 148189,26024
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+ 151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+ 176540,156388 181096,131196 181431,113977 181766,96758\
+ 182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 5'h0; \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit) //can only be a resume if line remains in Kbit state\n RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n resumeWaitCnt <= resumeWaitCnt + 1'b1; \n //if we've waited long enough, then\n if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n begin \n RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n resumeDetected <= 1'b1; //report resume detected\n end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+ 107061,21822 137747,20482 148467,20415 159187,20348\
+ 171381,21420 174463,22458 177545,23497 178090,26035\
+ 178157,27576
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+ 145117,36964 157043,31068 161599,29627 166155,28187\
+ 172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
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+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
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+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
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+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n RXSameBitCount <= RXSameBitCount + 1'b1; //inc 'RXSameBitCount'\n if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n bitStuffError <= 1'b1; //flag 'bitStuffError'\n else //else no bit stuffing error\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= { 1'b1, RXByte[7:1]}; //RZ bit = 1 (ie no change in 'RxBits')\n end\nend\nelse //else current 'RxBits' are different from old 'RxBits'\nbegin\n if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n begin\n RXBitCount <= RXBitCount + 1'b1;\n if (RXBitCount != 4'h7) begin\n processRxBitRdy <= 1'b1; //early indication of ready\n end\n RXByte <= {1'b0, RXByte[7:1]}; //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n end\n RXSameBitCount <= 4'h0; //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00; //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf (revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processTxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+OBJECTS
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+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate == 1'b0"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+ 157955,32952 139055,31533 132716,31415 126377,31297\
+ 121929,32154 118701,32626
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
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+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
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+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
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+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
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+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
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+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
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+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
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+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
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+I 844 0 130 Builtin Signal | 69660,223196 "" ""
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+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
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+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
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+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
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+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
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+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
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+I 884 880 0 Builtin Exit | 178131,23271
+I 883 880 0 Builtin Entry | 38120,248040
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
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+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1) //If this bit is 1, then\n TXOneCount <= TXOneCount + 1'b1; //increment 'TXOneCount'\nelse //else this is a zero bit\nbegin\n TXOneCount <= 4'h0; //reset 'TXOneCount'\n if (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\n else \n TXLineState <= JBit;\nend"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
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+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0; //reset 'TXOneCount'\nif (TXLineState == JBit) \n TXLineState <= KBit; //toggle the line state\nelse \n TXLineState <= JBit;"
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0; \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+ 40522,42856 31562,47464 29098,65320 26634,83176\
+ 25738,149992 26858,168968 27978,187944 33354,197032\
+ 36938,198888 40522,200744 49226,198568 51498,198152\
+ 53770,197736 54409,198230 54473,198230
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+ 113354,23912 154429,23527 174909,23271
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+ 90132,26172 93257,24084 94765,23272
+I 974 895 0 Builtin Exit | 97904,23272
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+I 977 895 0 Builtin Entry | 34452,259216
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+ 30972,218732 29812,212468 29638,189094 29464,165720\
+ 29928,78488 31900,55230 33872,31972 41296,26172\
+ 49358,24664 57420,23156 82353,23388 94765,23272
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+ 41124,121640 36948,124424 36020,132602 35092,140780\
+ 35556,170708 38166,179350 40776,187992 50140,192687\
+ 55128,195007
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+ 104561,139388 153745,139620 168013,138576 182281,137532\
+ 190169,133124 192141,121582 194113,110040 194113,68280\
+ 192025,55114 189937,41948 185529,28723 181353,23271
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit; \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 996 995 0 Builtin Entry | 86360,167640
+I 997 995 0 Builtin Exit | 129540,111760
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 1029 1027 0 Builtin Exit | 129540,111760
+I 1028 1027 0 Builtin Entry | 86360,167640
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+I 1075 1035 0 Builtin Entry | 75208,271435
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v (revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIEReceiver
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input clk;
+input rst;
+input [1:0]RxWireDataIn;
+input RxWireDataWEn;
+output [1:0]connectState;
+
+wire clk;
+reg [1:0]connectState, next_connectState;
+wire rst;
+wire [1:0]RxWireDataIn;
+wire RxWireDataWEn;
+
+// diagram signals declarations
+reg [1:0]RxBits, next_RxBits;
+reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+ NextState_rcvr <= CurrState_rcvr;
+ // Set default values for outputs and signals
+ next_RXWaitCount <= RXWaitCount;
+ next_connectState <= connectState;
+ next_RXStMachCurrState <= RXStMachCurrState;
+ next_RxBits <= RxBits;
+ case (CurrState_rcvr) // synopsys parallel_case full_case
+ `WAIT_BIT:
+ begin
+ if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+ begin
+ NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+ begin
+ NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+ next_RxBits <= RxWireDataIn;
+ end
+ else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+ begin
+ NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+ next_RxBits <= RxWireDataIn;
+ end
+ end
+ `START_SRX:
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_RXWaitCount <= 8'h00;
+ next_connectState <= `DISCONNECT;
+ next_RxBits <= 2'b00;
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `DISCNCT_CHK_RXBITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else if (RxBits == `ONE_ZERO)
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+ next_RXWaitCount <= 8'h00;
+ end
+ else
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ end
+ `WAIT_FS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ONE_ZERO)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `FULL_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `WAIT_LS_CONN_CHK_RX_BITS:
+ begin
+ if (RxBits == `ZERO_ONE)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `CONNECT_WAIT_TIME)
+ begin
+ next_connectState <= `LOW_SPEED_CONNECT;
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ end
+ NextState_rcvr <= `WAIT_BIT;
+ end
+ `LS_CONN_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `FS_CONN_CHK_RX_BITS1:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+ next_RXWaitCount <= 0;
+ end
+ end
+ `WAIT_LS_DIS_CHK_RX_BITS:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+ end
+ end
+ `WAIT_FS_DIS_CHK_RX_BITS2:
+ begin
+ NextState_rcvr <= `WAIT_BIT;
+ if (RxBits == `SE0)
+ begin
+ next_RXWaitCount <= RXWaitCount + 1'b1;
+ if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+ begin
+ next_RXStMachCurrState <= `DISCONNECT_ST;
+ next_connectState <= `DISCONNECT;
+ end
+ end
+ else
+ begin
+ next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_rcvr <= `START_SRX;
+ else
+ CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ connectState <= `DISCONNECT;
+ RXWaitCount <= 8'h00;
+ RXStMachCurrState <= `DISCONNECT_ST;
+ RxBits <= 2'b00;
+ end
+ else
+ begin
+ connectState <= next_connectState;
+ RXWaitCount <= next_RXWaitCount;
+ RXStMachCurrState <= next_RXStMachCurrState;
+ RxBits <= next_RxBits;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf (revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+ 200193,83454 202194,93721 199799,97969 197405,102218\
+ 189371,107780 182843,108050 176316,108321 158239,103840\
+ 151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n TxFSRate <= SIETxFSRate;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n TxFSRate <= prcTxByteFSRate;\n end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+ 70311,70629 71874,86691 76817,93064 81761,99437\
+ 89642,107471 97173,106158 104705,104845 116882,95874\
+ 123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf (revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 41
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 43
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 227
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 236
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+ 48213,88528 42471,75064 41184,67490 39897,59917\
+ 40491,43087 47668,36800 54846,30514 82962,22198\
+ 91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+ 200128,135446 205472,144130 205681,151728 205890,159327\
+ 201380,181037 194241,189595 187102,198154 163054,210680\
+ 152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+ 202640,35412 197280,23183 191376,19540 185472,15898\
+ 167213,13552 158043,13342 148873,13133 131482,15160\
+ 122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf (revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+ 94907,51569 61918,50756 52575,52503 43232,54250\
+ 38843,62050 37706,72734 36569,83418 36406,118357\
+ 40062,129609 43718,140862 58507,150938 67687,153172\
+ 76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf (revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 16 6 0 Builtin Reset | 76112,190530
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+ 119442,151760 119430,151725 119430,151571
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+ 105450,47318 105450,38252 107207,34228 108965,30205\
+ 115846,23167 119361,19652
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+ 70296,21816 59880,36936 57948,44622 56016,52308\
+ 59778,66554 61122,74366
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v (revision 264)
@@ -0,0 +1,198 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+ SIEPortCtrlInToSIE,
+ SIEPortCtrlInFromHost,
+ SIEPortCtrlInFromSlave,
+ SIEPortDataInToSIE,
+ SIEPortDataInFromHost,
+ SIEPortDataInFromSlave,
+ SIEPortWEnToSIE,
+ SIEPortWEnFromHost,
+ SIEPortWEnFromSlave,
+ fullSpeedPolarityToSIE,
+ fullSpeedPolarityFromHost,
+ fullSpeedPolarityFromSlave,
+ fullSpeedBitRateToSIE,
+ fullSpeedBitRateFromHost,
+ fullSpeedBitRateFromSlave,
+ noActivityTimeOutEnableToSIE,
+ noActivityTimeOutEnableFromHost,
+ noActivityTimeOutEnableFromSlave,
+ dataIn,
+ dataOut,
+ address,
+ writeEn,
+ strobe_i,
+ busClk,
+ usbClk,
+ hostSlaveMuxSel,
+ rstFromWire,
+ rstSyncToBusClkOut,
+ rstSyncToUsbClkOut
+);
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE;
+input [7:0] SIEPortDataInFromHost;
+input [7:0] SIEPortDataInFromSlave;
+output SIEPortWEnToSIE;
+input SIEPortWEnFromHost;
+input SIEPortWEnFromSlave;
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+output noActivityTimeOutEnableToSIE;
+input noActivityTimeOutEnableFromHost;
+input noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE;
+wire [7:0] SIEPortDataInFromHost;
+wire [7:0] SIEPortDataInFromSlave;
+reg SIEPortWEnToSIE;
+wire SIEPortWEnFromHost;
+wire SIEPortWEnFromSlave;
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+reg noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClkOut;
+wire rstSyncToUsbClkOut;
+wire rstFromWire;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+ SIEPortCtrlInFromHost or
+ SIEPortCtrlInFromSlave or
+ SIEPortDataInFromHost or
+ SIEPortDataInFromSlave or
+ SIEPortWEnFromHost or
+ SIEPortWEnFromSlave or
+ fullSpeedPolarityFromHost or
+ fullSpeedPolarityFromSlave or
+ fullSpeedBitRateFromHost or
+ fullSpeedBitRateFromSlave or
+ noActivityTimeOutEnableFromHost or
+ noActivityTimeOutEnableFromSlave)
+begin
+ if (hostMode == 1'b1)
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+ SIEPortDataInToSIE <= SIEPortDataInFromHost;
+ SIEPortWEnToSIE <= SIEPortWEnFromHost;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+ noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromHost;
+ end
+ else
+ begin
+ SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+ SIEPortDataInToSIE <= SIEPortDataInFromSlave;
+ SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+ fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+ fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+ noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromSlave;
+ end
+end
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+ .dataIn(dataIn),
+ .dataOut(dataOut),
+ .address(address),
+ .writeEn(writeEn),
+ .strobe_i(strobe_i),
+ .busClk(busClk),
+ .usbClk(usbClk),
+ .hostMode(hostMode),
+ .hostSlaveMuxSel(hostSlaveMuxSel),
+ .rstFromWire(rstFromWire),
+ .rstSyncToBusClkOut(rstSyncToBusClkOut),
+ .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v (revision 264)
@@ -0,0 +1,55 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
+// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
+// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+// speed, and TX resume is always low speed.
+// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
+// in missing receive packets.
+// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+// by adding kludged delay to softranmit. This needs to be fixed properly.
+// This version has undergone limited testing
+// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+// with uClinux, and is known to work with a full speed USB flash stick.
+// Moving Opencores project status from Beta to done.
+// TODO: Test isochronous mode, and low speed mode using uClinux driver
+// Create a seperate clock domain for the bus interface
+// Add frame period adjustment capability
+// Add compilation flags for slave only and host only versions
+// Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+// Removed TX and RX fifo status registers, and removed
+// TX fifo data count register.
+// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+// Fixed slave mode bug which caused receive fifo to be filled with
+// incoming data when the slave was responding with a NAK, and the
+// data should have been discarded.
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+// there was no detected activity on the USB data lines. This caused an infrequent
+// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+// the higher level state machines are actively looking for receive packets.
+// Modified USB RX data clock recovery, so that data is sampled during the middle
+// of a USB bit period. Fixed a bug which could result in double sampling
+// of USB RX data if clock phase adjustments were required in the middle of a
+// USB packet.
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h11
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf (revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIETransmitter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+END
+INSTHEADER 1073
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+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/19/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,209519
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/18/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 124599,219647 "" ""
+I 846 0 130 Builtin InPort | 125108,215006 "" ""
+L 845 846 0 TEXT "Labels" | 131108,215006 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[2:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 118825,194982 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/31/"
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+ 42326,129670 44202,125650 52711,124511 61220,123372\
+ 92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+ 161730,108850 152965,112617 149770,115182 146575,117747\
+ 142560,124240 140625,130720 138690,137200 144540,155815\
+ 141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+ 43361,99065 46384,95576 54928,94878 63472,94181\
+ 94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+ 104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1; \nresumeCnt <= resumeCnt + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+ 43973,74547 45899,68928 54485,67524 63072,66120\
+ 95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+ 102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+ 34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+ 107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+ 41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+ 46299,139871 48829,136075 59202,135063 69575,134052\
+ 106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+ 46931,109511 49715,104703 60024,103501 70334,102300\
+ 108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+ 48196,74723 50474,70169 60657,69030 70840,67892\
+ 108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+ 48829,42592 51359,37532 61605,36267 71852,35002\
+ 109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+ 128857,67252 162473,65260 171997,66691 181521,68123\
+ 186003,75843 187123,97692 188244,119542 188244,199222\
+ 184384,221196 180525,243170 165087,251388 155563,253628\
+ 146039,255869 123379,256617 115100,254625 106821,252633\
+ 98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+ 31250,150650 32250,89650 34750,72525 37250,55400\
+ 46250,47900 56000,46150 65750,44400 95896,46012\
+ 103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+ 124894,217487 107954,214253 97790,213829 87626,213406\
+ 65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v (revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processrxbit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processRxBitsWEn;
+input processRxByteRdy;
+input rst;
+input [1:0]RxBitsIn;
+input RxWireActive;
+output processRxBitRdy;
+output processRxByteWEn;
+output resumeDetected;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processRxBitRdy, next_processRxBitRdy;
+wire processRxBitsWEn;
+wire processRxByteRdy;
+reg processRxByteWEn, next_processRxByteWEn;
+reg resumeDetected, next_resumeDetected;
+wire rst;
+wire [1:0]RxBitsIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+wire RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg [1:0]oldRXBits, next_oldRXBits;
+reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg [3:0]RXBitCount, next_RXBitCount;
+reg [1:0]RxBits, next_RxBits;
+reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg [7:0]RXByte, next_RXByte;
+reg [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+ NextState_prRxBit <= CurrState_prRxBit;
+ // Set default values for outputs and signals
+ next_processRxByteWEn <= processRxByteWEn;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOut <= RxDataOut;
+ next_resumeDetected <= resumeDetected;
+ next_RXBitStMachCurrState <= RXBitStMachCurrState;
+ next_RxBits <= RxBits;
+ next_RXSameBitCount <= RXSameBitCount;
+ next_RXBitCount <= RXBitCount;
+ next_oldRXBits <= oldRXBits;
+ next_RXByte <= RXByte;
+ next_bitStuffError <= bitStuffError;
+ next_resumeWaitCnt <= resumeWaitCnt;
+ next_processRxBitRdy <= processRxBitRdy;
+ case (CurrState_prRxBit) // synopsys parallel_case full_case
+ `START:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOut <= 8'h00;
+ next_resumeDetected <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_RxBits <= 2'b00;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h0;
+ next_oldRXBits <= 2'b00;
+ next_RXByte <= 8'h00;
+ next_bitStuffError <= 1'b0;
+ next_resumeWaitCnt <= 5'h0;
+ next_processRxBitRdy <= 1'b1;
+ NextState_prRxBit <= `WAIT_BITS;
+ end
+ `WAIT_BITS:
+ begin
+ if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+ begin
+ NextState_prRxBit <= `DATA_RX_CHK_SE0;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+ begin
+ NextState_prRxBit <= `RES_RX_CHK;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+ begin
+ NextState_prRxBit <= `RES_END_CHK1;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+ begin
+ NextState_prRxBit <= `IDLE_CHK_KBIT;
+ next_RxBits <= RxBitsIn;
+ next_processRxBitRdy <= 1'b0;
+ end
+ end
+ `IDLE_FIRST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+ next_RXSameBitCount <= 4'h0;
+ next_RXBitCount <= 4'h1;
+ next_oldRXBits <= RxBits;
+ //zero is always the first RZ data bit of a new packet
+ next_RXByte <= 8'h00;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `IDLE_CHK_KBIT:
+ begin
+ if ((RxBits == KBit) && (RxWireActive == 1'b1))
+ begin
+ NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `IDLE_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `IDLE_FIRST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_START;
+ //start of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_LAST_BIT:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_CHK_SE0:
+ begin
+ next_bitStuffError <= 1'b0;
+ if (RxBits == `SE0)
+ begin
+ NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+ if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
+ begin
+ next_RXSameBitCount <= RXSameBitCount + 1'b1;
+ //inc 'RXSameBitCount'
+ if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+ next_bitStuffError <= 1'b1;
+ //flag 'bitStuffError'
+ else //else no bit stuffing error
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= { 1'b1, RXByte[7:1]};
+ //RZ bit <= 1 (ie no change in 'RxBits')
+ end
+ end
+ else //else current 'RxBits' are different from old 'RxBits'
+ begin
+ if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+ begin
+ next_RXBitCount <= RXBitCount + 1'b1;
+ if (RXBitCount != 4'h7) begin
+ next_processRxBitRdy <= 1'b1;
+ //early indication of ready
+ end
+ next_RXByte <= {1'b0, RXByte[7:1]};
+ //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+ end
+ next_RXSameBitCount <= 4'h0;
+ //reset 'RXSameBitCount'
+ end
+ next_oldRXBits <= RxBits;
+ end
+ end
+ `DATA_RX_WAIT_PRB_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_LAST_BIT;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_STOP;
+ //end of packet
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_DATA_DESTUFF:
+ begin
+ if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+ end
+ else if (bitStuffError == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+ end
+ else
+ begin
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ end
+ `DATA_RX_BYTE_SEND2:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_BYTE_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+ next_RXBitCount <= 4'h0;
+ next_RxDataOut <= RXByte;
+ next_RxCtrlOut <= `DATA_STREAM;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `DATA_RX_ERROR_CHK_RES:
+ begin
+ next_processRxByteWEn <= 1'b0;
+ if (RxBits == JBit) //if current bit is a JBit, then
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ //next state is idle
+ else //else
+ begin
+ next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+ //check for resume
+ next_resumeWaitCnt <= 5'h0;
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `DATA_RX_ERROR_WAIT_RDY:
+ begin
+ if (processRxByteRdy == 1'b1)
+ begin
+ NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+ next_RxDataOut <= 8'h00;
+ //redundant data
+ next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+ next_processRxByteWEn <= 1'b1;
+ end
+ end
+ `RES_RX_CHK:
+ begin
+ if (RxBits != KBit) //can only be a resume if line remains in Kbit state
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ else
+ begin
+ next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+ //if we've waited long enough, then
+ if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+ begin
+ next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+ next_resumeDetected <= 1'b1;
+ //report resume detected
+ end
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ `RES_END_CHK1:
+ begin
+ if (RxBits != KBit) //line must leave KBit state for the end of resume
+ begin
+ next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+ next_resumeDetected <= 1'b0;
+ //clear resume detected flag
+ end
+ NextState_prRxBit <= `WAIT_BITS;
+ next_processRxBitRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxBit <= `START;
+ else
+ CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processRxByteWEn <= 1'b0;
+ RxCtrlOut <= 8'h00;
+ RxDataOut <= 8'h00;
+ resumeDetected <= 1'b0;
+ processRxBitRdy <= 1'b1;
+ RXBitStMachCurrState <= `IDLE_BIT_ST;
+ RxBits <= 2'b00;
+ RXSameBitCount <= 4'h0;
+ RXBitCount <= 4'h0;
+ oldRXBits <= 2'b00;
+ RXByte <= 8'h00;
+ bitStuffError <= 1'b0;
+ resumeWaitCnt <= 5'h0;
+ end
+ else
+ begin
+ processRxByteWEn <= next_processRxByteWEn;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOut <= next_RxDataOut;
+ resumeDetected <= next_resumeDetected;
+ processRxBitRdy <= next_processRxBitRdy;
+ RXBitStMachCurrState <= next_RXBitStMachCurrState;
+ RxBits <= next_RxBits;
+ RXSameBitCount <= next_RXSameBitCount;
+ RXBitCount <= next_RXBitCount;
+ oldRXBits <= next_oldRXBits;
+ RXByte <= next_RXByte;
+ bitStuffError <= next_bitStuffError;
+ resumeWaitCnt <= next_resumeWaitCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v (revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processTxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteWEn;
+input rst;
+input [7:0]TxByteCtrlIn;
+input TxByteFullSpeedRateIn;
+input [7:0]TxByteIn;
+input USBWireGnt;
+input USBWireRdy;
+output processTxByteRdy;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+wire [1:0]JBit;
+wire [1:0]KBit;
+reg processTxByteRdy, next_processTxByteRdy;
+wire processTxByteWEn;
+wire rst;
+wire [7:0]TxByteCtrlIn;
+wire TxByteFullSpeedRateIn;
+wire [7:0]TxByteIn;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [3:0]i, next_i;
+reg [7:0]TxByte, next_TxByte;
+reg [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg [1:0]TXLineState, next_TXLineState;
+reg [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+ NextState_prcTxB <= CurrState_prcTxB;
+ // Set default values for outputs and signals
+ next_processTxByteRdy <= processTxByteRdy;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_USBWireReq <= USBWireReq;
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_TxByte <= TxByte;
+ next_TxByteCtrl <= TxByteCtrl;
+ next_TXLineState <= TXLineState;
+ next_TXOneCount <= TXOneCount;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+ case (CurrState_prcTxB) // synopsys parallel_case full_case
+ `START_PTBY:
+ begin
+ next_processTxByteRdy <= 1'b0;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_i <= 4'h0;
+ next_TxByte <= 8'h00;
+ next_TxByteCtrl <= 8'h00;
+ next_TXLineState <= 2'b0;
+ next_TXOneCount <= 4'h0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ next_TxByteFullSpeedRate <= 1'b0;
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `PTBY_WAIT_EN:
+ begin
+ next_processTxByteRdy <= 1'b1;
+ if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_GNT;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_TXOneCount <= 4'h0;
+ next_TXLineState <= JBit;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (processTxByteWEn == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_processTxByteRdy <= 1'b0;
+ next_TxByte <= TxByteIn;
+ next_TxByteCtrl <= TxByteCtrlIn;
+ next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+ next_i <= 4'h0;
+ end
+ end
+ `PTBY_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_WIRE;
+ end
+ end
+ `WAIT_RDY_WIRE:
+ begin
+ if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE1;
+ end
+ else if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `WAIT_RDY_PKT;
+ //actively drive the first J bit
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `WAIT_RDY_PKT:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `SEND_BYTE_UPDATE_BYTE:
+ begin
+ next_i <= i + 1'b1;
+ next_TxByte <= {1'b0, TxByte[7:1] };
+ if (TxByte[0] == 1'b1) //If this bit is 1, then
+ next_TXOneCount <= TXOneCount + 1'b1;
+ //increment 'TXOneCount'
+ else //else this is a zero bit
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ end
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+ end
+ `SEND_BYTE_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+ end
+ else if (i != 4'h8)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ else
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ end
+ `SEND_BYTE_BIT_STUFF:
+ begin
+ next_TXOneCount <= 4'h0;
+ //reset 'TXOneCount'
+ if (TXLineState == JBit)
+ next_TXLineState <= KBit;
+ //toggle the line state
+ else
+ next_TXLineState <= JBit;
+ NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+ end
+ `SEND_BYTE_WAIT_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= TXLineState;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `SEND_BYTE_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (i == 4'h8)
+ begin
+ NextState_prcTxB <= `STOP_CHK;
+ end
+ else
+ begin
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ end
+ end
+ `STOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY2;
+ end
+ `STOP_SND_SE0_1:
+ begin
+ NextState_prcTxB <= `STOP_W_RDY1;
+ end
+ `STOP_CHK:
+ begin
+ if (TxByteCtrl == `DATA_STOP)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_1;
+ end
+ else
+ begin
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ end
+ `STOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY3;
+ end
+ `STOP_SND_IDLE:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `STOP_W_RDY4;
+ end
+ `STOP_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ //release the wire
+ NextState_prcTxB <= `PTBY_WAIT_EN;
+ end
+ `STOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_SE0_2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_J;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_SND_IDLE;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ `STOP_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `STOP_FIN;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE3:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY2;
+ end
+ `LS_START_SND_J1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY3;
+ end
+ `LS_START_SND_IDLE1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE2;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_SND_IDLE2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `LS_START_W_RDY1;
+ end
+ `LS_START_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+ next_i <= 4'h0;
+ end
+ `LS_START_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_IDLE3;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_SND_J1;
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ end
+ end
+ `LS_START_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_prcTxB <= `LS_START_FIN;
+ //Drive the first JBit
+ next_USBWireWEn <= 1'b1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prcTxB <= `START_PTBY;
+ else
+ CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ processTxByteRdy <= 1'b0;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ USBWireReq <= 1'b0;
+ USBWireWEn <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ i <= 4'h0;
+ TxByte <= 8'h00;
+ TxByteCtrl <= 8'h00;
+ TXLineState <= 2'b0;
+ TXOneCount <= 4'h0;
+ TxByteFullSpeedRate <= 1'b0;
+ end
+ else
+ begin
+ processTxByteRdy <= next_processTxByteRdy;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ USBWireReq <= next_USBWireReq;
+ USBWireWEn <= next_USBWireWEn;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ i <= next_i;
+ TxByte <= next_TxByte;
+ TxByteCtrl <= next_TxByteCtrl;
+ TXLineState <= next_TXLineState;
+ TXOneCount <= next_TXOneCount;
+ TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v (revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC16.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [15:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [15:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 16'hffff;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0)
+ begin
+ if (CRCEn == 1'b1) begin
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ ready <= 1'b0;
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[15:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == 4'h7)
+ begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v (revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbTxWireArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input clk;
+input prcTxByteCtrl;
+input [1:0]prcTxByteData;
+input prcTxByteFSRate;
+input prcTxByteReq;
+input prcTxByteWEn;
+input rst;
+input SIETxCtrl;
+input [1:0]SIETxData;
+input SIETxFSRate;
+input SIETxReq;
+input SIETxWEn;
+input USBWireRdyIn;
+output prcTxByteGnt;
+output SIETxGnt;
+output [1:0]TxBits;
+output TxCtl;
+output TxFSRate;
+output USBWireRdyOut;
+output USBWireWEn;
+
+wire clk;
+wire prcTxByteCtrl;
+wire [1:0]prcTxByteData;
+wire prcTxByteFSRate;
+reg prcTxByteGnt, next_prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire rst;
+wire SIETxCtrl;
+wire [1:0]SIETxData;
+wire SIETxFSRate;
+reg SIETxGnt, next_SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+reg [1:0]TxBits, next_TxBits;
+reg TxCtl, next_TxCtl;
+reg TxFSRate, next_TxFSRate;
+wire USBWireRdyIn;
+reg USBWireRdyOut, next_USBWireRdyOut;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+ NextState_txWireArb <= CurrState_txWireArb;
+ // Set default values for outputs and signals
+ next_prcTxByteGnt <= prcTxByteGnt;
+ next_SIETxGnt <= SIETxGnt;
+ next_muxSIENotPTXB <= muxSIENotPTXB;
+ case (CurrState_txWireArb) // synopsys parallel_case full_case
+ `START_TARB:
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ end
+ `TARB_WAIT_REQ:
+ begin
+ if (prcTxByteReq == 1'b1)
+ begin
+ NextState_txWireArb <= `PTXB_ACT;
+ next_prcTxByteGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b0;
+ end
+ else if (SIETxReq == 1'b1)
+ begin
+ NextState_txWireArb <= `SIE_TX_ACT;
+ next_SIETxGnt <= 1'b1;
+ next_muxSIENotPTXB <= 1'b1;
+ end
+ end
+ `PTXB_ACT:
+ begin
+ if (prcTxByteReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_prcTxByteGnt <= 1'b0;
+ end
+ end
+ `SIE_TX_ACT:
+ begin
+ if (SIETxReq == 1'b0)
+ begin
+ NextState_txWireArb <= `TARB_WAIT_REQ;
+ next_SIETxGnt <= 1'b0;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_txWireArb <= `START_TARB;
+ else
+ CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ prcTxByteGnt <= 1'b0;
+ SIETxGnt <= 1'b0;
+ muxSIENotPTXB <= 1'b0;
+ end
+ else
+ begin
+ prcTxByteGnt <= next_prcTxByteGnt;
+ SIETxGnt <= next_SIETxGnt;
+ muxSIENotPTXB <= next_muxSIENotPTXB;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v (revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf (revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+PAGE 12700,12700 215900,279400
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+END
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+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v (revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v (revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts
+`define SC_RX_PACKET_TOUT 18
+
+`endif //usbSlaveControl_h_vdefined
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v (revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// lineControlUpdate.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+ if (fullSpeedPolarity == 1'b1)
+ begin
+ JBit = `ONE_ZERO;
+ KBit = `ZERO_ONE;
+ end
+ else
+ begin
+ JBit = `ZERO_ONE;
+ KBit = `ONE_ZERO;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v (revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// processRxByte
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input processRxDataInWEn;
+input rst;
+input [7:0]RxByteIn;
+input [7:0]RxCtrlIn;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processRxByteRdy;
+output rstCRC;
+output [7:0]RxCtrlOut;
+output [7:0]RxDataOut;
+output RxDataOutWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+reg processRxByteRdy, next_processRxByteRdy;
+wire processRxDataInWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]RxByteIn;
+wire [7:0]RxCtrlIn;
+reg [7:0]RxCtrlOut, next_RxCtrlOut;
+reg [7:0]RxDataOut, next_RxDataOut;
+reg RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg [7:0]RxByte, next_RxByte;
+reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg [7:0]RxCtrl, next_RxCtrl;
+reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+ NextState_prRxByte <= CurrState_prRxByte;
+ // Set default values for outputs and signals
+ next_RxByte <= RxByte;
+ next_RxCtrl <= RxCtrl;
+ next_RXByteStMachCurrState <= RXByteStMachCurrState;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RxOverflow <= RxOverflow;
+ next_RxTimeOut <= RxTimeOut;
+ next_NAKRxed <= NAKRxed;
+ next_stallRxed <= stallRxed;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_RxDataOut <= RxDataOut;
+ next_RxCtrlOut <= RxCtrlOut;
+ next_RxDataOutWEn <= RxDataOutWEn;
+ next_rstCRC <= rstCRC;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_RXDataByteCnt <= RXDataByteCnt;
+ next_processRxByteRdy <= processRxByteRdy;
+ case (CurrState_prRxByte) // synopsys parallel_case full_case
+ `CHK_ST:
+ begin
+ if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+ begin
+ NextState_prRxByte <= `TOKEN_WAIT_CRC;
+ end
+ else if (RXByteStMachCurrState == `HS_BYTE_ST)
+ begin
+ NextState_prRxByte <= `HSHAKE_CHK;
+ end
+ else if (RXByteStMachCurrState == `CHECK_PID_ST)
+ begin
+ NextState_prRxByte <= `CHK_PID_DO_CHK;
+ end
+ else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+ begin
+ NextState_prRxByte <= `CHK_SYNC_DO;
+ end
+ else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+ begin
+ NextState_prRxByte <= `IDLE_CHK_START;
+ end
+ else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+ begin
+ NextState_prRxByte <= `DATA_WAIT_CRC;
+ end
+ end
+ `START_PRBY:
+ begin
+ next_RxByte <= 8'h00;
+ next_RxCtrl <= 8'h00;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxDataOut <= 8'h00;
+ next_RxCtrlOut <= 8'h00;
+ next_RxDataOutWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_RXDataByteCnt <= 10'h00;
+ next_processRxByteRdy <= 1'b1;
+ NextState_prRxByte <= `WAIT_BYTE;
+ end
+ `WAIT_BYTE:
+ begin
+ if (processRxDataInWEn == 1'b1)
+ begin
+ NextState_prRxByte <= `CHK_ST;
+ next_RxByte <= RxByteIn;
+ next_RxCtrl <= RxCtrlIn;
+ next_processRxByteRdy <= 1'b0;
+ end
+ end
+ `HSHAKE_FIN:
+ begin
+ next_RxDataOutWEn <= 1'b0;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `HSHAKE_CHK:
+ begin
+ NextState_prRxByte <= `HSHAKE_FIN;
+ if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RxDataOutWEn <= 1'b1;
+ end
+ `CHK_PID_DO_CHK:
+ begin
+ if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+ begin
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ next_processRxByteRdy <= 1'b1;
+ end
+ else
+ begin
+ NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RxOverflow <= 1'b0;
+ next_NAKRxed <= 1'b0;
+ next_stallRxed <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_RxTimeOut <= 1'b0;
+ next_RXDataByteCnt <= 0;
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_START;
+ next_RxDataOutWEn <= 1'b1;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `CHK_PID_FIRST_BYTE_PROC:
+ begin
+ next_rstCRC <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ case (RxByte[1:0] )
+ `SPECIAL: //Special PID.
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ `TOKEN: //Token PID
+ begin
+ next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ `HANDSHAKE: //Handshake PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_ACKRxed <= 1'b1;
+ 2'b10:
+ next_NAKRxed <= 1'b1;
+ 2'b11:
+ next_stallRxed <= 1'b1;
+ default:
+ begin
+ $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+ end
+ endcase
+ next_RXByteStMachCurrState <= `HS_BYTE_ST;
+ end
+ `DATA: //Data PID
+ begin
+ case (RxByte[3:2] )
+ 2'b00:
+ next_dataSequence <= 1'b0;
+ 2'b10:
+ next_dataSequence <= 1'b1;
+ default:
+ $display ("Invalid DATA PID detected in ProcessRXByte\n");
+ endcase
+ next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+ next_RXDataByteCnt <= 0;
+ end
+ endcase
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_FIN:
+ begin
+ next_CRC16En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `DATA_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC16Result != 16'hb001)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC16En <= 1'b1;
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `DATA_FIN;
+ end
+ `DATA_WAIT_CRC:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `DATA_CHK_STRM;
+ end
+ end
+ `TOKEN_CHK_STRM:
+ begin
+ next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+ case (RxCtrl)
+ `DATA_STOP:
+ begin
+ if (CRC5Result != 5'h6)
+ next_CRCError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_BIT_STUFF_ERROR:
+ begin
+ next_bitStuffError <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ `DATA_STREAM:
+ begin
+ if (RXDataByteCnt > 10'h2)
+ begin
+ next_RxOverflow <= 1'b1;
+ next_RxDataOut <= RxStatus;
+ next_RxCtrlOut <= `RX_PACKET_STOP;
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ end
+ else
+ begin
+ next_RxDataOut <= RxByte;
+ next_RxCtrlOut <= `RX_PACKET_STREAM;
+ next_CRCData <= RxByte;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ end
+ end
+ endcase
+ next_RxDataOutWEn <= 1'b1;
+ NextState_prRxByte <= `TOKEN_FIN;
+ end
+ `TOKEN_FIN:
+ begin
+ next_CRC5En <= 1'b0;
+ next_RxDataOutWEn <= 1'b0;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `TOKEN_WAIT_CRC:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_prRxByte <= `TOKEN_CHK_STRM;
+ end
+ end
+ `CHK_SYNC_DO:
+ begin
+ if (RxByte == `SYNC_BYTE)
+ next_RXByteStMachCurrState <= `CHECK_PID_ST;
+ else
+ next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ `IDLE_CHK_START:
+ begin
+ if (RxCtrl == `DATA_START)
+ next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+ NextState_prRxByte <= `WAIT_BYTE;
+ next_processRxByteRdy <= 1'b1;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_prRxByte <= `START_PRBY;
+ else
+ CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RxDataOut <= 8'h00;
+ RxCtrlOut <= 8'h00;
+ RxDataOutWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ processRxByteRdy <= 1'b1;
+ RxByte <= 8'h00;
+ RxCtrl <= 8'h00;
+ RXByteStMachCurrState <= `IDLE_BYTE_ST;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RxOverflow <= 1'b0;
+ RxTimeOut <= 1'b0;
+ NAKRxed <= 1'b0;
+ stallRxed <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ RXDataByteCnt <= 10'h00;
+ end
+ else
+ begin
+ RxDataOut <= next_RxDataOut;
+ RxCtrlOut <= next_RxCtrlOut;
+ RxDataOutWEn <= next_RxDataOutWEn;
+ rstCRC <= next_rstCRC;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ processRxByteRdy <= next_processRxByteRdy;
+ RxByte <= next_RxByte;
+ RxCtrl <= next_RxCtrl;
+ RXByteStMachCurrState <= next_RXByteStMachCurrState;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RxOverflow <= next_RxOverflow;
+ RxTimeOut <= next_RxTimeOut;
+ NAKRxed <= next_NAKRxed;
+ stallRxed <= next_stallRxed;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ RXDataByteCnt <= next_RXDataByteCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf (revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SIEReceiver\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 23
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 55
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+END
+INSTHEADER 73
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+END
+INSTHEADER 82
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+END
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+END
+INSTHEADER 241
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+W 14 6 0 9 11 BEZIER "Transitions" | 53793,212320 54090,208657 54044,202830 54341,199167
+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
+L 10 11 0 TEXT "State Labels" | 54795,192690 1 0 0 "WAIT_BIT\n/4/"
+S 9 6 20480 ELLIPSE "States" | 54004,218793 6500 6500
+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SIEReceiver"
+F 6 0 671089152 228 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14253,12655 205887,234211
+L 7 6 0 TEXT "Labels" | 17253,231211 1 0 0 "rcvr"
+S 23 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 143681,32406 6500 6500
+L 22 23 0 TEXT "State Labels" | 143681,32406 1 0 0 "DISCNCT"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;"
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+I 16 6 0 Builtin Reset | 25106,221421
+H 39 23 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 40 39 12288 ELLIPSE "States" | 64508,213851 6500 6500
+L 41 40 0 TEXT "State Labels" | 64508,213851 1 0 0 "CHK_RXBITS\n/3/"
+I 42 39 0 Builtin Entry | 42918,241791
+I 43 39 0 Builtin Exit | 147281,109121
+W 44 39 0 42 40 BEZIER "Transitions" | 47426,241791 52025,234967 56275,226064 60875,219240
+S 46 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 142838,49983 6500 6500
+L 47 46 0 TEXT "State Labels" | 142838,49983 1 0 0 "WAIT_FS_CONN"
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 50 54 0 Builtin Exit | 145248,94624
+I 51 54 0 Builtin Entry | 86360,167640
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 59 63 0 Builtin Exit | 129540,111760
+I 60 63 0 Builtin Entry | 86360,167640
+L 61 62 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/1/"
+S 62 63 4096 ELLIPSE "States" | 107950,139700 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+I 68 72 0 Builtin Exit | 131860,37310
+I 69 72 0 Builtin Entry | 64536,194920
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+ 57971,146130 62339,145137 65812,144988 69286,144839\
+ 125497,147159 130261,147357
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+ 54597,124090 58369,121813 62636,121465 66904,121118\
+ 125138,124972 131490,125269
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+ 48543,109011 48344,105238 49038,103700 49733,102162\
+ 52773,100254 56507,99743 60241,99232 74292,101683\
+ 79033,101771 83774,101859 131499,104027 132998,104525
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+ 50130,82213 57873,81220 62984,81170 68095,81121\
+ 127305,85134 133657,85531
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+ 52215,60675 60863,63077 65955,63276 71048,63475\
+ 83004,63522 85042,64000 87080,64479 134402,67217\
+ 135100,67416
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+ 42587,49163 46360,45589 52513,44944 58666,44299\
+ 125961,48736 136382,49232
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+ 164206,62109 167707,83613 169507,92702
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+ 41595,29611 48940,28220 55540,28071 62140,27923\
+ 127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+ 22117,178006 22117,149970 33211,139263 44305,128556\
+ 88681,113764 103817,110238 118953,106712 136069,108777\
+ 144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+ 188903,162522 181196,168609 172535,178212 163875,187816\
+ 140506,197413 125270,198727 110035,200042 80303,196085\
+ 61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `LOW_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `CONNECT_WAIT_TIME) \n begin\n connectState <= `FULL_SPEED_CONNECT;\n RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n end\nend\nelse\nbegin\n RXStMachCurrState = `DISCONNECT_ST;\nend"
+W 169 72 0 71 68 BEZIER "Transitions" | 86442,160488 87123,152997 131179,46721 131860,39230
+S 174 81 53248 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/6/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+S 185 90 57344 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/7/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n RXWaitCount <= RXWaitCount + 1'b1;\n if (RXWaitCount == `DISCONNECT_WAIT_TIME) \n begin\n RXStMachCurrState <= `DISCONNECT_ST;\n connectState = `DISCONNECT;\n end\nend\nelse\nbegin\n RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n RXWaitCount <= 0;\nend"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v (revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSerialInterfaceEngine.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+ clk, rst,
+ //readUSBWireData
+ USBWireDataIn,
+ USBWireDataInTick,
+ //writeUSBWireData
+ USBWireDataOut,
+ USBWireCtrlOut,
+ USBWireDataOutTick,
+ //SIEReceiver
+ connectState,
+ //processRxBit
+ resumeDetected,
+ //processRxByte
+ RxCtrlOut,
+ RxDataOutWEn,
+ RxDataOut,
+ //SIETransmitter
+ SIEPortCtrlIn,
+ SIEPortDataIn,
+ SIEPortTxRdy,
+ SIEPortWEn,
+ //lineControlUpdate
+ fullSpeedPolarity,
+ fullSpeedBitRate,
+ noActivityTimeOut,
+ noActivityTimeOutEnable
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+output noActivityTimeOut;
+input noActivityTimeOutEnable;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut;
+output RxDataOutWEn;
+output [7:0] RxDataOut;
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy;
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut;
+wire RxDataOutWEn;
+wire [7:0] RxDataOut;
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy;
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En;
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En;
+wire [4:0] RxCRC5Result;
+wire RxCRC5_8Bit;
+wire [7:0] RxCRCData;
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En;
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En;
+wire [4:0] TxCRC5Result;
+wire TxCRC5_8Bit;
+wire [7:0] TxCRCData;
+wire TxRstCRC;
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy;
+wire processTxByteWEn;
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+ (.fullSpeedPolarity(fullSpeedPolarity),
+ .fullSpeedBitRate(fullSpeedBitRate),
+ .JBit(JBit),
+ .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+ (
+ .RxWireDataIn(RxWireDataFromWireRx),
+ .RxWireDataWEn(RxWireDataWEn),
+ .clk(clk),
+ .connectState(connectState),
+ .rst(rst) );
+
+
+processRxBit u_processRxBit
+ (.JBit(JBit),
+ .KBit(KBit),
+ .RxBitsIn(RxWireDataFromWireRx),
+ .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
+ .clk(clk),
+ .processRxBitRdy(processRxBitRdy),
+ .processRxBitsWEn(RxWireDataWEn),
+ .processRxByteWEn(processRxByteWEn),
+ .resumeDetected(resumeDetected),
+ .rst(rst),
+ .processRxByteRdy(processRxByteRdy),
+ .RxWireActive(RxWireActive)
+ );
+
+processRxByte u_processRxByte
+ (.CRC16En(RxCRC16En),
+ .CRC16Result(RxCRC16Result),
+ .CRC16UpdateRdy(RxCRC16UpdateRdy),
+ .CRC5En(RxCRC5En),
+ .CRC5Result(RxCRC5Result),
+ .CRC5_8Bit(RxCRC5_8Bit),
+ .CRC5UpdateRdy(RxCRC5UpdateRdy),
+ .CRCData(RxCRCData),
+ .RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
+ .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
+ .RxCtrlOut(RxCtrlOut),
+ .RxDataOutWEn(RxDataOutWEn),
+ .RxDataOut(RxDataOut),
+ .clk(clk),
+ .processRxDataInWEn(processRxByteWEn),
+ .rst(rst),
+ .rstCRC(RxRstCRC),
+ .processRxByteRdy(processRxByteRdy) );
+
+
+updateCRC5 RxUpdateCRC5
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC5Result),
+ .CRCEn(RxCRC5En),
+ .CRC5_8BitIn(RxCRC5_8Bit),
+ .dataIn(RxCRCData),
+ .ready(RxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 RxUpdateCRC16
+ (.rstCRC(RxRstCRC),
+ .CRCResult(RxCRC16Result),
+ .CRCEn(RxCRC16En),
+ .dataIn(RxCRCData),
+ .ready(RxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+SIETransmitter u_SIETransmitter
+ (.CRC16En(TxCRC16En),
+ .CRC16Result(TxCRC16Result),
+ .CRC5En(TxCRC5En),
+ .CRC5Result(TxCRC5Result),
+ .CRC5_8Bit(TxCRC5_8Bit),
+ .CRCData(TxCRCData),
+ .CRC5UpdateRdy(TxCRC5UpdateRdy),
+ .CRC16UpdateRdy(TxCRC16UpdateRdy),
+ .JBit(JBit),
+ .KBit(KBit),
+ .SIEPortCtrlIn(SIEPortCtrlIn),
+ .SIEPortDataIn(SIEPortDataIn),
+ .SIEPortTxRdy(SIEPortTxRdy),
+ .SIEPortWEn(SIEPortWEn),
+ .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
+ .TxByteOut(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(SIETxCtrl),
+ .USBWireData(SIETxData),
+ .USBWireGnt(SIETxGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(SIETxReq),
+ .USBWireWEn(SIETxWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .rstCRC(TxRstCRC),
+ .USBWireFullSpeedRate(SIEFsRate),
+ .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+ .fullSpeedRateIn(fullSpeedBitRate)
+ );
+
+updateCRC5 TxUpdateCRC5
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC5Result),
+ .CRCEn(TxCRC5En),
+ .CRC5_8BitIn(TxCRC5_8Bit),
+ .dataIn(TxCRCData),
+ .ready(TxCRC5UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+updateCRC16 TxUpdateCRC16
+ (.rstCRC(TxRstCRC),
+ .CRCResult(TxCRC16Result),
+ .CRCEn(TxCRC16En),
+ .dataIn(TxCRCData),
+ .ready(TxCRC16UpdateRdy),
+ .clk(clk),
+ .rst(rst) );
+
+processTxByte u_processTxByte
+ (.JBit(JBit),
+ .KBit(KBit),
+ .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
+ .TxByteIn(TxByteFromSIEToPrcTxByte),
+ .USBWireCtrl(prcTxByteCtrl),
+ .USBWireData(prcTxByteData),
+ .USBWireGnt(prcTxByteGnt),
+ .USBWireRdy(USBWireReadyFromTxArb),
+ .USBWireReq(prcTxByteReq),
+ .USBWireWEn(prcTxByteWEn),
+ .clk(clk),
+ .processTxByteRdy(processTxByteRdy),
+ .processTxByteWEn(processTxByteWEn),
+ .rst(rst),
+ .USBWireFullSpeedRate(prcTxByteFSRate),
+ .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+ );
+
+USBTxWireArbiter u_USBTxWireArbiter
+ (.SIETxCtrl(SIETxCtrl),
+ .SIETxData(SIETxData),
+ .SIETxGnt(SIETxGnt),
+ .SIETxReq(SIETxReq),
+ .SIETxWEn(SIETxWEn),
+ .TxBits(TxBitsFromArbToWire),
+ .TxCtl(TxCtrlFromArbToWire),
+ .USBWireRdyIn(USBWireRdy),
+ .USBWireRdyOut(USBWireReadyFromTxArb),
+ .USBWireWEn(USBWireWEn),
+ .clk(clk),
+ .prcTxByteCtrl(prcTxByteCtrl),
+ .prcTxByteData(prcTxByteData),
+ .prcTxByteGnt(prcTxByteGnt),
+ .prcTxByteReq(prcTxByteReq),
+ .prcTxByteWEn(prcTxByteWEn),
+ .rst(rst),
+ .SIETxFSRate(SIEFsRate),
+ .prcTxByteFSRate(prcTxByteFSRate),
+ .TxFSRate(FSRateFromArbiterToWire)
+ );
+
+writeUSBWireData u_writeUSBWireData
+ (.TxBitsIn(TxBitsFromArbToWire),
+ .TxBitsOut(USBWireDataOut),
+ .TxDataOutTick(USBWireDataOutTick),
+ .TxCtrlIn(TxCtrlFromArbToWire),
+ .TxCtrlOut(USBWireCtrlOut),
+ .USBWireRdy(USBWireRdy),
+ .USBWireWEn(USBWireWEn),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .fullSpeedRate(FSRateFromArbiterToWire),
+ .clk(clk),
+ .rst(rst)
+ );
+
+
+
+readUSBWireData u_readUSBWireData
+ (.RxBitsIn(USBWireDataIn),
+ .RxDataInTick(USBWireDataInTick),
+ .RxBitsOut(RxWireDataFromWireRx),
+ .SIERxRdyIn(processRxBitRdy),
+ .SIERxWEn(RxWireDataWEn),
+ .fullSpeedRate(fullSpeedBitRate),
+ .TxWireActiveDrive(TxWireActiveDrive),
+ .clk(clk),
+ .rst(rst),
+ .noActivityTimeOut(noActivityTimeOut),
+ .RxWireActive(RxWireActive),
+ .noActivityTimeOutEnable(noActivityTimeOutEnable)
+ );
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v (revision 264)
@@ -0,0 +1,527 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol;
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg NAKSentInSTB;
+reg SOFRxedInSTB;
+reg resetEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrEP0ReadySTB;
+reg clrEP1ReadySTB;
+reg clrEP2ReadySTB;
+reg clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB;
+reg fullSpeedRateSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP3StatusRegSTB;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP1TransTypeRegSTB;
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP2TransTypeRegSTB;
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP3TransTypeRegSTB;
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [10:0] frameNumSTB;
+
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0IsoEn <= 1'b0;
+ EP0SendStall <= 1'b0;
+ EP0DataSequence <= 1'b0;
+ EP0Enable <= 1'b0;
+ EP1IsoEn <= 1'b0;
+ EP1SendStall <= 1'b0;
+ EP1DataSequence <= 1'b0;
+ EP1Enable <= 1'b0;
+ EP2IsoEn <= 1'b0;
+ EP2SendStall <= 1'b0;
+ EP2DataSequence <= 1'b0;
+ EP2Enable <= 1'b0;
+ EP3IsoEn <= 1'b0;
+ EP3SendStall <= 1'b0;
+ EP3DataSequence <= 1'b0;
+ EP3Enable <= 1'b0;
+ SCControlReg <= 6'h00;
+ SCAddrReg <= 7'h00;
+ interruptMaskReg <= 5'h00;
+ end
+ else begin
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP1_CTRL_REG : begin
+ EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP2_CTRL_REG : begin
+ EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP3_CTRL_REG : begin
+ EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+ clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+ clrResetReq <= dataIn[`RESET_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ NAKSentInt <= 1'b0;
+ SOFRxedInt <= 1'b0;
+ resetEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (NAKSentInSTB == 1'b1)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedInSTB == 1'b1)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventInSTB == 1'b1)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntInSTB == 1'b1)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneInSTB == 1'b1)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0Ready <= 1'b0;
+ EP1Ready <= 1'b0;
+ EP2Ready <= 1'b0;
+ EP3Ready <= 1'b0;
+ end
+ else begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0ReadySTB == 1'b1)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1ReadySTB == 1'b1)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2ReadySTB == 1'b1)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3ReadySTB == 1'b1)
+ EP3Ready <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
+begin
+ endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+// async read mux
+// FIX ME
+// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
+// some translation bug
+always @(address or
+ EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+ EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+ EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+ EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+ EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
+ endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
+ endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or
+ endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
+ SCControlReg or connectStateIn or
+ NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+ interruptMaskReg or SCAddrReg or frameNumSTB)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+ `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+ `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+ `EP1_STS_REG : dataOut <= EP1StatusRegSTB;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+ `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+ `EP2_STS_REG : dataOut <= EP2StatusRegSTB;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+ `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+ `EP3_STS_REG : dataOut <= EP3StatusRegSTB;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+ `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+//re-sync from busClk to usbClk.
+always @(posedge usbClk) begin
+ endP0ControlReg <= endP0ControlRegSTB;
+ endP1ControlReg <= endP1ControlRegSTB;
+ endP2ControlReg <= endP2ControlRegSTB;
+ endP3ControlReg <= endP3ControlRegSTB;
+ SCGlobalEn <= SCGlobalEnSTB;
+ TxLineState <= TxLineStateSTB;
+ LineDirectControlEn <= LineDirectControlEnSTB;
+ fullSpeedPol <= fullSpeedPolSTB;
+ fullSpeedRate <= fullSpeedRateSTB;
+end
+
+//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+ NAKSentInSTB <= NAKSentIn;
+ SOFRxedInSTB <= SOFRxedIn;
+ resetEventInSTB <= resetEventIn;
+ resumeIntInSTB <= resumeIntIn;
+ transDoneInSTB <= transDoneIn;
+ clrEP0ReadySTB <= clrEP0Ready;
+ clrEP1ReadySTB <= clrEP1Ready;
+ clrEP2ReadySTB <= clrEP2Ready;
+ clrEP3ReadySTB <= clrEP3Ready;
+ EP0StatusRegSTB <= EP0StatusReg;
+ EP1StatusRegSTB <= EP1StatusReg;
+ EP2StatusRegSTB <= EP2StatusReg;
+ EP3StatusRegSTB <= EP3StatusReg;
+ endP0TransTypeRegSTB <= endP0TransTypeReg;
+ endP1TransTypeRegSTB <= endP1TransTypeReg;
+ endP2TransTypeRegSTB <= endP2TransTypeReg;
+ endP3TransTypeRegSTB <= endP3TransTypeReg;
+ endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
+ endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
+ endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
+ endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
+ frameNumSTB <= frameNum;
+end
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v (revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input clk;
+input [7:0]directCntlCntl;
+input [7:0]directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input SCTxPortRdyIn;
+input [7:0]sendPacketCntl;
+input [7:0]sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output directCntlGnt;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output sendPacketGnt;
+
+wire clk;
+wire [7:0]directCntlCntl;
+wire [7:0]directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire [7:0]sendPacketCntl;
+wire [7:0]sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb) // synopsys parallel_case full_case
+ `SARB1_WAIT_REQ:
+ begin
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ end
+ `SARB_SEND_PACKET:
+ begin
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ end
+ `SARB_DC:
+ begin
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ end
+ `START_SARB:
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ muxDCEn <= 1'b0;
+ end
+ else
+ begin
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ muxDCEn <= next_muxDCEn;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v (revision 264)
@@ -0,0 +1,390 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut, SIERxTimeOutEn);
+input clk;
+input endPointReady;
+input getPacketEn;
+input rst;
+input [7:0]RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0]RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+output ACKRxed;
+output bitStuffError;
+output CRCError;
+output dataSequence;
+output [7:0]RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output [3:0]RxPID;
+output RXTimeOut;
+output SIERxTimeOutEn;
+
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+wire endPointReady;
+wire getPacketEn;
+wire rst;
+wire [7:0]RXDataIn;
+wire RXDataValid;
+reg [7:0]RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+reg [3:0]RxPID, next_RxPID;
+wire [7:0]RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+wire SIERxTimeOut;
+reg SIERxTimeOutEn, next_SIERxTimeOutEn;
+
+// diagram signals declarations
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_slvGetPkt)
+begin
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_RXOverflow <= RXOverflow;
+ next_ACKRxed <= ACKRxed;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RXByteOldest <= RXByteOldest;
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_dataSequence <= dataSequence;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXTimeOut <= RXTimeOut;
+ next_RxPID <= RxPID;
+ next_SIERxTimeOutEn <= SIERxTimeOutEn;
+ case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+ `START_GP:
+ begin
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b1;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `CHK_PKT_START:
+ begin
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b0;
+ if (getPacketEn == 1'b1)
+ begin
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ begin
+ if (RXByte[1:0] == `HANDSHAKE)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ end
+ else if (RXByte[1:0] == `DATA)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ end
+ `PROC_PKT_HS:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ end
+ `PROC_PKT_DATA_W_D1:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D2:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_W_D3:
+ begin
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ begin
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ begin
+ if (endPointReady == 1'b0)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+ end
+ else if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ end
+ `PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ RXOverflow <= 1'b0;
+ ACKRxed <= 1'b0;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ dataSequence <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXTimeOut <= 1'b0;
+ RxPID <= 4'h0;
+ SIERxTimeOutEn <= 1'b0;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByteOld <= 8'h00;
+ end
+ else
+ begin
+ RXOverflow <= next_RXOverflow;
+ ACKRxed <= next_ACKRxed;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ dataSequence <= next_dataSequence;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXTimeOut <= next_RXTimeOut;
+ RxPID <= next_RxPID;
+ SIERxTimeOutEn <= next_SIERxTimeOutEn;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXByteOldest <= next_RXByteOldest;
+ RXByteOld <= next_RXByteOld;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf (revision 264)
@@ -0,0 +1,304 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=455
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+END
+INSTHEADER 51
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\n//now wait for 'transReq' to clear"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
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+ 170250,145750 137550,145450 128737,144962 119925,144475\
+ 117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
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+I 55 52 0 Builtin Entry | 88756,239499
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+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
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+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
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+ 110726,37400 115182,37514 117348,37514
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+ 129080,35838 133536,35952 135702,35952
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+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
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+ 79528,15331 86976,12405 94012,13028 97964,12876
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+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
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+I 96 6 0 Builtin Reset | 67359,192312
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+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+ 134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+ 58620,51804 60468,38868 64038,33660 67608,28452\
+ 80040,20556 84492,18330 88944,16104 95212,13380\
+ 97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+ 41567,48930 50502,39578 58559,36864 66617,34151\
+ 89914,32647 97658,32793 105403,32939 113545,36471\
+ 117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+L 445 446 0 TEXT "State Labels" | 91983,29847 1 0 0 "DEL1\n/33/"
+S 446 6 151552 ELLIPSE "States" | 91983,29847 6500 6500
+L 447 448 0 TEXT "State Labels" | 71118,38835 1 0 0 "DEL2\n/34/"
+S 448 6 155648 ELLIPSE "States" | 71118,38835 6500 6500
+W 451 6 0 294 446 BEZIER "Transitions" | 113064,28940 108490,29421 103055,29490 98481,29971
+W 452 6 0 446 448 BEZIER "Transitions" | 86012,32413 83123,33616 79949,35000 77060,36203
+W 454 6 0 448 41 BEZIER "Transitions" | 67046,43901 63355,51524 38215,83856 36770,94047\
+ 35326,104238 36932,129759 42870,138987 48808,148215\
+ 70958,159612 79745,162701 88532,165790 99731,166612\
+ 106231,167093
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v (revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input clk;
+input [7:0]fifoData;
+input fifoEmpty;
+input fullSpeedPolarity;
+input HCTxPortGnt;
+input HCTxPortRdy;
+input [3:0]PID;
+input rst;
+input sendPacketWEn;
+input [6:0]TxAddr;
+input [3:0]TxEndP;
+output fifoReadEn;
+output [10:0]frameNum;
+output [7:0]HCTxPortCntl;
+output [7:0]HCTxPortData;
+output HCTxPortReq;
+output HCTxPortWEn;
+output sendPacketRdy;
+
+wire clk;
+wire [7:0]fifoData;
+wire fifoEmpty;
+reg fifoReadEn, next_fifoReadEn;
+reg [10:0]frameNum, next_frameNum;
+wire fullSpeedPolarity;
+reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg [7:0]HCTxPortData, next_HCTxPortData;
+wire HCTxPortGnt;
+wire HCTxPortRdy;
+reg HCTxPortReq, next_HCTxPortReq;
+reg HCTxPortWEn, next_HCTxPortWEn;
+wire [3:0]PID;
+wire rst;
+reg sendPacketRdy, next_sendPacketRdy;
+wire sendPacketWEn;
+wire [6:0]TxAddr;
+wire [3:0]TxEndP;
+
+// diagram signals declarations
+reg [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <= { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+ NextState_sndPkt <= CurrState_sndPkt;
+ // Set default values for outputs and signals
+ next_sendPacketRdy <= sendPacketRdy;
+ next_fifoReadEn <= fifoReadEn;
+ next_HCTxPortData <= HCTxPortData;
+ next_HCTxPortCntl <= HCTxPortCntl;
+ next_HCTxPortWEn <= HCTxPortWEn;
+ next_HCTxPortReq <= HCTxPortReq;
+ next_frameNum <= frameNum;
+ case (CurrState_sndPkt) // synopsys parallel_case full_case
+ `START_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ end
+ `WAIT_ENABLE:
+ begin
+ if (sendPacketWEn == 1'b1)
+ begin
+ NextState_sndPkt <= `SP_WAIT_GNT;
+ next_sendPacketRdy <= 1'b0;
+ next_HCTxPortReq <= 1'b1;
+ end
+ end
+ `SP_WAIT_GNT:
+ begin
+ if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+ begin
+ NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+ end
+ else if (HCTxPortGnt == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+ end
+ end
+ `FIN_SP:
+ begin
+ NextState_sndPkt <= `WAIT_ENABLE;
+ next_sendPacketRdy <= 1'b1;
+ next_HCTxPortReq <= 1'b0;
+ end
+ `SEND_PID_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_PID_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= PIDNotPID;
+ next_HCTxPortCntl <= `TX_PACKET_START;
+ end
+ end
+ `SEND_PID_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ if (PID == `DATA0 || PID == `DATA1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ else if (PID == `SOF)
+ begin
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+ end
+ else if (PID == `OUT ||
+ PID == `IN ||
+ PID == `SETUP)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sndPkt <= `FIN_SP;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY1:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_WAIT_RDY2:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `OUT_IN_SETUP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `OUT_IN_SETUP_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+ end
+ `SEND_SOF_FIN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ next_frameNum <= frameNum + 1'b1;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `SEND_SOF_WAIT_RDY3:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= frameNum[7:0];
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_WAIT_RDY4:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `SEND_SOF_FIN1;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ end
+ end
+ `SEND_SOF_CLR_WEN1:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+ end
+ `DATA0_DATA1_READ_FIFO:
+ begin
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= fifoData;
+ next_HCTxPortCntl <= `TX_PACKET_STREAM;
+ NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+ end
+ `DATA0_DATA1_WAIT_READ_FIFO:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+ next_fifoReadEn <= 1'b1;
+ end
+ end
+ `DATA0_DATA1_FIFO_EMPTY:
+ begin
+ if (fifoEmpty == 1'b0)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+ end
+ else
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+ end
+ end
+ `DATA0_DATA1_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ `DATA0_DATA1_TERM_BYTE:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `DATA0_DATA1_FIN;
+ //Last byte is not valid data,
+ //but the 'TX_PACKET_STOP' flag is required
+ //by the SIE state machine to detect end of data packet
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_PACKET_STOP;
+ end
+ end
+ `DATA0_DATA1_CLR_WEN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+ end
+ `DATA0_DATA1_CLR_REN:
+ begin
+ next_fifoReadEn <= 1'b0;
+ NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+ end
+ `LS_EOP_WAIT_RDY:
+ begin
+ if (HCTxPortRdy == 1'b1)
+ begin
+ NextState_sndPkt <= `LS_EOP_FIN;
+ next_HCTxPortWEn <= 1'b1;
+ next_HCTxPortData <= 8'h00;
+ next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+ end
+ end
+ `LS_EOP_FIN:
+ begin
+ next_HCTxPortWEn <= 1'b0;
+ NextState_sndPkt <= `FIN_SP;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sndPkt <= `START_SP;
+ else
+ CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketRdy <= 1'b1;
+ fifoReadEn <= 1'b0;
+ HCTxPortData <= 8'h00;
+ HCTxPortCntl <= 8'h00;
+ HCTxPortWEn <= 1'b0;
+ HCTxPortReq <= 1'b0;
+ frameNum <= 11'h000;
+ end
+ else
+ begin
+ sendPacketRdy <= next_sendPacketRdy;
+ fifoReadEn <= next_fifoReadEn;
+ HCTxPortData <= next_HCTxPortData;
+ HCTxPortCntl <= next_HCTxPortCntl;
+ HCTxPortWEn <= next_HCTxPortWEn;
+ HCTxPortReq <= next_HCTxPortReq;
+ frameNum <= next_frameNum;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v (revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sendpacketcheckpreamble
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input clk;
+input preAmbleEnable;
+input rst;
+input [3:0]sendPacketCPPID;
+input sendPacketCPWEn;
+input sendPacketRdy;
+output sendPacketCPReady;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+
+wire clk;
+wire preAmbleEnable;
+wire rst;
+wire [3:0]sendPacketCPPID;
+reg sendPacketCPReady, next_sendPacketCPReady;
+wire sendPacketCPWEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+ NextState_sendPktCP <= CurrState_sendPktCP;
+ // Set default values for outputs and signals
+ next_sendPacketCPReady <= sendPacketCPReady;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ case (CurrState_sendPktCP) // synopsys parallel_case full_case
+ `SPC_WAIT_EN:
+ begin
+ if (sendPacketCPWEn == 1'b1)
+ begin
+ NextState_sendPktCP <= `CHK_PREAM;
+ next_sendPacketCPReady <= 1'b0;
+ end
+ end
+ `START_SPC:
+ begin
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `CHK_PREAM:
+ begin
+ if (preAmbleEnable == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+ end
+ end
+ `READY:
+ begin
+ next_sendPacketCPReady <= 1'b1;
+ NextState_sendPktCP <= `SPC_WAIT_EN;
+ end
+ `PREAM_PKT_SND_PREAM:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `PREAMBLE;
+ NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+ end
+ `PREAM_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+ end
+ end
+ `PREAM_PKT_PREAM_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+ end
+ `PREAM_PKT_SND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+ end
+ `PREAM_PKT_PID_SENT:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+ end
+ `PREAM_PKT_WAIT_RDY2:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+ end
+ end
+ `PREAM_PKT_WAIT_RDY3:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `READY;
+ end
+ end
+ `REG_PKT_SEND_PID:
+ begin
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= sendPacketCPPID;
+ NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+ end
+ `REG_PKT_WAIT_RDY1:
+ begin
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_sendPktCP <= `REG_PKT_SEND_PID;
+ end
+ end
+ `REG_PKT_WAIT_RDY:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ NextState_sendPktCP <= `READY;
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_sendPktCP <= `START_SPC;
+ else
+ CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ sendPacketCPReady <= 1'b1;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ end
+ else
+ begin
+ sendPacketCPReady <= next_sendPacketCPReady;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v (revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// softransmit
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input clk;
+input rst;
+input sendPacketArbiterGnt;
+input sendPacketRdy;
+input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input SOFSyncEn;
+input [15:0]SOFTimer;
+output sendPacketArbiterReq;
+output sendPacketWEn;
+output SOFSent; // single cycle pulse
+output SOFTimerClr; // Single cycle pulse
+
+wire clk;
+wire rst;
+wire sendPacketArbiterGnt;
+reg sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+wire SOFEnable;
+reg SOFSent, next_SOFSent;
+wire SOFSyncEn;
+wire [15:0]SOFTimer;
+reg SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+ NextState_SOFTx <= CurrState_SOFTx;
+ // Set default values for outputs and signals
+ next_SOFSent <= SOFSent;
+ next_SOFTimerClr <= SOFTimerClr;
+ next_sendPacketArbiterReq <= sendPacketArbiterReq;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_i <= i;
+ case (CurrState_SOFTx) // synopsys parallel_case full_case
+ `START_STX:
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ `WAIT_SOF_NEAR:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+ (SOFSyncEn == 1'b1 &&
+ SOFEnable == 1'b1))
+ begin
+ NextState_SOFTx <= `WAIT_SP_GNT;
+ next_sendPacketArbiterReq <= 1'b1;
+ end
+ end
+ `WAIT_SP_GNT:
+ begin
+ if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NOW;
+ end
+ end
+ `WAIT_SOF_NOW:
+ begin
+ if (SOFTimer >= `SOF_TX_TIME)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_sendPacketWEn <= 1'b1;
+ next_SOFTimerClr <= 1'b1;
+ next_SOFSent <= 1'b1;
+ end
+ else if (SOFEnable == 1'b0)
+ begin
+ NextState_SOFTx <= `SOF_FIN;
+ next_SOFTimerClr <= 1'b1;
+ end
+ end
+ `SOF_FIN:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ next_SOFTimerClr <= 1'b0;
+ next_SOFSent <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK1;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK1:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `DLY_SOF_CHK2;
+ next_sendPacketArbiterReq <= 1'b0;
+ next_i <= 8'h00;
+ end
+ end
+ `DLY_SOF_CHK2:
+ begin
+ next_i <= i + 1'b1;
+ if (i==8'hff)
+ begin
+ NextState_SOFTx <= `WAIT_SOF_NEAR;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SOFTx <= `START_STX;
+ else
+ CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SOFSent <= 1'b0;
+ SOFTimerClr <= 1'b0;
+ sendPacketArbiterReq <= 1'b0;
+ sendPacketWEn <= 1'b0;
+ i <= 8'h00;
+ end
+ else
+ begin
+ SOFSent <= next_SOFSent;
+ SOFTimerClr <= next_SOFTimerClr;
+ sendPacketArbiterReq <= next_sendPacketArbiterReq;
+ sendPacketWEn <= next_sendPacketWEn;
+ i <= next_i;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v (revision 264)
@@ -0,0 +1,125 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// hostSlaveMuxBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+ hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClkOut == 1'b1)
+ hostMode <= 1'b0;
+ else begin
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+ hostMode <= dataIn[0];
+ end
+ if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+ rstFromBus <= 1'b1;
+ else
+ rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+ case (address)
+ `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+ `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+ endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+ if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
+ rstShift <= 6'b111111;
+ else
+ rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+ rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+ rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+ rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v (revision 264)
@@ -0,0 +1,104 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+`define RX_EDGE_DET_TOUT 7
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
+`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v (revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SIETransmitter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input clk;
+input [15:0]CRC16Result;
+input CRC16UpdateRdy;
+input [4:0]CRC5Result;
+input CRC5UpdateRdy;
+input fullSpeedRateIn;
+input [1:0]JBit;
+input [1:0]KBit;
+input processTxByteRdy;
+input rst;
+input [7:0]SIEPortCtrlIn;
+input [7:0]SIEPortDataIn;
+input SIEPortWEn;
+input USBWireGnt;
+input USBWireRdy;
+output CRC16En;
+output CRC5_8Bit;
+output CRC5En;
+output [7:0]CRCData;
+output processTxByteWEn;
+output rstCRC;
+output SIEPortTxRdy;
+output [7:0]TxByteOut;
+output [7:0]TxByteOutCtrl;
+output TxByteOutFullSpeedRate;
+output USBWireCtrl;
+output [1:0]USBWireData;
+output USBWireFullSpeedRate;
+output USBWireReq;
+output USBWireWEn;
+
+wire clk;
+reg CRC16En, next_CRC16En;
+wire [15:0]CRC16Result;
+wire CRC16UpdateRdy;
+reg CRC5_8Bit, next_CRC5_8Bit;
+reg CRC5En, next_CRC5En;
+wire [4:0]CRC5Result;
+wire CRC5UpdateRdy;
+reg [7:0]CRCData, next_CRCData;
+wire fullSpeedRateIn;
+wire [1:0]JBit;
+wire [1:0]KBit;
+wire processTxByteRdy;
+reg processTxByteWEn, next_processTxByteWEn;
+wire rst;
+reg rstCRC, next_rstCRC;
+wire [7:0]SIEPortCtrlIn;
+wire [7:0]SIEPortDataIn;
+reg SIEPortTxRdy, next_SIEPortTxRdy;
+wire SIEPortWEn;
+reg [7:0]TxByteOut, next_TxByteOut;
+reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg USBWireCtrl, next_USBWireCtrl;
+reg [1:0]USBWireData, next_USBWireData;
+reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire USBWireGnt;
+wire USBWireRdy;
+reg USBWireReq, next_USBWireReq;
+reg USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg [2:0]i, next_i;
+reg [15:0]resumeCnt, next_resumeCnt;
+reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+ NextState_SIETx <= CurrState_SIETx;
+ // Set default values for outputs and signals
+ next_USBWireWEn <= USBWireWEn;
+ next_i <= i;
+ next_USBWireReq <= USBWireReq;
+ next_processTxByteWEn <= processTxByteWEn;
+ next_rstCRC <= rstCRC;
+ next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+ next_TxByteOut <= TxByteOut;
+ next_TxByteOutCtrl <= TxByteOutCtrl;
+ next_USBWireData <= USBWireData;
+ next_USBWireCtrl <= USBWireCtrl;
+ next_CRCData <= CRCData;
+ next_CRC5En <= CRC5En;
+ next_CRC5_8Bit <= CRC5_8Bit;
+ next_CRC16En <= CRC16En;
+ next_SIEPortTxRdy <= SIEPortTxRdy;
+ next_SIEPortData <= SIEPortData;
+ next_SIEPortCtrl <= SIEPortCtrl;
+ next_resumeCnt <= resumeCnt;
+ next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+ case (CurrState_SIETx) // synopsys parallel_case full_case
+ `IDLE:
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `START_SIETX:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_TxByteOut <= 8'h00;
+ next_TxByteOutCtrl <= 8'h00;
+ next_USBWireData <= 2'b00;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireReq <= 1'b0;
+ next_USBWireWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ next_CRCData <= 8'h00;
+ next_CRC5En <= 1'b0;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC16En <= 1'b0;
+ next_SIEPortTxRdy <= 1'b0;
+ next_SIEPortData <= 8'h00;
+ next_SIEPortCtrl <= 8'h00;
+ next_i <= 3'h0;
+ next_resumeCnt <= 16'h0000;
+ next_TxByteOutFullSpeedRate <= 1'b0;
+ next_USBWireFullSpeedRate <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `STX_CHK_ST:
+ begin
+ if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ next_TxByteOutFullSpeedRate <= 1'b1;
+ //SOF and PRE always at full speed
+ end
+ else if (SIEPortCtrl == `TX_PACKET_START)
+ begin
+ NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+ end
+ else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ end
+ else if (SIEPortCtrl == `TX_IDLE)
+ begin
+ NextState_SIETx <= `IDLE;
+ end
+ else if (SIEPortCtrl == `TX_RESUME_START)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_GNT;
+ next_USBWireReq <= 1'b1;
+ next_resumeCnt <= 16'h0000;
+ next_USBWireFullSpeedRate <= 1'b0;
+ //resume always uses low speed timing
+ end
+ end
+ `STX_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `STX_CHK_ST;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ end
+ `DIR_CTL_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_i <= i + 1'b1;
+ if (i == 3'h7)
+ begin
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_SIETx <= `DIR_CTL_DELAY;
+ end
+ end
+ `DIR_CTL_WAIT_GNT:
+ begin
+ next_i <= 3'h0;
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ end
+ `DIR_CTL_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `DIR_CTL_CHK_FIN;
+ next_USBWireData <= SIEPortData[1:0];
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `DIR_CTL_DELAY:
+ begin
+ NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+ end
+ `PKT_ST_CHK_PID:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ if (SIEPortData[1:0] == `TOKEN)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `HANDSHAKE)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `DATA)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+ end
+ else if (SIEPortData[1:0] == `SPECIAL)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+ end
+ end
+ `PKT_ST_WAIT_RDY_PKT:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_CHK_PID;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= `SYNC_BYTE;
+ next_TxByteOutCtrl <= `DATA_START;
+ end
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+ end
+ `PKT_ST_DATA_CRC_PKT_SENT2:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY1:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[7:0];
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_CRC_WAIT_RDY2:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= ~CRC16Result[15:8];
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_DATA_DATA_CHK_STOP:
+ begin
+ if (SIEPortCtrl == `TX_PACKET_STOP)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+ end
+ end
+ `PKT_ST_DATA_DATA_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_DATA_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC16En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+ end
+ `PKT_ST_DATA_DATA_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_RDY:
+ begin
+ next_CRC16En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+ begin
+ if (CRC16UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+ end
+ end
+ `PKT_ST_DATA_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+ end
+ `PKT_ST_DATA_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `PKT_ST_HS_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_HS_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_SPCL_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_SPCL_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_PKT_SENT1:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_BYTE1_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b1;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ end
+ end
+ `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_CRC_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_CRC_UPD_CRC:
+ begin
+ next_CRCData <= SIEPortData;
+ next_CRC5_8Bit <= 1'b0;
+ next_CRC5En <= 1'b1;
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+ end
+ `PKT_ST_TKN_CRC_WAIT_BYTE:
+ begin
+ next_SIEPortTxRdy <= 1'b1;
+ if (SIEPortWEn == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+ next_SIEPortData <= SIEPortDataIn;
+ next_SIEPortCtrl <= SIEPortCtrlIn;
+ next_SIEPortTxRdy <= 1'b0;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_RDY:
+ begin
+ next_CRC5En <= 1'b0;
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+ next_TxByteOutCtrl <= `DATA_STOP;
+ end
+ end
+ `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+ begin
+ if (CRC5UpdateRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+ end
+ end
+ `PKT_ST_TKN_PID_PKT_SENT:
+ begin
+ next_processTxByteWEn <= 1'b0;
+ next_rstCRC <= 1'b0;
+ NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+ end
+ `PKT_ST_TKN_PID_WAIT_RDY:
+ begin
+ if (processTxByteRdy == 1'b1)
+ begin
+ NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+ next_processTxByteWEn <= 1'b1;
+ next_TxByteOut <= SIEPortData;
+ next_TxByteOutCtrl <= `DATA_STREAM;
+ next_rstCRC <= 1'b1;
+ end
+ end
+ `RES_ST_CHK_FIN:
+ begin
+ next_USBWireWEn <= 1'b0;
+ if (resumeCnt == `HOST_TX_RESUME_TIME)
+ begin
+ NextState_SIETx <= `RES_ST_W_RDY1;
+ end
+ else
+ begin
+ NextState_SIETx <= `RES_ST_DELAY;
+ end
+ end
+ `RES_ST_SND_J_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY4;
+ end
+ `RES_ST_SND_J_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ next_USBWireFullSpeedRate <= fullSpeedRateIn;
+ end
+ `RES_ST_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY2;
+ end
+ `RES_ST_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `RES_ST_W_RDY3;
+ end
+ `RES_ST_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_WAIT_GNT:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ end
+ `RES_ST_WAIT_RDY:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_CHK_FIN;
+ next_USBWireData <= KBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ next_resumeCnt <= resumeCnt + 1'b1;
+ end
+ end
+ `RES_ST_DELAY:
+ begin
+ NextState_SIETx <= `RES_ST_WAIT_RDY;
+ end
+ `RES_ST_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_1;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `RES_ST_W_RDY4:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `RES_ST_SND_J_2;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `TRI_STATE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_WAIT_GNT1:
+ begin
+ if (USBWireGnt == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+ end
+ end
+ `TX_LS_EOP_SND_SE0_2:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+ end
+ `TX_LS_EOP_SND_SE0_1:
+ begin
+ next_USBWireWEn <= 1'b0;
+ NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+ end
+ `TX_LS_EOP_W_RDY1:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_SND_J:
+ begin
+ next_USBWireWEn <= 1'b0;
+ next_USBWireReq <= 1'b0;
+ NextState_SIETx <= `STX_WAIT_BYTE;
+ end
+ `TX_LS_EOP_W_RDY2:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+ next_USBWireData <= `SE0;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ `TX_LS_EOP_W_RDY3:
+ begin
+ if (USBWireRdy == 1'b1)
+ begin
+ NextState_SIETx <= `TX_LS_EOP_SND_J;
+ next_USBWireData <= JBit;
+ next_USBWireCtrl <= `DRIVE;
+ next_USBWireWEn <= 1'b1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_SIETx <= `START_SIETX;
+ else
+ CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ USBWireWEn <= 1'b0;
+ USBWireReq <= 1'b0;
+ processTxByteWEn <= 1'b0;
+ rstCRC <= 1'b0;
+ USBWireFullSpeedRate <= 1'b0;
+ TxByteOut <= 8'h00;
+ TxByteOutCtrl <= 8'h00;
+ USBWireData <= 2'b00;
+ USBWireCtrl <= `TRI_STATE;
+ CRCData <= 8'h00;
+ CRC5En <= 1'b0;
+ CRC5_8Bit <= 1'b0;
+ CRC16En <= 1'b0;
+ SIEPortTxRdy <= 1'b0;
+ TxByteOutFullSpeedRate <= 1'b0;
+ i <= 3'h0;
+ SIEPortData <= 8'h00;
+ SIEPortCtrl <= 8'h00;
+ resumeCnt <= 16'h0000;
+ end
+ else
+ begin
+ USBWireWEn <= next_USBWireWEn;
+ USBWireReq <= next_USBWireReq;
+ processTxByteWEn <= next_processTxByteWEn;
+ rstCRC <= next_rstCRC;
+ USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+ TxByteOut <= next_TxByteOut;
+ TxByteOutCtrl <= next_TxByteOutCtrl;
+ USBWireData <= next_USBWireData;
+ USBWireCtrl <= next_USBWireCtrl;
+ CRCData <= next_CRCData;
+ CRC5En <= next_CRC5En;
+ CRC5_8Bit <= next_CRC5_8Bit;
+ CRC16En <= next_CRC16En;
+ SIEPortTxRdy <= next_SIEPortTxRdy;
+ TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+ i <= next_i;
+ SIEPortData <= next_SIEPortData;
+ SIEPortCtrl <= next_SIEPortCtrl;
+ resumeCnt <= next_resumeCnt;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf (revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processRxByte\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+L 303 304 0 TEXT "Labels" | 84462,243195 1 0 0 "RxByteIn[7:0]"
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+I 20 17 0 Builtin Entry | 45216,248076
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+I 291 50 0 Builtin Exit | 90483,62922
+I 292 50 0 Builtin Entry | 33692,252435
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+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC16Result != 16'hb001)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC16En <= 1'b1;\n end\nendcase\nRxDataOutWEn <= 1'b1;"
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+I 360 358 0 Builtin Exit | 129540,111760
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n `DATA_STOP:\n begin\n if (CRC5Result != 5'h6)\n CRCError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_BIT_STUFF_ERROR:\n begin\n bitStuffError <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n `DATA_STREAM:\n begin\n if (RXDataByteCnt > 10'h2) \n begin\n RxOverflow <= 1'b1;\n RxDataOut <= RxStatus;\n RxCtrlOut <= `RX_PACKET_STOP;\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n end\n else \n begin\n RxDataOut <= RxByte;\n RxCtrlOut <= `RX_PACKET_STREAM;\n CRCData <= RxByte;\n CRC5_8Bit <= 1'b1;\n CRC5En <= 1'b1;\n end\n end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 221 217 0 Builtin Exit | 136710,89055
+I 220 217 0 Builtin Entry | 86360,167640
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+ 42170,142296 43639,139892 51882,139324 60126,138757\
+ 91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+ 42170,157448 43639,155445 51849,155011 60059,154577\
+ 91249,156261 106935,156394
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 228 224 0 Builtin Exit | 129540,111760
+I 227 224 0 Builtin Entry | 86360,167640
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+I 253 248 0 Builtin Exit | 78564,173120
+I 252 248 0 Builtin Entry | 35384,229000
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n `SPECIAL: //Special PID.\n RXByteStMachCurrState <= `IDLE_BYTE_ST;\n `TOKEN: //Token PID\n begin\n RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n RXDataByteCnt <= 0;\n end\n `HANDSHAKE: //Handshake PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n ACKRxed <= 1'b1;\n 2'b10:\n NAKRxed <= 1'b1;\n 2'b11:\n stallRxed <= 1'b1;\n default:\n begin\n $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n end\n endcase\n RXByteStMachCurrState <= `HS_BYTE_ST;\n end\n `DATA: //Data PID\n begin\n case (RxByte[3:2] )\n 2'b00:\n dataSequence <= 1'b0;\n 2'b10:\n dataSequence <= 1'b1;\n default:\n $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n endcase\n RXByteStMachCurrState <= `DATA_BYTE_ST;\n RXDataByteCnt <= 0;\n end\nendcase"
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n RXByteStMachCurrState = `IDLE_BYTE_ST;"
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+ 89364,102368 89220,95212 89220,94846
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+I 259 32 0 Builtin Entry | 66351,233704
+I 260 32 0 Builtin Exit | 110355,78302
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+ 110499,87996 110355,80840 110355,80474
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v (revision 264)
@@ -0,0 +1,266 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// readUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
+input [1:0] RxBitsIn;
+output RxDataInTick;
+input SIERxRdyIn;
+input clk;
+input fullSpeedRate;
+input rst;
+input TxWireActiveDrive;
+output [1:0] RxBitsOut;
+output SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+input noActivityTimeOutEnable;
+
+wire [1:0] RxBitsIn;
+reg RxDataInTick;
+wire SIERxRdyIn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg [1:0] RxBitsOut;
+reg SIERxWEn;
+reg noActivityTimeOut;
+reg RxWireActive;
+wire noActivityTimeOutEnable;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]sampleCnt;
+reg incBufferCnt;
+reg [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg [7:0] rxActiveCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ sampleCnt <= 5'b00000;
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ RxDataInTick <= 1'b0;
+ RxWireEdgeDetect <= 1'b0;
+ RxWireActiveReg <= 1'b0;
+ RxWireActiveReg2 <= 1'b0;
+ end
+ else begin
+ RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
+ RxBitsInReg <= RxBitsIn;
+ oldRxBitsIn <= RxBitsInReg;
+ incBufferCnt <= 1'b0; //default value
+ if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin //if edge detected then
+ sampleCnt <= 5'b00000;
+ RxWireEdgeDetect <= 1'b1; // flag receive activity
+ RxWireActiveReg <= 1'b1;
+ rxActiveCnt <= 8'h00;
+ end
+ else begin
+ sampleCnt <= sampleCnt + 1'b1;
+ RxWireEdgeDetect <= 1'b0;
+ rxActiveCnt <= rxActiveCnt + 1'b1;
+ //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods
+ if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
+ || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
+ RxWireActiveReg <= 1'b0;
+ end
+ if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
+ begin
+ RxDataInTick <= !RxDataInTick;
+ if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
+ begin
+ incBufferCnt <= 1'b1;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
+ 2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
+ 2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
+ 2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
+ endcase
+ end
+ end
+ end
+end
+
+
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutIndex <= 2'b00;
+ RxBitsOut <= 2'b00;
+ SIERxWEn <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ else begin
+ case (bufferOutStMachCurrState)
+ `WAIT_BUFFER_NOT_EMPTY:
+ begin
+ if (bufferCnt != 3'b000)
+ bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+ end
+ `WAIT_SIE_RX_READY:
+ begin
+ if (SIERxRdyIn == 1'b1)
+ begin
+ SIERxWEn <= 1'b1;
+ bufferOutStMachCurrState <= `SIE_RX_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+ 2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+ 2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+ 2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+ endcase
+ end
+ end
+ `SIE_RX_WRITE:
+ begin
+ SIERxWEn <= 1'b0;
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+ end
+ endcase
+ end
+end
+
+//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
+//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket
+//process enables via 'noActivityTimeOutEnable' signal
+//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if
+//there has been a response time out.
+always @(posedge clk) begin
+ if (rst) begin
+ timeOutCnt <= 16'h0000;
+ noActivityTimeOut <= 1'b0;
+ end
+ else begin
+ if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
+ timeOutCnt <= 16'h0000;
+ else
+ timeOutCnt <= timeOutCnt + 1'b1;
+ if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+ || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+ noActivityTimeOut <= 1'b1;
+ else
+ noActivityTimeOut <= 1'b0;
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v (revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// updateCRC5.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input rstCRC;
+input CRCEn;
+input CRC5_8BitIn;
+input [7:0] dataIn;
+input clk;
+input rst;
+output [4:0] CRCResult;
+output ready;
+
+wire rstCRC;
+wire CRCEn;
+wire CRC5_8BitIn;
+wire [7:0] dataIn;
+wire clk;
+wire rst;
+reg [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || rstCRC == 1'b1) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ CRCResult <= 5'h1f;
+ ready <= 1'b1;
+ end
+ else
+ begin
+ if (doUpdateCRC == 1'b0) begin
+ if (CRCEn == 1'b1) begin
+ ready <= 1'b0;
+ doUpdateCRC <= 1'b1;
+ data <= dataIn;
+ if (CRC5_8BitIn == 1'b1) begin
+ loopEnd <= 4'h7;
+ end
+ else begin
+ loopEnd <= 4'h2;
+ end
+ end
+ end
+ else begin
+ i <= i + 1'b1;
+ if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+ CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+ end
+ else begin
+ CRCResult <= {1'b0, CRCResult[4:1]};
+ end
+ data <= {1'b0, data[7:1]};
+ if (i == loopEnd) begin
+ doUpdateCRC <= 1'b0;
+ i <= 4'h0;
+ ready <= 1'b1;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v (revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// writeUSBWireData.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL 3'b100
+
+module writeUSBWireData (
+ TxBitsIn,
+ TxBitsOut,
+ TxDataOutTick,
+ TxCtrlIn,
+ TxCtrlOut,
+ USBWireRdy,
+ USBWireWEn,
+ TxWireActiveDrive,
+ fullSpeedRate,
+ clk,
+ rst
+ );
+
+input [1:0] TxBitsIn;
+input TxCtrlIn;
+input USBWireWEn;
+input clk;
+input fullSpeedRate;
+input rst;
+output [1:0] TxBitsOut;
+output TxDataOutTick;
+output TxCtrlOut;
+output USBWireRdy;
+output TxWireActiveDrive;
+
+wire [1:0] TxBitsIn;
+reg [1:0] TxBitsOut;
+reg TxDataOutTick;
+wire TxCtrlIn;
+reg TxCtrlOut;
+reg USBWireRdy;
+wire USBWireWEn;
+wire clk;
+wire fullSpeedRate;
+wire rst;
+reg TxWireActiveDrive;
+
+// local registers
+reg [2:0]buffer0;
+reg [2:0]buffer1;
+reg [2:0]buffer2;
+reg [2:0]buffer3;
+reg [2:0]bufferCnt;
+reg [1:0]bufferInIndex;
+reg [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ bufferCnt <= 3'b000;
+ end
+ else
+ begin
+ if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+ bufferCnt <= bufferCnt + 1'b1;
+ else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+ bufferCnt <= bufferCnt - 1'b1;
+ end
+end
+
+
+//buffer input state machine
+always @(posedge clk) begin
+ if (rst == 1'b1) begin
+ incBufferCnt <= 1'b0;
+ bufferInIndex <= 2'b00;
+ buffer0 <= 3'b000;
+ buffer1 <= 3'b000;
+ buffer2 <= 3'b000;
+ buffer3 <= 3'b000;
+ USBWireRdy <= 1'b0;
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ else begin
+ case (bufferInStMachCurrState)
+ `WAIT_BUFFER_NOT_FULL:
+ begin
+ if (bufferCnt != `BUFFER_FULL)
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ end
+ `WAIT_WRITE_REQ:
+ begin
+ if (USBWireWEn == 1'b1)
+ begin
+ incBufferCnt <= 1'b1;
+ USBWireRdy <= 1'b0;
+ bufferInIndex <= bufferInIndex + 1'b1;
+ case (bufferInIndex)
+ 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+ 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+ 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+ 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+ endcase
+ bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+ end
+ end
+ `CLR_INC_BUFFER_CNT:
+ begin
+ incBufferCnt <= 1'b0;
+ if (bufferCnt != (`BUFFER_FULL - 1'b1) )
+ begin
+ bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+ USBWireRdy <= 1'b1;
+ end
+ else begin
+ bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+ end
+ end
+ endcase
+ end
+end
+
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ i <= 5'b00000;
+ fullSpeedTick <= 1'b0;
+ lowSpeedTick <= 1'b0;
+ end
+ else
+ begin
+ i <= i + 1'b1;
+ if (i[1:0] == 2'b00)
+ fullSpeedTick <= 1'b1;
+ else
+ fullSpeedTick <= 1'b0;
+ if (i == 5'b00000)
+ lowSpeedTick <= 1'b1;
+ else
+ lowSpeedTick <= 1'b0;
+ end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+ if (rst == 1'b1)
+ begin
+ bufferOutIndex <= 2'b00;
+ decBufferCnt <= 1'b0;
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ TxDataOutTick <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ else
+ begin
+ case (bufferOutStMachCurrState)
+ `WAIT_LINE_WRITE:
+ begin
+ if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+ begin
+ TxDataOutTick <= !TxDataOutTick;
+ if (bufferCnt == 0) begin
+ TxBitsOut <= 2'b00;
+ TxCtrlOut <= `TRI_STATE;
+ end
+ else begin
+ bufferOutStMachCurrState <= `LINE_WRITE;
+ decBufferCnt <= 1'b1;
+ bufferOutIndex <= bufferOutIndex + 1'b1;
+ case (bufferOutIndex)
+ 2'b00 :
+ begin
+ TxBitsOut <= buffer0[2:1];
+ TxCtrlOut <= buffer0[0];
+ end
+ 2'b01 :
+ begin
+ TxBitsOut <= buffer1[2:1];
+ TxCtrlOut <= buffer1[0];
+ end
+ 2'b10 :
+ begin
+ TxBitsOut <= buffer2[2:1];
+ TxCtrlOut <= buffer2[0];
+ end
+ 2'b11 :
+ begin
+ TxBitsOut <= buffer3[2:1];
+ TxCtrlOut <= buffer3[0];
+ end
+ endcase
+ end
+ end
+ end
+ `LINE_WRITE:
+ begin
+ decBufferCnt <= 1'b0;
+ bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+ end
+ endcase
+ end
+end
+
+// control 'TxWireActiveDrive'
+always @(TxCtrlOut)
+begin
+ if (TxCtrlOut == `DRIVE)
+ TxWireActiveDrive <= 1'b1;
+ else
+ TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf (revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+GRID=OFF
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+END
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+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut = SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
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+I 52 0 2 Builtin InPort | 165981,490639 "" ""
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+ 264783,394808 242215,385739 236069,382112 229924,378486\
+ 228216,373858 227209,371138
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf (revision 264)
@@ -0,0 +1,292 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=294
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+ 159556,30336 149499,27398 125714,27614 113171,27388
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+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v (revision 264)
@@ -0,0 +1,518 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input bitStuffError;
+input clk;
+input CRCError;
+input getPacketRdy;
+input rst;
+input [7:0]RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0]RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input sendPacketRdy;
+input [4:0]USBEndPControlReg;
+input [6:0]USBTgtAddress;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output endPointReadyToGetPkt;
+output [10:0]frameNum;
+output getPacketREn;
+output NAKSent;
+output [3:0]sendPacketPID;
+output sendPacketWEn;
+output SOFRxed;
+output stallSent;
+output transDone;
+output [3:0]USBEndP;
+output [1:0]USBEndPNakTransTypeReg;
+output [1:0]USBEndPTransTypeReg;
+
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+wire CRCError;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg [10:0]frameNum, next_frameNum;
+wire getPacketRdy;
+reg getPacketREn, next_getPacketREn;
+reg NAKSent, next_NAKSent;
+wire rst;
+wire [7:0]RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0]RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg [3:0]sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg SOFRxed, next_SOFRxed;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+reg [3:0]USBEndP, next_USBEndP;
+wire [4:0]USBEndPControlReg;
+reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [7:0]PIDByte, next_PIDByte;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg [6:0]USBAddress, next_USBAddress;
+reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_getPacketREn <= getPacketREn;
+ next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+ next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+ case (CurrState_slvCntrl) // synopsys parallel_case full_case
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ begin
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `PID_ERROR;
+ end
+ end
+ `PID_ERROR:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_RDY:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ end
+ end
+ `SETUP_OUT_CHK:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ end
+ else if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_CHK_RDY:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ end
+ `IN_RESP_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ end
+ `IN_RESP_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+ end
+ end
+ `IN_RESP_CHK_ISO:
+ begin
+ if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ end
+ `START_S1:
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `GET_TOKEN_WAIT_CRC:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_ADDR:
+ begin
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_WAIT_STOP:
+ begin
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ end
+ else if (RxDataWEn == 1'b1)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ `GET_TOKEN_CHK_SOF:
+ begin
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ end
+ `GET_TOKEN_CHK_ADDR:
+ begin
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ next_USBEndPControlRegCopy <= USBEndPControlReg;
+ next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+ end
+ else
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ stallSent <= 1'b0;
+ NAKSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ transDone <= 1'b0;
+ clrEPRdy <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ sendPacketWEn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ getPacketREn <= 1'b0;
+ endPointReadyToGetPkt <= 1'b0;
+ PIDByte <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ addrEndPTemp <= 8'h00;
+ tempUSBEndPTransTypeReg <= 2'b00;
+ USBAddress <= 7'b0000000;
+ USBEndPControlRegCopy <= 5'b00000;
+ end
+ else
+ begin
+ stallSent <= next_stallSent;
+ NAKSent <= next_NAKSent;
+ SOFRxed <= next_SOFRxed;
+ transDone <= next_transDone;
+ clrEPRdy <= next_clrEPRdy;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ sendPacketWEn <= next_sendPacketWEn;
+ sendPacketPID <= next_sendPacketPID;
+ getPacketREn <= next_getPacketREn;
+ endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+ PIDByte <= next_PIDByte;
+ endpCRCTemp <= next_endpCRCTemp;
+ addrEndPTemp <= next_addrEndPTemp;
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ USBAddress <= next_USBAddress;
+ USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/doc/README.txt (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/doc/README.txt (revision 264)
@@ -0,0 +1,46 @@
+USBHostSlave has been successfully compiled using Quartus 4.2
+For some reason I have not been able to use SOPC Builder 4.2 to build the usb SOPC component
+However, SOPC Builder 4.1 generates a usable SOPC component. This may be an error on my part, I need to
+investigate further.
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+
+Release notes:
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
+// control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
+// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
+// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+// speed, and TX resume is always low speed.
+// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
+// in missing receive packets.
+// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+// by adding kludged delay to softranmit. This needs to be fixed properly.
+// This version has undergone limited testing
+// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+// with uClinux, and is known to work with a full speed USB flash stick.
+// Moving Opencores project status from Beta to done.
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+// Modified RX and TX fifo status registers, and removed TX fifo data count
+// register. Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+// Fixed slave mode bug which caused receive fifo to
+// be filled with incoming data when the slave was
+// responding with a NAK, and the data should have been discarded.
+// TODO: Test isochronous mode, and low speed mode using uClinux driver
+// Add frame period adjustment capability
+// Add compilation flags for slave only and host only versions
+// Create data bus width options beyond 8-bit
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+// there was no detected activity on the USB data lines. This caused an infrequent
+// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+// the higher level state machines are actively looking for receive packets.
+// Modified USB RX data clock recovery, so that data is sampled during the middle
+// of a USB bit period. Fixed a bug which could result in double sampling
+// of USB RX data if clock phase adjustments were required in the middle of a
+// USB packet.
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v (nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v (revision 264)
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module RxFifo(
+ clk,
+ rst,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk;
+wire rst;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf (revision 264)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+ 192923,24221 173766,19421 163644,19865 153522,20309\
+ 122483,20608 111915,23020 101347,25432 81761,37919\
+ 69710,37919
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+ 30330,86104 25492,143212 35905,156667 46318,170122\
+ 96612,168665 117496,167729
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+L 819 820 0 TEXT "State Labels" | 67420,66064 1 0 0 "RESP"
+S 820 589 102404 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 67420,66064 6500 6500
+H 821 820 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 828 821 2 847 833 BEZIER "Transitions" | 143788,176826 110094,161523 73824,121282 61589,104841
+A 829 828 16 TEXT "Actions" | 74668,133998 1 0 0 "getPacketREn <= 1'b1;"
+W 830 821 1 847 832 BEZIER "Transitions" | 149052,177611 172803,163396 180803,116530 192775,92880
+C 831 830 0 TEXT "Conditions" | 112905,152704 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+I 832 821 0 Builtin Exit | 195662,92880
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+I 862 0 2 Builtin OutPort | 120122,261308 "" ""
+L 861 862 0 TEXT "Labels" | 126122,261308 1 0 0 "endPointReadyToGetPkt"
+A 860 457 16 TEXT "Actions" | 93778,19821 1 0 0 "USBEndPControlRegCopy <= USBEndPControlReg;\nendPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT] ;"
+I 859 0 130 Builtin Signal | 35412,208838 "" ""
+L 858 859 0 TEXT "Labels" | 38412,208838 1 0 0 "USBEndPControlRegCopy[4:0]"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 205195,243792
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 850 821 0 Builtin Entry | 49920,240120
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+ 187314,234737 186141,226528 176133,223346 166125,220164\
+ 127582,215026 108152,212765
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+ 41052,159480 41752,153900 40959,141711 40167,129522\
+ 46701,89176 50135,78506 53570,67837 54978,65340\
+ 57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+ 162008,130636 151291,117855 140238,106874 129185,95894\
+ 77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+ 209214,43082 209522,23062 208983,17094 208444,11127\
+ 205980,7277 191773,6353 177567,5429 123205,5583\
+ 106804,9317 90403,13052 79161,27836 75696,31763\
+ 72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+ 53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+ 60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 122196,51478 1 0 0 "Insert delay to allow USBEndP etc to update"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+ 197587,175015 201929,162657 202973,147251 204017,131846\
+ 203849,82580 202847,68719 201846,54859 198970,48147\
+ 197050,45058
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 69699,59883 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 803 805 0 Builtin Exit | 144780,101600
+I 804 805 0 Builtin Entry | 96520,152400
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+ 33432,172010 34721,79558 53522,54375 72324,29193\
+ 153226,30396 173104,33029 192983,35662 193169,40577\
+ 192962,43440
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v (revision 264)
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbHostSlaveWrap.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+ clk,
+ reset,
+ address,
+ writedata,
+ readdata,
+ write,
+ read,
+ waitrequest,
+ chipselect,
+ irq,
+ usbClk,
+ USBWireVPI,
+ USBWireVMI,
+ USBWireDataInTick,
+ USBWireVPO,
+ USBWireVMO,
+ USBWireDataOutTick,
+ USBWireOutEn_n,
+ USBFullSpeed
+ );
+
+input clk;
+input reset;
+input [7:0] address;
+input [7:0] writedata;
+output [7:0] readdata;
+input write;
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input usbClk;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address;
+wire [7:0] writedata;
+wire [7:0] readdata;
+wire write;
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire usbClk;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut;
+wire hostConnEventIntOut;
+wire hostResumeIntOut;
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut;
+wire slaveResetEventIntOut;
+wire slaveResumeIntOut;
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+ hostResumeIntOut | hostTransDoneIntOut |
+ slaveSOFRxedIntOut | slaveResetEventIntOut |
+ slaveResumeIntOut | slaveTransDoneIntOut |
+ slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut;
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration:
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+ .clk_i(clk),
+ .rst_i(reset),
+ .address_i(address),
+ .data_i(writedata),
+ .data_o(readdata),
+ .we_i(write),
+ .strobe_i(strobe_i),
+ .ack_o(ack_o),
+ .usbClk(usbClk),
+ .hostSOFSentIntOut(hostSOFSentIntOut),
+ .hostConnEventIntOut(hostConnEventIntOut),
+ .hostResumeIntOut(hostResumeIntOut),
+ .hostTransDoneIntOut(hostTransDoneIntOut),
+ .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+ .slaveResetEventIntOut(slaveResetEventIntOut),
+ .slaveResumeIntOut(slaveResumeIntOut),
+ .slaveTransDoneIntOut(slaveTransDoneIntOut),
+ .slaveNAKSentIntOut(slaveNAKSentIntOut),
+ .USBWireDataIn(USBWireDataIn),
+ .USBWireDataInTick(USBWireDataInTick),
+ .USBWireDataOut(USBWireDataOut),
+ .USBWireDataOutTick(USBWireDataOutTick),
+ .USBWireCtrlOut(USBWireCtrlOut),
+ .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v (revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v (revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input clk;
+input directControlEn;
+input [1:0]directControlLineState;
+input rst;
+input SCTxPortGnt;
+input SCTxPortRdy;
+output [7:0]SCTxPortCntl;
+output [7:0]SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+wire clk;
+wire directControlEn;
+wire [1:0]directControlLineState;
+wire rst;
+reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0]SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortCntl <= SCTxPortCntl;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortReq <= SCTxPortReq;
+ case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+ `START_SDC:
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `CHK_DRCT_CNTL:
+ begin
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ begin
+ if (SCTxPortGnt == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ end
+ end
+ `IDLE_WAIT_RDY:
+ begin
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ end
+ endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf (revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
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+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
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+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+ 84500,7962 56262,8416 48108,10114 39955,11813\
+ 35575,18155 34480,31669 33386,45184 33386,92900\
+ 35198,110038 37010,127177 44258,148015 49996,153300\
+ 55734,158585 71438,158887 78535,158887 85632,158887\
+ 97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
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+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
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+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
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+ 139792,40658 161594,38692 165369,38074 169145,37457\
+ 170187,37688 173773,37229
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+ 57625,199045 54697,174705 54514,164091 54331,153478\
+ 57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
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+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
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+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
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+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v (nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v (revision 264)
@@ -0,0 +1,510 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output SIERxTimeOutEn;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(usbClk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rstSyncToUsbClk),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone),
+ .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+
+endpMux u_endpMux (
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(usbClk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rstSyncToUsbClk),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(usbClk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rstSyncToUsbClk) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(usbClk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .SIERxTimeOutEn(SIERxTimeOutEn),
+ .clk(usbClk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rstSyncToUsbClk),
+ .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v (nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v (revision 264)
@@ -0,0 +1,102 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ .rclk(clk),
+ .rrst(1'b0),
+ .rce(1'b1),
+ .oe(readEn),
+ .raddr(addrOut),
+ .do(dataOut),
+ .wclk(clk),
+ .wrst(1'b0),
+ .wce(1'b1),
+ .we(writeEn),
+ .waddr(addrIn),
+ .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
+ .addrIn(addrIn),
+ .addrOut(addrOut),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(writeEn),
+ .readEn(readEn),
+ .dataOut(dataOut));
+
+endmodule
\ No newline at end of file
Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v (nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v (revision 264)
@@ -0,0 +1,264 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBHostControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+////
+
+ 
+