Index: mcc216_5200/simulate_sdram.sh
===================================================================
--- mcc216_5200/simulate_sdram.sh	(nonexistent)
+++ mcc216_5200/simulate_sdram.sh	(revision 288)
@@ -0,0 +1,63 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=sdram_ctrl_3_ports
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_sdram/* .
+
+        # copy source files
+	cp ../*3*.v .
+
+        # set up project definition file
+	ls *.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat >> $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: mcc216_5200/simulate_sdram.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcc216_5200/svideo/sin_rom.mif
===================================================================
--- mcc216_5200/svideo/sin_rom.mif	(nonexistent)
+++ mcc216_5200/svideo/sin_rom.mif	(revision 288)
@@ -0,0 +1,2054 @@
+WIDTH=8;
+DEPTH=2048;
+ADDRESS_RADIX=UNS;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+    0      : 00;
+    1      : 00;
+    2      : 00;
+    3      : 00;
+    4      : 00;
+    5      : 00;
+    6      : 00;
+    7      : 00;
+    8      : 00;
+    9      : 00;
+    10     : 00;
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+    12     : 00;
+    13     : 00;
+    14     : 00;
+    15     : 01;
+    16     : 00;
+    17     : 00;
+    18     : 00;
+    19     : 01;
+    20     : 01;
+    21     : 01;
+    22     : 01;
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+    24     : 00;
+    25     : 00;
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+    27     : 01;
+    28     : 02;
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+    31     : 03;
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+    444    : 2A;
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+    446    : 34;
+    447    : 37;
+    448    : 05;
+    449    : 10;
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+    457    : 10;
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+    463    : 39;
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+    474    : 1B;
+    475    : 25;
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+    478    : 38;
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+    483    : 26;
+    484    : 2E;
+    485    : 35;
+    486    : 39;
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+    488    : 06;
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+    491    : 26;
+    492    : 2F;
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+    494    : 3A;
+    495    : 3D;
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+    497    : 12;
+    498    : 1D;
+    499    : 27;
+    500    : 30;
+    501    : 36;
+    502    : 3B;
+    503    : 3E;
+    504    : 06;
+    505    : 12;
+    506    : 1D;
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+    508    : 30;
+    509    : 37;
+    510    : 3C;
+    511    : 3F;
+    512    : 06;
+    513    : 12;
+    514    : 1E;
+    515    : 28;
+    516    : 31;
+    517    : 38;
+    518    : 3D;
+    519    : 40;
+    520    : 06;
+    521    : 12;
+    522    : 1E;
+    523    : 29;
+    524    : 32;
+    525    : 39;
+    526    : 3E;
+    527    : 41;
+    528    : 06;
+    529    : 13;
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+    531    : 2A;
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+    533    : 3A;
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+    536    : 06;
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+    562    : 21;
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+    567    : 46;
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+    569    : 14;
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+    583    : 48;
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+    591    : 49;
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+    593    : 15;
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+    614    : 49;
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+    676    : 41;
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+    682    : 28;
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+    684    : 42;
+    685    : 4B;
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+    689    : 19;
+    690    : 28;
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+    692    : 42;
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+    695    : 56;
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+    730    : 2B;
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+    732    : 46;
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+    749    : 52;
+    750    : 59;
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+    756    : 49;
+    757    : 53;
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+    759    : 5E;
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+    1559   : C2;
+    1560   : 13;
+    1561   : 38;
+    1562   : 5C;
+    1563   : 7C;
+    1564   : 97;
+    1565   : AC;
+    1566   : BB;
+    1567   : C3;
+    1568   : 13;
+    1569   : 39;
+    1570   : 5C;
+    1571   : 7C;
+    1572   : 98;
+    1573   : AD;
+    1574   : BC;
+    1575   : C4;
+    1576   : 13;
+    1577   : 39;
+    1578   : 5D;
+    1579   : 7D;
+    1580   : 99;
+    1581   : AE;
+    1582   : BD;
+    1583   : C5;
+    1584   : 13;
+    1585   : 39;
+    1586   : 5D;
+    1587   : 7E;
+    1588   : 99;
+    1589   : AF;
+    1590   : BE;
+    1591   : C6;
+    1592   : 13;
+    1593   : 3A;
+    1594   : 5E;
+    1595   : 7E;
+    1596   : 9A;
+    1597   : B0;
+    1598   : BF;
+    1599   : C7;
+    1600   : 13;
+    1601   : 3A;
+    1602   : 5E;
+    1603   : 7F;
+    1604   : 9B;
+    1605   : B1;
+    1606   : C0;
+    1607   : C8;
+    1608   : 13;
+    1609   : 3A;
+    1610   : 5F;
+    1611   : 80;
+    1612   : 9C;
+    1613   : B2;
+    1614   : C1;
+    1615   : C9;
+    1616   : 13;
+    1617   : 3A;
+    1618   : 5F;
+    1619   : 80;
+    1620   : 9C;
+    1621   : B3;
+    1622   : C2;
+    1623   : CA;
+    1624   : 13;
+    1625   : 3B;
+    1626   : 60;
+    1627   : 81;
+    1628   : 9D;
+    1629   : B3;
+    1630   : C3;
+    1631   : CB;
+    1632   : 14;
+    1633   : 3B;
+    1634   : 60;
+    1635   : 82;
+    1636   : 9E;
+    1637   : B4;
+    1638   : C4;
+    1639   : CC;
+    1640   : 14;
+    1641   : 3B;
+    1642   : 61;
+    1643   : 82;
+    1644   : 9F;
+    1645   : B5;
+    1646   : C5;
+    1647   : CD;
+    1648   : 14;
+    1649   : 3C;
+    1650   : 61;
+    1651   : 83;
+    1652   : A0;
+    1653   : B6;
+    1654   : C6;
+    1655   : CE;
+    1656   : 14;
+    1657   : 3C;
+    1658   : 62;
+    1659   : 83;
+    1660   : A0;
+    1661   : B7;
+    1662   : C7;
+    1663   : CF;
+    1664   : 14;
+    1665   : 3C;
+    1666   : 62;
+    1667   : 84;
+    1668   : A1;
+    1669   : B8;
+    1670   : C8;
+    1671   : D0;
+    1672   : 14;
+    1673   : 3C;
+    1674   : 62;
+    1675   : 85;
+    1676   : A2;
+    1677   : B9;
+    1678   : C8;
+    1679   : D1;
+    1680   : 14;
+    1681   : 3D;
+    1682   : 63;
+    1683   : 85;
+    1684   : A3;
+    1685   : BA;
+    1686   : C9;
+    1687   : D2;
+    1688   : 14;
+    1689   : 3D;
+    1690   : 63;
+    1691   : 86;
+    1692   : A3;
+    1693   : BA;
+    1694   : CA;
+    1695   : D3;
+    1696   : 14;
+    1697   : 3D;
+    1698   : 64;
+    1699   : 87;
+    1700   : A4;
+    1701   : BB;
+    1702   : CB;
+    1703   : D4;
+    1704   : 14;
+    1705   : 3E;
+    1706   : 64;
+    1707   : 87;
+    1708   : A5;
+    1709   : BC;
+    1710   : CC;
+    1711   : D5;
+    1712   : 15;
+    1713   : 3E;
+    1714   : 65;
+    1715   : 88;
+    1716   : A6;
+    1717   : BD;
+    1718   : CD;
+    1719   : D6;
+    1720   : 15;
+    1721   : 3E;
+    1722   : 65;
+    1723   : 89;
+    1724   : A7;
+    1725   : BE;
+    1726   : CE;
+    1727   : D7;
+    1728   : 15;
+    1729   : 3F;
+    1730   : 66;
+    1731   : 89;
+    1732   : A7;
+    1733   : BF;
+    1734   : CF;
+    1735   : D8;
+    1736   : 15;
+    1737   : 3F;
+    1738   : 66;
+    1739   : 8A;
+    1740   : A8;
+    1741   : C0;
+    1742   : D0;
+    1743   : D9;
+    1744   : 15;
+    1745   : 3F;
+    1746   : 67;
+    1747   : 8A;
+    1748   : A9;
+    1749   : C1;
+    1750   : D1;
+    1751   : DA;
+    1752   : 15;
+    1753   : 3F;
+    1754   : 67;
+    1755   : 8B;
+    1756   : AA;
+    1757   : C2;
+    1758   : D2;
+    1759   : DB;
+    1760   : 15;
+    1761   : 40;
+    1762   : 68;
+    1763   : 8C;
+    1764   : AA;
+    1765   : C2;
+    1766   : D3;
+    1767   : DC;
+    1768   : 15;
+    1769   : 40;
+    1770   : 68;
+    1771   : 8C;
+    1772   : AB;
+    1773   : C3;
+    1774   : D4;
+    1775   : DD;
+    1776   : 15;
+    1777   : 40;
+    1778   : 69;
+    1779   : 8D;
+    1780   : AC;
+    1781   : C4;
+    1782   : D5;
+    1783   : DE;
+    1784   : 15;
+    1785   : 41;
+    1786   : 69;
+    1787   : 8E;
+    1788   : AD;
+    1789   : C5;
+    1790   : D6;
+    1791   : DF;
+    1792   : 16;
+    1793   : 41;
+    1794   : 6A;
+    1795   : 8E;
+    1796   : AD;
+    1797   : C6;
+    1798   : D7;
+    1799   : E0;
+    1800   : 16;
+    1801   : 41;
+    1802   : 6A;
+    1803   : 8F;
+    1804   : AE;
+    1805   : C7;
+    1806   : D8;
+    1807   : E1;
+    1808   : 16;
+    1809   : 41;
+    1810   : 6B;
+    1811   : 90;
+    1812   : AF;
+    1813   : C8;
+    1814   : D9;
+    1815   : E2;
+    1816   : 16;
+    1817   : 42;
+    1818   : 6B;
+    1819   : 90;
+    1820   : B0;
+    1821   : C9;
+    1822   : DA;
+    1823   : E3;
+    1824   : 16;
+    1825   : 42;
+    1826   : 6B;
+    1827   : 91;
+    1828   : B1;
+    1829   : CA;
+    1830   : DB;
+    1831   : E4;
+    1832   : 16;
+    1833   : 42;
+    1834   : 6C;
+    1835   : 91;
+    1836   : B1;
+    1837   : CA;
+    1838   : DC;
+    1839   : E5;
+    1840   : 16;
+    1841   : 43;
+    1842   : 6C;
+    1843   : 92;
+    1844   : B2;
+    1845   : CB;
+    1846   : DD;
+    1847   : E6;
+    1848   : 16;
+    1849   : 43;
+    1850   : 6D;
+    1851   : 93;
+    1852   : B3;
+    1853   : CC;
+    1854   : DE;
+    1855   : E7;
+    1856   : 16;
+    1857   : 43;
+    1858   : 6D;
+    1859   : 93;
+    1860   : B4;
+    1861   : CD;
+    1862   : DF;
+    1863   : E8;
+    1864   : 16;
+    1865   : 43;
+    1866   : 6E;
+    1867   : 94;
+    1868   : B4;
+    1869   : CE;
+    1870   : E0;
+    1871   : E9;
+    1872   : 17;
+    1873   : 44;
+    1874   : 6E;
+    1875   : 95;
+    1876   : B5;
+    1877   : CF;
+    1878   : E1;
+    1879   : EA;
+    1880   : 17;
+    1881   : 44;
+    1882   : 6F;
+    1883   : 95;
+    1884   : B6;
+    1885   : D0;
+    1886   : E1;
+    1887   : EB;
+    1888   : 17;
+    1889   : 44;
+    1890   : 6F;
+    1891   : 96;
+    1892   : B7;
+    1893   : D1;
+    1894   : E2;
+    1895   : EC;
+    1896   : 17;
+    1897   : 45;
+    1898   : 70;
+    1899   : 97;
+    1900   : B8;
+    1901   : D2;
+    1902   : E3;
+    1903   : ED;
+    1904   : 17;
+    1905   : 45;
+    1906   : 70;
+    1907   : 97;
+    1908   : B8;
+    1909   : D2;
+    1910   : E4;
+    1911   : EE;
+    1912   : 17;
+    1913   : 45;
+    1914   : 71;
+    1915   : 98;
+    1916   : B9;
+    1917   : D3;
+    1918   : E5;
+    1919   : EF;
+    1920   : 17;
+    1921   : 46;
+    1922   : 71;
+    1923   : 98;
+    1924   : BA;
+    1925   : D4;
+    1926   : E6;
+    1927   : F0;
+    1928   : 17;
+    1929   : 46;
+    1930   : 72;
+    1931   : 99;
+    1932   : BB;
+    1933   : D5;
+    1934   : E7;
+    1935   : F1;
+    1936   : 17;
+    1937   : 46;
+    1938   : 72;
+    1939   : 9A;
+    1940   : BB;
+    1941   : D6;
+    1942   : E8;
+    1943   : F2;
+    1944   : 17;
+    1945   : 46;
+    1946   : 73;
+    1947   : 9A;
+    1948   : BC;
+    1949   : D7;
+    1950   : E9;
+    1951   : F3;
+    1952   : 18;
+    1953   : 47;
+    1954   : 73;
+    1955   : 9B;
+    1956   : BD;
+    1957   : D8;
+    1958   : EA;
+    1959   : F4;
+    1960   : 18;
+    1961   : 47;
+    1962   : 74;
+    1963   : 9C;
+    1964   : BE;
+    1965   : D9;
+    1966   : EB;
+    1967   : F5;
+    1968   : 18;
+    1969   : 47;
+    1970   : 74;
+    1971   : 9C;
+    1972   : BF;
+    1973   : DA;
+    1974   : EC;
+    1975   : F6;
+    1976   : 18;
+    1977   : 48;
+    1978   : 74;
+    1979   : 9D;
+    1980   : BF;
+    1981   : DA;
+    1982   : ED;
+    1983   : F7;
+    1984   : 18;
+    1985   : 48;
+    1986   : 75;
+    1987   : 9E;
+    1988   : C0;
+    1989   : DB;
+    1990   : EE;
+    1991   : F8;
+    1992   : 18;
+    1993   : 48;
+    1994   : 75;
+    1995   : 9E;
+    1996   : C1;
+    1997   : DC;
+    1998   : EF;
+    1999   : F9;
+    2000   : 18;
+    2001   : 48;
+    2002   : 76;
+    2003   : 9F;
+    2004   : C2;
+    2005   : DD;
+    2006   : F0;
+    2007   : FA;
+    2008   : 18;
+    2009   : 49;
+    2010   : 76;
+    2011   : A0;
+    2012   : C2;
+    2013   : DE;
+    2014   : F1;
+    2015   : FB;
+    2016   : 18;
+    2017   : 49;
+    2018   : 77;
+    2019   : A0;
+    2020   : C3;
+    2021   : DF;
+    2022   : F2;
+    2023   : FC;
+    2024   : 18;
+    2025   : 49;
+    2026   : 77;
+    2027   : A1;
+    2028   : C4;
+    2029   : E0;
+    2030   : F3;
+    2031   : FD;
+    2032   : 19;
+    2033   : 4A;
+    2034   : 78;
+    2035   : A1;
+    2036   : C5;
+    2037   : E1;
+    2038   : F4;
+    2039   : FE;
+    2040   : 19;
+    2041   : 4A;
+    2042   : 78;
+    2043   : A2;
+    2044   : C6;
+    2045   : E1;
+    2046   : F5;
+    2047   : FF;
+END;
Index: mcc216_5200/svideo/svideo.vhd
===================================================================
--- mcc216_5200/svideo/svideo.vhd	(nonexistent)
+++ mcc216_5200/svideo/svideo.vhd	(revision 288)
@@ -0,0 +1,397 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+--PACKAGE svideo_pkg IS
+--  COMPONENT svideo
+--  PORT(
+--    -- Power up reset
+--    areset_n    : IN  STD_LOGIC;
+--    -- Main clock (28.636363 MHz)
+--    ecs_clk     : IN  STD_LOGIC;
+--    -- DAC clock (114.545454 MHz)
+--    dac_clk     : IN  STD_LOGIC;
+--    -- RGB input
+--    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    -- Start of frame flag
+--    sof         : IN  STD_LOGIC;
+--    -- PAL burst phase
+--    vpos_lsb    : IN  STD_LOGIC;
+--    -- Burst/Synchro/Blanking inputs
+--    blank       : IN  STD_LOGIC;
+--    burst       : IN  STD_LOGIC;
+--    csync_n     : IN  STD_LOGIC;
+--    -- S-Video output
+--    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--    -- PAL(0)/NTSC(1) mode
+--    pal_ntsc    : IN  STD_LOGIC
+--  );
+--  END COMPONENT;
+--
+--END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.SIN_COS_PKG.ALL;
+
+ENTITY svideo IS
+  PORT(
+    -- Power up reset
+    areset_n    : IN  STD_LOGIC;
+    -- Main clock (28.636363 MHz)
+    ecs_clk     : IN  STD_LOGIC;
+    -- DAC clock (114.545454 MHz)
+    dac_clk     : IN  STD_LOGIC;
+    -- RGB input
+    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    -- Start of frame flag
+    sof         : IN  STD_LOGIC;
+    -- PAL burst phase
+    vpos_lsb    : IN  STD_LOGIC;
+    -- Burst/Synchro/Blanking inputs
+    blank       : IN  STD_LOGIC;
+    burst       : IN  STD_LOGIC;
+    csync_n     : IN  STD_LOGIC;
+    -- S-Video output
+    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    -- PAL(0)/NTSC(1) mode
+    pal_ntsc    : IN  STD_LOGIC
+  );
+END svideo;
+
+ARCHITECTURE rtl OF svideo IS
+
+  -- Color carrier phase (0 - 31)
+  SIGNAL   col_ctr      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+  -------------------------
+  -- RGB -> Y conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_YR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YB      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_Y2      : STD_LOGIC_VECTOR(16 DOWNTO 0);
+  SIGNAL   comp_Y3      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   comp_Y4      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+  CONSTANT Y_LVL_SYNC   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "00000000000000000";
+  CONSTANT Y_LVL_BLANK  : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+  CONSTANT Y_LVL_PICT   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+
+  -------------------------
+  -- RGB -> U conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_UR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_U       : STD_LOGIC;
+  SIGNAL   ampl_U       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_U       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000100100000000000"; -- +15%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111011100000000000"; -- -15%
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000110000000000000"; -- +20%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111010000000000000"; -- -20%
+  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000111111000000000"; -- +25%
+  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111000000000000000"; -- -25%
+
+  -------------------------
+  -- RGB -> V conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_VR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_V       : STD_LOGIC;
+  SIGNAL   ampl_V       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_V       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+  -----------------
+  -- Y/C signals --
+  -----------------
+  SIGNAL   luma         : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_1       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_2       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_acc     : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   chroma       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL   chroma_1     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_2     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_acc   : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+  -- Delayed input signals
+  SIGNAL   blank_dly    : STD_LOGIC;
+  SIGNAL   burst_dly    : STD_LOGIC;
+  SIGNAL   csync_dly    : STD_LOGIC;
+  SIGNAL   sof_dly      : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+  PROCESS
+  (
+    areset_n,    -- Global reset
+    ecs_clk,     -- Main clock
+    csync_n,     -- Composite synchro (active low)
+    blank,       -- Composite blanking
+    burst,       -- Burst enable flag
+    pal_ntsc,    -- PAL(0) / NTSC(1)
+    sof          -- Start of frame flag
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      -- Color carrier phase
+      col_ctr <= (OTHERS => '0');
+      -- Y component
+      comp_YR <= (OTHERS => '0');
+      comp_YG <= (OTHERS => '0');
+      comp_YB <= (OTHERS => '0');
+      comp_Y2 <= (OTHERS => '0');
+      comp_Y3 <= (OTHERS => '0');
+      comp_Y4 <= (OTHERS => '0');
+      -- U component
+      comp_UR <= (OTHERS => '0');
+      comp_UG <= (OTHERS => '0');
+      comp_UB <= (OTHERS => '0');
+      comp_pU <= (OTHERS => '0');
+      comp_mU <= (OTHERS => '0');
+      sign_U  <= '0';
+      ampl_U  <= (OTHERS => '0');
+      -- V component
+      comp_VR <= (OTHERS => '0');
+      comp_VG <= (OTHERS => '0');
+      comp_VB <= (OTHERS => '0');
+      comp_pV <= (OTHERS => '0');
+      comp_mV <= (OTHERS => '0');
+      sign_V  <= '0';
+      ampl_V  <= (OTHERS => '0');
+    ELSIF (rising_edge(ecs_clk)) THEN
+      -----------------
+      -----------------
+      -- First stage --
+      -----------------
+      -----------------
+
+      -- RGB -> Y conversion :
+      ------------------------
+      --     Y = (0.299*R + 0.587*G + 0.114*B) * 140 / 256
+      --     Y =  0.164*R + 0.321*G + 0.062*B
+      -- 512*Y =     84*R +   164*G +    32*B
+      comp_YR <= "001010100" * unsigned(r_in);
+      comp_YG <= "010100100" * unsigned(g_in);
+      comp_YB <= "000100000" * unsigned(b_in);
+
+      -- RGB -> U conversion :
+      ------------------------
+      --     U = -0.147*R - 0.289*G + 0.436*B
+      -- 512*U =    -75*R -   148*G +   223*B
+      comp_UR <= "001001011" * unsigned(r_in);
+      comp_UG <= "010010100" * unsigned(g_in);
+      comp_UB <= "011011111" * unsigned(b_in);
+
+      -- RGB -> V conversion :
+      ------------------------
+      --     V =  0.615*R - 0.515*G - 0.100*B
+      -- 512*V =    315*R -   264*G -    51*B
+      comp_VR <= "100111011" * unsigned(r_in);
+      comp_VG <= "100001000" * unsigned(g_in);
+      comp_VB <= "000110011" * unsigned(b_in);
+      
+      -- Delayed signals :
+      --------------------
+      csync_dly <= csync_n;          -- to 2nd stage
+      blank_dly <= blank;            -- to 2nd stage
+      burst_dly <= burst;            -- to 2nd stage
+      sof_dly   <= sof_dly(0) & sof; -- to 3rd stage
+
+      ------------------
+      ------------------
+      -- Second stage --
+      ------------------
+      ------------------
+
+      -- Compute Y
+      IF (csync_dly = '0') THEN
+        -- Synchro level
+        comp_Y2 <= Y_LVL_SYNC;
+      ELSIF (blank_dly = '1') THEN
+        -- Blanking level
+        comp_Y2 <= Y_LVL_BLANK;
+      ELSE
+        -- Picture level
+        comp_Y2 <= std_logic_vector(comp_YR)
+                 + std_logic_vector(comp_YG)
+                 + std_logic_vector(comp_YB)
+                 + Y_LVL_PICT;
+      END IF;
+
+      -- Compute U
+      IF (burst_dly = '1') THEN
+        comp_pU <= mU_LVL_BURST;
+        comp_mU <= pU_LVL_BURST;
+      ELSE
+        comp_pU <= std_logic_vector('0' & comp_UB)
+                 - std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UR);
+        comp_mU <= std_logic_vector('0' & comp_UR)
+                 + std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UB);
+      END IF;
+
+      -- Compute V
+      IF (burst_dly = '1') THEN
+        IF (pal_ntsc = '1') THEN
+          -- NTSC burst
+          comp_pV <= (OTHERS => '0');
+          comp_mV <= (OTHERS => '0');
+        ELSE
+          -- PAL burst
+          comp_pV <= pU_LVL_BURST;
+          comp_mV <= mU_LVL_BURST;
+        END IF;
+      ELSE
+        comp_pV <= std_logic_vector('0' & comp_VR)
+                 - std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VB);
+        comp_mV <= std_logic_vector('0' & comp_VB)
+                 + std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VR);
+      END IF;
+
+      -----------------
+      -----------------
+      -- Third stage --
+      -----------------
+      -----------------
+      
+      -- Copy Y
+      comp_Y3 <= comp_Y2(16 DOWNTO 7);
+
+      -- Phase and amplitude for U,V
+      sign_U <= comp_pU(17);
+      sign_V <= comp_pV(17) XOR (vpos_lsb AND (NOT pal_ntsc));
+      IF (comp_pU(17) = '1') THEN
+        ampl_U <= comp_mU(16 DOWNTO 9);
+      ELSE
+        ampl_U <= comp_pU(16 DOWNTO 9);
+      END IF;
+      IF (comp_pV(17) = '1') THEN
+        ampl_V <= comp_mV(16 DOWNTO 9);
+      ELSE
+        ampl_V <= comp_pV(16 DOWNTO 9);
+      END IF;
+
+      -- Color carrier phase
+      IF (sof_dly(1) = '1') THEN
+        col_ctr <= (OTHERS => '0');
+      ELSE
+        -- +4 for NTSC, +5 for PAL
+        col_ctr <= col_ctr + ("0010" & (NOT pal_ntsc));
+      END IF;
+
+      ------------------
+      ------------------
+      -- Fourth stage --
+      ------------------
+      ------------------
+      
+      -- Copy Y
+      comp_Y4 <= comp_Y3;
+
+      -----------------
+      -----------------
+      -- Fifth stage --
+      -----------------
+      -----------------
+
+      -- Y/C signal
+      luma <= comp_Y4;
+      chroma <= comp_U + comp_V;
+
+    END IF;
+
+  END PROCESS;
+
+  -----------------------------------
+  -----------------------------------
+  -- 4th stage : chroma modulation --
+  -----------------------------------
+  -----------------------------------
+
+  tab_inst : sin_cos
+  PORT MAP
+  (
+    clk                => ecs_clk,
+    clk_ena            => '1',
+    sin_ph(4)          => col_ctr(4) XOR sign_U,
+    sin_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    sin_amp            => ampl_U,
+    sin_out            => comp_U,
+    cos_ph(4)          => col_ctr(4) XOR sign_V,
+    cos_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    cos_amp            => ampl_V,
+    cos_out            => comp_V
+  );
+
+  -----------------------------------
+  -- High-speed DAC with dithering --
+  -----------------------------------
+  PROCESS
+  (
+    areset_n,   -- Global reset
+    dac_clk,    -- DAC clock (114.545454 MHz)
+    luma,       -- Luminance data
+    chroma      -- Chrominance data
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      luma_1     <= (OTHERS => '0');
+      luma_2     <= (OTHERS => '0');
+      luma_acc   <= (OTHERS => '0');
+      chroma_1   <= (OTHERS => '0');
+      chroma_2   <= (OTHERS => '0');
+      chroma_acc <= (OTHERS => '0');
+    ELSE
+      IF (rising_edge(dac_clk)) THEN
+        -- Clock domain crossing
+        luma_1   <= luma;
+        luma_2   <= luma_1;
+        chroma_1 <= (NOT chroma(8)) & chroma(7 DOWNTO 1);
+        chroma_2 <= chroma_1;
+        -- First order delta-sigma
+        luma_acc   <= luma_2 + ("00000000" & luma_acc(1 DOWNTO 0));
+        chroma_acc <= chroma_2 + ("000000" & chroma_acc(1 DOWNTO 0));
+      END IF;
+    END IF;
+  END PROCESS;
+  -- Y/C outputs
+  y_out <= luma_acc(9 DOWNTO 2);
+  c_out <= chroma_acc(7 DOWNTO 2);
+
+END rtl;
Index: mcc216_5200/tb_sdram/sdram_ctrl_3_ports_tb.vhd
===================================================================
--- mcc216_5200/tb_sdram/sdram_ctrl_3_ports_tb.vhd	(nonexistent)
+++ mcc216_5200/tb_sdram/sdram_ctrl_3_ports_tb.vhd	(revision 288)
@@ -0,0 +1,265 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity sdram_ctrl_3_ports_tb is
+end;
+
+architecture rtl of sdram_ctrl_3_ports_tb is
+
+  constant CLK_A_PERIOD : time := 1 us / (1.79*32);
+
+COMPONENT sdram_ctrl
+port
+(
+  --//--------------------
+  --// Clocks and reset --
+  --//--------------------
+  --// Global reset
+  rst : in std_logic;
+  --// Controller clock
+  clk : in std_logic;
+  --// Sequencer cycles
+  seq_cyc : in std_logic_vector(11 downto 0);
+  --// Sequencer phase
+  seq_ph : in std_logic;
+  --// Refresh cycle
+  refr_cyc : in std_logic;
+  --//------------------------
+  --// Access port #1 (CPU) --
+  --//------------------------
+  --// RAM select
+  ap1_ram_sel : in std_logic;
+  --// Address bus
+  ap1_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap1_rden : in std_logic;
+  --// Write enable
+  ap1_wren : in std_logic;
+  --// Byte enable
+  ap1_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap1_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap1_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap1_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap1_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap1_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #2 (GPU) --
+  --//------------------------
+  --// RAM select
+  ap2_ram_sel : in std_logic;
+  --// Address bus
+  ap2_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap2_rden : in std_logic;
+  --// Write enable
+  ap2_wren : in std_logic;
+  --// Byte enable
+  ap2_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap2_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap2_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap2_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap2_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap2_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #3 (CTL) --
+  --//------------------------
+  --// RAM select
+  ap3_ram_sel : in std_logic;
+  --// Address bus
+  ap3_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap3_rden : in std_logic;
+  --// Write enable
+  ap3_wren : in std_logic;
+  --// Byte enable
+  ap3_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap3_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap3_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap3_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap3_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap3_wr_bst_act : out std_logic;
+  --//------------------------
+  --// SDRAM memory signals --
+  --//------------------------
+  --// SDRAM controller ready
+  sdram_rdy : out std_logic;
+  --// SDRAM chip select
+  sdram_cs_n : out std_logic;
+  --// SDRAM row address strobe
+  sdram_ras_n : out std_logic;
+  --// SDRAM column address strobe
+  sdram_cas_n : out std_logic;
+  --// SDRAM write enable
+  sdram_we_n : out std_logic;
+  --// SDRAM DQ masks
+  sdram_dqm_n : out std_logic_vector(1 downto 0);
+  --// SDRAM bank address
+  sdram_ba : out std_logic_vector(1 downto 0);
+  --// SDRAM address
+  sdram_addr : out std_logic_vector(11 downto 0);
+  --// SDRAM data
+  sdram_dq_oe : out std_logic;
+  sdram_dq_o : out std_logic_vector(15 downto 0);
+  sdram_dq_i : in std_logic_vector(15 downto 0)
+);
+END COMPONENT;
+
+  signal CLK_A : std_logic;
+
+  signal reset_n : std_logic;
+  signal reset : std_logic;
+
+  signal sdram_rdy : std_logic;
+  signal sdram_cs_n : std_logic;
+  signal sdram_ras_n : std_logic;
+  signal sdram_cas_n : std_logic;
+  signal sdram_we_n : std_logic;
+  signal sdram_dqm_n : std_logic_vector(1 downto 0);
+  signal sdram_ba : std_logic_vector(1 downto 0);
+  signal sdram_addr : std_logic_vector(11 downto 0);
+  signal sdram_dq_oe : std_logic;
+  signal sdram_dq_o : std_logic_vector(15 downto 0);
+  signal sdram_dq_i : std_logic_vector(15 downto 0);
+	
+  signal ram_address : std_logic_vector(23 downto 0);
+  signal ram_read : std_logic_vector(2 downto 0);
+  signal ram_write : std_logic_vector(2 downto 0);
+  signal ram_do : std_logic_vector(15 downto 0);
+  signal ram_do2 : std_logic_vector(15 downto 0);
+  signal ram_di : std_logic_vector(15 downto 0);
+  signal ram_di2 : std_logic_vector(15 downto 0);
+  signal ram_rd_active : std_logic_vector(2 downto 0);
+  signal ram_wr_active : std_logic_vector(2 downto 0);
+
+  signal seq_reg : std_logic_vector(11 downto 0);
+  signal seq_next : std_logic_vector(11 downto 0);
+
+  signal seq_ph_reg : std_logic;
+  signal seq_ph_next : std_logic;
+
+  signal ref_reg : std_logic;
+  signal ref_next : std_logic;
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk_a <= '1';
+	wait for CLK_A_PERIOD/2;
+	clk_a <= '0';
+	wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+	reset <= not(reset_n);
+
+	ram_address <= X"123456";
+	ram_read <= "010";
+	ram_write <= "001";
+	ram_di <= X"f00"&seq_reg(3 downto 0);
+	ram_di2 <= X"abc"&seq_reg(3 downto 0);
+
+	process(clk_a,reset_n)
+	begin
+		if (reset_n='0') then
+			seq_reg <= "000000000001";
+			seq_ph_reg <= '0';
+			ref_reg <= '0';
+		elsif (clk_a'event and clk_a = '1') then
+			seq_reg <= seq_next;
+			seq_ph_reg <= seq_ph_next;
+			ref_reg <= ref_next;
+		end if;
+	end process;
+
+	process(seq_reg, seq_ph_reg, ref_reg)
+	begin
+		seq_next <= seq_reg(10 downto 0)&seq_reg(11);
+		seq_ph_next <= seq_ph_reg;
+		ref_next <= ref_reg;
+		if (seq_reg(10) = '1') then
+			seq_ph_next <= not(seq_ph_reg);
+			ref_next <= not(ref_reg);
+		end if;
+	end process;
+
+sdram_controller : sdram_ctrl
+	PORT MAP
+	(
+		CLK => clk_a,
+		rst => reset,
+		seq_cyc => seq_reg(11 downto 0),
+		seq_ph => seq_ph_reg,
+		refr_cyc => '0', -- TODO - try toggling refresh...
+
+		ap1_ram_sel => '1',
+		ap1_address => ram_address(23 downto 1),
+		ap1_rden => ram_read(0),
+		ap1_wren => ram_write(0),
+		ap1_bena => "01",
+		ap1_rddata => ram_do,
+		ap1_wrdata => ram_di,
+		ap1_bst_siz => "010",
+		ap1_rd_bst_act => ram_rd_active(0),
+		ap1_wr_bst_act => ram_wr_active(0),
+
+		ap2_ram_sel => '1',
+		ap2_address => ram_address(23 downto 1),
+		ap2_rden => ram_read(1),
+		ap2_wren => ram_write(1),
+		ap2_bena => "11",
+		ap2_rddata => ram_do2,
+		ap2_wrdata => ram_di2,
+		ap2_bst_siz => "111",
+		ap2_rd_bst_act => ram_rd_active(1),
+		ap2_wr_bst_act => ram_wr_active(1),
+
+		ap3_ram_sel => '0',
+		ap3_address => ram_address(23 downto 1),
+		ap3_rden => '0',
+		ap3_wren => '0',
+		ap3_bena => "11",
+		ap3_rddata => open,
+		ap3_wrdata => X"0000",
+		ap3_bst_siz => "111",
+		ap3_rd_bst_act => ram_rd_active(2),
+		ap3_wr_bst_act => ram_wr_active(2),
+
+		sdram_rdy => sdram_rdy,
+		sdram_cs_n => sdram_cs_n,
+		sdram_ras_n => sdram_ras_n,
+		sdram_cas_n => sdram_cas_n,
+		sdram_we_n => sdram_we_n,
+		sdram_dqm_n => sdram_dqm_n,
+		sdram_ba => sdram_ba,
+		sdram_addr => sdram_addr,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+	);
+
+sdram_dq_i <= X"d"&seq_reg(11 downto 0);
+
+end rtl;
+
Index: mcc216_5200/usbpll.cmp
===================================================================
--- mcc216_5200/usbpll.cmp	(nonexistent)
+++ mcc216_5200/usbpll.cmp	(revision 288)
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component usbpll
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcc216_5200/._.DS_Store
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcc216_5200/._.DS_Store
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216_5200/atari5200core.jdi
===================================================================
--- mcc216_5200/atari5200core.jdi	(nonexistent)
+++ mcc216_5200/atari5200core.jdi	(revision 288)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: mcc216_5200/atari5200core.qpf
===================================================================
--- mcc216_5200/atari5200core.qpf	(nonexistent)
+++ mcc216_5200/atari5200core.qpf	(revision 288)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: mcc216_5200/atari5200core.qsf
===================================================================
--- mcc216_5200/atari5200core.qsf	(nonexistent)
+++ mcc216_5200/atari5200core.qsf	(revision 288)
@@ -0,0 +1,304 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari5200core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari5200core_mcc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_134 -to VGA_R[1]
+set_location_assignment PIN_133 -to VGA_R[2]
+set_location_assignment PIN_132 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_G[0]
+set_location_assignment PIN_142 -to VGA_G[1]
+set_location_assignment PIN_143 -to VGA_G[2]
+set_location_assignment PIN_144 -to VGA_G[3]
+set_location_assignment PIN_4 -to VGA_B[0]
+set_location_assignment PIN_7 -to VGA_B[1]
+set_location_assignment PIN_10 -to VGA_B[2]
+set_location_assignment PIN_11 -to VGA_B[3]
+set_location_assignment PIN_136 -to VGA_HS
+set_location_assignment PIN_137 -to VGA_VS
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_44 -to SD_CLK
+set_location_assignment PIN_46 -to SD_CMD
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_location_assignment PIN_28 -to AUDIO_L
+set_location_assignment PIN_30 -to AUDIO_R
+set_location_assignment PIN_53 -to CPU_RESET_n
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_127 -to JOY1_n[0]
+set_location_assignment PIN_91 -to JOY1_n[1]
+set_location_assignment PIN_90 -to JOY1_n[2]
+set_location_assignment PIN_88 -to JOY1_n[3]
+set_location_assignment PIN_89 -to JOY1_n[4]
+set_location_assignment PIN_126 -to JOY1_n[5]
+set_location_assignment PIN_128 -to JOY2_n[0]
+set_location_assignment PIN_25 -to JOY2_n[1]
+set_location_assignment PIN_24 -to JOY2_n[2]
+set_location_assignment PIN_22 -to JOY2_n[3]
+set_location_assignment PIN_23 -to JOY2_n[4]
+set_location_assignment PIN_129 -to JOY2_n[5]
+set_location_assignment PIN_33 -to PS2K_DAT
+set_location_assignment PIN_39 -to PS2K_CLK
+set_location_assignment PIN_32 -to PS2M_DAT
+set_location_assignment PIN_31 -to PS2M_CLK
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_49 -to SD_DAT3
+set_location_assignment PIN_42 -to USB_P
+set_location_assignment PIN_43 -to USB_N
+set_location_assignment PIN_50 -to USB2_P
+set_location_assignment PIN_51 -to USB2_N
+set_location_assignment PIN_112 -to SDRAM_CLK
+set_location_assignment PIN_61 -to SDRAM_A[0]
+set_location_assignment PIN_60 -to SDRAM_A[1]
+set_location_assignment PIN_59 -to SDRAM_A[2]
+set_location_assignment PIN_58 -to SDRAM_A[3]
+set_location_assignment PIN_125 -to SDRAM_A[4]
+set_location_assignment PIN_121 -to SDRAM_A[5]
+set_location_assignment PIN_120 -to SDRAM_A[6]
+set_location_assignment PIN_119 -to SDRAM_A[7]
+set_location_assignment PIN_115 -to SDRAM_A[8]
+set_location_assignment PIN_114 -to SDRAM_A[9]
+set_location_assignment PIN_64 -to SDRAM_A[10]
+set_location_assignment PIN_113 -to SDRAM_A[11]
+set_location_assignment PIN_111 -to SDRAM_A[12]
+set_location_assignment PIN_66 -to SDRAM_BA[0]
+set_location_assignment PIN_65 -to SDRAM_BA[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_79 -to SDRAM_DQ[5]
+set_location_assignment PIN_77 -to SDRAM_DQ[6]
+set_location_assignment PIN_76 -to SDRAM_DQ[7]
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_67 -to SDRAM_CS_n
+set_location_assignment PIN_68 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_CAS_n
+set_location_assignment PIN_71 -to SDRAM_WE_n
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_13 -to CFG_DIN
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+
+
+set_global_assignment -name QIP_FILE usbpll.qip
+set_global_assignment -name QIP_FILE pal_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_pal.qip
+set_global_assignment -name QIP_FILE ntsc_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
+set_global_assignment -name SDC_FILE atari5200core.sdc
+set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+set_global_assignment -name VHDL_FILE atari5200core_mcc.vhd
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: mcc216_5200/atari5200core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcc216_5200/atari5200core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216_5200/atari5200core.sdc
===================================================================
--- mcc216_5200/atari5200core.sdc	(nonexistent)
+++ mcc216_5200/atari5200core.sdc	(revision 288)
@@ -0,0 +1,3 @@
+create_clock -period 5MHz [get_ports FPGA_CLK]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: mcc216_5200/atari5200core_assignment_defaults.qdf
===================================================================
--- mcc216_5200/atari5200core_assignment_defaults.qdf	(nonexistent)
+++ mcc216_5200/atari5200core_assignment_defaults.qdf	(revision 288)
@@ -0,0 +1,805 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 14:59:26  November 15, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
Index: mcc216_5200/atari5200core_mcc.cmd
===================================================================
--- mcc216_5200/atari5200core_mcc.cmd	(nonexistent)
+++ mcc216_5200/atari5200core_mcc.cmd	(revision 288)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcc216_5200/atari5200core_mcc.vhd
===================================================================
--- mcc216_5200/atari5200core_mcc.vhd	(nonexistent)
+++ mcc216_5200/atari5200core_mcc.vhd	(revision 288)
@@ -0,0 +1,931 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari5200core_mcc IS 
+	GENERIC
+	(
+		TV : integer;  -- 1 = PAL, 0=NTSC
+		VIDEO : integer; -- 1 = SVIDEO, 2 = VGA
+		SCANDOUBLE : integer; -- 1 = YES, 0=NO, (+ later scanlines etc)
+		internal_rom : integer;
+		internal_ram : integer;
+		ext_clock : integer
+	);
+	PORT
+	(
+		FPGA_CLK :  IN  STD_LOGIC;
+
+		-- For test bench
+		EXT_CLK_SDRAM : in std_logic_vector(ext_clock downto 1);
+		EXT_CLK : in std_logic_vector(ext_clock downto 1);
+		EXT_SDRAM_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_SVIDEO_DAC_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_SCANDOUBLE_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);
+
+		PS2K_CLK :  IN  STD_LOGIC;
+		PS2K_DAT :  IN  STD_LOGIC;
+		PS2M_CLK :  IN  STD_LOGIC;
+		PS2M_DAT :  IN  STD_LOGIC;		
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		
+		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_CS_N :  OUT  STD_LOGIC;
+		SDRAM_RAS_N :  OUT  STD_LOGIC;
+		SDRAM_CAS_N :  OUT  STD_LOGIC;
+		SDRAM_WE_N :  OUT  STD_LOGIC;
+		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		--SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC;
+
+		USB2_P :  INOUT  STD_LOGIC;
+		USB2_N :  INOUT  STD_LOGIC
+	);
+END atari5200core_mcc;
+
+ARCHITECTURE vhdl OF atari5200core_mcc IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+COMPONENT sdram_ctrl
+port
+(
+  --//--------------------
+  --// Clocks and reset --
+  --//--------------------
+  --// Global reset
+  rst : in std_logic;
+  --// Controller clock
+  clk : in std_logic;
+  --// Sequencer cycles
+  seq_cyc : in std_logic_vector(11 downto 0);
+  --// Sequencer phase
+  seq_ph : in std_logic;
+  --// Refresh cycle
+  refr_cyc : in std_logic;
+  --//------------------------
+  --// Access port #1 (CPU) --
+  --//------------------------
+  --// RAM select
+  ap1_ram_sel : in std_logic;
+  --// Address bus
+  ap1_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap1_rden : in std_logic;
+  --// Write enable
+  ap1_wren : in std_logic;
+  --// Byte enable
+  ap1_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap1_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap1_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap1_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap1_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap1_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #2 (GPU) --
+  --//------------------------
+  --// RAM select
+  ap2_ram_sel : in std_logic;
+  --// Address bus
+  ap2_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap2_rden : in std_logic;
+  --// Write enable
+  ap2_wren : in std_logic;
+  --// Byte enable
+  ap2_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap2_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap2_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap2_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap2_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap2_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #3 (CTL) --
+  --//------------------------
+  --// RAM select
+  ap3_ram_sel : in std_logic;
+  --// Address bus
+  ap3_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap3_rden : in std_logic;
+  --// Write enable
+  ap3_wren : in std_logic;
+  --// Byte enable
+  ap3_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap3_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap3_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap3_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap3_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap3_wr_bst_act : out std_logic;
+  --//------------------------
+  --// SDRAM memory signals --
+  --//------------------------
+  --// SDRAM controller ready
+  sdram_rdy : out std_logic;
+  --// SDRAM chip select
+  sdram_cs_n : out std_logic;
+  --// SDRAM row address strobe
+  sdram_ras_n : out std_logic;
+  --// SDRAM column address strobe
+  sdram_cas_n : out std_logic;
+  --// SDRAM write enable
+  sdram_we_n : out std_logic;
+  --// SDRAM DQ masks
+  sdram_dqm_n : out std_logic_vector(1 downto 0);
+  --// SDRAM bank address
+  sdram_ba : out std_logic_vector(1 downto 0);
+  --// SDRAM address
+  sdram_addr : out std_logic_vector(11 downto 0);
+  --// SDRAM data
+  sdram_dq_oe : out std_logic;
+  sdram_dq_o : out std_logic_vector(15 downto 0);
+  sdram_dq_i : in std_logic_vector(15 downto 0)
+);
+END COMPONENT;
+
+	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+	
+	signal VIDEO_VS : std_logic;
+	signal VIDEO_HS : std_logic;
+	signal VIDEO_R : std_logic_vector(7 downto 0);
+	signal VIDEO_G : std_logic_vector(7 downto 0);
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+	signal VIDEO_BLANK : std_logic;
+	signal VIDEO_BURST : std_logic;
+	signal VIDEO_START_OF_FIELD : std_logic;
+	signal VIDEO_ODD_LINE : std_logic;
+
+	signal JOY1_USB : std_logic_vector(5 downto 0);
+	signal JOY2_USB : std_logic_vector(5 downto 0);
+	signal JOY1_USB_n : std_logic_vector(4 downto 0);
+	signal JOY2_USB_n : std_logic_vector(4 downto 0);
+
+	signal PLL1_LOCKED : std_logic;
+	signal CLK_PLL1 : std_logic;
+	
+	signal RESET_n : std_logic;
+	signal PLL_LOCKED : std_logic;
+	signal CLK : std_logic;
+	signal CLK_SDRAM : std_logic;
+
+	-- SDRAM
+	signal PREREG_SDRAM_REQUEST : std_logic;
+	signal PREREG_SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
+	signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
+	SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+	signal SDRAM_REQUEST : std_logic;
+	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal SDRAM_WRITE_ENABLE : std_logic;
+	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);
+	SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+
+	signal SDRAM_REQUEST_COMPLETE : std_logic;
+	
+	signal SDRAM_REFRESH : std_logic;
+
+	signal SYSTEM_RESET_REQUEST: std_logic;
+
+	signal seq_reg : std_logic_vector(11 downto 0);
+	signal seq_next : std_logic_vector(11 downto 0);
+	
+	signal seq_ph_reg : std_logic;
+	signal seq_ph_next : std_logic;
+	
+	signal ref_reg : std_logic;
+	signal ref_next : std_logic;
+
+	signal sdram_request_complete_next : std_logic;
+	signal sdram_request_complete_reg : std_logic;
+
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+
+	signal ram_di_next : std_logic_vector(15 downto 0);
+	signal ram_di_reg : std_logic_vector(15 downto 0);
+
+	signal ram_do_next : std_logic_vector(31 downto 0);
+	signal ram_do_reg : std_logic_vector(31 downto 0);
+
+	signal ram_do : std_logic_vector(15 downto 0);
+
+	signal ram_bena_next : std_logic_vector(1 downto 0);
+	signal ram_bena_reg : std_logic_vector(1 downto 0);
+
+	signal ram_rd_active : std_logic;
+	signal ram_wr_active : std_logic;
+
+	signal sdram_dq_oe : std_logic;
+	signal sdram_dq_o : std_logic_vector(15 downto 0);
+	signal sdram_dq_i : std_logic_vector(15 downto 0);
+	
+	signal sdram_rdy : std_logic;
+	signal sdram_reset_ctrl_n_next : std_logic;
+	signal sdram_reset_ctrl_n_reg : std_logic;
+	signal sdram_reset_n_next : std_logic;
+	signal sdram_reset_n_reg : std_logic;
+
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	signal controller_select : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- scandoubler
+	signal scandouble_clk : std_logic;
+
+	signal half_scandouble_enable_reg : std_logic;
+	signal half_scandouble_enable_next : std_logic;
+
+	function palette_from_scandouble( scandouble : integer ) return integer is
+	begin
+		if (scandouble = 1) then
+			return 0;
+		else
+			return 1;
+		end if;
+	end palette_from_scandouble;
+	
+	-- svideo
+	signal svideo_dac_clk : std_logic;
+
+	signal svideo_y : std_logic_vector(7 downto 0);
+	signal svideo_c : std_logic_vector(5 downto 0);
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT5 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
+	-- usb
+	signal CLK_USB : std_logic;
+
+	signal USBWireVPin : std_logic;
+	signal USBWireVMin : std_logic;
+	signal USBWireVPout : std_logic;
+	signal USBWireVMout : std_logic;
+	signal USBWireOE_n : std_logic;
+
+	signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
+	signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
+
+	-- paddles
+	signal		JOY1X : std_logic_vector(7 downto 0);
+	signal		JOY1Y : std_logic_vector(7 downto 0);
+	signal		JOY2X : std_logic_vector(7 downto 0);
+	signal		JOY2Y : std_logic_vector(7 downto 0);
+
+BEGIN 
+
+USB2_N <= USBWireVPout when USBWireOE_n='0' else 'Z';
+USB2_P <= USBWireVMout when USBWireOE_n='0' else 'Z';
+USBWireVPin <= USB2_N;
+USBWireVMin <= USB2_P;
+
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => audio_r
+);
+
+gen_fake_pll : if ext_clock=1 generate
+	CLK_SDRAM <= EXT_CLK_SDRAM(1);
+	CLK <= EXT_CLK(1);
+	SDRAM_CLK <= EXT_CLK_SDRAM(1);
+	SVIDEO_DAC_CLK <= EXT_SVIDEO_DAC_CLK(1);
+	SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);
+	PLL_LOCKED <= EXT_PLL_LOCKED(1);
+end generate;
+
+usb_pll : entity work.usbpll
+PORT MAP(inclk0 => FPGA_CLK,
+	 c0 => CLK_USB,
+	 locked => open);
+
+gen_real_pll : if ext_clock=0 generate
+	gen_tv_ntsc : if tv=0 generate
+		mcc_pll : entity work.ntsc_pll
+		PORT MAP(inclk0 => FPGA_CLK,
+				 c0 => CLK_PLL1,
+				 locked => PLL1_LOCKED);
+		mcc_pll2 : entity work.pll_downstream_ntsc
+		PORT MAP(inclk0 => CLK_PLL1,
+				 c0 => CLK_SDRAM,
+				 c1 => CLK,
+				 c2 => SDRAM_CLK,
+				 c3 => SVIDEO_DAC_CLK,
+				 c4 => SCANDOUBLE_CLK,      
+				 areset => not(PLL1_LOCKED),
+				 locked => PLL_LOCKED);
+	end generate;
+end generate;
+
+reset_n <= PLL_LOCKED;
+--JOY1_IN_N <= JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3);
+--JOY2_IN_N <= JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari5200
+	GENERIC MAP
+	(
+		ps2_enable => 1,
+		direct_enable => 1
+	)
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2k_clk,
+		PS2_DAT => ps2k_dat,
+
+		INPUT => zpu_out4,
+
+		FIRE2 => '0'&'0'&joy2_usb(4)&joy1_usb(4),
+		CONTROLLER_SELECT => CONTROLLER_SELECT, -- selected stick keyboard/shift button
+
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		
+		FKEYS => FKEYS,
+
+		PS2_KEYS_NEXT_OUT => ps2_keys_next,
+		PS2_KEYS => ps2_keys
+	);
+
+
+JOY1_USB <= zpu_out2(5 downto 4)&zpu_out2(0)&zpu_out2(1)&zpu_out2(2)&zpu_out2(3);
+JOY2_USB <= zpu_out3(5 downto 4)&zpu_out3(0)&zpu_out3(1)&zpu_out3(2)&zpu_out3(3);
+JOY1_USB_N <= not(JOY1_USB(5)&JOY1_USB(3 downto 0));
+JOY2_USB_N <= not(JOY2_USB(5)&JOY2_USB(3 downto 0));
+
+JOY1X <= zpu_out5(7 downto 0);
+JOY1Y <= zpu_out5(15 downto 8);
+JOY2X <= zpu_out5(23 downto 16);
+JOY2Y <= zpu_out5(31 downto 24);
+
+atari5200_simple_sdram1 : entity work.atari5200core_simplesdram
+	GENERIC MAP
+	(
+		cycle_length => 16,
+		internal_rom => internal_rom,
+		internal_ram => internal_ram,
+		video_bits => 8,
+		palette => palette_from_scandouble(scandouble)
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
+		RESET_N => RESET_N and SDRAM_RESET_N_REG,
+
+		VIDEO_VS => VIDEO_VS,
+		VIDEO_HS => VIDEO_HS,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => VIDEO_G,
+		VIDEO_R => VIDEO_R,
+		VIDEO_BLANK =>VIDEO_BLANK,
+		VIDEO_BURST =>VIDEO_BURST,
+		VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,
+		VIDEO_ODD_LINE =>VIDEO_ODD_LINE,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => PREREG_SDRAM_ADDR,
+		SDRAM_DO => ram_do_reg,
+		SDRAM_DI => PREREG_SDRAM_DI,
+		SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_REFRESH => SDRAM_REFRESH,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
+
+		THROTTLE_COUNT_6502 => speed_6502,
+		HALT => pause_atari,
+
+		-- JOYSTICK
+		JOY1_X => signed(joy1x),
+		JOY1_Y => signed(joy1y),
+		JOY1_BUTTON => joy1_usb_n(4),
+		JOY2_X => signed(joy2x),
+		JOY2_Y => signed(joy2y),
+		JOY2_BUTTON => joy2_usb_n(4),
+
+		-- Pokey keyboard matrix
+		-- Standard component available to connect this to PS2
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		CONTROLLER_SELECT => CONTROLLER_SELECT
+	);
+
+	process(clk_sdram,sdram_reset_ctrl_n_reg)
+	begin
+		if (sdram_reset_ctrl_n_reg='0') then
+			seq_reg <= "010000000000";
+			seq_ph_reg <= '1';
+			ref_reg <= '0';
+
+			ram_do_reg <= (others=>'0');
+			ram_di_reg <= (others=>'0');
+			ram_bena_reg <= (others=>'0');
+			sdram_request_complete_reg <= '0';
+			sdram_request_reg <= '0';
+		elsif (clk_sdram'event and clk_sdram = '1') then
+			seq_reg <= seq_next;
+			seq_ph_reg <= seq_ph_next;
+			ref_reg <= ref_next;
+
+			ram_do_reg <= ram_do_next;
+			ram_di_reg <= ram_di_next;
+			ram_bena_reg <= ram_bena_next;
+			sdram_request_complete_reg <= sdram_request_complete_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			sdram_reset_n_reg <= '0';
+			sdram_reset_ctrl_n_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			sdram_reset_n_reg <= sdram_reset_n_next;
+			sdram_reset_ctrl_n_reg <= reset_n;
+		end if;
+	end process;
+
+	-- Generate sdram sequence
+	process(seq_reg, seq_ph_reg, ref_reg)
+	begin
+		seq_next <= seq_reg(10 downto 0)&seq_reg(11);
+		seq_ph_next <= seq_ph_reg;
+		ref_next <= ref_reg;
+		if (seq_reg(11) = '1') then
+			seq_ph_next <= not(seq_ph_reg);
+			ref_next <= not(ref_reg);
+		end if;
+	end process;
+
+	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
+	begin
+		sdram_reset_n_next <= sdram_reset_n_reg;
+		if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
+			sdram_reset_n_next <= '1';
+		end if;
+		if (reset_atari = '1') then
+			sdram_reset_n_next <= '0';
+		end if;
+	end process;
+
+	-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			SDRAM_REQUEST <= '0';
+			SDRAM_READ_ENABLE <= '0';
+			SDRAM_WRITE_ENABLE <= '0';
+			SDRAM_ADDR <= (others=>'0');
+			SDRAM_DI <= (others=>'0');
+			SDRAM_WIDTH_32BIT_ACCESS <= '0';
+			SDRAM_WIDTH_16BIT_ACCESS <= '0';
+			SDRAM_WIDTH_8BIT_ACCESS <= '0';
+		elsif(clk'event and clk='0') then -- FALLING EDGE
+			SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
+			SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
+			SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
+			SDRAM_ADDR <= PREREG_SDRAM_ADDR;
+			SDRAM_DI <= PREREG_SDRAM_DI;
+			SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
+			SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
+			SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
+		end if;
+	end process;
+
+	-- Adapt SDRAM
+	process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
+	begin
+		sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
+		sdram_request_complete_next <= sdram_request_complete_reg;
+		ram_bena_next <= "00";
+		ram_di_next <= (others=>'0');
+		ram_do_next <= ram_do_reg;
+
+		case seq_reg is
+		when "000000000001" =>
+			-- nop
+		when "000000000010" => -- write data from next...
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);
+					ram_bena_next <= SDRAM_ADDR(0)&not(SDRAM_ADDR(0));
+				else
+					ram_di_next <= SDRAM_DI(15 downto 0);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+		when "000000000100" =>
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= (others=>'0');
+				else
+					ram_di_next <= SDRAM_DI(31 downto 16);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+			if ((ram_wr_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000000001000" =>
+			-- nop
+		when "000000010000" =>
+			-- nop
+		when "000000100000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when "000001000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					if (SDRAM_ADDR(0) = '0') then
+						ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);
+					else
+						ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);
+					end if;
+				else
+					ram_do_next(15 downto 0) <= ram_do;
+				end if;
+			end if;
+		when "000010000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_do_next(31 downto 16) <= (others=>'0');
+				else
+					ram_do_next(31 downto 16) <= ram_do;
+				end if;
+			end if;
+			if ((ram_rd_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000100000000" =>
+			-- nop
+		when "001000000000" =>
+			-- nop
+		when "010000000000" =>
+			-- nop
+		when "100000000000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when others =>
+			-- never
+		end case;
+	end process;
+
+	SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;
+sdram_controller : sdram_ctrl
+	PORT MAP
+	(
+		CLK => CLK_SDRAM,
+		rst => not(sdram_reset_ctrl_n_reg),
+		seq_cyc => seq_reg(11 downto 0),
+		seq_ph => seq_ph_reg,
+		--refr_cyc => ref_reg,
+		refr_cyc => SDRAM_REFRESH,
+
+		ap1_ram_sel => SDRAM_REQUEST_NEXT,
+		ap1_address => '0'&SDRAM_ADDR(22 downto 1),
+		ap1_rden => SDRAM_READ_ENABLE,
+		ap1_wren => SDRAM_WRITE_ENABLE,
+		ap1_bena => ram_bena_reg,
+		ap1_rddata => ram_do,
+		ap1_wrdata => ram_di_reg,
+		ap1_bst_siz => "001",
+		ap1_rd_bst_act => ram_rd_active,
+		ap1_wr_bst_act => ram_wr_active,
+
+		ap2_ram_sel => '0',
+		ap2_address => "00000000000000000000000",
+		ap2_rden => '0',
+		ap2_wren => '0',
+		ap2_bena => "11",
+		ap2_rddata => open,
+		ap2_wrdata => X"0000",
+		ap2_bst_siz => "111",
+		ap2_rd_bst_act => open,
+		ap2_wr_bst_act => open,
+
+		ap3_ram_sel => '0',
+		ap3_address => "00000000000000000000000",
+		ap3_rden => '0',
+		ap3_wren => '0',
+		ap3_bena => "11",
+		ap3_rddata => open,
+		ap3_wrdata => X"0000",
+		ap3_bst_siz => "111",
+		ap3_rd_bst_act => open,
+		ap3_wr_bst_act => open,
+
+		sdram_rdy => sdram_rdy,
+		sdram_cs_n => sdram_cs_n,
+		sdram_ras_n => sdram_ras_n,
+		sdram_cas_n => sdram_cas_n,
+		sdram_we_n => sdram_we_n,
+		sdram_dqm_n => sdram_dqm_n,
+		sdram_ba => sdram_ba,
+		sdram_addr => sdram_a(11 downto 0),
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+	);
+
+sdram_dq <= sdram_dq_o when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i <= sdram_dq;
+sdram_a(12) <= '1';
+
+-- Video options
+gen_video_vga : if video=2 generate
+	gen_scandouble_off: if scandouble=0 generate
+		VGA_HS <= not(VIDEO_HS xor VIDEO_VS);
+		VGA_VS <= not(VIDEO_VS);
+		VGA_B <= VIDEO_B(7 downto 4);
+		VGA_G <= VIDEO_G(7 downto 4);
+		VGA_R <= VIDEO_R(7 downto 4);
+	end generate;
+
+	gen_scandouble_on: if scandouble=1 generate
+		process(scandouble_clk,sdram_reset_n_reg)
+		begin
+			if (sdram_reset_n_reg='0') then
+				half_scandouble_enable_reg <= '0';
+			elsif (scandouble_clk'event and scandouble_clk='1') then
+				half_scandouble_enable_reg <= half_scandouble_enable_next;
+			end if;
+		end process;
+
+		half_scandouble_enable_next <= not(half_scandouble_enable_reg);
+
+		scandoubler1: entity work.scandoubler
+		PORT MAP
+		( 
+			CLK => SCANDOUBLE_CLK,
+		        RESET_N => sdram_reset_n_reg,
+			
+			VGA => '1',
+			COMPOSITE_ON_HSYNC => '0', -- TODO
+
+			colour_enable => half_scandouble_enable_reg,
+			doubled_enable => '1',
+			
+			-- GTIA interface
+			pal => '0',
+			colour_in => VIDEO_B,
+			vsync_in => VIDEO_VS,
+			hsync_in => VIDEO_HS,
+			
+			-- TO TV...
+			R => VGA_R,
+			G => VGA_G,
+			B => VGA_B,
+			
+			VSYNC => VGA_VS,
+			HSYNC => VGA_HS
+		);
+	end generate;
+
+end generate;
+
+gen_video_svideo: if video=1 generate
+
+	-- SVIDEO COMPONENT
+	svideo : entity work.svideo
+	PORT MAP
+	(
+		areset_n => RESET_N,
+		ecs_clk => CLK,
+		dac_clk => SVIDEO_DAC_CLK,
+		r_in => VIDEO_R,
+		g_in => VIDEO_G,
+		b_in => VIDEO_B,
+		sof => VIDEO_VS, -- base on vsync?
+		vpos_lsb => VIDEO_ODD_LINE,
+		blank => VIDEO_BLANK,
+		burst => VIDEO_BURST,
+		csync_n => not(VIDEO_HS xor VIDEO_VS),
+		
+		y_out => svideo_y,
+		c_out => svideo_c,
+		
+		pal_ntsc => not('0')
+	);
+	VGA_B <= svideo_y(7 downto 4);
+	VGA_G <= svideo_y(3 downto 0);
+	VGA_R <= svideo_c(5 downto 2);
+	VGA_HS <= svideo_c(1);
+	VGA_VS <= svideo_c(0);
+
+end generate;
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
+		memory => 8192,
+		usb => 1
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_rdy,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_dat0,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_dat3,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"000"&
+			"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+			FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2, --joy0
+		ZPU_OUT3 => zpu_out3, --joy1
+		ZPU_OUT4 => zpu_out4, --keyboard
+		ZPU_OUT5 => zpu_out5, --analog stick
+
+		-- USB host
+		CLK_USB => CLK_USB,
+	
+		USBWireVPin(0) => USBWireVPin,
+		USBWireVMin(0) => USBWireVMin,
+		USBWireVPout(0) => USBWireVPout,
+		USBWireVMout(0) => USBWireVMout,
+		USBWireOE_n(0) => USBWireOE_n
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(14 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>16) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+END vhdl;
Index: mcc216_5200/rbf2arg/rbf2arg.exe
===================================================================
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Index: mcc216_5200/sdram_clock_sync.wcfg
===================================================================
--- mcc216_5200/sdram_clock_sync.wcfg	(nonexistent)
+++ mcc216_5200/sdram_clock_sync.wcfg	(revision 288)
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="26" />
+   <wvobject fp_name="/atari800core_mcc_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_two" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_two</obj_property>
+      <obj_property name="ObjectShortName">clk_two</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_three" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_three</obj_property>
+      <obj_property name="ObjectShortName">clk_three</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_four" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_four</obj_property>
+      <obj_property name="ObjectShortName">clk_four</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/enable_179" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_179</obj_property>
+      <obj_property name="ObjectShortName">enable_179</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/throttle_count_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="ObjectShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready</obj_property>
+      <obj_property name="ObjectShortName">memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel_dly" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel_dly[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel_dly[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_refresh" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_refresh</obj_property>
+      <obj_property name="ObjectShortName">sdram_refresh</obj_property>
+   </wvobject>
+</wave_config>
Index: mcc216_5200/sdram_ctrl_3_ports.v
===================================================================
--- mcc216_5200/sdram_ctrl_3_ports.v	(nonexistent)
+++ mcc216_5200/sdram_ctrl_3_ports.v	(revision 288)
@@ -0,0 +1,629 @@
+//`include "arg_defs.vh"
+
+module sdram_ctrl /* verilator tracing_off */
+(
+  //--------------------
+  // Clocks and reset --
+  //--------------------
+  // Global reset
+  input             rst,
+  // Controller clock
+  input             clk,
+  // Sequencer cycles
+  input      [11:0] seq_cyc,
+  // Sequencer phase
+  input             seq_ph,
+  // Refresh cycle
+  input             refr_cyc,
+  //------------------------
+  // Access port #1 (CPU) --
+  //------------------------
+  // RAM select
+  input             ap1_ram_sel,
+  // Address bus
+  input      [23:1] ap1_address,
+  // Read enable
+  input             ap1_rden,
+  // Write enable
+  input             ap1_wren,
+  // Byte enable
+  input       [1:0] ap1_bena,
+  // Data bus (read)
+  output     [15:0] ap1_rddata,
+  // Data bus (write)
+  input      [15:0] ap1_wrdata,
+  // Burst size
+  input       [2:0] ap1_bst_siz,
+  // Read burst active
+  output reg        ap1_rd_bst_act,
+  // Write burst active
+  output            ap1_wr_bst_act,
+  //------------------------
+  // Access port #2 (GPU) --
+  //------------------------
+  // RAM select
+  input             ap2_ram_sel,
+  // Address bus
+  input      [23:1] ap2_address,
+  // Read enable
+  input             ap2_rden,
+  // Write enable
+  input             ap2_wren,
+  // Byte enable
+  input       [1:0] ap2_bena,
+  // Data bus (read)
+  output     [15:0] ap2_rddata,
+  // Data bus (write)
+  input      [15:0] ap2_wrdata,
+  // Burst size
+  input       [2:0] ap2_bst_siz,
+  // Read burst active
+  output reg        ap2_rd_bst_act,
+  // Write burst active
+  output            ap2_wr_bst_act,
+  //------------------------
+  // Access port #3 (CTL) --
+  //------------------------
+  // RAM select
+  input             ap3_ram_sel,
+  // Address bus
+  input      [23:1] ap3_address,
+  // Read enable
+  input             ap3_rden,
+  // Write enable
+  input             ap3_wren,
+  // Byte enable
+  input       [1:0] ap3_bena,
+  // Data bus (read)
+  output     [15:0] ap3_rddata,
+  // Data bus (write)
+  input      [15:0] ap3_wrdata,
+  // Burst size
+  input       [2:0] ap3_bst_siz,
+  // Read burst active
+  output reg        ap3_rd_bst_act,
+  // Write burst active
+  output            ap3_wr_bst_act,
+  //------------------------
+  // SDRAM memory signals --
+  //------------------------
+  // SDRAM controller ready
+  output reg        sdram_rdy,
+  // SDRAM chip select
+  output reg        sdram_cs_n,
+  // SDRAM row address strobe
+  output reg        sdram_ras_n,
+  // SDRAM column address strobe
+  output reg        sdram_cas_n,
+  // SDRAM write enable
+  output reg        sdram_we_n,
+  // SDRAM DQ masks
+  output reg  [1:0] sdram_dqm_n,
+  // SDRAM bank address
+  output reg  [1:0] sdram_ba,
+  // SDRAM address
+  output reg [11:0] sdram_addr,
+  // SDRAM data
+  output reg        sdram_dq_oe,
+  output reg [15:0] sdram_dq_o,
+  input      [15:0] sdram_dq_i
+);
+
+// SDRAM memory size
+parameter SDRAM_SIZE     = 16;
+// SDRAM operational frequency
+parameter SDRAM_FREQ     = 85909090;
+// Hidden refresh mode
+parameter HIDDEN_REFRESH = 0;
+// MODE REGISTER SET value (RS = 00, WB = 0, OP = 00, CL = 010, BT = 0, BL = 011)
+parameter MRS_VALUE = 12'b000000100011;
+// Refresh period
+parameter REF_COUNT = ((SDRAM_FREQ / ((12 * 64000)))) - 1;
+// Clock-to-output delay
+parameter Tco_dly = 4.5;
+
+// Port select signals
+reg   [2:0] r_psel;       // Port select (one hot)
+reg   [2:0] r_psel_dly;   // Port select delayed
+
+// Refresh signals
+reg         r_refr_req;   // Refresh requested
+reg         r_refr_act;   // Refresh active
+reg         r_refr_ack;   // Refresh acknowledged
+reg  [31:0] r_refr_ctr;   // Refresh counter
+
+// Port multiplexer signals
+wire        w_rden;       // Read enable
+reg         r_rd_reg;     // Registered read enable
+reg         r_rd_act;     // Read active
+wire        w_wren;       // Write enable
+reg         r_wr_reg;     // Registered write enable
+reg         r_wr_act;     // Write active
+wire        w_ram_sel;    // RAM select
+reg   [2:0] r_rd_bctr;    // Read burst counter
+reg   [2:0] r_wr_bctr;    // Write burst counter
+wire  [2:0] w_bst_siz;    // Burst size (load value of burst counters)
+reg   [2:0] r_bst_stp;    // Burst stop
+wire  [1:0] w_dqm;        // Bytes masks
+wire [23:1] w_addr;       // Address
+reg  [15:0] r_rddata;     // Data read
+wire [15:0] w_wrdata;     // Data written
+
+// SDRAM speed adjustment
+wire        w_rd_start;   // Read start condition
+wire        w_wr_start;   // Write start condition
+wire  [3:0] w_rd_cycle;   // First read cycle number
+
+// Initialization signals
+reg   [2:0] r_init_fsm;   // SDRAM initialization state machine
+reg  [10:0] r_init_tmr;   // SDRAM initialization timer
+
+// Output registers
+reg         r_sdram_cs_n;  // SDRAM chip select
+reg         r_sdram_ras_n; // SDRAM row address strobe
+reg         r_sdram_cas_n; // SDRAM column address strobe
+reg         r_sdram_we_n;  // SDRAM write enable
+reg   [1:0] r_sdram_dqm_n; // SDRAM DQ masks
+reg   [1:0] r_sdram_ba;    // SDRAM bank address
+reg  [11:0] r_sdram_addr;  // SDRAM address
+reg  [15:0] r_sdram_dq_o;  // SDRAM DQ output
+reg         r_sdram_dq_oe; // SDRAM DQ output enable
+
+  // Signal multiplexing based on the port select
+  assign w_wren         = (ap1_wren & r_psel[0])
+                        | (ap2_wren & r_psel[1])
+                        | (ap3_wren & r_psel[2]);
+  assign w_rden         = (ap1_rden & r_psel[0])
+                        | (ap2_rden & r_psel[1])
+                        | (ap3_rden & r_psel[2]);
+  assign w_ram_sel      = (HIDDEN_REFRESH == 1)
+                        ? (r_psel[0] | r_psel[1] | r_psel[2])
+                        : (r_psel[0] | r_psel[1] | r_psel[2]) & ~r_refr_req;
+  assign w_dqm[0]       = (ap1_bena[0] & r_psel[0])
+                        | (ap2_bena[0] & r_psel[1])
+                        | (ap3_bena[0] & r_psel[2]);
+  assign w_dqm[1]       = (ap1_bena[1] & r_psel[0])
+                        | (ap2_bena[1] & r_psel[1])
+                        | (ap3_bena[1] & r_psel[2]);
+  assign w_bst_siz[2]   = (ap1_bst_siz[2] & r_psel[0])
+                        | (ap2_bst_siz[2] & r_psel[1])
+                        | (ap3_bst_siz[2] & r_psel[2]);
+  assign w_bst_siz[1]   = (ap1_bst_siz[1] & r_psel[0])
+                        | (ap2_bst_siz[1] & r_psel[1])
+                        | (ap3_bst_siz[1] & r_psel[2]);
+  assign w_bst_siz[0]   = (ap1_bst_siz[0] & r_psel[0])
+                        | (ap2_bst_siz[0] & r_psel[1])
+                        | (ap3_bst_siz[0] & r_psel[2]);
+  assign w_addr[23:1]   = (ap1_address[23:1] & {23{r_psel[0]}})
+                        | (ap2_address[23:1] & {23{r_psel[1]}})
+                        | (ap3_address[23:1] & {23{r_psel[2]}});
+  assign w_wrdata[15:0] = (ap1_wrdata[15:0] & {16{r_psel[0]}})
+                        | (ap2_wrdata[15:0] & {16{r_psel[1]}})
+                        | (ap3_wrdata[15:0] & {16{r_psel[2]}});
+
+  // SDRAM speed adjustment
+  assign w_rd_cycle = (SDRAM_FREQ < 50000000) ? 4'd2 : 4'd3;
+  assign w_rd_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[2] & r_rd_reg) : (seq_cyc[4] & r_rd_reg);
+  assign w_wr_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[0] & w_wren & w_ram_sel) : (seq_cyc[1] & r_wr_reg);
+  
+  // Write burst active flags, one cycle before "r_wr_act"
+  assign ap1_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[0];
+  assign ap2_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[1];
+  assign ap3_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[2];
+  
+  // SDRAM data read
+  assign ap1_rddata = r_rddata;
+  assign ap2_rddata = r_rddata;
+  assign ap3_rddata = r_rddata;
+  
+  // Hidden refresh / port select :
+  //-------------------------------
+  // rst         : Global reset
+  // clk         : SDRAM controller clock
+  // seq_cyc     : Sequencer cycle (0 to 11)
+  // seq_ph      : Sequencer phase (0 or 1)
+  // r_refr_req  : Internal refresh cycle request
+  // r_refr_ack  : Internal refresh cycle acknowledge
+  // r_refr_ctr  : Internal refresh counter
+  // r_psel      : Port select (one hot)
+  // r_psel_dly  : Delayed port select
+  // ap1_ram_sel : Port #1 access
+  // ap2_ram_sel : Port #2 access
+  // ap3_ram_sel : Port #3 access
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Refresh counter
+      r_refr_ctr <= REF_COUNT;
+      // Refresh cycle request
+      r_refr_req <= 1'b0;
+    end else begin
+      // Hidden refresh case
+      if (HIDDEN_REFRESH == 1) begin
+        // Sequencer cycle #11
+        if (seq_cyc[11]) begin
+          // Internal refresh counter
+          if (r_refr_ctr == 0) begin
+            r_refr_req <= 1'b1;
+            r_refr_ctr <= REF_COUNT;
+          end
+          else begin
+            r_refr_ctr <= r_refr_ctr - 1;
+          end
+        end
+        // When refresh cycle is acknowledged
+        if (r_refr_ack == 1'b1) begin
+          // Clear the refresh cycle request
+          r_refr_req <= 1'b0;
+        end
+      end else begin
+        // External refresh
+        r_refr_req <= refr_cyc;
+      end
+    end
+    
+    if (rst) begin
+      // Port select
+      r_psel     <= 3'b000;
+      r_psel_dly <= 3'b000;
+    end else begin
+      // Access port select
+      if (seq_cyc[11]) begin
+        if (!seq_ph) begin
+          // Phase #0 : select port #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel;
+          r_psel[1] <= 1'b0;
+          r_psel[2] <= ap3_ram_sel & ~ap1_ram_sel;
+        end
+        else begin
+          // Phase #1 : select port #2 (GPU) -> #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel & ~ap2_ram_sel;
+          r_psel[1] <= ap2_ram_sel;
+          r_psel[2] <= ap3_ram_sel & ~(ap1_ram_sel | ap2_ram_sel);
+        end
+      end
+      // Delayed port select for data read multiplexer
+      if (seq_cyc[1]) begin
+        r_psel_dly <= r_psel;
+      end
+    end
+  end
+
+  // Burst activities :
+  //-------------------
+  // rst        : Global reset
+  // clk        : SDRAM controller clock
+  // w_rd_start : Read start conditions
+  // w_wr_start : Write start conditions
+  // r_rd_reg   : Read mode (registered)
+  // r_rd_act   : Read active
+  // r_wr_act   : Write active
+  // r_rd_bctr  : Burst read counter
+  // r_wr_bctr  : Burst write counter
+  // r_psel_dly : Port select delayed
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Burst signals
+      r_rd_act       <= 1'b0;
+      r_wr_act       <= 1'b0;
+      r_rd_bctr      <= 3'b000;
+      r_wr_bctr      <= 3'b000;
+      ap1_rd_bst_act <= 1'b0;
+      ap2_rd_bst_act <= 1'b0;
+      ap3_rd_bst_act <= 1'b0;
+      // Data bus
+      r_rddata       <= 16'h0000;
+      r_sdram_dqm_n  <= 2'b11;
+      r_sdram_dq_oe  <= 1'b0;
+      r_sdram_dq_o   <= 16'h0000;
+    end else begin
+      // Prepare write burst cycles
+      if (w_wr_start) begin
+        // Set the active bits
+        r_wr_act  <= 1'b1;
+        // Start the burst counter
+        r_wr_bctr <= w_bst_siz;
+      end
+      // Prepare read burst cycles
+      if (w_rd_start) begin
+        // Set the active bits
+        r_rd_act  <= 1'b1;
+        // Start the burst counter
+        r_rd_bctr <= r_bst_stp;
+      end
+      // Read burst counter management
+      if (r_rd_act) begin
+        if (r_rd_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_rd_act <= 1'b0;
+        end
+        else begin
+          r_rd_bctr <= r_rd_bctr - 3'b1;
+        end
+      end
+      // Write burst counter management
+      if (r_wr_act) begin
+        if (r_wr_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_wr_act <= 1'b0;
+        end
+        else begin
+          r_wr_bctr <= r_wr_bctr - 3'b1;
+        end
+      end
+      // Read burst active flags, one cycle after "r_rd_act"
+      ap1_rd_bst_act <= r_rd_act & r_psel_dly[0];
+      ap2_rd_bst_act <= r_rd_act & r_psel_dly[1];
+      ap3_rd_bst_act <= r_rd_act & r_psel_dly[2];
+      // Read SDRAM data
+      r_rddata <= sdram_dq_i;
+      // Write SDRAM data / DQM management
+      if (r_wr_act) begin
+        r_sdram_dqm_n[0] <= ~w_dqm[0];
+        r_sdram_dqm_n[1] <= ~w_dqm[1];
+        r_sdram_dq_oe    <= 1'b1;
+        r_sdram_dq_o     <= w_wrdata;
+      end
+      else begin
+        r_sdram_dqm_n[0] <= ~r_rd_reg;
+        r_sdram_dqm_n[1] <= ~r_rd_reg;
+        r_sdram_dq_oe    <= 1'b0;
+        r_sdram_dq_o     <= 16'h0000;
+      end
+    end
+  end
+
+  // SDRAM controller state machine :
+  //---------------------------------
+  //  rst        : Global reset
+  //  clk        : SDRAM controller clock
+  //  seq_cyc    : Sequencer cycle
+  //  r_refr_req : Refresh cycle requested
+  //  r_refr_act : Refresh cycle active
+  //  r_refr_ack : Refresh cycle acknowledge
+  //  w_ram_sel  : SDRAM selected
+  //  w_rden     : Read enable flag
+  //  w_wren     : Write enable flag
+  //  r_rd_reg   : Read mode (registered)
+  //  r_wr_reg   : Write mode (registered)
+  //  w_bst_siz  : Burst size (1 to 8 words)
+  //  r_bst_stp  : Burst stop cycle
+  //  r_init_fsm : SDRAM initialization state
+  //  r_init_tmr : SDRAM initialization timer (>100 us)
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // SDRAM outputs
+      r_sdram_cs_n  <= 1'b1;
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      r_sdram_ba    <= 2'b00;
+      r_sdram_addr  <= 12'b000000000000;
+      // Controller state
+      r_rd_reg      <= 1'b0;
+      r_wr_reg      <= 1'b0;
+      r_bst_stp     <= 3'b000;
+      sdram_rdy     <= 1'b0;
+      r_refr_ack    <= 1'b0;
+      r_refr_act    <= 1'b0;
+      // 1024 * 12 cycles > 100 us
+      r_init_tmr    <= 11'd0;    // 143 us
+      r_init_fsm    <= 3'b000;
+    end else begin
+      // Default : NOPs
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      if (r_init_fsm[2]) begin
+        // Chip select management
+        if (seq_cyc[0]) begin
+          // RAM selected or refresh request
+          r_sdram_cs_n <= ~(w_ram_sel | r_refr_req);
+        end
+        // If there is an active refresh
+        if (r_refr_act) begin
+          //------------------
+          // Refresh cycles --
+          //------------------
+          // Cycle #0 : clear read/write enable signals
+          r_rd_reg <= 1'b0;
+          r_wr_reg <= 1'b0;
+          // Cycle #2 : prepare AUTO REFRESH cmd for cycle #3
+          if (seq_cyc[2]) begin
+            r_sdram_ras_n <= 1'b0;
+            r_sdram_cas_n <= 1'b0;
+          end
+          // Cycle #9 : acknowledge the refresh request
+          if (seq_cyc[9]) begin
+            // Hidden refresh case
+            if (HIDDEN_REFRESH == 1) begin
+              r_refr_ack <= 1'b1;
+            end
+            r_refr_act <= 1'b0;
+          end
+        end
+        else begin
+          //-----------------
+          // Normal cycles --
+          //-----------------
+          // Hidden refresh case
+          if (HIDDEN_REFRESH == 1) begin
+            // Clear any refresh acknowledge
+            r_refr_ack <= 1'b0;
+          end
+          if (seq_cyc[0]) begin
+            // If no access, activate refresh
+            r_refr_act <= ~((w_rden | w_wren) & w_ram_sel) & r_refr_req;
+            // Register read/write enable signals
+            r_rd_reg   <= w_rden & w_ram_sel;
+            r_wr_reg   <= w_wren & w_ram_sel;
+            // Register the burst stop
+            r_bst_stp  <= w_bst_siz;
+          end
+          // Cycle #0 : prepare ACTIVATE cmd for cycle #1
+          //            set the row address and the bank number
+          if ((seq_cyc[0]) && (w_ram_sel) && ((w_rden) || (w_wren))) begin
+            r_sdram_ras_n <= 1'b0;
+            if (SDRAM_SIZE == 16) begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[23:12];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[11:10];
+            end else begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[22:11];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[10:9];
+            end
+          end
+          // Cycle #1/2 : prepare READ/WRITE cmd for next cycle
+          //              set the column address and the bank number
+          if ((seq_cyc[w_rd_cycle - 1]) && ((r_rd_reg) || (r_wr_reg))) begin
+            r_sdram_cas_n <= 1'b0;
+            r_sdram_we_n  <= ~r_wr_reg;
+            if (SDRAM_SIZE == 16)
+              // 512 columns : 9 address lines
+              r_sdram_addr  <= {3'b010, w_addr[9:1]};
+            else
+              // 256 columns : 8 address lines
+              r_sdram_addr  <= {4'b0100, w_addr[8:1]};
+          end
+          // Cycles #2/3+ : prepare the PRECHARGE cmd (burst stop)
+          //if ((seq_cyc[w_rd_cycle + r_bst_stp]) && ((r_rd_reg) || (r_wr_reg))) begin
+          //  r_sdram_ras_n <= 1'b0;
+          //  r_sdram_we_n  <= 1'b0;
+          //end
+        end
+      end
+      else begin
+        //---------------
+        // Init cycles --
+        //---------------
+        if (r_init_tmr[10]) begin
+          // Select SDRAM
+          r_sdram_cs_n <= 1'b0;
+          case (r_init_fsm[1:0])
+            2'd0 : begin
+              // Prepare PRECHARGE ALL cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n    <= 1'b0;
+                r_sdram_we_n     <= 1'b0;
+                r_sdram_addr[10] <= 1'b1;
+              end
+            end
+            2'd1 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd2 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd3 : begin
+              // Prepare MODE REGISTER SET value
+              if (seq_cyc[1]) begin
+                r_sdram_addr <= MRS_VALUE;
+              end
+              // Prepare MODE REGISTER SET cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+                r_sdram_we_n  <= 1'b0;
+              end
+              // SDRAM is initialized
+              if (seq_cyc[10]) begin
+                sdram_rdy <= 1'b1;
+              end
+            end
+            default : begin
+            end
+          endcase
+          // Cycle #11 : next state
+          if (seq_cyc[11]) begin
+            r_init_fsm <= r_init_fsm + 3'd1;
+          end
+        end
+        else begin
+          // Deselect SDRAM
+          r_sdram_cs_n <= 1'b1;
+          // Cycle #11 : timer management
+          if (seq_cyc[11]) begin
+            r_init_tmr <= r_init_tmr + 11'd1;
+          end
+        end
+      end
+    end
+  end
+  
+  // TCO delay on all outputs
+  always@(r_sdram_cs_n or r_sdram_ras_n or r_sdram_cas_n or r_sdram_we_n or
+          r_sdram_dqm_n or r_sdram_ba or r_sdram_addr or r_sdram_dq_oe or r_sdram_dq_o) begin
+  `ifdef SIMULATION
+  
+    `ifdef verilator3
+      // Cycle based simulation
+      sdram_cs_n   = r_sdram_cs_n;
+      sdram_ras_n  = r_sdram_ras_n;
+      sdram_cas_n  = r_sdram_cas_n;
+      sdram_we_n   = r_sdram_we_n;
+      sdram_dqm_n  = r_sdram_dqm_n;
+      sdram_ba     = r_sdram_ba;
+      sdram_addr   = r_sdram_addr;
+      sdram_dq_oe  = r_sdram_dq_oe;
+      sdram_dq_o   = r_sdram_dq_o;
+    `else
+      // Timing based simulation
+      sdram_cs_n   = #Tco_dly r_sdram_cs_n;
+      sdram_ras_n  = #Tco_dly r_sdram_ras_n;
+      sdram_cas_n  = #Tco_dly r_sdram_cas_n;
+      sdram_we_n   = #Tco_dly r_sdram_we_n;
+      sdram_dqm_n  = #Tco_dly r_sdram_dqm_n;
+      sdram_ba     = #Tco_dly r_sdram_ba;
+      sdram_addr   = #Tco_dly r_sdram_addr;
+      sdram_dq_oe  = #Tco_dly r_sdram_dq_oe;
+      sdram_dq_o   = #Tco_dly r_sdram_dq_o;
+    `endif
+    
+  `else
+    // Synthesis
+    sdram_cs_n   = r_sdram_cs_n;
+    sdram_ras_n  = r_sdram_ras_n;
+    sdram_cas_n  = r_sdram_cas_n;
+    sdram_we_n   = r_sdram_we_n;
+    sdram_dqm_n  = r_sdram_dqm_n;
+    sdram_ba     = r_sdram_ba;
+    sdram_addr   = r_sdram_addr;
+    sdram_dq_oe  = r_sdram_dq_oe;
+    sdram_dq_o   = r_sdram_dq_o;
+  `endif
+  end
+
+`ifdef SIMULATION
+
+`ifndef verilator3
+  // Setup and hold times check for DQ
+  reg r_dq_noti;
+
+  specify
+    specparam
+      Tsu_dly =  0.7, // Input setup time
+      Th_dly  = -0.5; // Input hold time
+    $setuphold(posedge clk, sdram_dq_i, Tsu_dly, Th_dly, r_dq_noti);
+  endspecify
+
+  always @(r_dq_noti)
+  begin
+    $display($realtime, " ns : Setup/Hold time violation on DQ inputs");
+  end
+`endif
+  
+`endif
+
+endmodule
+
+/* verilator tracing_off */
Index: mcc216_5200/sdram_ctrl_4_ports.v
===================================================================
--- mcc216_5200/sdram_ctrl_4_ports.v	(nonexistent)
+++ mcc216_5200/sdram_ctrl_4_ports.v	(revision 288)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: mcc216_5200/simulate_full.sh
===================================================================
--- mcc216_5200/simulate_full.sh	(nonexistent)
+++ mcc216_5200/simulate_full.sh	(revision 288)
@@ -0,0 +1,73 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=atari800core_mcc
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_full/* .
+
+        # copy source files
+	cp `find ../../common/a8core/ -iname "*.vhd"` .
+	cp `find ../../common/a8core/ -iname "*.vhdl"` .
+	cp `find ../../common/components/ -iname "*.vhd"` .
+	cp `find ../../common/components/ -iname "*.vhdl"` .
+	cp `find ../../common/zpu/ -iname "*.vhd"` .
+	cp `find ../../common/zpu/ -iname "*.vhdl"` .
+	cp ../atari800core_mcc.vhd .
+	cp ../zpu_rom.vhdl .
+	cp ../sdram_ctrl_3_ports.v .
+	cp ../*pll*.vhd* .
+	cp ../svideo/* .
+
+        # set up project definition file
+	ls *.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat >> $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: mcc216_5200/simulate_full.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcc216_5200/svideo/sin_cos.vhd
===================================================================
--- mcc216_5200/svideo/sin_cos.vhd	(nonexistent)
+++ mcc216_5200/svideo/sin_cos.vhd	(revision 288)
@@ -0,0 +1,102 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE sin_cos_pkg IS
+  COMPONENT sin_cos
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+  END COMPONENT;
+END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+ENTITY sin_cos IS
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+END sin_cos;
+
+ARCHITECTURE rtl OF sin_cos IS
+
+  COMPONENT sin_rom IS
+  PORT
+  (
+    clock     : IN STD_LOGIC;
+    enable    : IN STD_LOGIC := '1';
+    address_a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    q_a       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+  END COMPONENT sin_rom;
+
+  SIGNAL sin_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL cos_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL sin_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL cos_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+BEGIN
+
+  sin_inst : sin_rom
+  PORT MAP
+  (
+    clock                  => clk,
+    enable                 => clk_ena,
+    address_a(10 DOWNTO 3) => sin_amp,
+    address_a(2)           => sin_ph(2) XOR sin_ph(3),
+    address_a(1)           => sin_ph(1) XOR sin_ph(3),
+    address_a(0)           => sin_ph(0) XOR sin_ph(3),
+    q_a                    => sin_val(7 DOWNTO 0),
+    address_b(10 DOWNTO 3) => cos_amp,
+    address_b(2)           => cos_ph(2) XOR (NOT cos_ph(3)),
+    address_b(1)           => cos_ph(1) XOR (NOT cos_ph(3)),
+    address_b(0)           => cos_ph(0) XOR (NOT cos_ph(3)),
+    q_b                    => cos_val(7 DOWNTO 0)
+  );
+  sin_val(8) <= '0';
+  cos_val(8) <= '0';
+  
+  -- Delayed phase for output generation
+  sin_ph_dly <= sin_ph WHEN rising_edge(clk);
+  cos_ph_dly <= cos_ph WHEN rising_edge(clk);
+
+  -- Output generation using sine and cosine symetries
+  sin_cos_gen:
+  FOR i IN 0 TO 8 GENERATE
+    sin_out(i) <= sin_val(i) XOR sin_ph_dly(4);
+    cos_out(i) <= cos_val(i) XOR cos_ph_dly(3) XOR cos_ph_dly(4);
+  END GENERATE;
+
+END rtl;
\ No newline at end of file
Index: mcc216_5200/svideo/sin_rom.vhd
===================================================================
--- mcc216_5200/svideo/sin_rom.vhd	(nonexistent)
+++ mcc216_5200/svideo/sin_rom.vhd	(revision 288)
@@ -0,0 +1,266 @@
+-- megafunction wizard: %ROM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: sin_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.0 Build 132 02/25/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sin_rom IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		enable		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END sin_rom;
+
+
+ARCHITECTURE SYN OF sin_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3_bv	: BIT_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clocken0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2    <= '0';
+	sub_wire3_bv(7 DOWNTO 0) <= "00000000";
+	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		init_file => "sin_rom.mif",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		numwords_b => 2048,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 11,
+		widthad_b => 11,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		clocken0 => enable,
+		wren_a => sub_wire2,
+		wren_b => sub_wire2,
+		clock0 => clock,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => sub_wire3,
+		data_b => sub_wire3,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "sin_rom.mif"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "sin_rom.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
+-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC enable
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mcc216_5200/tb_full/atari800core_mcc_tb.vhd
===================================================================
--- mcc216_5200/tb_full/atari800core_mcc_tb.vhd	(nonexistent)
+++ mcc216_5200/tb_full/atari800core_mcc_tb.vhd	(revision 288)
@@ -0,0 +1,165 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity atari800core_mcc_tb is
+end;
+
+architecture rtl of atari800core_mcc_tb is
+
+--  constant CLK_PERIOD : time := 1 us / (1.79*16);
+--  constant CLK_PERIOD_FOUR : time := 1 us / (1.79*64);
+--  constant CLK_PERIOD_THREE : time := 1 us / (1.79*48);
+--  constant CLK_PERIOD_TWO : time := 1 us / (1.79*32);
+  constant CLK_PERIOD : time := 36ns;
+  constant CLK_PERIOD_FOUR : time := 9ns;
+  constant CLK_PERIOD_THREE : time := 12ns;
+  constant CLK_PERIOD_TWO : time := 18ns;
+  signal CLK : std_logic;
+  signal CLK_TWO : std_logic;
+  signal CLK_THREE : std_logic;
+  signal CLK_FOUR : std_logic;
+
+  signal reset_n : std_logic;
+  signal reset : std_logic;
+
+  signal	VGA_VS : std_logic;
+  signal	VGA_HS : std_logic;
+  signal	VGA_B : std_logic_vector(3 downto 0);
+  signal	VGA_G : std_logic_vector(3 downto 0);
+  signal	VGA_R : std_logic_vector(3 downto 0);
+  signal	AUDIO_L : std_logic;
+  signal	AUDIO_R : std_logic;
+  signal	SDRAM_BA : std_logic_vector(1 downto 0);
+  signal	SDRAM_CS_N : std_logic;
+  signal	SDRAM_RAS_N : std_logic;
+  signal	SDRAM_CAS_N : std_logic;
+  signal	SDRAM_WE_N : std_logic;
+  signal	SDRAM_DQM_n : std_logic_vector(1 downto 0);
+  signal	SDRAM_CLK : std_logic;
+  signal	SDRAM_A : std_logic_vector(12 downto 0);
+  signal	SDRAM_DQ : std_logic_vector(15 downto 0);
+
+  signal sd_clk : std_logic;
+  signal sd_dat : std_logic;
+
+begin
+	p_clk_gen_1 : process
+	begin
+	clk <= '1';
+	wait for CLK_PERIOD/2;
+	clk <= '0';
+	wait for CLK_PERIOD - (CLK_PERIOD/2 );
+	end process;
+
+	p_clk_gen_2 : process
+	begin
+	clk_two <= '1';
+	wait for CLK_PERIOD_TWO/2;
+	clk_two <= '0';
+	wait for CLK_PERIOD_TWO - (CLK_PERIOD_TWO/2 );
+	end process;
+
+	p_clk_gen_3 : process
+	begin
+	clk_three <= '1';
+	wait for CLK_PERIOD_three/2;
+	clk_three <= '0';
+	wait for CLK_PERIOD_three - (CLK_PERIOD_three/2 );
+	end process;
+
+	p_clk_gen_4 : process
+	begin
+	clk_four <= '1';
+	wait for CLK_PERIOD_four/2;
+	clk_four <= '0';
+	wait for CLK_PERIOD_four - (CLK_PERIOD_four/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+	reset <= not(reset_n);
+
+atari : ENTITY work.atari800core_mcc 
+	GENERIC map
+	(
+		TV => 1,
+		VIDEO => 2,
+		SCANDOUBLE => 0,
+		internal_ram => 0,
+		internal_rom => 1,
+		ext_clock => 1
+	)
+	port map
+	(
+		FPGA_CLK => '0',
+
+		EXT_CLK_SDRAM(1) => clk_three,
+		EXT_CLK(1) => clk,
+		EXT_SDRAM_CLK(1) => clk_three,
+                EXT_SVIDEO_DAC_CLK(1) => clk_four,
+                EXT_SCANDOUBLE_CLK(1) => clk_two,
+                EXT_PLL_LOCKED(1) => reset_n,
+
+		PS2K_CLK => '1',
+		PS2K_DAT => '1',
+		PS2M_CLK => '1',
+		PS2M_DAT => '1',
+
+		VGA_VS => VGA_VS,
+		VGA_HS => VGA_HS,
+		VGA_B => VGA_B,
+		VGA_G => VGA_G,
+		VGA_R => VGA_R,
+		
+		JOY1_n => "111111",
+		JOY2_n => "111111",
+		
+		AUDIO_L => AUDIO_L,
+		AUDIO_R => AUDIO_R,
+
+		SDRAM_BA => SDRAM_BA,
+		SDRAM_CS_N => SDRAM_CS_N,
+		SDRAM_RAS_N => SDRAM_RAS_N,
+		SDRAM_CAS_N => SDRAM_CAS_N,
+		SDRAM_WE_N => SDRAM_WE_N,
+		SDRAM_DQM_n => SDRAM_DQM_n,
+		SDRAM_CLK => SDRAM_CLK,
+		--SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A => SDRAM_A,
+		SDRAM_DQ => SDRAM_DQ,
+
+		SD_DAT0 => sd_dat,
+		SD_CLK => sd_clk,
+		SD_CMD => open,
+		SD_DAT3 => open
+	);
+
+--ENTITY pokey_poly_5 IS
+--PORT 
+--( 
+--	CLK : IN STD_LOGIC;
+--	RESET_N : IN STD_LOGIC;
+--	ENABLE : IN STD_LOGIC;
+--	INIT : IN STD_LOGIC;
+--	
+--	BIT_OUT : OUT STD_LOGIC
+--);
+--END pokey_poly_5;
+	poly : entity work.pokey_poly_5
+	port map
+	(
+		clk=>sd_clk,
+		reset_n=>reset_n,
+		enable=>'1',
+		init=>not(reset_n),
+		bit_out=>sd_dat
+	);
+
+end rtl;
+
Index: mcc216_5200/turbo.wcfg
===================================================================
--- mcc216_5200/turbo.wcfg	(nonexistent)
+++ mcc216_5200/turbo.wcfg	(revision 288)
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="9" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/speed_shift_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">speed_shift_next[15:0]</obj_property>
+      <obj_property name="ObjectShortName">speed_shift_next[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/speed_shift_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">speed_shift_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">speed_shift_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/throttle_count_6502" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle_count_6502[5:0]</obj_property>
+      <obj_property name="ObjectShortName">throttle_count_6502[5:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/enable_179" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_179</obj_property>
+      <obj_property name="ObjectShortName">enable_179</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/cpu_enable_out" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_enable_out</obj_property>
+      <obj_property name="ObjectShortName">cpu_enable_out</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_read_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_read_enable</obj_property>
+      <obj_property name="ObjectShortName">sdram_read_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_write_enable</obj_property>
+      <obj_property name="ObjectShortName">sdram_write_enable</obj_property>
+   </wvobject>
+</wave_config>
Index: mcc216_5200/atari_mcc_auto_stripped.stp
===================================================================
--- mcc216_5200/atari_mcc_auto_stripped.stp	(nonexistent)
+++ mcc216_5200/atari_mcc_auto_stripped.stp	(revision 288)
@@ -0,0 +1,1585 @@
+<session jtag_chain="USB-Blaster [1-2]" jtag_device="@1: EP3C16/EP4CE15 (0x020F20DD)" sof_file="">
+  <display_tree gui_logging_enabled="1">
+    <display_branch instance="auto_signaltap_0" log="log: 2014/04/26 08:28:05  #1" signal_set="signal_set: 2014/04/25 22:38:45  #0" trigger="trigger: 2014/04/26 08:28:05  #0"/>
+  </display_tree>
+  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <signal_set is_expanded="true" name="signal_set: 2014/04/25 22:38:45  #0">
+      <clock name="sdram_ctrl:sdram_controller|clk" polarity="posedge" tap_mode="classic"/>
+      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <node data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <node data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <node data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <node data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <node data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <node data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <node data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <node data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <node data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <node data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <node data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <node data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <node data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <node data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <node data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <node data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <node data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <node data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <node data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <node data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <node data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <node data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <node data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <node data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </node>
+          <node data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <node data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <node name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <node data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <node data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <node data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <node data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <node data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <node data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <node data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <node data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <node data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <node data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <node data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <node data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <node data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <node data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <node data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <node data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </node>
+          <node data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <node name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <node data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <node data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <node data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <node data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <node data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <node data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <node data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <node data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <node data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <node data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <node data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <node data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <node data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <node data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <node data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <node data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <node data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <node data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <node data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <node data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <node data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <node data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <node data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <node data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <node data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <node data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <node data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <node data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <node data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <node data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <node data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <node data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <node data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <node data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <node data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <node data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <node data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <node data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <node data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <node data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <node data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <node data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <node data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <node data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <node data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <node data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <node data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <node data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </node>
+          <node data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <node data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </node>
+          <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <node data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <node data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <node data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <node data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <node data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <node data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <node data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <node data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <node data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <node data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <node data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <node data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
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+            <node data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
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+            <node data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <node data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <node data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <node data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
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+            <node data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <node data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <node data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <node data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <node data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <node data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <node data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
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+            <node data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
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+            <node data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
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+          <node data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
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+            <node data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
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+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
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+            <node data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <node data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <node data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <node data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <node data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <node data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <node data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </node>
+          <node data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <node data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </unified_setup_data_view>
+        <data_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </data_view>
+        <setup_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger CRC="FA424211" attribute_mem_mode="false" gap_record="true" is_expanded="true" name="trigger: 2014/04/26 08:28:05  #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1024" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="no">
+          <level enabled="no" name="condition1" type="basic">'SDRAM_WE_N' == falling edge
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="no" name="condition2" type="basic">'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]' == low
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition3" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition4" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition5" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <custom_flow_control>
+            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
+            <flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </flow_expression>
+            <power_up_flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </power_up_flow_expression>
+          </custom_flow_control>
+        </events>
+        <storage_qualifier_events>
+          <transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
+            <pwr_up_transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+      </trigger>
+    </signal_set>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="360"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="64"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="2032"/>
+    </position_info>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <multi attribute="frame size" size="2" value="1625,976"/>
+    <multi attribute="jtag widget size" size="2" value="398,120"/>
+  </global_info>
+</session>
Index: mcc216_5200/build.err
===================================================================
Index: mcc216_5200/build.sh
===================================================================
--- mcc216_5200/build.sh	(nonexistent)
+++ mcc216_5200/build.sh	(revision 288)
@@ -0,0 +1,124 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $SVIDEO = 1;
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+	"SIMPLE" =>
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $VGA,
+		"internal_ram" => 16384,
+		"internal_rom" => 1,
+		"ext_clock" => 0
+	},
+	"NTSC_SVIDEO" =>
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $SVIDEO,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	},
+	"NTSC_RGB" => 
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $VGA,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	},
+	"NTSC_VGA" => 
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 1,
+		"VIDEO" => $VGA,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari5200core_mcc.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp sdram_ctrl_3_ports.v $dir`;
+	`cp zpu_rom.vhdl $dir`;
+	`cp atari5200core.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`mkdir $dir/svideo`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	mkdir "./$dir/common/components/usbhostslave";
+	`cp ../common/components/usbhostslave/trunk/RTL/*/*.v ./$dir/common/components/usbhostslave`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+	`cp ./svideo/* ./$dir/svideo`;
+
+	chdir $dir;
+	`../makeqsf ../atari5200core.qsf ./svideo ./common/a8core ./common/components ./common/zpu ./common/components/usbhostslave`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari5200core.qsf`;
+	}
+
+	`quartus_sh --flow compile atari5200core > build.log 2> build.err`;
+
+	`quartus_cpf --convert ../output_file.cof`;
+	my $vga = 1;
+	if ($variant =~ /SVIDEO/)
+	{
+		$vga = 0;
+	}
+	
+	#TODO - generate automated version number
+	my $version = `svn info  | grep Revision: | cut -d' ' -f 2`;
+	chomp $version;
+	$version = `date +%y%m`;
+	my $version2 = `date +%d`;
+	chomp $version;
+	chomp $version2;
+	my $cmd = "wine ../rbf2arg/rbf2arg.exe $vga A $version.$version2 \"Atari 5200 $variant\" output_files/atari5200core.rbf output_files/atari5200core_$variant.arg";
+	print "Running $cmd\n";
+	`$cmd`;
+	
+	chdir "..";
+}
+
+
+#--for the MCC216 S-Video
+#--rbf2arg 0 A <version.revison> "description" <filename.rbf> <filename.arg>
+#--for the MCC216 VGA
+#--rbf2arg 1 A <version.revison> "description" <filename.rbf> <filename.arg>
+
+

Property changes on: mcc216_5200/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcc216_5200/clocks.txt
===================================================================
--- mcc216_5200/clocks.txt	(nonexistent)
+++ mcc216_5200/clocks.txt	(revision 288)
@@ -0,0 +1,15 @@
+he ARG file are generated by the RBF2ARG tool.
+Please find it attached the encrypted ZIP file (your last name as a password).
+IIRC, the usage is :
+for the MCC216 S-Video
+rbf2arg 0 A <version.revison> "description" <filename.rbf> <filename.arg>
+for the MCC216 VGA
+rbf2arg 1 A <version.revison> "description" <filename.rbf> <filename.arg>
+Then, you have to put the ARG file under /System/core and voila, you are ready to flash it on your HW.
+
+As for the S-Video, I have attached the S-Video core.
+It uses Direct Digital Synthesis (DDS). It needs clocks at 28 and 114 MHz but it can be adapted for 57 MHz.
+It is compatible with PAL and NTSC providing you set correctly the "pal_ntsc" signal and the clock is 28.375 MHz for PAL and 28.636363 for NTSC.
+BTW, I do not know how you generate the clock for your core but, what we do is : 
+5 x 227 / 40 = 28.375
+5 x 63 / 11 = 28.6363
Index: mcc216_5200/cparg
===================================================================
--- mcc216_5200/cparg	(nonexistent)
+++ mcc216_5200/cparg	(revision 288)
@@ -0,0 +1,5 @@
+ln -s build_NTSC_SVIDEO/output_files/atari800core.arg atari800core.arg_NTSC_SVIDEO
+ln -s build_PAL_SVIDEO/output_files/atari800core.arg atari800core.arg_PAL_SVIDEO
+ln -s build_NTSC_VGA/output_files/atari800core.arg atari800core.arg_NTSC_VGA
+ln -s build_PAL_VGA/output_files/atari800core.arg atari800core.arg_PAL_VGA
+ln -s build_SIMPLE/output_files/atari800core.arg atari800core.arg_SIMPLE

Property changes on: mcc216_5200/cparg
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcc216_5200/makeqsf
===================================================================
--- mcc216_5200/makeqsf	(nonexistent)
+++ mcc216_5200/makeqsf	(revision 288)
@@ -0,0 +1,40 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+print QSF_OUT "\n";
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: mcc216_5200/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcc216_5200/ntsc_pll.cmp
===================================================================
--- mcc216_5200/ntsc_pll.cmp	(nonexistent)
+++ mcc216_5200/ntsc_pll.cmp	(revision 288)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component ntsc_pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcc216_5200/ntsc_pll.ppf
===================================================================
--- mcc216_5200/ntsc_pll.ppf	(nonexistent)
+++ mcc216_5200/ntsc_pll.ppf	(revision 288)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="ntsc_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcc216_5200/ntsc_pll.qip
===================================================================
--- mcc216_5200/ntsc_pll.qip	(nonexistent)
+++ mcc216_5200/ntsc_pll.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ntsc_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.ppf"]
Index: mcc216_5200/ntsc_pll.vhd
===================================================================
--- mcc216_5200/ntsc_pll.vhd	(nonexistent)
+++ mcc216_5200/ntsc_pll.vhd	(revision 288)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: ntsc_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ntsc_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END ntsc_pll;
+
+
+ARCHITECTURE SYN OF ntsc_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 63,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=ntsc_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636364"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcc216_5200/output_file.cof
===================================================================
--- mcc216_5200/output_file.cof	(nonexistent)
+++ mcc216_5200/output_file.cof	(revision 288)
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>CFI_128Mb</eprom_name>
+	<output_filename>output_files/atari800core.rbf</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>0</mode>
+	<sof_data>
+		<user_name>Page_0</user_name>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>output_files/atari800core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
+		</bit0>
+	</sof_data>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<options>
+	</options>
+</cof>
Index: mcc216_5200/phases.txt
===================================================================
--- mcc216_5200/phases.txt	(nonexistent)
+++ mcc216_5200/phases.txt	(revision 288)
@@ -0,0 +1,2 @@
+CPU->CTL : 0
+GPU->CPU->CTL : 1
Index: mcc216_5200/pll_downstream_ntsc.cmp
===================================================================
--- mcc216_5200/pll_downstream_ntsc.cmp	(nonexistent)
+++ mcc216_5200/pll_downstream_ntsc.cmp	(revision 288)
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_downstream_ntsc
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcc216_5200/pll_downstream_ntsc.ppf
===================================================================
--- mcc216_5200/pll_downstream_ntsc.ppf	(nonexistent)
+++ mcc216_5200/pll_downstream_ntsc.ppf	(revision 288)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_downstream_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcc216_5200/pll_downstream_ntsc.qip
===================================================================
--- mcc216_5200/pll_downstream_ntsc.qip	(nonexistent)
+++ mcc216_5200/pll_downstream_ntsc.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.ppf"]
Index: mcc216_5200/pll_downstream_ntsc.vhd
===================================================================
--- mcc216_5200/pll_downstream_ntsc.vhd	(nonexistent)
+++ mcc216_5200/pll_downstream_ntsc.vhd	(revision 288)
@@ -0,0 +1,493 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_downstream_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_downstream_ntsc IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_downstream_ntsc;
+
+
+ARCHITECTURE SYN OF pll_downstream_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "HIGH",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 1,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 3,
+		clk2_phase_shift => "7500",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 34921,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_downstream_ntsc",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "28.636000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "114.543999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "57.271999"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.636"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "7.50000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_downstream.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "7500"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "34921"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcc216_5200/rbf2arg.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcc216_5200/rbf2arg.zip
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216_5200/sdram_ctrl_3_ports.cmd
===================================================================
--- mcc216_5200/sdram_ctrl_3_ports.cmd	(nonexistent)
+++ mcc216_5200/sdram_ctrl_3_ports.cmd	(revision 288)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcc216_5200/sdram_ctrl_3_ports.wcfg
===================================================================
--- mcc216_5200/sdram_ctrl_3_ports.wcfg	(nonexistent)
+++ mcc216_5200/sdram_ctrl_3_ports.wcfg	(revision 288)
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="sdram_ctrl_3_ports.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="numeric_std" />
+            <top_module name="sdram_ctrl_3_ports_tb" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="24" />
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cs_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cs_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cs_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dqm_n" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_oe" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_oe</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_oe</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_rd_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_rd_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_rd_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_wr_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_wr_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_wr_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ref_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ref_reg</obj_property>
+      <obj_property name="ObjectShortName">ref_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_refr_req" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_refr_req</obj_property>
+      <obj_property name="ObjectShortName">r_refr_req</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+</wave_config>
Index: mcc216_5200/sdram_statemachine_mcc.vhdl
===================================================================
--- mcc216_5200/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ mcc216_5200/sdram_statemachine_mcc.vhdl	(revision 288)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: mcc216_5200/spi_dma.wcfg
===================================================================
--- mcc216_5200/spi_dma.wcfg	(nonexistent)
+++ mcc216_5200/spi_dma.wcfg	(revision 288)
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="33" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.b_inst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">.b_inst</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.b_inst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_addr[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write_bits" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/paused_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">paused_reg</obj_property>
+      <obj_property name="ObjectShortName">paused_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addr_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addrend_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_reg</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_write</obj_property>
+      <obj_property name="ObjectShortName">sd_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_clk</obj_property>
+      <obj_property name="ObjectShortName">sdcard_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_cmd</obj_property>
+      <obj_property name="ObjectShortName">sdcard_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat3</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/ram_7_0/data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+</wave_config>
Index: mcc216_5200/svideo/sin_rom.qip
===================================================================
--- mcc216_5200/svideo/sin_rom.qip	(nonexistent)
+++ mcc216_5200/svideo/sin_rom.qip	(revision 288)
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "9.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sin_rom.vhd"]
Index: mcc216_5200/svideo.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcc216_5200/svideo.zip
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216_5200/test.pl
===================================================================
--- mcc216_5200/test.pl	(nonexistent)
+++ mcc216_5200/test.pl	(revision 288)
@@ -0,0 +1,4 @@
+       my $version = `svn info  | grep Revision: | cut -c11`;
+	chomp $version;
+        $version.=".0";
+	print $version;
Index: mcc216_5200/usbpll.vhd
===================================================================
--- mcc216_5200/usbpll.vhd	(nonexistent)
+++ mcc216_5200/usbpll.vhd	(revision 288)
@@ -0,0 +1,365 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: usbpll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY usbpll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END usbpll;
+
+
+ARCHITECTURE SYN OF usbpll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 48,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=usbpll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "usbpll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "48"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv_5200/atari5200core.jdi
===================================================================
--- mcctv_5200/atari5200core.jdi	(nonexistent)
+++ mcctv_5200/atari5200core.jdi	(revision 288)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: mcctv_5200/atari5200core.sdc
===================================================================
--- mcctv_5200/atari5200core.sdc	(nonexistent)
+++ mcctv_5200/atari5200core.sdc	(revision 288)
@@ -0,0 +1,3 @@
+create_clock -period 5MHz [get_ports FPGA_CLK]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: mcc216_5200/usbpll.qip
===================================================================
--- mcc216_5200/usbpll.qip	(nonexistent)
+++ mcc216_5200/usbpll.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "usbpll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.ppf"]
Index: mcctv_5200/TODO
===================================================================
--- mcctv_5200/TODO	(nonexistent)
+++ mcctv_5200/TODO	(revision 288)
@@ -0,0 +1,3 @@
+Merge with mcc216 core - with generic to select composite, sdram size, keyboard/usb etc.
+USB keyboard support?
+On screen keyboard support?
Index: mcctv_5200/atari5200core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcctv_5200/atari5200core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216_5200/usbpll.ppf
===================================================================
--- mcc216_5200/usbpll.ppf	(nonexistent)
+++ mcc216_5200/usbpll.ppf	(revision 288)
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="usbpll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcc216_5200/zpu.wcfg
===================================================================
--- mcc216_5200/zpu.wcfg	(nonexistent)
+++ mcc216_5200/zpu.wcfg	(revision 288)
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="47" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">zpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_32bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_32bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_32bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_16bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_16bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_16bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_read_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_read_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_read_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_ready</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_fetch" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">cpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_fetch</obj_property>
+      <obj_property name="ObjectShortName">antic_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request</obj_property>
+      <obj_property name="ObjectShortName">ram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">ram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out1" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out3" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out4" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/reset_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_atari</obj_property>
+      <obj_property name="ObjectShortName">reset_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/pause_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_atari</obj_property>
+      <obj_property name="ObjectShortName">pause_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_ram_sel" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_ram_sel</obj_property>
+      <obj_property name="ObjectShortName">ap1_ram_sel</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_address" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="ObjectShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rden</obj_property>
+      <obj_property name="ObjectShortName">ap1_rden</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wren</obj_property>
+      <obj_property name="ObjectShortName">ap1_wren</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bena" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rddata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wrdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bst_siz" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wr_bst_act" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wr_bst_act</obj_property>
+      <obj_property name="ObjectShortName">ap1_wr_bst_act</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_zpu" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_zpu</obj_property>
+      <obj_property name="ObjectShortName">pause_zpu</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_next[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_next[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat0</obj_property>
+      <obj_property name="ObjectShortName">sd_dat0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat3</obj_property>
+      <obj_property name="ObjectShortName">sd_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv_5200/atari5200core.qpf
===================================================================
--- mcctv_5200/atari5200core.qpf	(nonexistent)
+++ mcctv_5200/atari5200core.qpf	(revision 288)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari5200core"
Index: mcctv_5200/atari5200core_mcc.cmd
===================================================================
--- mcctv_5200/atari5200core_mcc.cmd	(nonexistent)
+++ mcctv_5200/atari5200core_mcc.cmd	(revision 288)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcctv_5200/build.sh
===================================================================
--- mcctv_5200/build.sh	(nonexistent)
+++ mcctv_5200/build.sh	(revision 288)
@@ -0,0 +1,96 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+#variants...
+my $NTSC = 0;
+
+my $SVIDEO = 1;
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+	"NTSC_COMPOSITE" =>
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $SVIDEO,
+		"internal_ram" => 0,
+		"internal_rom" => 0,
+		"ext_clock" => 0
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari5200core_mcc.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp sdram_ctrl_3_ports.v $dir`;
+	`cp zpu_rom.vhdl $dir`;
+	`cp atari5200core.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`mkdir $dir/svideo`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	mkdir "./$dir/common/components/usbhostslave";
+	`cp ../common/components/usbhostslave/trunk/RTL/*/*.v ./$dir/common/components/usbhostslave`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+	`cp ./svideo/* ./$dir/svideo`;
+
+	chdir $dir;
+	`../makeqsf ../atari5200core.qsf ./svideo ./common/a8core ./common/components ./common/zpu ./common/components/usbhostslave`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari5200core.qsf`;
+	}
+
+	`quartus_sh --flow compile atari5200core > build.log 2> build.err`;
+
+	`quartus_cpf --convert ../output_file.cof`;
+	my $vga = 1;
+	if ($variant =~ /SVIDEO/)
+	{
+		$vga = 0;
+	}
+	
+	#TODO - generate automated version number
+	my $version = `svn info  | grep Revision: | cut -d' ' -f 2`;
+	chomp $version;
+	$version = `date +%y%m`;
+	my $version2 = `date +%d`;
+	chomp $version;
+	chomp $version2;
+	my $cmd = "wine ../rbf2arg/rbf2arg.exe 2 A $version.$version2 \"Atari 5200 $variant\" output_files/atari5200core.rbf output_files/atari5200core_$variant.arg";
+	print "Running $cmd\n";
+	`$cmd`;
+	
+	chdir "..";
+}
+
+
+#--for the MCC216 S-Video
+#--rbf2arg 0 A <version.revison> "description" <filename.rbf> <filename.arg>
+#--for the MCC216 VGA
+#--rbf2arg 1 A <version.revison> "description" <filename.rbf> <filename.arg>
+
+

Property changes on: mcctv_5200/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv_5200/atari5200core_mcc.wcfg
===================================================================
--- mcctv_5200/atari5200core_mcc.wcfg	(nonexistent)
+++ mcctv_5200/atari5200core_mcc.wcfg	(revision 288)
@@ -0,0 +1,234 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari5200core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari5200core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="50" />
+   <wvobject fp_name="/atari5200core_mcc_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_cs_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cs_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cs_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_dqm_n" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_clk</obj_property>
+      <obj_property name="ObjectShortName">sdram_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_a[12:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_a[12:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/sdram_dq" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">di[7:0]</obj_property>
+      <obj_property name="ObjectShortName">di[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">do[7:0]</obj_property>
+      <obj_property name="ObjectShortName">do[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">a[15:0]</obj_property>
+      <obj_property name="ObjectShortName">a[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/throttle" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle</obj_property>
+      <obj_property name="ObjectShortName">throttle</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/cpu6502/memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready</obj_property>
+      <obj_property name="ObjectShortName">memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request_complete_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/sdram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_addr[22:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_addr[22:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">cpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/atarixl_simple_sdram1/atari5200xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_fetch</obj_property>
+      <obj_property name="ObjectShortName">antic_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rden</obj_property>
+      <obj_property name="ObjectShortName">ap1_rden</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wren</obj_property>
+      <obj_property name="ObjectShortName">ap1_wren</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/ram_rd_active" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_rd_active</obj_property>
+      <obj_property name="ObjectShortName">ram_rd_active</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/ram_wr_active" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_wr_active</obj_property>
+      <obj_property name="ObjectShortName">ram_wr_active</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat0</obj_property>
+      <obj_property name="ObjectShortName">sd_dat0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sd_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sd_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/sd_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat3</obj_property>
+      <obj_property name="ObjectShortName">sd_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/clock" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clock</obj_property>
+      <obj_property name="ObjectShortName">clock</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable</obj_property>
+      <obj_property name="ObjectShortName">enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/cpol" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpol</obj_property>
+      <obj_property name="ObjectShortName">cpol</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/cpha" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpha</obj_property>
+      <obj_property name="ObjectShortName">cpha</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/cont" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cont</obj_property>
+      <obj_property name="ObjectShortName">cont</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/clk_div" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_div</obj_property>
+      <obj_property name="ObjectShortName">clk_div</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/addr" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">addr</obj_property>
+      <obj_property name="ObjectShortName">addr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/tx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">tx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">tx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">miso</obj_property>
+      <obj_property name="ObjectShortName">miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/mosi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mosi</obj_property>
+      <obj_property name="ObjectShortName">mosi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">busy</obj_property>
+      <obj_property name="ObjectShortName">busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari5200core_mcc_tb/atari/zpu/config_regs/spi_master1/rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv_5200/cparg
===================================================================
--- mcctv_5200/cparg	(nonexistent)
+++ mcctv_5200/cparg	(revision 288)
@@ -0,0 +1,5 @@
+ln -s build_NTSC_SVIDEO/output_files/atari800core.arg atari800core.arg_NTSC_SVIDEO
+ln -s build_PAL_SVIDEO/output_files/atari800core.arg atari800core.arg_PAL_SVIDEO
+ln -s build_NTSC_VGA/output_files/atari800core.arg atari800core.arg_NTSC_VGA
+ln -s build_PAL_VGA/output_files/atari800core.arg atari800core.arg_PAL_VGA
+ln -s build_SIMPLE/output_files/atari800core.arg atari800core.arg_SIMPLE

Property changes on: mcctv_5200/cparg
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv_5200/ntsc_pll.qip
===================================================================
--- mcctv_5200/ntsc_pll.qip	(nonexistent)
+++ mcctv_5200/ntsc_pll.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ntsc_pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ntsc_pll.ppf"]
Index: mcctv_5200/pll_downstream_ntsc.ppf
===================================================================
--- mcctv_5200/pll_downstream_ntsc.ppf	(nonexistent)
+++ mcctv_5200/pll_downstream_ntsc.ppf	(revision 288)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_downstream_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv_5200/sdram_clock_sync.wcfg
===================================================================
--- mcctv_5200/sdram_clock_sync.wcfg	(nonexistent)
+++ mcctv_5200/sdram_clock_sync.wcfg	(revision 288)
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="26" />
+   <wvobject fp_name="/atari800core_mcc_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_two" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_two</obj_property>
+      <obj_property name="ObjectShortName">clk_two</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_three" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_three</obj_property>
+      <obj_property name="ObjectShortName">clk_three</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/clk_four" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_four</obj_property>
+      <obj_property name="ObjectShortName">clk_four</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/enable_179" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_179</obj_property>
+      <obj_property name="ObjectShortName">enable_179</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_request_complete_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/throttle_count_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="ObjectShortName">throttle_count_reg[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/enables/memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready</obj_property>
+      <obj_property name="ObjectShortName">memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/r_psel_dly" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel_dly[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel_dly[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_next" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_next</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_next</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_refresh" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_refresh</obj_property>
+      <obj_property name="ObjectShortName">sdram_refresh</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv_5200/ntsc_pll.cmp
===================================================================
--- mcctv_5200/ntsc_pll.cmp	(nonexistent)
+++ mcctv_5200/ntsc_pll.cmp	(revision 288)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component ntsc_pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv_5200/output_file.cof
===================================================================
--- mcctv_5200/output_file.cof	(nonexistent)
+++ mcctv_5200/output_file.cof	(revision 288)
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>CFI_128Mb</eprom_name>
+	<output_filename>output_files/atari800core.rbf</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>0</mode>
+	<sof_data>
+		<user_name>Page_0</user_name>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>output_files/atari800core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
+		</bit0>
+	</sof_data>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<options>
+	</options>
+</cof>
Index: mcctv_5200/pll_downstream_ntsc.vhd
===================================================================
--- mcctv_5200/pll_downstream_ntsc.vhd	(nonexistent)
+++ mcctv_5200/pll_downstream_ntsc.vhd	(revision 288)
@@ -0,0 +1,493 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_downstream_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_downstream_ntsc IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_downstream_ntsc;
+
+
+ARCHITECTURE SYN OF pll_downstream_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "HIGH",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 1,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 3,
+		clk2_phase_shift => "7500",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 34921,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_downstream_ntsc",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "28.636000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.907997"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "114.543999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "57.271999"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.636"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "7.50000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_downstream.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "7500"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "34921"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_downstream_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv_5200/sdram_ctrl_3_ports.v
===================================================================
--- mcctv_5200/sdram_ctrl_3_ports.v	(nonexistent)
+++ mcctv_5200/sdram_ctrl_3_ports.v	(revision 288)
@@ -0,0 +1,629 @@
+//`include "arg_defs.vh"
+
+module sdram_ctrl /* verilator tracing_off */
+(
+  //--------------------
+  // Clocks and reset --
+  //--------------------
+  // Global reset
+  input             rst,
+  // Controller clock
+  input             clk,
+  // Sequencer cycles
+  input      [11:0] seq_cyc,
+  // Sequencer phase
+  input             seq_ph,
+  // Refresh cycle
+  input             refr_cyc,
+  //------------------------
+  // Access port #1 (CPU) --
+  //------------------------
+  // RAM select
+  input             ap1_ram_sel,
+  // Address bus
+  input      [23:1] ap1_address,
+  // Read enable
+  input             ap1_rden,
+  // Write enable
+  input             ap1_wren,
+  // Byte enable
+  input       [1:0] ap1_bena,
+  // Data bus (read)
+  output     [15:0] ap1_rddata,
+  // Data bus (write)
+  input      [15:0] ap1_wrdata,
+  // Burst size
+  input       [2:0] ap1_bst_siz,
+  // Read burst active
+  output reg        ap1_rd_bst_act,
+  // Write burst active
+  output            ap1_wr_bst_act,
+  //------------------------
+  // Access port #2 (GPU) --
+  //------------------------
+  // RAM select
+  input             ap2_ram_sel,
+  // Address bus
+  input      [23:1] ap2_address,
+  // Read enable
+  input             ap2_rden,
+  // Write enable
+  input             ap2_wren,
+  // Byte enable
+  input       [1:0] ap2_bena,
+  // Data bus (read)
+  output     [15:0] ap2_rddata,
+  // Data bus (write)
+  input      [15:0] ap2_wrdata,
+  // Burst size
+  input       [2:0] ap2_bst_siz,
+  // Read burst active
+  output reg        ap2_rd_bst_act,
+  // Write burst active
+  output            ap2_wr_bst_act,
+  //------------------------
+  // Access port #3 (CTL) --
+  //------------------------
+  // RAM select
+  input             ap3_ram_sel,
+  // Address bus
+  input      [23:1] ap3_address,
+  // Read enable
+  input             ap3_rden,
+  // Write enable
+  input             ap3_wren,
+  // Byte enable
+  input       [1:0] ap3_bena,
+  // Data bus (read)
+  output     [15:0] ap3_rddata,
+  // Data bus (write)
+  input      [15:0] ap3_wrdata,
+  // Burst size
+  input       [2:0] ap3_bst_siz,
+  // Read burst active
+  output reg        ap3_rd_bst_act,
+  // Write burst active
+  output            ap3_wr_bst_act,
+  //------------------------
+  // SDRAM memory signals --
+  //------------------------
+  // SDRAM controller ready
+  output reg        sdram_rdy,
+  // SDRAM chip select
+  output reg        sdram_cs_n,
+  // SDRAM row address strobe
+  output reg        sdram_ras_n,
+  // SDRAM column address strobe
+  output reg        sdram_cas_n,
+  // SDRAM write enable
+  output reg        sdram_we_n,
+  // SDRAM DQ masks
+  output reg  [1:0] sdram_dqm_n,
+  // SDRAM bank address
+  output reg  [1:0] sdram_ba,
+  // SDRAM address
+  output reg [11:0] sdram_addr,
+  // SDRAM data
+  output reg        sdram_dq_oe,
+  output reg [15:0] sdram_dq_o,
+  input      [15:0] sdram_dq_i
+);
+
+// SDRAM memory size
+parameter SDRAM_SIZE     = 8;
+// SDRAM operational frequency
+parameter SDRAM_FREQ     = 85909090;
+// Hidden refresh mode
+parameter HIDDEN_REFRESH = 0;
+// MODE REGISTER SET value (RS = 00, WB = 0, OP = 00, CL = 010, BT = 0, BL = 011)
+parameter MRS_VALUE = 12'b000000100011;
+// Refresh period
+parameter REF_COUNT = ((SDRAM_FREQ / ((12 * 64000)))) - 1;
+// Clock-to-output delay
+parameter Tco_dly = 4.5;
+
+// Port select signals
+reg   [2:0] r_psel;       // Port select (one hot)
+reg   [2:0] r_psel_dly;   // Port select delayed
+
+// Refresh signals
+reg         r_refr_req;   // Refresh requested
+reg         r_refr_act;   // Refresh active
+reg         r_refr_ack;   // Refresh acknowledged
+reg  [31:0] r_refr_ctr;   // Refresh counter
+
+// Port multiplexer signals
+wire        w_rden;       // Read enable
+reg         r_rd_reg;     // Registered read enable
+reg         r_rd_act;     // Read active
+wire        w_wren;       // Write enable
+reg         r_wr_reg;     // Registered write enable
+reg         r_wr_act;     // Write active
+wire        w_ram_sel;    // RAM select
+reg   [2:0] r_rd_bctr;    // Read burst counter
+reg   [2:0] r_wr_bctr;    // Write burst counter
+wire  [2:0] w_bst_siz;    // Burst size (load value of burst counters)
+reg   [2:0] r_bst_stp;    // Burst stop
+wire  [1:0] w_dqm;        // Bytes masks
+wire [23:1] w_addr;       // Address
+reg  [15:0] r_rddata;     // Data read
+wire [15:0] w_wrdata;     // Data written
+
+// SDRAM speed adjustment
+wire        w_rd_start;   // Read start condition
+wire        w_wr_start;   // Write start condition
+wire  [3:0] w_rd_cycle;   // First read cycle number
+
+// Initialization signals
+reg   [2:0] r_init_fsm;   // SDRAM initialization state machine
+reg  [10:0] r_init_tmr;   // SDRAM initialization timer
+
+// Output registers
+reg         r_sdram_cs_n;  // SDRAM chip select
+reg         r_sdram_ras_n; // SDRAM row address strobe
+reg         r_sdram_cas_n; // SDRAM column address strobe
+reg         r_sdram_we_n;  // SDRAM write enable
+reg   [1:0] r_sdram_dqm_n; // SDRAM DQ masks
+reg   [1:0] r_sdram_ba;    // SDRAM bank address
+reg  [11:0] r_sdram_addr;  // SDRAM address
+reg  [15:0] r_sdram_dq_o;  // SDRAM DQ output
+reg         r_sdram_dq_oe; // SDRAM DQ output enable
+
+  // Signal multiplexing based on the port select
+  assign w_wren         = (ap1_wren & r_psel[0])
+                        | (ap2_wren & r_psel[1])
+                        | (ap3_wren & r_psel[2]);
+  assign w_rden         = (ap1_rden & r_psel[0])
+                        | (ap2_rden & r_psel[1])
+                        | (ap3_rden & r_psel[2]);
+  assign w_ram_sel      = (HIDDEN_REFRESH == 1)
+                        ? (r_psel[0] | r_psel[1] | r_psel[2])
+                        : (r_psel[0] | r_psel[1] | r_psel[2]) & ~r_refr_req;
+  assign w_dqm[0]       = (ap1_bena[0] & r_psel[0])
+                        | (ap2_bena[0] & r_psel[1])
+                        | (ap3_bena[0] & r_psel[2]);
+  assign w_dqm[1]       = (ap1_bena[1] & r_psel[0])
+                        | (ap2_bena[1] & r_psel[1])
+                        | (ap3_bena[1] & r_psel[2]);
+  assign w_bst_siz[2]   = (ap1_bst_siz[2] & r_psel[0])
+                        | (ap2_bst_siz[2] & r_psel[1])
+                        | (ap3_bst_siz[2] & r_psel[2]);
+  assign w_bst_siz[1]   = (ap1_bst_siz[1] & r_psel[0])
+                        | (ap2_bst_siz[1] & r_psel[1])
+                        | (ap3_bst_siz[1] & r_psel[2]);
+  assign w_bst_siz[0]   = (ap1_bst_siz[0] & r_psel[0])
+                        | (ap2_bst_siz[0] & r_psel[1])
+                        | (ap3_bst_siz[0] & r_psel[2]);
+  assign w_addr[23:1]   = (ap1_address[23:1] & {23{r_psel[0]}})
+                        | (ap2_address[23:1] & {23{r_psel[1]}})
+                        | (ap3_address[23:1] & {23{r_psel[2]}});
+  assign w_wrdata[15:0] = (ap1_wrdata[15:0] & {16{r_psel[0]}})
+                        | (ap2_wrdata[15:0] & {16{r_psel[1]}})
+                        | (ap3_wrdata[15:0] & {16{r_psel[2]}});
+
+  // SDRAM speed adjustment
+  assign w_rd_cycle = (SDRAM_FREQ < 50000000) ? 4'd2 : 4'd3;
+  assign w_rd_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[2] & r_rd_reg) : (seq_cyc[4] & r_rd_reg);
+  assign w_wr_start = (SDRAM_FREQ < 50000000) ? (seq_cyc[0] & w_wren & w_ram_sel) : (seq_cyc[1] & r_wr_reg);
+  
+  // Write burst active flags, one cycle before "r_wr_act"
+  assign ap1_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[0];
+  assign ap2_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[1];
+  assign ap3_wr_bst_act = (r_wr_bctr[0] | r_wr_bctr[1] | r_wr_bctr[2] | w_wr_start) & r_psel[2];
+  
+  // SDRAM data read
+  assign ap1_rddata = r_rddata;
+  assign ap2_rddata = r_rddata;
+  assign ap3_rddata = r_rddata;
+  
+  // Hidden refresh / port select :
+  //-------------------------------
+  // rst         : Global reset
+  // clk         : SDRAM controller clock
+  // seq_cyc     : Sequencer cycle (0 to 11)
+  // seq_ph      : Sequencer phase (0 or 1)
+  // r_refr_req  : Internal refresh cycle request
+  // r_refr_ack  : Internal refresh cycle acknowledge
+  // r_refr_ctr  : Internal refresh counter
+  // r_psel      : Port select (one hot)
+  // r_psel_dly  : Delayed port select
+  // ap1_ram_sel : Port #1 access
+  // ap2_ram_sel : Port #2 access
+  // ap3_ram_sel : Port #3 access
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Refresh counter
+      r_refr_ctr <= REF_COUNT;
+      // Refresh cycle request
+      r_refr_req <= 1'b0;
+    end else begin
+      // Hidden refresh case
+      if (HIDDEN_REFRESH == 1) begin
+        // Sequencer cycle #11
+        if (seq_cyc[11]) begin
+          // Internal refresh counter
+          if (r_refr_ctr == 0) begin
+            r_refr_req <= 1'b1;
+            r_refr_ctr <= REF_COUNT;
+          end
+          else begin
+            r_refr_ctr <= r_refr_ctr - 1;
+          end
+        end
+        // When refresh cycle is acknowledged
+        if (r_refr_ack == 1'b1) begin
+          // Clear the refresh cycle request
+          r_refr_req <= 1'b0;
+        end
+      end else begin
+        // External refresh
+        r_refr_req <= refr_cyc;
+      end
+    end
+    
+    if (rst) begin
+      // Port select
+      r_psel     <= 3'b000;
+      r_psel_dly <= 3'b000;
+    end else begin
+      // Access port select
+      if (seq_cyc[11]) begin
+        if (!seq_ph) begin
+          // Phase #0 : select port #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel;
+          r_psel[1] <= 1'b0;
+          r_psel[2] <= ap3_ram_sel & ~ap1_ram_sel;
+        end
+        else begin
+          // Phase #1 : select port #2 (GPU) -> #1 (CPU) -> #3 (CTL) -> none
+          r_psel[0] <= ap1_ram_sel & ~ap2_ram_sel;
+          r_psel[1] <= ap2_ram_sel;
+          r_psel[2] <= ap3_ram_sel & ~(ap1_ram_sel | ap2_ram_sel);
+        end
+      end
+      // Delayed port select for data read multiplexer
+      if (seq_cyc[1]) begin
+        r_psel_dly <= r_psel;
+      end
+    end
+  end
+
+  // Burst activities :
+  //-------------------
+  // rst        : Global reset
+  // clk        : SDRAM controller clock
+  // w_rd_start : Read start conditions
+  // w_wr_start : Write start conditions
+  // r_rd_reg   : Read mode (registered)
+  // r_rd_act   : Read active
+  // r_wr_act   : Write active
+  // r_rd_bctr  : Burst read counter
+  // r_wr_bctr  : Burst write counter
+  // r_psel_dly : Port select delayed
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // Burst signals
+      r_rd_act       <= 1'b0;
+      r_wr_act       <= 1'b0;
+      r_rd_bctr      <= 3'b000;
+      r_wr_bctr      <= 3'b000;
+      ap1_rd_bst_act <= 1'b0;
+      ap2_rd_bst_act <= 1'b0;
+      ap3_rd_bst_act <= 1'b0;
+      // Data bus
+      r_rddata       <= 16'h0000;
+      r_sdram_dqm_n  <= 2'b11;
+      r_sdram_dq_oe  <= 1'b0;
+      r_sdram_dq_o   <= 16'h0000;
+    end else begin
+      // Prepare write burst cycles
+      if (w_wr_start) begin
+        // Set the active bits
+        r_wr_act  <= 1'b1;
+        // Start the burst counter
+        r_wr_bctr <= w_bst_siz;
+      end
+      // Prepare read burst cycles
+      if (w_rd_start) begin
+        // Set the active bits
+        r_rd_act  <= 1'b1;
+        // Start the burst counter
+        r_rd_bctr <= r_bst_stp;
+      end
+      // Read burst counter management
+      if (r_rd_act) begin
+        if (r_rd_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_rd_act <= 1'b0;
+        end
+        else begin
+          r_rd_bctr <= r_rd_bctr - 3'b1;
+        end
+      end
+      // Write burst counter management
+      if (r_wr_act) begin
+        if (r_wr_bctr == 0) begin
+          // Burst finished : clear the active bit
+          r_wr_act <= 1'b0;
+        end
+        else begin
+          r_wr_bctr <= r_wr_bctr - 3'b1;
+        end
+      end
+      // Read burst active flags, one cycle after "r_rd_act"
+      ap1_rd_bst_act <= r_rd_act & r_psel_dly[0];
+      ap2_rd_bst_act <= r_rd_act & r_psel_dly[1];
+      ap3_rd_bst_act <= r_rd_act & r_psel_dly[2];
+      // Read SDRAM data
+      r_rddata <= sdram_dq_i;
+      // Write SDRAM data / DQM management
+      if (r_wr_act) begin
+        r_sdram_dqm_n[0] <= ~w_dqm[0];
+        r_sdram_dqm_n[1] <= ~w_dqm[1];
+        r_sdram_dq_oe    <= 1'b1;
+        r_sdram_dq_o     <= w_wrdata;
+      end
+      else begin
+        r_sdram_dqm_n[0] <= ~r_rd_reg;
+        r_sdram_dqm_n[1] <= ~r_rd_reg;
+        r_sdram_dq_oe    <= 1'b0;
+        r_sdram_dq_o     <= 16'h0000;
+      end
+    end
+  end
+
+  // SDRAM controller state machine :
+  //---------------------------------
+  //  rst        : Global reset
+  //  clk        : SDRAM controller clock
+  //  seq_cyc    : Sequencer cycle
+  //  r_refr_req : Refresh cycle requested
+  //  r_refr_act : Refresh cycle active
+  //  r_refr_ack : Refresh cycle acknowledge
+  //  w_ram_sel  : SDRAM selected
+  //  w_rden     : Read enable flag
+  //  w_wren     : Write enable flag
+  //  r_rd_reg   : Read mode (registered)
+  //  r_wr_reg   : Write mode (registered)
+  //  w_bst_siz  : Burst size (1 to 8 words)
+  //  r_bst_stp  : Burst stop cycle
+  //  r_init_fsm : SDRAM initialization state
+  //  r_init_tmr : SDRAM initialization timer (>100 us)
+  always @(posedge rst or posedge clk) begin
+    if (rst) begin
+      // SDRAM outputs
+      r_sdram_cs_n  <= 1'b1;
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      r_sdram_ba    <= 2'b00;
+      r_sdram_addr  <= 12'b000000000000;
+      // Controller state
+      r_rd_reg      <= 1'b0;
+      r_wr_reg      <= 1'b0;
+      r_bst_stp     <= 3'b000;
+      sdram_rdy     <= 1'b0;
+      r_refr_ack    <= 1'b0;
+      r_refr_act    <= 1'b0;
+      // 1024 * 12 cycles > 100 us
+      r_init_tmr    <= 11'd0;    // 143 us
+      r_init_fsm    <= 3'b000;
+    end else begin
+      // Default : NOPs
+      r_sdram_ras_n <= 1'b1;
+      r_sdram_cas_n <= 1'b1;
+      r_sdram_we_n  <= 1'b1;
+      if (r_init_fsm[2]) begin
+        // Chip select management
+        if (seq_cyc[0]) begin
+          // RAM selected or refresh request
+          r_sdram_cs_n <= ~(w_ram_sel | r_refr_req);
+        end
+        // If there is an active refresh
+        if (r_refr_act) begin
+          //------------------
+          // Refresh cycles --
+          //------------------
+          // Cycle #0 : clear read/write enable signals
+          r_rd_reg <= 1'b0;
+          r_wr_reg <= 1'b0;
+          // Cycle #2 : prepare AUTO REFRESH cmd for cycle #3
+          if (seq_cyc[2]) begin
+            r_sdram_ras_n <= 1'b0;
+            r_sdram_cas_n <= 1'b0;
+          end
+          // Cycle #9 : acknowledge the refresh request
+          if (seq_cyc[9]) begin
+            // Hidden refresh case
+            if (HIDDEN_REFRESH == 1) begin
+              r_refr_ack <= 1'b1;
+            end
+            r_refr_act <= 1'b0;
+          end
+        end
+        else begin
+          //-----------------
+          // Normal cycles --
+          //-----------------
+          // Hidden refresh case
+          if (HIDDEN_REFRESH == 1) begin
+            // Clear any refresh acknowledge
+            r_refr_ack <= 1'b0;
+          end
+          if (seq_cyc[0]) begin
+            // If no access, activate refresh
+            r_refr_act <= ~((w_rden | w_wren) & w_ram_sel) & r_refr_req;
+            // Register read/write enable signals
+            r_rd_reg   <= w_rden & w_ram_sel;
+            r_wr_reg   <= w_wren & w_ram_sel;
+            // Register the burst stop
+            r_bst_stp  <= w_bst_siz;
+          end
+          // Cycle #0 : prepare ACTIVATE cmd for cycle #1
+          //            set the row address and the bank number
+          if ((seq_cyc[0]) && (w_ram_sel) && ((w_rden) || (w_wren))) begin
+            r_sdram_ras_n <= 1'b0;
+            if (SDRAM_SIZE == 16) begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[23:12];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[11:10];
+            end else begin
+              // 4096 rows : 12 address lines
+              r_sdram_addr  <= w_addr[22:11];
+              // 4 banks : 2 address lines
+              r_sdram_ba    <= w_addr[10:9];
+            end
+          end
+          // Cycle #1/2 : prepare READ/WRITE cmd for next cycle
+          //              set the column address and the bank number
+          if ((seq_cyc[w_rd_cycle - 1]) && ((r_rd_reg) || (r_wr_reg))) begin
+            r_sdram_cas_n <= 1'b0;
+            r_sdram_we_n  <= ~r_wr_reg;
+            if (SDRAM_SIZE == 16)
+              // 512 columns : 9 address lines
+              r_sdram_addr  <= {3'b010, w_addr[9:1]};
+            else
+              // 256 columns : 8 address lines
+              r_sdram_addr  <= {4'b0100, w_addr[8:1]};
+          end
+          // Cycles #2/3+ : prepare the PRECHARGE cmd (burst stop)
+          //if ((seq_cyc[w_rd_cycle + r_bst_stp]) && ((r_rd_reg) || (r_wr_reg))) begin
+          //  r_sdram_ras_n <= 1'b0;
+          //  r_sdram_we_n  <= 1'b0;
+          //end
+        end
+      end
+      else begin
+        //---------------
+        // Init cycles --
+        //---------------
+        if (r_init_tmr[10]) begin
+          // Select SDRAM
+          r_sdram_cs_n <= 1'b0;
+          case (r_init_fsm[1:0])
+            2'd0 : begin
+              // Prepare PRECHARGE ALL cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n    <= 1'b0;
+                r_sdram_we_n     <= 1'b0;
+                r_sdram_addr[10] <= 1'b1;
+              end
+            end
+            2'd1 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd2 : begin
+              // Prepare AUTO REFRESH cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+              end
+            end
+            2'd3 : begin
+              // Prepare MODE REGISTER SET value
+              if (seq_cyc[1]) begin
+                r_sdram_addr <= MRS_VALUE;
+              end
+              // Prepare MODE REGISTER SET cmd
+              if (seq_cyc[3]) begin
+                r_sdram_ras_n <= 1'b0;
+                r_sdram_cas_n <= 1'b0;
+                r_sdram_we_n  <= 1'b0;
+              end
+              // SDRAM is initialized
+              if (seq_cyc[10]) begin
+                sdram_rdy <= 1'b1;
+              end
+            end
+            default : begin
+            end
+          endcase
+          // Cycle #11 : next state
+          if (seq_cyc[11]) begin
+            r_init_fsm <= r_init_fsm + 3'd1;
+          end
+        end
+        else begin
+          // Deselect SDRAM
+          r_sdram_cs_n <= 1'b1;
+          // Cycle #11 : timer management
+          if (seq_cyc[11]) begin
+            r_init_tmr <= r_init_tmr + 11'd1;
+          end
+        end
+      end
+    end
+  end
+  
+  // TCO delay on all outputs
+  always@(r_sdram_cs_n or r_sdram_ras_n or r_sdram_cas_n or r_sdram_we_n or
+          r_sdram_dqm_n or r_sdram_ba or r_sdram_addr or r_sdram_dq_oe or r_sdram_dq_o) begin
+  `ifdef SIMULATION
+  
+    `ifdef verilator3
+      // Cycle based simulation
+      sdram_cs_n   = r_sdram_cs_n;
+      sdram_ras_n  = r_sdram_ras_n;
+      sdram_cas_n  = r_sdram_cas_n;
+      sdram_we_n   = r_sdram_we_n;
+      sdram_dqm_n  = r_sdram_dqm_n;
+      sdram_ba     = r_sdram_ba;
+      sdram_addr   = r_sdram_addr;
+      sdram_dq_oe  = r_sdram_dq_oe;
+      sdram_dq_o   = r_sdram_dq_o;
+    `else
+      // Timing based simulation
+      sdram_cs_n   = #Tco_dly r_sdram_cs_n;
+      sdram_ras_n  = #Tco_dly r_sdram_ras_n;
+      sdram_cas_n  = #Tco_dly r_sdram_cas_n;
+      sdram_we_n   = #Tco_dly r_sdram_we_n;
+      sdram_dqm_n  = #Tco_dly r_sdram_dqm_n;
+      sdram_ba     = #Tco_dly r_sdram_ba;
+      sdram_addr   = #Tco_dly r_sdram_addr;
+      sdram_dq_oe  = #Tco_dly r_sdram_dq_oe;
+      sdram_dq_o   = #Tco_dly r_sdram_dq_o;
+    `endif
+    
+  `else
+    // Synthesis
+    sdram_cs_n   = r_sdram_cs_n;
+    sdram_ras_n  = r_sdram_ras_n;
+    sdram_cas_n  = r_sdram_cas_n;
+    sdram_we_n   = r_sdram_we_n;
+    sdram_dqm_n  = r_sdram_dqm_n;
+    sdram_ba     = r_sdram_ba;
+    sdram_addr   = r_sdram_addr;
+    sdram_dq_oe  = r_sdram_dq_oe;
+    sdram_dq_o   = r_sdram_dq_o;
+  `endif
+  end
+
+`ifdef SIMULATION
+
+`ifndef verilator3
+  // Setup and hold times check for DQ
+  reg r_dq_noti;
+
+  specify
+    specparam
+      Tsu_dly =  0.7, // Input setup time
+      Th_dly  = -0.5; // Input hold time
+    $setuphold(posedge clk, sdram_dq_i, Tsu_dly, Th_dly, r_dq_noti);
+  endspecify
+
+  always @(r_dq_noti)
+  begin
+    $display($realtime, " ns : Setup/Hold time violation on DQ inputs");
+  end
+`endif
+  
+`endif
+
+endmodule
+
+/* verilator tracing_off */
Index: mcctv_5200/spi_dma.wcfg
===================================================================
--- mcctv_5200/spi_dma.wcfg	(nonexistent)
+++ mcctv_5200/spi_dma.wcfg	(revision 288)
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="33" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.b_inst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">.b_inst</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.b_inst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_addr[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_sd_dma_write_bits" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_sd_dma_write_bits[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_stack_write_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_stack_write_dma[3:0]</obj_property>
+      <obj_property name="Radix">BINARYRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_do_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_do_dma[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_rom_ram_dma" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom_ram_dma[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/paused_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">paused_reg</obj_property>
+      <obj_property name="ObjectShortName">paused_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addr_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addr_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_addrend_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_addrend_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_dma_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_dma_reg</obj_property>
+      <obj_property name="ObjectShortName">spi_dma_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_write</obj_property>
+      <obj_property name="ObjectShortName">sd_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sd_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sd_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_clk</obj_property>
+      <obj_property name="ObjectShortName">sdcard_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_cmd</obj_property>
+      <obj_property name="ObjectShortName">sdcard_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/sdcard_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdcard_dat3</obj_property>
+      <obj_property name="ObjectShortName">sdcard_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/spi_master1/rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/ram_7_0/data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+</wave_config>
Index: mcc216_5200/zpu_rom.vhdl
===================================================================
--- mcc216_5200/zpu_rom.vhdl	(nonexistent)
+++ mcc216_5200/zpu_rom.vhdl	(revision 288)
@@ -0,0 +1,8226 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(12 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 8191) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
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+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: mcctv_5200/atari5200core.qsf
===================================================================
--- mcctv_5200/atari5200core.qsf	(nonexistent)
+++ mcctv_5200/atari5200core.qsf	(revision 288)
@@ -0,0 +1,212 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors.  Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 20:12:08  December 25, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari5200core_mcc_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name DEVICE EP4CE15E22C7
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name TOP_LEVEL_ENTITY atari5200core_mcc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:12:08  DECEMBER 25, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS128
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+
+set_location_assignment PIN_46 -to AUDIO_L
+set_location_assignment PIN_49 -to AUDIO_R
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_42 -to SD_CLK
+set_location_assignment PIN_43 -to SD_CMD
+set_location_assignment PIN_44 -to SD_DAT3
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_59 -to SDRAM_A[0]
+set_location_assignment PIN_58 -to SDRAM_A[1]
+set_location_assignment PIN_51 -to SDRAM_A[2]
+set_location_assignment PIN_50 -to SDRAM_A[3]
+set_location_assignment PIN_132 -to SDRAM_A[4]
+set_location_assignment PIN_125 -to SDRAM_A[5]
+set_location_assignment PIN_121 -to SDRAM_A[6]
+set_location_assignment PIN_120 -to SDRAM_A[7]
+set_location_assignment PIN_119 -to SDRAM_A[8]
+set_location_assignment PIN_115 -to SDRAM_A[9]
+set_location_assignment PIN_60 -to SDRAM_A[10]
+set_location_assignment PIN_114 -to SDRAM_A[11]
+set_location_assignment PIN_113 -to SDRAM_A[12]
+set_location_assignment PIN_111 -to SDRAM_CLK
+set_location_assignment PIN_110 -to SDRAM_DQMH_n
+set_location_assignment PIN_71 -to SDRAM_DQML_n
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_72 -to SDRAM_DQ[7]
+set_location_assignment PIN_76 -to SDRAM_DQ[6]
+set_location_assignment PIN_77 -to SDRAM_DQ[5]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_68 -to SDRAM_CAS_n
+set_location_assignment PIN_66 -to SDRAM_CS_n
+set_location_assignment PIN_64 -to SDRAM_BA[1]
+set_location_assignment PIN_65 -to SDRAM_BA[0]
+set_location_assignment PIN_67 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_WE_n
+set_location_assignment PIN_112 -to SDRAM_CKE
+set_location_assignment PIN_144 -to VGA_G[0]
+set_location_assignment PIN_143 -to VGA_G[1]
+set_location_assignment PIN_142 -to VGA_G[2]
+set_location_assignment PIN_141 -to VGA_G[3]
+set_location_assignment PIN_137 -to VGA_B[0]
+set_location_assignment PIN_136 -to VGA_B[1]
+set_location_assignment PIN_135 -to VGA_B[2]
+set_location_assignment PIN_133 -to VGA_B[3]
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_13 -to CFG_DIN
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_31 -to dplus1
+set_location_assignment PIN_30 -to dminus1
+set_location_assignment PIN_33 -to dplus2
+set_location_assignment PIN_32 -to dminus2
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_SIGNALTAP_FILE atari.stp
+set_location_assignment PLL_2 -to "clk_reset:clk_rst_inst|pll_main:main_inst"
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQMH_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQML_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name IGNORE_LCELL_BUFFERS ON
+set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
+set_location_assignment PLL_4 -to "clk_reset:clk_rst_inst|pll_5M_pal_ntsc:pll_5m_inst" -disable
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name QIP_FILE usbpll.qip
+set_global_assignment -name QIP_FILE pal_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_pal.qip
+set_global_assignment -name QIP_FILE ntsc_pll.qip
+set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
+set_global_assignment -name SDC_FILE atari5200core.sdc
+set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+set_global_assignment -name VHDL_FILE atari5200core_mcc.vhd
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: mcctv_5200/atari5200core_mcc.vhd
===================================================================
--- mcctv_5200/atari5200core_mcc.vhd	(nonexistent)
+++ mcctv_5200/atari5200core_mcc.vhd	(revision 288)
@@ -0,0 +1,934 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+--USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+
+ENTITY atari5200core_mcc IS 
+	GENERIC
+	(
+		TV : integer;  -- 1 = PAL, 0=NTSC
+		internal_rom : integer;
+		internal_ram : integer;
+		ext_clock : integer
+	);
+	PORT
+	(
+		FPGA_CLK :  IN  STD_LOGIC; -- crystal appears to be still 5MHz despite comment in file I was sent...
+
+		-- For test bench
+		EXT_CLK_SDRAM : in std_logic_vector(ext_clock downto 1);
+		EXT_CLK : in std_logic_vector(ext_clock downto 1);
+		EXT_SDRAM_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_SVIDEO_DAC_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);
+
+		--PS2K_CLK :  IN  STD_LOGIC;
+		--PS2K_DAT :  IN  STD_LOGIC;
+		--PS2M_CLK :  IN  STD_LOGIC;
+		--PS2M_DAT :  IN  STD_LOGIC;		
+
+		-- VGA/cough cough... (composite...)
+		--VGA_VS :  OUT  STD_LOGIC;
+		--VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0); -- high bits composite
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0); -- low bits composite
+		--VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		
+		--JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		--JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+		----USB CONNECTIONS (with one 1.5K pull up to 3.3v)  ---------------
+		dplus1  			: inout std_logic;           --D+ data line , pin D16   
+		dminus1 			: inout std_logic;           --D- data line, pin E14
+		----USB CONNECTIONS (with one 1.5K pull up to 3.3v)  ---------------
+		dplus2  			: inout std_logic;           --D+ data line , pin D16   
+		dminus2 			: inout std_logic;           --D- data line, pin E14
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_CS_N :  OUT  STD_LOGIC;
+		SDRAM_RAS_N :  OUT  STD_LOGIC;
+		SDRAM_CAS_N :  OUT  STD_LOGIC;
+		SDRAM_WE_N :  OUT  STD_LOGIC;
+		SDRAM_DQMH_n :  OUT  STD_LOGIC;
+		SDRAM_DQML_n :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC;
+
+		-- SPI flash clock
+		CFG_CLK       : OUT   STD_LOGIC;
+		CFG_CS_n      : OUT   STD_LOGIC;
+		CFG_DOUT      : OUT   STD_LOGIC;
+		CFG_DIN       : IN    STD_LOGIC
+	);
+END atari5200core_mcc;
+
+ARCHITECTURE vhdl OF atari5200core_mcc IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+COMPONENT sdram_ctrl
+port
+(
+  --//--------------------
+  --// Clocks and reset --
+  --//--------------------
+  --// Global reset
+  rst : in std_logic;
+  --// Controller clock
+  clk : in std_logic;
+  --// Sequencer cycles
+  seq_cyc : in std_logic_vector(11 downto 0);
+  --// Sequencer phase
+  seq_ph : in std_logic;
+  --// Refresh cycle
+  refr_cyc : in std_logic;
+  --//------------------------
+  --// Access port #1 (CPU) --
+  --//------------------------
+  --// RAM select
+  ap1_ram_sel : in std_logic;
+  --// Address bus
+  ap1_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap1_rden : in std_logic;
+  --// Write enable
+  ap1_wren : in std_logic;
+  --// Byte enable
+  ap1_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap1_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap1_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap1_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap1_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap1_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #2 (GPU) --
+  --//------------------------
+  --// RAM select
+  ap2_ram_sel : in std_logic;
+  --// Address bus
+  ap2_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap2_rden : in std_logic;
+  --// Write enable
+  ap2_wren : in std_logic;
+  --// Byte enable
+  ap2_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap2_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap2_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap2_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap2_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap2_wr_bst_act : out std_logic;
+  --//------------------------
+  --// Access port #3 (CTL) --
+  --//------------------------
+  --// RAM select
+  ap3_ram_sel : in std_logic;
+  --// Address bus
+  ap3_address : in std_logic_vector(23 downto 1);
+  --// Read enable
+  ap3_rden : in std_logic;
+  --// Write enable
+  ap3_wren : in std_logic;
+  --// Byte enable
+  ap3_bena : in std_logic_vector(1 downto 0);
+  --// Data bus (read)
+  ap3_rddata : out std_logic_vector(15 downto 0);
+  --// Data bus (write)
+  ap3_wrdata : in std_logic_vector(15 downto 0);
+  --// Burst size
+  ap3_bst_siz : in std_logic_vector(2 downto 0);
+  --// Read burst active
+  ap3_rd_bst_act : out std_logic;
+  --// Write burst active
+  ap3_wr_bst_act : out std_logic;
+  --//------------------------
+  --// SDRAM memory signals --
+  --//------------------------
+  --// SDRAM controller ready
+  sdram_rdy : out std_logic;
+  --// SDRAM chip select
+  sdram_cs_n : out std_logic;
+  --// SDRAM row address strobe
+  sdram_ras_n : out std_logic;
+  --// SDRAM column address strobe
+  sdram_cas_n : out std_logic;
+  --// SDRAM write enable
+  sdram_we_n : out std_logic;
+  --// SDRAM DQ masks
+  sdram_dqm_n : out std_logic_vector(1 downto 0);
+  --// SDRAM bank address
+  sdram_ba : out std_logic_vector(1 downto 0);
+  --// SDRAM address
+  sdram_addr : out std_logic_vector(11 downto 0);
+  --// SDRAM data
+  sdram_dq_oe : out std_logic;
+  sdram_dq_o : out std_logic_vector(15 downto 0);
+  sdram_dq_i : in std_logic_vector(15 downto 0)
+);
+END COMPONENT;
+
+	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+	
+	signal VIDEO_VS : std_logic;
+	signal VIDEO_HS : std_logic;
+	signal VIDEO_R : std_logic_vector(7 downto 0);
+	signal VIDEO_G : std_logic_vector(7 downto 0);
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+	signal VIDEO_BLANK : std_logic;
+	signal VIDEO_BURST : std_logic;
+	signal VIDEO_START_OF_FIELD : std_logic;
+	signal VIDEO_ODD_LINE : std_logic;
+
+	signal JOY1 : std_logic_vector(5 downto 0);
+	signal JOY2 : std_logic_vector(5 downto 0);
+	signal JOY1_n : std_logic_vector(4 downto 0);
+	signal JOY2_n : std_logic_vector(4 downto 0);
+
+	signal PLL1_LOCKED : std_logic;
+	signal CLK_PLL1 : std_logic;
+	
+	signal RESET_n : std_logic;
+	signal PLL_LOCKED : std_logic;
+	signal CLK : std_logic;
+	signal CLK_SDRAM : std_logic;
+
+	-- SDRAM
+	signal PREREG_SDRAM_REQUEST : std_logic;
+	signal PREREG_SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
+	signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
+	SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+	signal SDRAM_REQUEST : std_logic;
+	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal SDRAM_WRITE_ENABLE : std_logic;
+	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	SIGNAL SDRAM_DI : std_logic_vector(31 downto 0);
+	SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+
+	signal SDRAM_REQUEST_COMPLETE : std_logic;
+	
+	signal SDRAM_REFRESH : std_logic;
+
+	signal SYSTEM_RESET_REQUEST: std_logic;
+
+	signal seq_reg : std_logic_vector(11 downto 0);
+	signal seq_next : std_logic_vector(11 downto 0);
+	
+	signal seq_ph_reg : std_logic;
+	signal seq_ph_next : std_logic;
+	
+	signal ref_reg : std_logic;
+	signal ref_next : std_logic;
+
+	signal sdram_request_complete_next : std_logic;
+	signal sdram_request_complete_reg : std_logic;
+
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+
+	signal ram_di_next : std_logic_vector(15 downto 0);
+	signal ram_di_reg : std_logic_vector(15 downto 0);
+
+	signal ram_do_next : std_logic_vector(31 downto 0);
+	signal ram_do_reg : std_logic_vector(31 downto 0);
+
+	signal ram_do : std_logic_vector(15 downto 0);
+
+	signal ram_bena_next : std_logic_vector(1 downto 0);
+	signal ram_bena_reg : std_logic_vector(1 downto 0);
+
+	signal ram_rd_active : std_logic;
+	signal ram_wr_active : std_logic;
+
+	signal sdram_dq_oe : std_logic;
+	signal sdram_dq_o : std_logic_vector(15 downto 0);
+	signal sdram_dq_i : std_logic_vector(15 downto 0);
+	signal sdram_dqm_n_temp : std_logic_vector(1 downto 0);
+	
+	signal sdram_rdy : std_logic;
+	signal sdram_reset_ctrl_n_next : std_logic;
+	signal sdram_reset_ctrl_n_reg : std_logic;
+	signal sdram_reset_n_next : std_logic;
+	signal sdram_reset_n_reg : std_logic;
+
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	signal controller_select : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- svideo
+	signal svideo_dac_clk : std_logic;
+
+	signal svideo_y : std_logic_vector(7 downto 0);
+	signal svideo_c : std_logic_vector(5 downto 0);
+
+	-- composite
+	SIGNAL svideo_yout : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL svideo_yout_dly3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	--SIGNAL svideo_cout : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL cvbs1_out : STD_LOGIC_VECTOR(9 DOWNTO 0);
+	SIGNAL cvbs2_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL luma : STD_LOGIC_VECTOR(9 DOWNTO 0);
+	SIGNAL chroma : STD_LOGIC_VECTOR(8 DOWNTO 0);
+	SIGNAL luma_saturated : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT5 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+	signal emulated_cartridge_select: std_logic_vector(5 downto 0);
+
+	-- usb
+	signal CLK_USB : std_logic;
+
+	signal USBWireVPin : std_logic_vector(1 downto 0);
+	signal USBWireVMin : std_logic_vector(1 downto 0);
+	signal USBWireVPout : std_logic_vector(1 downto 0);
+	signal USBWireVMout : std_logic_vector(1 downto 0);
+	signal USBWireOE_n : std_logic_vector(1 downto 0);
+
+	signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
+	signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
+
+	-- paddles
+	signal		JOY1X : std_logic_vector(7 downto 0);
+	signal		JOY1Y : std_logic_vector(7 downto 0);
+	signal		JOY2X : std_logic_vector(7 downto 0);
+	signal		JOY2Y : std_logic_vector(7 downto 0);
+
+BEGIN 
+
+-- disable flash (not used)
+CFG_CLK <= 'Z';
+CFG_CS_n <= '1';
+CFG_DOUT <= 'Z';
+
+-- usb
+--dplus1 <= USBWireVPout(0) when USBWireOE_n(0)='0' else 'Z';
+--dminus1 <= USBWireVMout(0) when USBWireOE_n(0)='0' else 'Z';
+--USBWireVPin(0) <= dplus1;
+--USBWireVMin(0) <= dminus1;
+--
+--dplus2 <= USBWireVPout(1) when USBWireOE_n(1)='0' else 'Z';
+--dminus2 <= USBWireVMout(1) when USBWireOE_n(1)='0' else 'Z';
+--USBWireVPin(1) <= dplus2;
+--USBWireVMin(1) <= dminus2;
+
+
+dplus2 <= USBWireVMout(0) when USBWireOE_n(0)='0' else 'Z';
+dminus2 <= USBWireVPout(0) when USBWireOE_n(0)='0' else 'Z';
+USBWireVMin(0) <= dplus2;
+USBWireVPin(0) <= dminus2;
+
+dplus1 <= USBWireVMout(1) when USBWireOE_n(1)='0' else 'Z';
+dminus1 <= USBWireVPout(1) when USBWireOE_n(1)='0' else 'Z';
+USBWireVMin(1) <= dplus1;
+USBWireVPin(1) <= dminus1;
+
+usb_pll : entity work.usbpll
+PORT MAP(inclk0 => FPGA_CLK,
+	 c0 => CLK_USB,
+	 locked => open);
+
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => audio_r
+);
+
+gen_fake_pll : if ext_clock=1 generate
+	CLK_SDRAM <= EXT_CLK_SDRAM(1);
+	CLK <= EXT_CLK(1);
+	SDRAM_CLK <= EXT_CLK_SDRAM(1);
+	SVIDEO_DAC_CLK <= EXT_SVIDEO_DAC_CLK(1);
+	--SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);
+	PLL_LOCKED <= EXT_PLL_LOCKED(1);
+end generate;
+
+gen_real_pll : if ext_clock=0 generate
+	gen_tv_ntsc : if tv=0 generate
+		mcc_pll : entity work.ntsc_pll
+		PORT MAP(inclk0 => FPGA_CLK,
+				 c0 => CLK_PLL1,
+				 locked => PLL1_LOCKED);
+		mcc_pll2 : entity work.pll_downstream_ntsc
+		PORT MAP(inclk0 => CLK_PLL1,
+				 c0 => CLK_SDRAM,
+				 c1 => CLK,
+				 c2 => SDRAM_CLK,
+				 c3 => SVIDEO_DAC_CLK,
+				 c4 => open, --SCANDOUBLE_CLK,      
+				 areset => not(PLL1_LOCKED),
+				 locked => PLL_LOCKED);
+	end generate;
+end generate;
+
+reset_n <= PLL_LOCKED;
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari5200
+	GENERIC MAP
+	(
+		ps2_enable => 0,
+		direct_enable => 1
+	)
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		
+		INPUT => zpu_out4,
+
+		FIRE2 => '0'&'0'&joy2(4)&joy1(4),
+		CONTROLLER_SELECT => CONTROLLER_SELECT, -- selected stick keyboard/shift button
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+
+		FKEYS => FKEYS,
+		
+		PS2_KEYS_NEXT_OUT => ps2_keys_next,
+		PS2_KEYS => ps2_keys
+	);
+
+JOY1 <= zpu_out2(5 downto 4)&zpu_out2(0)&zpu_out2(1)&zpu_out2(2)&zpu_out2(3);
+JOY2 <= zpu_out3(5 downto 4)&zpu_out3(0)&zpu_out3(1)&zpu_out3(2)&zpu_out3(3);
+
+JOY1X <= zpu_out5(7 downto 0);
+JOY1Y <= zpu_out5(15 downto 8);
+JOY2X <= zpu_out5(23 downto 16);
+JOY2Y <= zpu_out5(31 downto 24);
+
+atari5200_simple_sdram1 : entity work.atari5200core_simplesdram
+	GENERIC MAP
+	(
+		cycle_length => 16,
+		internal_rom => 0, --internal_rom,
+		internal_ram => 0, --internal_ram,
+		video_bits => 8,
+		palette => 1
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
+		RESET_N => RESET_N and SDRAM_RESET_N_REG,
+
+		VIDEO_VS => VIDEO_VS,
+		VIDEO_HS => VIDEO_HS,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => VIDEO_G,
+		VIDEO_R => VIDEO_R,
+		VIDEO_BLANK =>VIDEO_BLANK,
+		VIDEO_BURST =>VIDEO_BURST,
+		VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,
+		VIDEO_ODD_LINE =>VIDEO_ODD_LINE,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => PREREG_SDRAM_ADDR,
+		SDRAM_DO => ram_do_reg,
+		SDRAM_DI => PREREG_SDRAM_DI,
+		SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_REFRESH => SDRAM_REFRESH,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
+
+		THROTTLE_COUNT_6502 => speed_6502,
+		HALT => pause_atari,
+
+		-- JOYSTICK
+		JOY1_X => signed(joy1x),
+		JOY1_Y => signed(joy1y),
+		JOY1_BUTTON => not(joy1(5)),
+		JOY2_X => signed(joy2x),
+		JOY2_Y => signed(joy2y),
+		JOY2_BUTTON => not(joy2(5)),
+
+		-- Pokey keyboard matrix
+		-- Standard component available to connect this to PS2
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		CONTROLLER_SELECT => CONTROLLER_SELECT
+	);
+
+	process(clk_sdram,sdram_reset_ctrl_n_reg)
+	begin
+		if (sdram_reset_ctrl_n_reg='0') then
+			seq_reg <= "010000000000";
+			seq_ph_reg <= '1';
+			ref_reg <= '0';
+
+			ram_do_reg <= (others=>'0');
+			ram_di_reg <= (others=>'0');
+			ram_bena_reg <= (others=>'0');
+			sdram_request_complete_reg <= '0';
+			sdram_request_reg <= '0';
+		elsif (clk_sdram'event and clk_sdram = '1') then
+			seq_reg <= seq_next;
+			seq_ph_reg <= seq_ph_next;
+			ref_reg <= ref_next;
+
+			ram_do_reg <= ram_do_next;
+			ram_di_reg <= ram_di_next;
+			ram_bena_reg <= ram_bena_next;
+			sdram_request_complete_reg <= sdram_request_complete_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			sdram_reset_n_reg <= '0';
+			sdram_reset_ctrl_n_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			sdram_reset_n_reg <= sdram_reset_n_next;
+			sdram_reset_ctrl_n_reg <= reset_n;
+		end if;
+	end process;
+
+	-- Generate sdram sequence
+	process(seq_reg, seq_ph_reg, ref_reg)
+	begin
+		seq_next <= seq_reg(10 downto 0)&seq_reg(11);
+		seq_ph_next <= seq_ph_reg;
+		ref_next <= ref_reg;
+		if (seq_reg(11) = '1') then
+			seq_ph_next <= not(seq_ph_reg);
+			ref_next <= not(ref_reg);
+		end if;
+	end process;
+
+	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
+	begin
+		sdram_reset_n_next <= sdram_reset_n_reg;
+		if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
+			sdram_reset_n_next <= '1';
+		end if;
+		if (reset_atari = '1') then
+			sdram_reset_n_next <= '0';
+		end if;
+	end process;
+
+	-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			SDRAM_REQUEST <= '0';
+			SDRAM_READ_ENABLE <= '0';
+			SDRAM_WRITE_ENABLE <= '0';
+			SDRAM_ADDR <= (others=>'0');
+			SDRAM_DI <= (others=>'0');
+			SDRAM_WIDTH_32BIT_ACCESS <= '0';
+			SDRAM_WIDTH_16BIT_ACCESS <= '0';
+			SDRAM_WIDTH_8BIT_ACCESS <= '0';
+		elsif(clk'event and clk='0') then -- FALLING EDGE
+			SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
+			SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
+			SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
+			SDRAM_ADDR <= PREREG_SDRAM_ADDR;
+			SDRAM_DI <= PREREG_SDRAM_DI;
+			SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
+			SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
+			SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
+		end if;
+	end process;
+
+	-- Adapt SDRAM
+	process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
+	begin
+		sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
+		sdram_request_complete_next <= sdram_request_complete_reg;
+		ram_bena_next <= "00";
+		ram_di_next <= (others=>'0');
+		ram_do_next <= ram_do_reg;
+
+		case seq_reg is
+		when "000000000001" =>
+			-- nop
+		when "000000000010" => -- write data from next...
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= SDRAM_DI(7 downto 0)&SDRAM_DI(7 downto 0);
+					ram_bena_next <= SDRAM_ADDR(0)&not(SDRAM_ADDR(0));
+				else
+					ram_di_next <= SDRAM_DI(15 downto 0);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+		when "000000000100" =>
+			if (SDRAM_WRITE_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_di_next <= (others=>'0');
+				else
+					ram_di_next <= SDRAM_DI(31 downto 16);
+					ram_bena_next <= "11";
+				end if;
+			end if;
+			if ((ram_wr_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000000001000" =>
+			-- nop
+		when "000000010000" =>
+			-- nop
+		when "000000100000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when "000001000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					if (SDRAM_ADDR(0) = '0') then
+						ram_do_next(15 downto 0) <= ram_do(7 downto 0)&ram_do(7 downto 0);
+					else
+						ram_do_next(15 downto 0) <= ram_do(15 downto 8)&ram_do(15 downto 8);
+					end if;
+				else
+					ram_do_next(15 downto 0) <= ram_do;
+				end if;
+			end if;
+		when "000010000000" =>
+			if (SDRAM_READ_ENABLE = '1') then
+				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
+					ram_do_next(31 downto 16) <= (others=>'0');
+				else
+					ram_do_next(31 downto 16) <= ram_do;
+				end if;
+			end if;
+			if ((ram_rd_active)='1') then
+				sdram_request_complete_next <= '1';
+				sdram_request_next <= '0';
+			end if;
+		when "000100000000" =>
+			-- nop
+		when "001000000000" =>
+			-- nop
+		when "010000000000" =>
+			-- nop
+		when "100000000000" =>
+			sdram_request_complete_next <= '0';
+			-- nop
+		when others =>
+			-- never
+		end case;
+	end process;
+
+	SDRAM_REQUEST_COMPLETE <= SDRAM_REQUEST_COMPLETE_REG;
+sdram_controller : sdram_ctrl
+	PORT MAP
+	(
+		CLK => CLK_SDRAM,
+		rst => not(sdram_reset_ctrl_n_reg),
+		seq_cyc => seq_reg(11 downto 0),
+		seq_ph => seq_ph_reg,
+		--refr_cyc => ref_reg,
+		refr_cyc => SDRAM_REFRESH,
+
+		ap1_ram_sel => SDRAM_REQUEST_NEXT,
+		ap1_address => '0'&SDRAM_ADDR(22 downto 1),
+		ap1_rden => SDRAM_READ_ENABLE,
+		ap1_wren => SDRAM_WRITE_ENABLE,
+		ap1_bena => ram_bena_reg,
+		ap1_rddata => ram_do,
+		ap1_wrdata => ram_di_reg,
+		ap1_bst_siz => "001",
+		ap1_rd_bst_act => ram_rd_active,
+		ap1_wr_bst_act => ram_wr_active,
+
+		ap2_ram_sel => '0',
+		ap2_address => "00000000000000000000000",
+		ap2_rden => '0',
+		ap2_wren => '0',
+		ap2_bena => "11",
+		ap2_rddata => open,
+		ap2_wrdata => X"0000",
+		ap2_bst_siz => "111",
+		ap2_rd_bst_act => open,
+		ap2_wr_bst_act => open,
+
+		ap3_ram_sel => '0',
+		ap3_address => "00000000000000000000000",
+		ap3_rden => '0',
+		ap3_wren => '0',
+		ap3_bena => "11",
+		ap3_rddata => open,
+		ap3_wrdata => X"0000",
+		ap3_bst_siz => "111",
+		ap3_rd_bst_act => open,
+		ap3_wr_bst_act => open,
+
+		sdram_rdy => sdram_rdy,
+		sdram_cs_n => sdram_cs_n,
+		sdram_ras_n => sdram_ras_n,
+		sdram_cas_n => sdram_cas_n,
+		sdram_we_n => sdram_we_n,
+		sdram_dqm_n => sdram_dqm_n_temp,
+		sdram_ba => sdram_ba,
+		sdram_addr => sdram_a(11 downto 0),
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+	);
+
+sdram_dqmh_n <= sdram_dqm_n_temp(1);
+sdram_dqml_n <= sdram_dqm_n_temp(0);
+
+sdram_dq <= sdram_dq_o when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i <= sdram_dq;
+sdram_a(12) <= '1';
+sdram_cke <= '1';
+
+-- Video options
+	-- SVIDEO COMPONENT
+	svideo : entity work.svideo
+	PORT MAP
+	(
+		areset_n => RESET_N,
+		ecs_clk => CLK,
+		dac_clk => SVIDEO_DAC_CLK,
+		r_in => VIDEO_R,
+		g_in => VIDEO_G,
+		b_in => VIDEO_B,
+		sof => VIDEO_VS, -- base on vsync?
+		vpos_lsb => VIDEO_ODD_LINE,
+		blank => VIDEO_BLANK,
+		burst => VIDEO_BURST,
+		csync_n => not(VIDEO_HS xor VIDEO_VS),
+		
+		y_out => svideo_yout,
+		c_out => open,
+
+ 		luma_out => luma,
+		chroma_out => chroma,
+		
+		pal_ntsc => not('0')
+	);
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
+		memory => 8192,
+		usb => 2
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_rdy,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_dat0,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_dat3,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"000"&
+			"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+			FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1, --misc
+		ZPU_OUT2 => zpu_out2, --joy0
+		ZPU_OUT3 => zpu_out3, --joy1
+		ZPU_OUT4 => zpu_out4, --keyboard
+		ZPU_OUT5 => zpu_out5, --analog stick
+
+		-- USB host
+		CLK_USB => CLK_USB,
+	
+		USBWireVPin => USBWireVPin,
+		USBWireVMin => USBWireVMin,
+		USBWireVPout => USBWireVPout,
+		USBWireVMout => USBWireVMout,
+		USBWireOE_n => USBWireOE_n
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(14 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>16) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+  ---------------------------------
+  -- process for CVBS output (TODO - merge this into the svideo.vhd component, as an option...)
+  ---------------------------------
+ -- cvbs_block:
+ -- IF (SVIDEO_OUT = 2) GENERATE
+  PROCESS
+  (
+    svideo_dac_clk,
+    svideo_yout_dly1,
+    svideo_yout_dly2,
+	 svideo_yout_dly3
+  )
+  BEGIN
+	IF (rising_edge(svideo_dac_clk)) THEN
+		svideo_yout_dly1			<= 	svideo_yout;
+		svideo_yout_dly2			<= 	svideo_yout_dly1;
+		svideo_yout_dly3			<= 	svideo_yout_dly2;
+		luma_saturated		    	<= 	luma - "0000011111";
+		cvbs1_out  					<= 	luma_saturated + (chroma(8) & chroma(8 DOWNTO 0)) ;
+		IF (svideo_yout_dly2 = "00000000") THEN
+			cvbs2_out  				<=  "00000000";
+		ELSE 
+			cvbs2_out  				<=  cvbs1_out(9 DOWNTO 2);
+		END IF;
+     END IF;
+  END PROCESS;
+
+  VGA_B				<= cvbs2_out(7 DOWNTO 4); -- WHEN JOY1_n(2) = '1' ELSE svideo_yout(7 DOWNTO 4) ;
+  VGA_G				<= cvbs2_out(3 DOWNTO 0); -- WHEN JOY1_n(2) = '1' ELSE svideo_yout(3 DOWNTO 0) ; 
+ -- END GENERATE;
+
+END vhdl;
Index: mcctv_5200/changes
===================================================================
--- mcctv_5200/changes	(nonexistent)
+++ mcctv_5200/changes	(revision 288)
@@ -0,0 +1,131 @@
+Index: atari800core_mcc.vhd
+===================================================================
+--- atari800core_mcc.vhd	(revision 270)
++++ atari800core_mcc.vhd	(working copy)
+@@ -245,8 +223,15 @@
+ 	signal CLK_SDRAM : std_logic;
+ 
+ 	-- SDRAM
++	signal PREREG_SDRAM_REQUEST : std_logic;
++	signal PREREG_SDRAM_READ_ENABLE :  STD_LOGIC;
++	signal PREREG_SDRAM_WRITE_ENABLE : std_logic;
++	signal PREREG_SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
++	SIGNAL PREREG_SDRAM_DI : std_logic_vector(31 downto 0);
++	SIGNAL PREREG_SDRAM_WIDTH_32BIT_ACCESS : std_logic;
++	SIGNAL PREREG_SDRAM_WIDTH_16BIT_ACCESS : std_logic;
++	SIGNAL PREREG_SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+ 	signal SDRAM_REQUEST : std_logic;
+-	signal SDRAM_REQUEST_COMPLETE : std_logic;
+ 	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+ 	signal SDRAM_WRITE_ENABLE : std_logic;
+ 	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+@@ -254,6 +239,8 @@
+ 	SIGNAL SDRAM_WIDTH_32BIT_ACCESS : std_logic;
+ 	SIGNAL SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+ 	SIGNAL SDRAM_WIDTH_8BIT_ACCESS : std_logic;
++
++	signal SDRAM_REQUEST_COMPLETE : std_logic;
+ 	
+ 	signal SDRAM_REFRESH : std_logic;
+ 
+@@ -570,16 +535,16 @@
+ 		CONSOL_SELECT => CONSOL_SELECT,
+ 		CONSOL_START => CONSOL_START,
+ 
+-		SDRAM_REQUEST => SDRAM_REQUEST,
++		SDRAM_REQUEST => PREREG_SDRAM_REQUEST,
+ 		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+-		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+-		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+-		SDRAM_ADDR => SDRAM_ADDR,
++		SDRAM_READ_ENABLE => PREREG_SDRAM_READ_ENABLE,
++		SDRAM_WRITE_ENABLE => PREREG_SDRAM_WRITE_ENABLE,
++		SDRAM_ADDR => PREREG_SDRAM_ADDR,
+ 		SDRAM_DO => ram_do_reg,
+-		SDRAM_DI => SDRAM_DI,
+-		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
+-		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
+-		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
++		SDRAM_DI => PREREG_SDRAM_DI,
++		SDRAM_32BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_32bit_ACCESS,
++		SDRAM_16BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_16bit_ACCESS,
++		SDRAM_8BIT_WRITE_ENABLE => PREREG_SDRAM_WIDTH_8bit_ACCESS,
+ 		SDRAM_REFRESH => SDRAM_REFRESH,
+ 
+ 		DMA_FETCH => dma_fetch,
+@@ -605,7 +570,7 @@
+ 	process(clk_sdram,sdram_reset_ctrl_n_reg)
+ 	begin
+ 		if (sdram_reset_ctrl_n_reg='0') then
+-			seq_reg <= "100000000000";
++			seq_reg <= "010000000000";
+ 			seq_ph_reg <= '1';
+ 			ref_reg <= '0';
+ 
+@@ -653,7 +618,7 @@
+ 	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
+ 	begin
+ 		sdram_reset_n_next <= sdram_reset_n_reg;
+-		if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
++		if (sdram_rdy = '1' and seq_next(7)='1' and seq_reg(7)='0') then
+ 			sdram_reset_n_next <= '1';
+ 		end if;
+ 		if (reset_atari = '1') then
+@@ -661,10 +626,34 @@
+ 		end if;
+ 	end process;
+ 
++	-- register sdram request on the falling edge, 1/3 timing not enough, but 1/2 timing should be... This pushes back request 1 clock cycle. Result can also be clocking on the falling edge!
++	process(clk,reset_n)
++	begin
++		if (reset_n='0') then
++			SDRAM_REQUEST <= '0';
++			SDRAM_READ_ENABLE <= '0';
++			SDRAM_WRITE_ENABLE <= '0';
++			SDRAM_ADDR <= (others=>'0');
++			SDRAM_DI <= (others=>'0');
++			SDRAM_WIDTH_32BIT_ACCESS <= '0';
++			SDRAM_WIDTH_16BIT_ACCESS <= '0';
++			SDRAM_WIDTH_8BIT_ACCESS <= '0';
++		elsif(clk'event and clk='0') then -- FALLING EDGE
++			SDRAM_REQUEST <= PREREG_SDRAM_REQUEST;
++			SDRAM_READ_ENABLE <= PREREG_SDRAM_READ_ENABLE;
++			SDRAM_WRITE_ENABLE <= PREREG_SDRAM_WRITE_ENABLE;
++			SDRAM_ADDR <= PREREG_SDRAM_ADDR;
++			SDRAM_DI <= PREREG_SDRAM_DI;
++			SDRAM_WIDTH_32BIT_ACCESS <= PREREG_SDRAM_WIDTH_32BIT_ACCESS;
++			SDRAM_WIDTH_16BIT_ACCESS <= PREREG_SDRAM_WIDTH_16BIT_ACCESS;
++			SDRAM_WIDTH_8BIT_ACCESS <= PREREG_SDRAM_WIDTH_8BIT_ACCESS;
++		end if;
++	end process;
++
+ 	-- Adapt SDRAM
+ 	process(sdram_request_reg, sdram_request, sdram_request_complete_reg, ram_do_reg, seq_reg, ram_do, ram_rd_active, ram_wr_active, SDRAM_WIDTH_8BIT_ACCESS, SDRAM_WRITE_ENABLE, SDRAM_READ_ENABLE, SDRAM_DI, SDRAM_ADDR)
+ 	begin
+-		sdram_request_next <= sdram_request_reg or sdram_request;
++		sdram_request_next <= (sdram_request_reg or sdram_request) and not(sdram_request_complete_reg);
+ 		sdram_request_complete_next <= sdram_request_complete_reg;
+ 		ram_bena_next <= "00";
+ 		ram_di_next <= (others=>'0');
+@@ -699,9 +688,9 @@
+ 		when "000000001000" =>
+ 			-- nop
+ 		when "000000010000" =>
+-			sdram_request_complete_next <= '0';
+ 			-- nop
+ 		when "000000100000" =>
++			sdram_request_complete_next <= '0';
+ 			-- nop
+ 		when "000001000000" =>
+ 			if (SDRAM_READ_ENABLE = '1') then
+@@ -732,9 +721,9 @@
+ 		when "001000000000" =>
+ 			-- nop
+ 		when "010000000000" =>
+-			sdram_request_complete_next <= '0';
+ 			-- nop
+ 		when "100000000000" =>
++			sdram_request_complete_next <= '0';
+ 			-- nop
+ 		when others =>
+ 			-- never
Index: mcctv_5200/ntsc_pll.ppf
===================================================================
--- mcctv_5200/ntsc_pll.ppf	(nonexistent)
+++ mcctv_5200/ntsc_pll.ppf	(revision 288)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="ntsc_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv_5200/pll_downstream_ntsc.cmp
===================================================================
--- mcctv_5200/pll_downstream_ntsc.cmp	(nonexistent)
+++ mcctv_5200/pll_downstream_ntsc.cmp	(revision 288)
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_downstream_ntsc
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv_5200/rbf2arg/rbf2arg.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcctv_5200/rbf2arg/rbf2arg.exe
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcctv_5200/sdram_ctrl_3_ports.wcfg
===================================================================
--- mcctv_5200/sdram_ctrl_3_ports.wcfg	(nonexistent)
+++ mcctv_5200/sdram_ctrl_3_ports.wcfg	(revision 288)
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="sdram_ctrl_3_ports.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="numeric_std" />
+            <top_module name="sdram_ctrl_3_ports_tb" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="24" />
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_rdy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_rdy</obj_property>
+      <obj_property name="ObjectShortName">sdram_rdy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cs_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cs_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cs_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ras_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ras_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_ras_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_cas_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_cas_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_cas_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_we_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_we_n</obj_property>
+      <obj_property name="ObjectShortName">sdram_we_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dqm_n" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dqm_n[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_addr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_oe" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_oe</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_oe</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_o[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_dq_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sdram_dq_i[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="ObjectShortName">seq_reg[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/seq_ph_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">seq_ph_reg</obj_property>
+      <obj_property name="ObjectShortName">seq_ph_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_rd_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_rd_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_rd_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_wr_active" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_wr_active[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_wr_active[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ref_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ref_reg</obj_property>
+      <obj_property name="ObjectShortName">ref_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_refr_req" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_refr_req</obj_property>
+      <obj_property name="ObjectShortName">r_refr_req</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/sdram_controller/r_psel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_psel[2:0]</obj_property>
+      <obj_property name="ObjectShortName">r_psel[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_di2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_di2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/sdram_ctrl_3_ports_tb/ram_do2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_do2[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#0000ff</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv_5200/svideo/sin_cos.vhd
===================================================================
--- mcctv_5200/svideo/sin_cos.vhd	(nonexistent)
+++ mcctv_5200/svideo/sin_cos.vhd	(revision 288)
@@ -0,0 +1,102 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE sin_cos_pkg IS
+  COMPONENT sin_cos
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+  END COMPONENT;
+END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+ENTITY sin_cos IS
+  PORT(
+    -- Clock
+    clk      : IN  STD_LOGIC;
+    clk_ena  : IN  STD_LOGIC;
+    -- Sine computation
+    sin_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sin_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sin_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- Cosine computation
+    cos_ph   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+    cos_amp  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    cos_out  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+  );
+END sin_cos;
+
+ARCHITECTURE rtl OF sin_cos IS
+
+  COMPONENT sin_rom IS
+  PORT
+  (
+    clock     : IN STD_LOGIC;
+    enable    : IN STD_LOGIC := '1';
+    address_a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    q_a       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+  END COMPONENT sin_rom;
+
+  SIGNAL sin_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL cos_val    : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL sin_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL cos_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+BEGIN
+
+  sin_inst : sin_rom
+  PORT MAP
+  (
+    clock                  => clk,
+    enable                 => clk_ena,
+    address_a(10 DOWNTO 3) => sin_amp,
+    address_a(2)           => sin_ph(2) XOR sin_ph(3),
+    address_a(1)           => sin_ph(1) XOR sin_ph(3),
+    address_a(0)           => sin_ph(0) XOR sin_ph(3),
+    q_a                    => sin_val(7 DOWNTO 0),
+    address_b(10 DOWNTO 3) => cos_amp,
+    address_b(2)           => cos_ph(2) XOR (NOT cos_ph(3)),
+    address_b(1)           => cos_ph(1) XOR (NOT cos_ph(3)),
+    address_b(0)           => cos_ph(0) XOR (NOT cos_ph(3)),
+    q_b                    => cos_val(7 DOWNTO 0)
+  );
+  sin_val(8) <= '0';
+  cos_val(8) <= '0';
+  
+  -- Delayed phase for output generation
+  sin_ph_dly <= sin_ph WHEN rising_edge(clk);
+  cos_ph_dly <= cos_ph WHEN rising_edge(clk);
+
+  -- Output generation using sine and cosine symetries
+  sin_cos_gen:
+  FOR i IN 0 TO 8 GENERATE
+    sin_out(i) <= sin_val(i) XOR sin_ph_dly(4);
+    cos_out(i) <= cos_val(i) XOR cos_ph_dly(3) XOR cos_ph_dly(4);
+  END GENERATE;
+
+END rtl;
\ No newline at end of file
Index: mcctv_5200/svideo/svideo.vhd
===================================================================
--- mcctv_5200/svideo/svideo.vhd	(nonexistent)
+++ mcctv_5200/svideo/svideo.vhd	(revision 288)
@@ -0,0 +1,404 @@
+-- ===================================================================================
+-- Package / Component definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+--PACKAGE svideo_pkg IS
+--  COMPONENT svideo
+--  PORT(
+--    -- Power up reset
+--    areset_n    : IN  STD_LOGIC;
+--    -- Main clock (28.636363 MHz)
+--    ecs_clk     : IN  STD_LOGIC;
+--    -- DAC clock (114.545454 MHz)
+--    dac_clk     : IN  STD_LOGIC;
+--    -- RGB input
+--    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    -- Start of frame flag
+--    sof         : IN  STD_LOGIC;
+--    -- PAL burst phase
+--    vpos_lsb    : IN  STD_LOGIC;
+--    -- Burst/Synchro/Blanking inputs
+--    blank       : IN  STD_LOGIC;
+--    burst       : IN  STD_LOGIC;
+--    csync_n     : IN  STD_LOGIC;
+--    -- S-Video output
+--    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+--    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--    -- PAL(0)/NTSC(1) mode
+--    pal_ntsc    : IN  STD_LOGIC
+--  );
+--  END COMPONENT;
+--
+--END PACKAGE;
+
+-- ===================================================================================
+-- Entity / Architecture definition
+-- ===================================================================================
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.SIN_COS_PKG.ALL;
+
+ENTITY svideo IS
+  PORT(
+    -- Power up reset
+    areset_n    : IN  STD_LOGIC;
+    -- Main clock (28.636363 MHz)
+    ecs_clk     : IN  STD_LOGIC;
+    -- DAC clock (114.545454 MHz)
+    dac_clk     : IN  STD_LOGIC;
+    -- RGB input
+    r_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    g_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    b_in        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    -- Start of frame flag
+    sof         : IN  STD_LOGIC;
+    -- PAL burst phase
+    vpos_lsb    : IN  STD_LOGIC;
+    -- Burst/Synchro/Blanking inputs
+    blank       : IN  STD_LOGIC;
+    burst       : IN  STD_LOGIC;
+    csync_n     : IN  STD_LOGIC;
+    -- S-Video output
+    y_out       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    c_out       : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    -- raw chroma/luma output
+    luma_out       : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+    chroma_out     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    -- PAL(0)/NTSC(1) mode
+    pal_ntsc    : IN  STD_LOGIC
+  );
+END svideo;
+
+ARCHITECTURE rtl OF svideo IS
+
+  -- Color carrier phase (0 - 31)
+  SIGNAL   col_ctr      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+  -------------------------
+  -- RGB -> Y conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_YR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_YB      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_Y2      : STD_LOGIC_VECTOR(16 DOWNTO 0);
+  SIGNAL   comp_Y3      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   comp_Y4      : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+  CONSTANT Y_LVL_SYNC   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "00000000000000000";
+  CONSTANT Y_LVL_BLANK  : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+  CONSTANT Y_LVL_PICT   : STD_LOGIC_VECTOR(16 DOWNTO 0) := "01110011000000000";
+
+  -------------------------
+  -- RGB -> U conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_UR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_UB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mU      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_U       : STD_LOGIC;
+  SIGNAL   ampl_U       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_U       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000100100000000000"; -- +15%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111011100000000000"; -- -15%
+--  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000110000000000000"; -- +20%
+--  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111010000000000000"; -- -20%
+  CONSTANT pU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "000111111000000000"; -- +25%
+  CONSTANT mU_LVL_BURST : STD_LOGIC_VECTOR(17 DOWNTO 0) := "111000000000000000"; -- -25%
+
+  -------------------------
+  -- RGB -> V conversion --
+  -------------------------
+  -- 1st stage
+  SIGNAL   comp_VR      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VG      : UNSIGNED(16 DOWNTO 0);
+  SIGNAL   comp_VB      : UNSIGNED(16 DOWNTO 0);
+  -- 2nd stage
+  SIGNAL   comp_pV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  SIGNAL   comp_mV      : STD_LOGIC_VECTOR(17 DOWNTO 0);
+  -- 3rd stage
+  SIGNAL   sign_V       : STD_LOGIC;
+  SIGNAL   ampl_V       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  -- 4th stage
+  SIGNAL   comp_V       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+
+  -----------------
+  -- Y/C signals --
+  -----------------
+  SIGNAL   luma         : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_1       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_2       : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   luma_acc     : STD_LOGIC_VECTOR(9 DOWNTO 0);
+  SIGNAL   chroma       : STD_LOGIC_VECTOR(8 DOWNTO 0);
+  SIGNAL   chroma_1     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_2     : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   chroma_acc   : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+  -- Delayed input signals
+  SIGNAL   blank_dly    : STD_LOGIC;
+  SIGNAL   burst_dly    : STD_LOGIC;
+  SIGNAL   csync_dly    : STD_LOGIC;
+  SIGNAL   sof_dly      : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+  PROCESS
+  (
+    areset_n,    -- Global reset
+    ecs_clk,     -- Main clock
+    csync_n,     -- Composite synchro (active low)
+    blank,       -- Composite blanking
+    burst,       -- Burst enable flag
+    pal_ntsc,    -- PAL(0) / NTSC(1)
+    sof          -- Start of frame flag
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      -- Color carrier phase
+      col_ctr <= (OTHERS => '0');
+      -- Y component
+      comp_YR <= (OTHERS => '0');
+      comp_YG <= (OTHERS => '0');
+      comp_YB <= (OTHERS => '0');
+      comp_Y2 <= (OTHERS => '0');
+      comp_Y3 <= (OTHERS => '0');
+      comp_Y4 <= (OTHERS => '0');
+      -- U component
+      comp_UR <= (OTHERS => '0');
+      comp_UG <= (OTHERS => '0');
+      comp_UB <= (OTHERS => '0');
+      comp_pU <= (OTHERS => '0');
+      comp_mU <= (OTHERS => '0');
+      sign_U  <= '0';
+      ampl_U  <= (OTHERS => '0');
+      -- V component
+      comp_VR <= (OTHERS => '0');
+      comp_VG <= (OTHERS => '0');
+      comp_VB <= (OTHERS => '0');
+      comp_pV <= (OTHERS => '0');
+      comp_mV <= (OTHERS => '0');
+      sign_V  <= '0';
+      ampl_V  <= (OTHERS => '0');
+    ELSIF (rising_edge(ecs_clk)) THEN
+      -----------------
+      -----------------
+      -- First stage --
+      -----------------
+      -----------------
+
+      -- RGB -> Y conversion :
+      ------------------------
+      --     Y = (0.299*R + 0.587*G + 0.114*B) * 140 / 256
+      --     Y =  0.164*R + 0.321*G + 0.062*B
+      -- 512*Y =     84*R +   164*G +    32*B
+      comp_YR <= "001010100" * unsigned(r_in);
+      comp_YG <= "010100100" * unsigned(g_in);
+      comp_YB <= "000100000" * unsigned(b_in);
+
+      -- RGB -> U conversion :
+      ------------------------
+      --     U = -0.147*R - 0.289*G + 0.436*B
+      -- 512*U =    -75*R -   148*G +   223*B
+      comp_UR <= "001001011" * unsigned(r_in);
+      comp_UG <= "010010100" * unsigned(g_in);
+      comp_UB <= "011011111" * unsigned(b_in);
+
+      -- RGB -> V conversion :
+      ------------------------
+      --     V =  0.615*R - 0.515*G - 0.100*B
+      -- 512*V =    315*R -   264*G -    51*B
+      comp_VR <= "100111011" * unsigned(r_in);
+      comp_VG <= "100001000" * unsigned(g_in);
+      comp_VB <= "000110011" * unsigned(b_in);
+      
+      -- Delayed signals :
+      --------------------
+      csync_dly <= csync_n;          -- to 2nd stage
+      blank_dly <= blank;            -- to 2nd stage
+      burst_dly <= burst;            -- to 2nd stage
+      sof_dly   <= sof_dly(0) & sof; -- to 3rd stage
+
+      ------------------
+      ------------------
+      -- Second stage --
+      ------------------
+      ------------------
+
+      -- Compute Y
+      IF (csync_dly = '0') THEN
+        -- Synchro level
+        comp_Y2 <= Y_LVL_SYNC;
+      ELSIF (blank_dly = '1') THEN
+        -- Blanking level
+        comp_Y2 <= Y_LVL_BLANK;
+      ELSE
+        -- Picture level
+        comp_Y2 <= std_logic_vector(comp_YR)
+                 + std_logic_vector(comp_YG)
+                 + std_logic_vector(comp_YB)
+                 + Y_LVL_PICT;
+      END IF;
+
+      -- Compute U
+      IF (burst_dly = '1') THEN
+        comp_pU <= mU_LVL_BURST;
+        comp_mU <= pU_LVL_BURST;
+      ELSE
+        comp_pU <= std_logic_vector('0' & comp_UB)
+                 - std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UR);
+        comp_mU <= std_logic_vector('0' & comp_UR)
+                 + std_logic_vector('0' & comp_UG)
+                 - std_logic_vector('0' & comp_UB);
+      END IF;
+
+      -- Compute V
+      IF (burst_dly = '1') THEN
+        IF (pal_ntsc = '1') THEN
+          -- NTSC burst
+          comp_pV <= (OTHERS => '0');
+          comp_mV <= (OTHERS => '0');
+        ELSE
+          -- PAL burst
+          comp_pV <= pU_LVL_BURST;
+          comp_mV <= mU_LVL_BURST;
+        END IF;
+      ELSE
+        comp_pV <= std_logic_vector('0' & comp_VR)
+                 - std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VB);
+        comp_mV <= std_logic_vector('0' & comp_VB)
+                 + std_logic_vector('0' & comp_VG)
+                 - std_logic_vector('0' & comp_VR);
+      END IF;
+
+      -----------------
+      -----------------
+      -- Third stage --
+      -----------------
+      -----------------
+      
+      -- Copy Y
+      comp_Y3 <= comp_Y2(16 DOWNTO 7);
+
+      -- Phase and amplitude for U,V
+      sign_U <= comp_pU(17);
+      sign_V <= comp_pV(17) XOR (vpos_lsb AND (NOT pal_ntsc));
+      IF (comp_pU(17) = '1') THEN
+        ampl_U <= comp_mU(16 DOWNTO 9);
+      ELSE
+        ampl_U <= comp_pU(16 DOWNTO 9);
+      END IF;
+      IF (comp_pV(17) = '1') THEN
+        ampl_V <= comp_mV(16 DOWNTO 9);
+      ELSE
+        ampl_V <= comp_pV(16 DOWNTO 9);
+      END IF;
+
+      -- Color carrier phase
+      IF (sof_dly(1) = '1') THEN
+        col_ctr <= (OTHERS => '0');
+      ELSE
+        -- +4 for NTSC, +5 for PAL
+        col_ctr <= col_ctr + ("0010" & (NOT pal_ntsc));
+      END IF;
+
+      ------------------
+      ------------------
+      -- Fourth stage --
+      ------------------
+      ------------------
+      
+      -- Copy Y
+      comp_Y4 <= comp_Y3;
+
+      -----------------
+      -----------------
+      -- Fifth stage --
+      -----------------
+      -----------------
+
+      -- Y/C signal
+      luma <= comp_Y4;
+      chroma <= comp_U + comp_V;
+
+    END IF;
+
+  END PROCESS;
+
+  -----------------------------------
+  -----------------------------------
+  -- 4th stage : chroma modulation --
+  -----------------------------------
+  -----------------------------------
+
+  tab_inst : sin_cos
+  PORT MAP
+  (
+    clk                => ecs_clk,
+    clk_ena            => '1',
+    sin_ph(4)          => col_ctr(4) XOR sign_U,
+    sin_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    sin_amp            => ampl_U,
+    sin_out            => comp_U,
+    cos_ph(4)          => col_ctr(4) XOR sign_V,
+    cos_ph(3 DOWNTO 0) => col_ctr(3 DOWNTO 0),
+    cos_amp            => ampl_V,
+    cos_out            => comp_V
+  );
+
+  -----------------------------------
+  -- High-speed DAC with dithering --
+  -----------------------------------
+  PROCESS
+  (
+    areset_n,   -- Global reset
+    dac_clk,    -- DAC clock (114.545454 MHz)
+    luma,       -- Luminance data
+    chroma      -- Chrominance data
+  )
+  BEGIN
+    IF (areset_n = '0') THEN
+      luma_1     <= (OTHERS => '0');
+      luma_2     <= (OTHERS => '0');
+      luma_acc   <= (OTHERS => '0');
+      chroma_1   <= (OTHERS => '0');
+      chroma_2   <= (OTHERS => '0');
+      chroma_acc <= (OTHERS => '0');
+    ELSE
+      IF (rising_edge(dac_clk)) THEN
+        -- Clock domain crossing
+        luma_1   <= luma;
+        luma_2   <= luma_1;
+        chroma_1 <= (NOT chroma(8)) & chroma(7 DOWNTO 1);
+        chroma_2 <= chroma_1;
+        -- First order delta-sigma
+        luma_acc   <= luma_2 + ("00000000" & luma_acc(1 DOWNTO 0));
+        chroma_acc <= chroma_2 + ("000000" & chroma_acc(1 DOWNTO 0));
+      END IF;
+    END IF;
+  END PROCESS;
+  -- Y/C outputs
+  y_out <= luma_acc(9 DOWNTO 2);
+  c_out <= chroma_acc(7 DOWNTO 2);
+
+  -- raw luma/chroma
+  luma_out <= luma;
+  chroma_out <= chroma;
+
+END rtl;
Index: mcctv_5200/usbpll.vhd
===================================================================
--- mcctv_5200/usbpll.vhd	(nonexistent)
+++ mcctv_5200/usbpll.vhd	(revision 288)
@@ -0,0 +1,365 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: usbpll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY usbpll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END usbpll;
+
+
+ARCHITECTURE SYN OF usbpll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 48,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=usbpll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "usbpll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "48"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL usbpll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv_5200/sdram_ctrl_4_ports.v
===================================================================
--- mcctv_5200/sdram_ctrl_4_ports.v	(nonexistent)
+++ mcctv_5200/sdram_ctrl_4_ports.v	(revision 288)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: mcctv_5200/svideo/sin_rom.mif
===================================================================
--- mcctv_5200/svideo/sin_rom.mif	(nonexistent)
+++ mcctv_5200/svideo/sin_rom.mif	(revision 288)
@@ -0,0 +1,2054 @@
+WIDTH=8;
+DEPTH=2048;
+ADDRESS_RADIX=UNS;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+    0      : 00;
+    1      : 00;
+    2      : 00;
+    3      : 00;
+    4      : 00;
+    5      : 00;
+    6      : 00;
+    7      : 00;
+    8      : 00;
+    9      : 00;
+    10     : 00;
+    11     : 00;
+    12     : 00;
+    13     : 00;
+    14     : 00;
+    15     : 01;
+    16     : 00;
+    17     : 00;
+    18     : 00;
+    19     : 01;
+    20     : 01;
+    21     : 01;
+    22     : 01;
+    23     : 02;
+    24     : 00;
+    25     : 00;
+    26     : 01;
+    27     : 01;
+    28     : 02;
+    29     : 02;
+    30     : 02;
+    31     : 03;
+    32     : 00;
+    33     : 01;
+    34     : 01;
+    35     : 02;
+    36     : 03;
+    37     : 03;
+    38     : 03;
+    39     : 04;
+    40     : 00;
+    41     : 01;
+    42     : 02;
+    43     : 03;
+    44     : 03;
+    45     : 04;
+    46     : 04;
+    47     : 05;
+    48     : 00;
+    49     : 01;
+    50     : 02;
+    51     : 03;
+    52     : 04;
+    53     : 05;
+    54     : 05;
+    55     : 06;
+    56     : 00;
+    57     : 02;
+    58     : 03;
+    59     : 04;
+    60     : 05;
+    61     : 06;
+    62     : 06;
+    63     : 07;
+    64     : 00;
+    65     : 02;
+    66     : 03;
+    67     : 05;
+    68     : 06;
+    69     : 07;
+    70     : 07;
+    71     : 08;
+    72     : 00;
+    73     : 02;
+    74     : 04;
+    75     : 05;
+    76     : 06;
+    77     : 07;
+    78     : 08;
+    79     : 09;
+    80     : 00;
+    81     : 02;
+    82     : 04;
+    83     : 06;
+    84     : 07;
+    85     : 08;
+    86     : 09;
+    87     : 0A;
+    88     : 01;
+    89     : 03;
+    90     : 05;
+    91     : 07;
+    92     : 08;
+    93     : 09;
+    94     : 0A;
+    95     : 0B;
+    96     : 01;
+    97     : 03;
+    98     : 05;
+    99     : 07;
+    100    : 09;
+    101    : 0A;
+    102    : 0B;
+    103    : 0C;
+    104    : 01;
+    105    : 03;
+    106    : 06;
+    107    : 08;
+    108    : 0A;
+    109    : 0B;
+    110    : 0C;
+    111    : 0D;
+    112    : 01;
+    113    : 04;
+    114    : 06;
+    115    : 08;
+    116    : 0A;
+    117    : 0C;
+    118    : 0D;
+    119    : 0E;
+    120    : 01;
+    121    : 04;
+    122    : 07;
+    123    : 09;
+    124    : 0B;
+    125    : 0D;
+    126    : 0E;
+    127    : 0F;
+    128    : 01;
+    129    : 04;
+    130    : 07;
+    131    : 0A;
+    132    : 0C;
+    133    : 0E;
+    134    : 0F;
+    135    : 10;
+    136    : 01;
+    137    : 04;
+    138    : 08;
+    139    : 0A;
+    140    : 0D;
+    141    : 0F;
+    142    : 10;
+    143    : 11;
+    144    : 01;
+    145    : 05;
+    146    : 08;
+    147    : 0B;
+    148    : 0D;
+    149    : 0F;
+    150    : 11;
+    151    : 12;
+    152    : 01;
+    153    : 05;
+    154    : 08;
+    155    : 0C;
+    156    : 0E;
+    157    : 10;
+    158    : 12;
+    159    : 13;
+    160    : 01;
+    161    : 05;
+    162    : 09;
+    163    : 0C;
+    164    : 0F;
+    165    : 11;
+    166    : 13;
+    167    : 14;
+    168    : 02;
+    169    : 06;
+    170    : 09;
+    171    : 0D;
+    172    : 10;
+    173    : 12;
+    174    : 14;
+    175    : 15;
+    176    : 02;
+    177    : 06;
+    178    : 0A;
+    179    : 0E;
+    180    : 11;
+    181    : 13;
+    182    : 15;
+    183    : 16;
+    184    : 02;
+    185    : 06;
+    186    : 0A;
+    187    : 0E;
+    188    : 11;
+    189    : 14;
+    190    : 16;
+    191    : 17;
+    192    : 02;
+    193    : 07;
+    194    : 0B;
+    195    : 0F;
+    196    : 12;
+    197    : 15;
+    198    : 17;
+    199    : 18;
+    200    : 02;
+    201    : 07;
+    202    : 0B;
+    203    : 0F;
+    204    : 13;
+    205    : 16;
+    206    : 18;
+    207    : 19;
+    208    : 02;
+    209    : 07;
+    210    : 0C;
+    211    : 10;
+    212    : 14;
+    213    : 17;
+    214    : 19;
+    215    : 1A;
+    216    : 02;
+    217    : 07;
+    218    : 0C;
+    219    : 11;
+    220    : 14;
+    221    : 17;
+    222    : 19;
+    223    : 1B;
+    224    : 02;
+    225    : 08;
+    226    : 0D;
+    227    : 11;
+    228    : 15;
+    229    : 18;
+    230    : 1A;
+    231    : 1C;
+    232    : 02;
+    233    : 08;
+    234    : 0D;
+    235    : 12;
+    236    : 16;
+    237    : 19;
+    238    : 1B;
+    239    : 1D;
+    240    : 02;
+    241    : 08;
+    242    : 0E;
+    243    : 13;
+    244    : 17;
+    245    : 1A;
+    246    : 1C;
+    247    : 1E;
+    248    : 03;
+    249    : 09;
+    250    : 0E;
+    251    : 13;
+    252    : 18;
+    253    : 1B;
+    254    : 1D;
+    255    : 1F;
+    256    : 03;
+    257    : 09;
+    258    : 0F;
+    259    : 14;
+    260    : 18;
+    261    : 1C;
+    262    : 1E;
+    263    : 20;
+    264    : 03;
+    265    : 09;
+    266    : 0F;
+    267    : 15;
+    268    : 19;
+    269    : 1D;
+    270    : 1F;
+    271    : 21;
+    272    : 03;
+    273    : 09;
+    274    : 10;
+    275    : 15;
+    276    : 1A;
+    277    : 1E;
+    278    : 20;
+    279    : 22;
+    280    : 03;
+    281    : 0A;
+    282    : 10;
+    283    : 16;
+    284    : 1B;
+    285    : 1F;
+    286    : 21;
+    287    : 23;
+    288    : 03;
+    289    : 0A;
+    290    : 11;
+    291    : 16;
+    292    : 1B;
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+    1918   : E5;
+    1919   : EF;
+    1920   : 17;
+    1921   : 46;
+    1922   : 71;
+    1923   : 98;
+    1924   : BA;
+    1925   : D4;
+    1926   : E6;
+    1927   : F0;
+    1928   : 17;
+    1929   : 46;
+    1930   : 72;
+    1931   : 99;
+    1932   : BB;
+    1933   : D5;
+    1934   : E7;
+    1935   : F1;
+    1936   : 17;
+    1937   : 46;
+    1938   : 72;
+    1939   : 9A;
+    1940   : BB;
+    1941   : D6;
+    1942   : E8;
+    1943   : F2;
+    1944   : 17;
+    1945   : 46;
+    1946   : 73;
+    1947   : 9A;
+    1948   : BC;
+    1949   : D7;
+    1950   : E9;
+    1951   : F3;
+    1952   : 18;
+    1953   : 47;
+    1954   : 73;
+    1955   : 9B;
+    1956   : BD;
+    1957   : D8;
+    1958   : EA;
+    1959   : F4;
+    1960   : 18;
+    1961   : 47;
+    1962   : 74;
+    1963   : 9C;
+    1964   : BE;
+    1965   : D9;
+    1966   : EB;
+    1967   : F5;
+    1968   : 18;
+    1969   : 47;
+    1970   : 74;
+    1971   : 9C;
+    1972   : BF;
+    1973   : DA;
+    1974   : EC;
+    1975   : F6;
+    1976   : 18;
+    1977   : 48;
+    1978   : 74;
+    1979   : 9D;
+    1980   : BF;
+    1981   : DA;
+    1982   : ED;
+    1983   : F7;
+    1984   : 18;
+    1985   : 48;
+    1986   : 75;
+    1987   : 9E;
+    1988   : C0;
+    1989   : DB;
+    1990   : EE;
+    1991   : F8;
+    1992   : 18;
+    1993   : 48;
+    1994   : 75;
+    1995   : 9E;
+    1996   : C1;
+    1997   : DC;
+    1998   : EF;
+    1999   : F9;
+    2000   : 18;
+    2001   : 48;
+    2002   : 76;
+    2003   : 9F;
+    2004   : C2;
+    2005   : DD;
+    2006   : F0;
+    2007   : FA;
+    2008   : 18;
+    2009   : 49;
+    2010   : 76;
+    2011   : A0;
+    2012   : C2;
+    2013   : DE;
+    2014   : F1;
+    2015   : FB;
+    2016   : 18;
+    2017   : 49;
+    2018   : 77;
+    2019   : A0;
+    2020   : C3;
+    2021   : DF;
+    2022   : F2;
+    2023   : FC;
+    2024   : 18;
+    2025   : 49;
+    2026   : 77;
+    2027   : A1;
+    2028   : C4;
+    2029   : E0;
+    2030   : F3;
+    2031   : FD;
+    2032   : 19;
+    2033   : 4A;
+    2034   : 78;
+    2035   : A1;
+    2036   : C5;
+    2037   : E1;
+    2038   : F4;
+    2039   : FE;
+    2040   : 19;
+    2041   : 4A;
+    2042   : 78;
+    2043   : A2;
+    2044   : C6;
+    2045   : E1;
+    2046   : F5;
+    2047   : FF;
+END;
Index: mcctv_5200/usbpll.cmp
===================================================================
--- mcctv_5200/usbpll.cmp	(nonexistent)
+++ mcctv_5200/usbpll.cmp	(revision 288)
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component usbpll
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcctv_5200/zpu.wcfg
===================================================================
--- mcctv_5200/zpu.wcfg	(nonexistent)
+++ mcctv_5200/zpu.wcfg	(revision 288)
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="atari800core_mcc.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="atari800core_mcc_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="vl_types" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="47" />
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">zpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_32bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_32bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_32bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_16bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_16bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_16bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_read_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_read_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_read_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_ready</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_memory_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_addr_fetch" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_fetch[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/cpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">cpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/atari800xl/mmu1/antic_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_fetch</obj_property>
+      <obj_property name="ObjectShortName">antic_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request</obj_property>
+      <obj_property name="ObjectShortName">sdram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/sdram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">sdram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request</obj_property>
+      <obj_property name="ObjectShortName">ram_request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/ram_request_complete" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_request_complete</obj_property>
+      <obj_property name="ObjectShortName">ram_request_complete</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out1" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out1[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out2[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out3" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out3[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_out4" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_out4[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/atarixl_simple_sdram1/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/reset_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_atari</obj_property>
+      <obj_property name="ObjectShortName">reset_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/pause_atari" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_atari</obj_property>
+      <obj_property name="ObjectShortName">pause_atari</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_reset_n_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdram_reset_n_reg</obj_property>
+      <obj_property name="ObjectShortName">sdram_reset_n_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_ram_sel" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_ram_sel</obj_property>
+      <obj_property name="ObjectShortName">ap1_ram_sel</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_address" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="ObjectShortName">ap1_address[23:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rden" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rden</obj_property>
+      <obj_property name="ObjectShortName">ap1_rden</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wren" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wren</obj_property>
+      <obj_property name="ObjectShortName">ap1_wren</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bena" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bena[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_rddata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_rddata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wrdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_wrdata[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_bst_siz" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ap1_bst_siz[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sdram_controller/ap1_wr_bst_act" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ap1_wr_bst_act</obj_property>
+      <obj_property name="ObjectShortName">ap1_wr_bst_act</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_zpu" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_zpu</obj_property>
+      <obj_property name="ObjectShortName">pause_zpu</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_next[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_next[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/pause_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pause_reg[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[4:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/config_regs/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat0</obj_property>
+      <obj_property name="ObjectShortName">sd_dat0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_cmd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/sd_dat3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sd_dat3</obj_property>
+      <obj_property name="ObjectShortName">sd_dat3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.opcode" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.opcode</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.opcode</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.pc" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.pc</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.pc</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.sp</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.sp</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_a</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_a</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/atari800core_mcc_tb/atari/zpu/zpu_and_glue/myzpu/dbg_o.stk_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">.stk_b</obj_property>
+      <obj_property name="ObjectShortName">dbg_o.stk_b</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: mcctv_5200/atari_mcc_auto_stripped.stp
===================================================================
--- mcctv_5200/atari_mcc_auto_stripped.stp	(nonexistent)
+++ mcctv_5200/atari_mcc_auto_stripped.stp	(revision 288)
@@ -0,0 +1,1585 @@
+<session jtag_chain="USB-Blaster [1-2]" jtag_device="@1: EP3C16/EP4CE15 (0x020F20DD)" sof_file="">
+  <display_tree gui_logging_enabled="1">
+    <display_branch instance="auto_signaltap_0" log="log: 2014/04/26 08:28:05  #1" signal_set="signal_set: 2014/04/25 22:38:45  #0" trigger="trigger: 2014/04/26 08:28:05  #0"/>
+  </display_tree>
+  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <signal_set is_expanded="true" name="signal_set: 2014/04/25 22:38:45  #0">
+      <clock name="sdram_ctrl:sdram_controller|clk" polarity="posedge" tap_mode="classic"/>
+      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="SDRAM_CAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[0]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[10]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[11]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[12]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[13]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[14]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[15]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[1]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[2]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[3]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[4]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[5]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[6]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[7]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[8]" tap_mode="classic"/>
+          <wire name="SDRAM_DQ[9]" tap_mode="classic"/>
+          <wire name="SDRAM_RAS_N" tap_mode="classic"/>
+          <wire name="SDRAM_WE_N" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" tap_mode="classic"/>
+          <wire name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[16]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[17]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[18]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[19]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[20]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[21]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[22]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[23]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_address[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_rden" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|ap1_wren" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" tap_mode="classic"/>
+          <wire name="sdram_ctrl:sdram_controller|sdram_dq_oe" tap_mode="classic"/>
+          <wire name="sdram_request_complete_reg" tap_mode="classic"/>
+          <wire name="sdram_request_reg" tap_mode="classic"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <node data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <node data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <node data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <node data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <node data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <node data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <node data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <node data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <node data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <node data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <node data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <node data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <node data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <node data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <node data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <node data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <node data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <node data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <node data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <node data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <node data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <node data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <node data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <node data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </node>
+          <node data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <node data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <node name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <node data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <node data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <node data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <node data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <node data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <node data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <node data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <node data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <node data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <node data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <node data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <node data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <node data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <node data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <node data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <node data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </node>
+          <node data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <node name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <node data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <node data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <node data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <node data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <node data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <node data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <node data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <node data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <node data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <node data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <node data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <node data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <node data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <node data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <node data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <node data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <node data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <node data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <node data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <node data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <node data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <node data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <node data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <node data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <node data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <node data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <node data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <node data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <node data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <node data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <node data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <node data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </node>
+          <node name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <node data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <node data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <node data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <node data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <node data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <node data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <node data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <node data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <node data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <node data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <node data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <node data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <node data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <node data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <node data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <node data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </node>
+          <node data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <node data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </node>
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+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <node data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <node data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <node data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <node data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <node data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <node data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <node data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <node data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <node data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <node data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <node data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <node data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <node data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <node data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <node data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <node data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <node data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <node data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <node data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <node data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <node data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
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+            <node data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <node data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <node data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <node data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <node data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <node data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <node data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <node data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <node data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <node data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <node data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <node data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <node data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
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+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
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+            <node data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <node data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <node data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <node data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <node data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <node data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <node data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <node data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <node data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <node data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <node data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <node data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <node data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <node data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <node data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <node data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <node data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <node data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <node data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <node data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <node data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </node>
+          <node name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <node data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <node data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <node data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <node data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <node data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <node data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <node data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <node data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </node>
+          <node data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <node data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </unified_setup_data_view>
+        <data_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </data_view>
+        <setup_view>
+          <bus name="sdram_ctrl:sdram_controller|ap1_address" order="msb_to_lsb" type="combinatorial">
+            <net data_index="233" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_oe" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="combinatorial"/>
+            <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="bidir pin"/>
+            <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="bidir pin"/>
+            <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="bidir pin"/>
+            <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="bidir pin"/>
+            <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="bidir pin"/>
+            <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="bidir pin"/>
+            <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="bidir pin"/>
+            <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="bidir pin"/>
+            <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="bidir pin"/>
+            <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="bidir pin"/>
+            <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="bidir pin"/>
+            <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="bidir pin"/>
+            <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="bidir pin"/>
+            <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="bidir pin"/>
+            <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="bidir pin"/>
+            <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_DQ[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="bidir pin"/>
+            <net data_index="157" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="combinatorial"/>
+            <net data_index="156" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="combinatorial"/>
+            <net data_index="155" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="combinatorial"/>
+            <net data_index="154" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="combinatorial"/>
+            <net data_index="152" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="combinatorial"/>
+            <net data_index="151" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="combinatorial"/>
+            <net data_index="150" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="combinatorial"/>
+            <net data_index="149" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="combinatorial"/>
+            <net data_index="148" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="combinatorial"/>
+            <net data_index="147" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="combinatorial"/>
+            <net data_index="146" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="combinatorial"/>
+            <net data_index="145" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="combinatorial"/>
+            <net data_index="144" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="combinatorial"/>
+            <net data_index="143" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="combinatorial"/>
+            <net data_index="165" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="combinatorial"/>
+            <net data_index="164" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="combinatorial"/>
+            <net data_index="163" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="combinatorial"/>
+            <net data_index="162" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="combinatorial"/>
+            <net data_index="161" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="combinatorial"/>
+            <net data_index="160" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="combinatorial"/>
+            <net data_index="159" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="combinatorial"/>
+            <net data_index="158" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="combinatorial"/>
+            <net data_index="153" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_address[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="combinatorial"/>
+          </bus>
+          <net data_index="166" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_rden" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="combinatorial"/>
+          <net data_index="167" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wr_bst_act" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="combinatorial"/>
+          <bus name="sdram_ctrl:sdram_controller|ap1_wrdata" order="msb_to_lsb" type="combinatorial">
+            <net data_index="174" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="combinatorial"/>
+            <net data_index="173" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="combinatorial"/>
+            <net data_index="172" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="combinatorial"/>
+            <net data_index="171" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="combinatorial"/>
+            <net data_index="170" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="combinatorial"/>
+            <net data_index="169" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="combinatorial"/>
+            <net data_index="183" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="combinatorial"/>
+            <net data_index="182" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="combinatorial"/>
+            <net data_index="181" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="combinatorial"/>
+            <net data_index="180" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="combinatorial"/>
+            <net data_index="179" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="combinatorial"/>
+            <net data_index="178" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="combinatorial"/>
+            <net data_index="177" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="combinatorial"/>
+            <net data_index="176" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="combinatorial"/>
+            <net data_index="175" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="combinatorial"/>
+            <net data_index="168" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wrdata[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="combinatorial"/>
+          </bus>
+          <net data_index="184" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|ap1_wren" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="combinatorial"/>
+          <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_CAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="output pin"/>
+          <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_RAS_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="output pin"/>
+          <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="falling edge" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="SDRAM_WE_N" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="output pin"/>
+          <bus name="sdram_ctrl:sdram_controller|r_sdram_dq_o" order="msb_to_lsb" type="register">
+            <net data_index="191" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="register"/>
+            <net data_index="190" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="register"/>
+            <net data_index="189" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="register"/>
+            <net data_index="188" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="register"/>
+            <net data_index="187" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="register"/>
+            <net data_index="186" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="register"/>
+            <net data_index="200" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="register"/>
+            <net data_index="199" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="register"/>
+            <net data_index="198" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="register"/>
+            <net data_index="197" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="register"/>
+            <net data_index="196" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="register"/>
+            <net data_index="195" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="register"/>
+            <net data_index="194" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="register"/>
+            <net data_index="193" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="register"/>
+            <net data_index="192" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="register"/>
+            <net data_index="185" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|r_sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="register"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_i" order="msb_to_lsb" type="combinatorial">
+            <net data_index="207" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="combinatorial"/>
+            <net data_index="206" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="combinatorial"/>
+            <net data_index="205" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="combinatorial"/>
+            <net data_index="204" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="combinatorial"/>
+            <net data_index="203" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="combinatorial"/>
+            <net data_index="202" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="combinatorial"/>
+            <net data_index="216" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="combinatorial"/>
+            <net data_index="215" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="combinatorial"/>
+            <net data_index="214" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="combinatorial"/>
+            <net data_index="213" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="combinatorial"/>
+            <net data_index="212" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="combinatorial"/>
+            <net data_index="211" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="combinatorial"/>
+            <net data_index="210" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="combinatorial"/>
+            <net data_index="209" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="combinatorial"/>
+            <net data_index="208" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="combinatorial"/>
+            <net data_index="201" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_i[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="combinatorial"/>
+          </bus>
+          <bus name="sdram_ctrl:sdram_controller|sdram_dq_o" order="msb_to_lsb" type="combinatorial">
+            <net data_index="223" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="combinatorial"/>
+            <net data_index="222" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="combinatorial"/>
+            <net data_index="221" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="combinatorial"/>
+            <net data_index="220" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="combinatorial"/>
+            <net data_index="219" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="combinatorial"/>
+            <net data_index="218" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="combinatorial"/>
+            <net data_index="232" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="combinatorial"/>
+            <net data_index="231" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="combinatorial"/>
+            <net data_index="230" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="combinatorial"/>
+            <net data_index="229" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="combinatorial"/>
+            <net data_index="228" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="combinatorial"/>
+            <net data_index="227" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="combinatorial"/>
+            <net data_index="226" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="combinatorial"/>
+            <net data_index="225" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="combinatorial"/>
+            <net data_index="224" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="combinatorial"/>
+            <net data_index="217" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_ctrl:sdram_controller|sdram_dq_o[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="combinatorial"/>
+          </bus>
+          <net data_index="234" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_complete_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="register"/>
+          <net data_index="235" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="sdram_request_reg" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="register"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR" order="msb_to_lsb" type="combinatorial">
+            <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>
+            <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>
+            <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>
+            <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>
+            <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>
+            <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>
+            <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>
+            <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>
+            <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>
+            <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>
+            <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>
+            <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>
+            <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>
+            <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>
+            <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>
+            <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>
+            <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>
+            <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>
+            <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>
+            <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>
+            <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>
+            <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>
+            <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_ADDR[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>
+          </bus>
+          <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_8BIT_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="combinatorial"/>
+            <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="combinatorial"/>
+            <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="combinatorial"/>
+            <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="combinatorial"/>
+            <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="combinatorial"/>
+            <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="combinatorial"/>
+            <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="combinatorial"/>
+            <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="combinatorial"/>
+            <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="combinatorial"/>
+            <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="combinatorial"/>
+            <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="combinatorial"/>
+            <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="combinatorial"/>
+            <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="combinatorial"/>
+            <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="combinatorial"/>
+            <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="combinatorial"/>
+            <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="combinatorial"/>
+            <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="combinatorial"/>
+            <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>
+            <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>
+            <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>
+            <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>
+            <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>
+            <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="combinatorial"/>
+            <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="combinatorial"/>
+            <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="combinatorial"/>
+            <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="combinatorial"/>
+            <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="combinatorial"/>
+            <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="combinatorial"/>
+            <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="combinatorial"/>
+            <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="combinatorial"/>
+            <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="combinatorial"/>
+            <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[31]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="combinatorial"/>
+            <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[30]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="combinatorial"/>
+            <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[29]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="combinatorial"/>
+            <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[28]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="combinatorial"/>
+            <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[27]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="combinatorial"/>
+            <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[26]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="combinatorial"/>
+            <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[25]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="combinatorial"/>
+            <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[24]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="combinatorial"/>
+            <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[23]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="combinatorial"/>
+            <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[22]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="combinatorial"/>
+            <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[21]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="combinatorial"/>
+            <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[20]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="combinatorial"/>
+            <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[19]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="combinatorial"/>
+            <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[18]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="combinatorial"/>
+            <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[17]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="combinatorial"/>
+            <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[16]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="combinatorial"/>
+            <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="combinatorial"/>
+            <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="combinatorial"/>
+            <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="combinatorial"/>
+            <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="combinatorial"/>
+            <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="combinatorial"/>
+            <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="combinatorial"/>
+            <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="combinatorial"/>
+            <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="combinatorial"/>
+            <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="combinatorial"/>
+            <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="combinatorial"/>
+            <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="combinatorial"/>
+            <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="combinatorial"/>
+            <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="combinatorial"/>
+            <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="combinatorial"/>
+            <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="combinatorial"/>
+            <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="combinatorial"/>
+          </bus>
+          <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_READ_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="combinatorial"/>
+          <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|SDRAM_WRITE_ENABLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="combinatorial"/>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A" order="msb_to_lsb" type="combinatorial">
+            <net data_index="115" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="combinatorial"/>
+            <net data_index="114" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="combinatorial"/>
+            <net data_index="113" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="combinatorial"/>
+            <net data_index="112" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="combinatorial"/>
+            <net data_index="111" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="combinatorial"/>
+            <net data_index="110" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="combinatorial"/>
+            <net data_index="124" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="combinatorial"/>
+            <net data_index="123" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="combinatorial"/>
+            <net data_index="122" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="combinatorial"/>
+            <net data_index="121" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="combinatorial"/>
+            <net data_index="120" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="combinatorial"/>
+            <net data_index="119" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="combinatorial"/>
+            <net data_index="118" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="combinatorial"/>
+            <net data_index="117" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="high" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="combinatorial"/>
+            <net data_index="116" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="combinatorial"/>
+            <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="low" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI" order="msb_to_lsb" type="combinatorial">
+            <net data_index="132" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="combinatorial"/>
+            <net data_index="131" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="combinatorial"/>
+            <net data_index="130" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="combinatorial"/>
+            <net data_index="129" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="combinatorial"/>
+            <net data_index="128" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="combinatorial"/>
+            <net data_index="127" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="combinatorial"/>
+            <net data_index="126" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="combinatorial"/>
+            <net data_index="125" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DI[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="combinatorial"/>
+          </bus>
+          <bus name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO" order="msb_to_lsb" type="combinatorial">
+            <net data_index="140" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[7]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="combinatorial"/>
+            <net data_index="139" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[6]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="combinatorial"/>
+            <net data_index="138" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[5]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="combinatorial"/>
+            <net data_index="137" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[4]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="combinatorial"/>
+            <net data_index="136" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[3]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="combinatorial"/>
+            <net data_index="135" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[2]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="combinatorial"/>
+            <net data_index="134" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[1]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="combinatorial"/>
+            <net data_index="133" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|DO[0]" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="combinatorial"/>
+          </bus>
+          <net data_index="142" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|THROTTLE" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="combinatorial"/>
+          <net data_index="141" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" level-1="dont_care" level-2="dont_care" level-3="dont_care" level-4="dont_care" name="atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|MEMORY_READY" pwr_level-0="dont_care" pwr_level-1="dont_care" pwr_level-2="dont_care" pwr_level-3="dont_care" pwr_level-4="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="combinatorial"/>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger CRC="FA424211" attribute_mem_mode="false" gap_record="true" is_expanded="true" name="trigger: 2014/04/26 08:28:05  #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1024" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="no">
+          <level enabled="no" name="condition1" type="basic">'SDRAM_WE_N' == falling edge
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="no" name="condition2" type="basic">'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[0]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[10]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[11]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[12]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[13]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[14]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[15]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[1]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[2]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[3]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[4]' == high &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[5]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[6]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[7]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[8]' == low &amp;&amp; 'atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|A[9]' == low
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition3" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition4" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <level enabled="yes" name="condition5" type="basic"><power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+          <custom_flow_control>
+            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
+            <flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </flow_expression>
+            <power_up_flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </power_up_flow_expression>
+          </custom_flow_control>
+        </events>
+        <storage_qualifier_events>
+          <transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
+            <pwr_up_transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+      </trigger>
+    </signal_set>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="360"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="64"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="2032"/>
+    </position_info>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <multi attribute="frame size" size="2" value="1625,976"/>
+    <multi attribute="jtag widget size" size="2" value="398,120"/>
+  </global_info>
+</session>
Index: mcctv_5200/makeqsf
===================================================================
--- mcctv_5200/makeqsf	(nonexistent)
+++ mcctv_5200/makeqsf	(revision 288)
@@ -0,0 +1,40 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+print QSF_OUT "\n";
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: mcctv_5200/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mcctv_5200/ntsc_pll.vhd
===================================================================
--- mcctv_5200/ntsc_pll.vhd	(nonexistent)
+++ mcctv_5200/ntsc_pll.vhd	(revision 288)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: ntsc_pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ntsc_pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END ntsc_pll;
+
+
+ARCHITECTURE SYN OF ntsc_pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 63,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=ntsc_pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636364"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcctv_5200/pll_downstream_ntsc.qip
===================================================================
--- mcctv_5200/pll_downstream_ntsc.qip	(nonexistent)
+++ mcctv_5200/pll_downstream_ntsc.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.ppf"]
Index: mcctv_5200/sdram_ctrl_3_ports.cmd
===================================================================
--- mcctv_5200/sdram_ctrl_3_ports.cmd	(nonexistent)
+++ mcctv_5200/sdram_ctrl_3_ports.cmd	(revision 288)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mcctv_5200/sdram_statemachine_mcc.vhdl
===================================================================
--- mcctv_5200/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ mcctv_5200/sdram_statemachine_mcc.vhdl	(revision 288)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: mcctv_5200/svideo/sin_rom.qip
===================================================================
--- mcctv_5200/svideo/sin_rom.qip	(nonexistent)
+++ mcctv_5200/svideo/sin_rom.qip	(revision 288)
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "9.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sin_rom.vhd"]
Index: mcctv_5200/usbpll.ppf
===================================================================
--- mcctv_5200/usbpll.ppf	(nonexistent)
+++ mcctv_5200/usbpll.ppf	(revision 288)
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="usbpll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcctv_5200/zpu_rom.vhdl
===================================================================
--- mcctv_5200/zpu_rom.vhdl	(nonexistent)
+++ mcctv_5200/zpu_rom.vhdl	(revision 288)
@@ -0,0 +1,8226 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(12 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 8191) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b81ca",
+X"d0738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b81d1",
+X"e00c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83c08008",
+X"83c08408",
+X"83c08808",
+X"757581c4",
+X"ff2d5050",
+X"83c08008",
+X"5683c088",
+X"0c83c084",
+X"0c83c080",
+X"0c510483",
+X"c0800883",
+X"c0840883",
+X"c0880875",
+X"7581c393",
+X"2d505083",
+X"c0800856",
+X"83c0880c",
+X"83c0840c",
+X"83c0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"80dea704",
+X"f43d0d7e",
+X"8f3dec11",
+X"56565890",
+X"53f01552",
+X"775193c4",
+X"3f83c080",
+X"0880d638",
+X"78902e09",
+X"810680cd",
+X"3802ab05",
+X"3381d1e8",
+X"0b81d1e8",
+X"33575856",
+X"8c397476",
+X"2e8a3884",
+X"17703356",
+X"5774f338",
+X"76337057",
+X"5574802e",
+X"ac388217",
+X"22708a2b",
+X"903dec05",
+X"56705556",
+X"5696800a",
+X"52775192",
+X"f33f83c0",
+X"80088638",
+X"78752e85",
+X"38805685",
+X"39811733",
+X"567583c0",
+X"800c8e3d",
+X"0d04fc3d",
+X"0d767052",
+X"55b3aa3f",
+X"83c08008",
+X"15ff0554",
+X"73752e8e",
+X"38733353",
+X"72ae2e86",
+X"38ff1454",
+X"ef397752",
+X"811451b2",
+X"c23f83c0",
+X"80083070",
+X"83c08008",
+X"07802583",
+X"c0800c53",
+X"863d0d04",
+X"fc3d0d76",
+X"70525599",
+X"e03f83c0",
+X"80085481",
+X"5383c080",
+X"0880c738",
+X"745199a3",
+X"3f83c080",
+X"080b0b81",
+X"cffc5383",
+X"c0800852",
+X"53ff8f3f",
+X"83c08008",
+X"a5380b0b",
+X"81d08052",
+X"7251fefe",
+X"3f83c080",
+X"0894380b",
+X"0b81d084",
+X"527251fe",
+X"ed3f83c0",
+X"8008802e",
+X"83388154",
+X"73537283",
+X"c0800c86",
+X"3d0d04fd",
+X"3d0d7570",
+X"525498f9",
+X"3f815383",
+X"c0800898",
+X"38735198",
+X"c23f83c0",
+X"b0085283",
+X"c0800851",
+X"feb43f83",
+X"c0800853",
+X"7283c080",
+X"0c853d0d",
+X"04df3d0d",
+X"a43d0870",
+X"525e8ee7",
+X"3f83c080",
+X"0833953d",
+X"56547396",
+X"3881d384",
+X"527451b1",
+X"9c3f9a39",
+X"7d527851",
+X"91e83f84",
+X"e3397d51",
+X"8ecd3f83",
+X"c0800852",
+X"74518dfd",
+X"3f804380",
+X"42804180",
+X"4083c0b8",
+X"0852943d",
+X"70525d94",
+X"d03f83c0",
+X"80085980",
+X"0b83c080",
+X"08555b83",
+X"c080087b",
+X"2e943881",
+X"1b74525b",
+X"97d23f83",
+X"c0800854",
+X"83c08008",
+X"ee38805a",
+X"ff5f7909",
+X"709f2c7b",
+X"065b547a",
+X"7a248438",
+X"ff1b5af6",
+X"1a700970",
+X"9f2c7206",
+X"7bff125a",
+X"5a525555",
+X"80752595",
+X"38765197",
+X"973f83c0",
+X"800876ff",
+X"18585557",
+X"738024ed",
+X"38747f2e",
+X"873880c3",
+X"853f745f",
+X"78ff1b70",
+X"585d5880",
+X"7a259538",
+X"775196ec",
+X"3f83c080",
+X"0876ff18",
+X"58555873",
+X"8024ed38",
+X"800b83c7",
+X"cc0c800b",
+X"83c8900c",
+X"0b0b81d0",
+X"88518bbe",
+X"3f81800b",
+X"83c8900c",
+X"0b0b81d0",
+X"90518bae",
+X"3fa80b83",
+X"c7cc0c76",
+X"802e80e8",
+X"3883c7cc",
+X"08777932",
+X"70307072",
+X"07802570",
+X"872b83c8",
+X"900c5156",
+X"78535656",
+X"969f3f83",
+X"c0800880",
+X"2e8a380b",
+X"0b81d098",
+X"518af33f",
+X"765195df",
+X"3f83c080",
+X"08520b0b",
+X"81d1ac51",
+X"8ae03f76",
+X"5195e53f",
+X"83c08008",
+X"83c7cc08",
+X"55577574",
+X"258638a8",
+X"1656f739",
+X"7583c7cc",
+X"0c86f076",
+X"24ff9438",
+X"87980b83",
+X"c7cc0c77",
+X"802eb738",
+X"7751959b",
+X"3f83c080",
+X"08785255",
+X"95bb3f0b",
+X"0b81d0a0",
+X"5483c080",
+X"088f3887",
+X"39807634",
+X"81d8390b",
+X"0b81d09c",
+X"54745373",
+X"520b0b81",
+X"cfec5189",
+X"f93f8054",
+X"0b0b81cf",
+X"f45189ee",
+X"3f811454",
+X"73a82e09",
+X"8106ed38",
+X"868da051",
+X"befb3f80",
+X"52903d70",
+X"525780d2",
+X"943f8352",
+X"765180d2",
+X"8c3f6281",
+X"91386180",
+X"2e80fd38",
+X"7b5473ff",
+X"2e963878",
+X"802e818c",
+X"38785194",
+X"b73f83c0",
+X"8008ff15",
+X"5559e739",
+X"78802e80",
+X"f7387851",
+X"94b33f83",
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+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: mcctv_5200/svideo/sin_rom.vhd
===================================================================
--- mcctv_5200/svideo/sin_rom.vhd	(nonexistent)
+++ mcctv_5200/svideo/sin_rom.vhd	(revision 288)
@@ -0,0 +1,266 @@
+-- megafunction wizard: %ROM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: sin_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.0 Build 132 02/25/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sin_rom IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		enable		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END sin_rom;
+
+
+ARCHITECTURE SYN OF sin_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3_bv	: BIT_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clocken0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2    <= '0';
+	sub_wire3_bv(7 DOWNTO 0) <= "00000000";
+	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		init_file => "sin_rom.mif",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		numwords_b => 2048,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 11,
+		widthad_b => 11,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		clocken0 => enable,
+		wren_a => sub_wire2,
+		wren_b => sub_wire2,
+		clock0 => clock,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => sub_wire3,
+		data_b => sub_wire3,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "sin_rom.mif"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "sin_rom.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
+-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC enable
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 GND 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sin_rom_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mcctv_5200/usbpll.qip
===================================================================
--- mcctv_5200/usbpll.qip	(nonexistent)
+++ mcctv_5200/usbpll.qip	(revision 288)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "usbpll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "usbpll.ppf"]
