Index: papilioduo/atari800core_papilioduo.vhd
===================================================================
--- papilioduo/atari800core_papilioduo.vhd	(revision 329)
+++ papilioduo/atari800core_papilioduo.vhd	(revision 330)
@@ -196,8 +196,6 @@
 	signal CLK : std_logic;
 	signal CLK_SDRAM : std_logic;
 
-	signal SYSTEM_RESET_REQUEST: std_logic;
-
 	-- pokey keyboard
 	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
 	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
@@ -269,6 +267,7 @@
 	signal ram_addr : std_logic_vector(22 downto 0);
 	signal ram_do : std_logic_vector(31 downto 0);
 	signal ram_di : std_logic_vector(31 downto 0);
+	signal ram_width32bit : std_logic;
 BEGIN 
 
 ARDUINO_RESET <= '0'; -- hold arduino in reset for now
@@ -399,13 +398,16 @@
 		internal_rom => internal_rom,
 		internal_ram => internal_ram,
 		video_bits => 8,
-		palette => palette_from_scandouble(scandouble)
+		palette => palette_from_scandouble(scandouble),
+		low_memory => 2,
+                STEREO                     => 0,
+                COVOX                      => 0
 	)
 	PORT MAP
 	(
 		CLK => CLK,
 		--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
-		RESET_N => RESET_N,
+		RESET_N => RESET_N and not(RESET_ATARI),
 
 		VIDEO_VS => VIDEO_VS,
 		VIDEO_HS => VIDEO_HS,
@@ -442,7 +444,7 @@
 		SDRAM_ADDR => ram_addr,
 		SDRAM_DO => ram_do,
 		SDRAM_DI => ram_di,
-		SDRAM_32BIT_WRITE_ENABLE => open,
+		SDRAM_32BIT_WRITE_ENABLE => ram_width32bit,
 		SDRAM_16BIT_WRITE_ENABLE => open,
 		SDRAM_8BIT_WRITE_ENABLE => open,
 		SDRAM_REFRESH => open,
@@ -457,21 +459,21 @@
 		MEMORY_READY_DMA => dma_memory_ready,
 		DMA_MEMORY_DATA => dma_memory_data, 
 
---   		RAM_SELECT => ram_select,
---    		ROM_SELECT => rom_select,
---		PAL => PAL,
---		HALT => pause_atari,
---		THROTTLE_COUNT_6502 => speed_6502,
---		emulated_cartridge_select => emulated_cartridge_select,
+   		RAM_SELECT => ram_select,
+    		ROM_SELECT => rom_select,
+		PAL => PAL,
+		HALT => pause_atari,
+		THROTTLE_COUNT_6502 => speed_6502,
+		emulated_cartridge_select => emulated_cartridge_select,
 --		freezer_enable => freezer_enable,
 --		freezer_activate => freezer_activate
 
-   		RAM_SELECT => (others=>'0'),
-    		ROM_SELECT => "000001",
-		PAL => PAL,
-		HALT => '0',
-		THROTTLE_COUNT_6502 => "000001",
-		emulated_cartridge_select => (others=>'0'),
+--   		RAM_SELECT => (others=>'0'),
+--    		ROM_SELECT => "000001",
+--		PAL => PAL,
+--		HALT => '0',
+--		THROTTLE_COUNT_6502 => "000001",
+--		emulated_cartridge_select => (others=>'0'),
 		freezer_enable => '0',
 		freezer_activate => '0'
 	);
@@ -504,7 +506,7 @@
 		        RESET_N => reset_n,
 			
 			VGA => '1',
-			COMPOSITE_ON_HSYNC => '0', -- TODO
+			COMPOSITE_ON_HSYNC => '1', -- TODO
 
 			colour_enable => half_scandouble_enable_reg,
 			doubled_enable => '1',
@@ -530,7 +532,6 @@
 	(
 		platform => 1,
 		spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
-		memory => 8192,
 		usb => 0
 	)
 	PORT MAP
@@ -537,7 +538,7 @@
 	(
 		-- standard...
 		CLK => CLK,
-		RESET_N => '0', -- RESET_N and sdram_rdy, TODO, allow ZPU to run!
+		RESET_N => RESET_N,
 
 		-- dma bus master (with many waitstates...)
 		ZPU_ADDR_FETCH => dma_addr_fetch,
@@ -610,7 +611,7 @@
 	PORT MAP
 	( 
 		ADDRESS => ram_addr(20 downto 0),
-		DIN => ram_di(7 downto 0),
+		DIN => ram_di,
 		WREN => ram_write_enable,
 		
 		clk => clk,
@@ -617,6 +618,8 @@
 		reset_n => reset_n,
 		
 		request => ram_request,
+
+		width32bit => ram_width32bit,
 		
 		-- SRAM interface
 		SRAM_ADDR => sram_addr,
@@ -627,9 +630,8 @@
 		SRAM_DQ => sram_data,
 		
 		-- Provide data to system
-		DOUT => ram_do(7 downto 0),
+		DOUT => ram_do,
 		complete => ram_request_complete
 	);
-	ram_do(31 downto 8) <= (others=>'0');
 
 END vhdl;
Index: papilioduo/sram.vhdl
===================================================================
--- papilioduo/sram.vhdl	(revision 329)
+++ papilioduo/sram.vhdl	(revision 330)
@@ -12,7 +12,7 @@
 PORT 
 ( 
 	ADDRESS : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
-	DIN : IN STD_LOGIC_vector(7 downto 0);
+	DIN : IN STD_LOGIC_vector(31 downto 0);
 	WREN : IN STD_LOGIC;
 	
 	clk : in std_logic;
@@ -19,6 +19,8 @@
 	reset_n : in std_logic;
 	
 	request : in std_logic;
+
+	width32bit : in std_logic;	-- 32-bit read/write
 	
 	-- SRAM interface
 	SRAM_ADDR: OUT STD_LOGIC_VECTOR(20 downto 0);
@@ -29,14 +31,12 @@
 	SRAM_DQ: INOUT STD_LOGIC_VECTOR(7 downto 0);
 	
 	-- Provide data to system
-	DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	DOUT : OUT STD_LOGIC_VECTOR(31 downto 0);
 	complete : out std_logic
 );
 
 END sram;
 
--- TODO, implement 32-bit accesses in two cycles
-
 -- first cycle, capture inputs
 -- second cycle, sram access
 ARCHITECTURE slow OF sram IS
@@ -45,12 +45,34 @@
 	
 	signal we_n_next : std_logic;
 	signal we_n_reg : std_logic;	
+
+	signal address_next : std_logic_vector(20 downto 0);
+	signal address_reg : std_logic_vector(20 downto 0);
 	
-	signal data_next : std_logic_vector(7 downto 0);
-	signal data_reg : std_logic_vector(7 downto 0);
+	signal data_write_next : std_logic_vector(31 downto 0);
+	signal data_write_reg : std_logic_vector(31 downto 0);
+
+	signal data_read_next : std_logic_vector(31 downto 0);
+	signal data_read_reg : std_logic_vector(31 downto 0);
 	
-	signal request_next : std_logic;
-	signal request_reg : std_logic;
+	signal complete_next : std_logic;
+	signal complete_reg : std_logic;
+
+	constant state_idle : std_logic_vector(3 downto 0) := "0000";
+	constant state_read_byte1   : std_logic_vector(3 downto 0) := "0001";
+	constant state_read_byte2   : std_logic_vector(3 downto 0) := "0010";
+	constant state_read_byte3   : std_logic_vector(3 downto 0) := "0011";
+	constant state_read_byte4   : std_logic_vector(3 downto 0) := "0100";
+	constant state_write_byte1a : std_logic_vector(3 downto 0) := "0101";
+	constant state_write_byte1b : std_logic_vector(3 downto 0) := "0110";
+	constant state_write_byte2a : std_logic_vector(3 downto 0) := "0111";
+	constant state_write_byte2b : std_logic_vector(3 downto 0) := "1000";
+	constant state_write_byte3a : std_logic_vector(3 downto 0) := "1001";
+	constant state_write_byte3b : std_logic_vector(3 downto 0) := "1010";
+	constant state_write_byte4a : std_logic_vector(3 downto 0) := "1011";
+	constant state_read_byte4b  : std_logic_vector(3 downto 0) := "1101";
+	signal state_next : std_logic_vector(3 downto 0);
+	signal state_reg : std_logic_vector(3 downto 0);
 BEGIN
 	-- registers
 	process(clk,reset_n)
@@ -58,43 +80,125 @@
 		if (reset_n = '0') then
 			oe_n_reg <= '1';
 			we_n_reg <= '1';
-			data_reg <= (others=>'0');
-			request_reg <= '0';
+			data_write_reg <= (others=>'0');
+			data_read_reg <= (others=>'0');
+			complete_reg <= '0';
+			state_reg <= state_idle;
+			address_reg <= (others=>'0');
 		elsif (clk'event and clk='1') then
 			oe_n_reg <= oe_n_next;
 			we_n_reg <= we_n_next;
-			data_reg <= data_next;
-			request_reg <= request_next;
+			data_write_reg <= data_write_next;
+			data_read_reg <= data_read_next;
+			complete_reg <= complete_next;
+			state_reg <= state_next;
+			address_reg <= address_next;
 		end if;
 	end process;
 
 	-- next state
-	process(din,wren,request,request_reg)
+	process(din,wren,request,state_reg,width32bit,sram_dq,data_read_reg,data_write_reg,address_reg,address)
 	begin		
-		data_next <= din;
-		request_next <= '0';
+		state_next <= state_reg;
+		data_write_next <= data_write_reg;
+		data_read_next <= data_read_reg;
+		complete_next <= '0';
 		
 		oe_n_next <= '0';
 		we_n_next <= '1';
+		address_next <= address_reg;
 		
-		if (request = '1') then
 			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
-			oe_n_next <= wren;
-			we_n_next <= not(wren);		
-			request_next <= '1';
-		end if;
+
+		case state_reg is
+		when state_idle =>
+			if (request = '1') then
+				data_write_next <= din;
+				address_next <= address;
+				if (width32bit = '1') then
+					if (wren = '1') then
+						address_next(1 downto 0) <= "00";
+						state_next <= state_write_byte1a;
+					else
+						address_next(1 downto 0) <= "11";
+						state_next <= state_read_byte1;
+					end if;
+				else
+					if (wren = '1') then
+						state_next <= state_write_byte4a;
+					else
+						state_next <= state_read_byte4;
+					end if;
+				end if;
+			end if;
+
+		when state_read_byte1 =>
+			address_next(1 downto 0) <= "10";
+			data_read_next(31 downto 24) <= SRAM_DQ;
+			state_next <= state_read_byte2;
+		when state_read_byte2 =>
+			address_next(1 downto 0) <= "01";
+			data_read_next(23 downto 16) <= SRAM_DQ;
+			state_next <= state_read_byte3;
+		when state_read_byte3 =>
+			address_next(1 downto 0) <= "00";
+			data_read_next(15 downto 8) <= SRAM_DQ;
+			state_next <= state_read_byte4;
+		when state_read_byte4 =>
+			data_read_next(7 downto 0) <= SRAM_DQ;
+			state_next <= state_idle;
+			complete_next <= '1';
+
+		when state_write_byte1a =>
+			state_next <= state_write_byte1b;
+			we_n_next <= '0';
+			oe_n_next <= '1';
+		when state_write_byte1b =>
+			address_next(1 downto 0) <= "01";
+			data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
+			state_next <= state_write_byte2a;
+			we_n_next <= '1';
+			oe_n_next <= '1';
+		when state_write_byte2a =>
+			state_next <= state_write_byte2b;
+			we_n_next <= '0';
+			oe_n_next <= '1';
+		when state_write_byte2b =>
+			address_next(1 downto 0) <= "10";
+			data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
+			state_next <= state_write_byte3a;
+			we_n_next <= '1';
+			oe_n_next <= '1';
+		when state_write_byte3a =>
+			state_next <= state_write_byte3b;
+			we_n_next <= '0';
+			oe_n_next <= '1';
+		when state_write_byte3b =>
+			address_next(1 downto 0) <= "11";
+			data_write_next(23 downto 0) <= data_write_reg(31 downto 8);
+			state_next <= state_write_byte4a;
+			we_n_next <= '1';
+			oe_n_next <= '1';
+		when state_write_byte4a =>
+			we_n_next <= '0';
+			oe_n_next <= '1';
+			complete_next <= '1';
+			state_next <= state_idle;
+		when others =>
+			state_next <= state_idle;
+		end case;
 	end process;
 	
 	-- output
-	SRAM_ADDR <= address;
 	SRAM_CE_N <= '0';
 	SRAM_OE_N <= oe_n_reg;
 	SRAM_WE_N <= we_n_reg;
-	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+	SRAM_DQ <= data_write_reg(7 downto 0) when we_n_reg = '0' else (others=>'Z');
+	SRAM_ADDR <= address_reg;
 
-	DOUT <= SRAM_DQ;
+	DOUT <= data_read_next;
 			
-	complete <= request_reg;		
+	complete <= complete_reg;		
 		
 	--GPIO <= (others=>'0');
 END slow;
