Index: eclaireXL/atari800core_eclaireXL.qpf
===================================================================
--- eclaireXL/atari800core_eclaireXL.qpf	(nonexistent)
+++ eclaireXL/atari800core_eclaireXL.qpf	(revision 381)
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 20:32:21  July 11, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "20:32:21  July 11, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core_eclaireXL"
Index: eclaireXL/atari800core_eclaireXL.qsf
===================================================================
--- eclaireXL/atari800core_eclaireXL.qsf	(nonexistent)
+++ eclaireXL/atari800core_eclaireXL.qsf	(revision 381)
@@ -0,0 +1,259 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 20:32:21  July 11, 2015
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_eclaireXL_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CEBA2F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_eclaireXL
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:21  JULY 11, 2015"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name VHDL_FILE atari800core_eclaireXL.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE gpiov2.vhd
+set_global_assignment -name VHDL_FILE atari800core_de1.vhd
+set_global_assignment -name QIP_FILE pll_pal.qip
+set_global_assignment -name QIP_FILE pll_ntsc.qip
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+set_location_assignment PIN_H16 -to CLOCK_5
+
+set_location_assignment PIN_A5 -to VGA_R[0]
+set_location_assignment PIN_B5 -to VGA_R[1]
+set_location_assignment PIN_B6 -to VGA_R[2]
+set_location_assignment PIN_D6 -to VGA_R[3]
+set_location_assignment PIN_C6 -to VGA_R[4]
+set_location_assignment PIN_A7 -to VGA_R[5]
+set_location_assignment PIN_B7 -to VGA_R[6]
+set_location_assignment PIN_E7 -to VGA_R[7]
+set_location_assignment PIN_D7 -to VGA_G[0]
+set_location_assignment PIN_F7 -to VGA_G[1]
+set_location_assignment PIN_A8 -to VGA_G[2]
+set_location_assignment PIN_G8 -to VGA_G[3]
+set_location_assignment PIN_C8 -to VGA_G[4]
+set_location_assignment PIN_H8 -to VGA_G[5]
+set_location_assignment PIN_A9 -to VGA_G[6]
+set_location_assignment PIN_D9 -to VGA_G[7]
+set_location_assignment PIN_C9 -to VGA_BLANK_N
+set_location_assignment PIN_E9 -to VGA_B[0]
+set_location_assignment PIN_F9 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_E10 -to VGA_B[4]
+set_location_assignment PIN_F10 -to VGA_B[5]
+set_location_assignment PIN_G10 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_G11 -to VGA_CLK
+set_location_assignment PIN_C11 -to VGA_HS
+set_location_assignment PIN_H11 -to VGA_VS
+set_location_assignment PIN_J11 -to AUDIO_LEFT
+set_location_assignment PIN_A12 -to AUDIO_RIGHT
+set_location_assignment PIN_B12 -to GPIOC[17]
+set_location_assignment PIN_D12 -to GPIOC[16]
+set_location_assignment PIN_E12 -to GPIOC[15]
+set_location_assignment PIN_F12 -to GPIOC[14]
+set_location_assignment PIN_A13 -to GPIOC[13]
+set_location_assignment PIN_B13 -to GPIOC[12]
+set_location_assignment PIN_D13 -to GPIOC[11]
+set_location_assignment PIN_C13 -to GPIOC[10]
+set_location_assignment PIN_F13 -to GPIOC[9]
+set_location_assignment PIN_G13 -to GPIOC[8]
+set_location_assignment PIN_A14 -to GPIOC[7]
+set_location_assignment PIN_E14 -to GPIOC[6]
+set_location_assignment PIN_F14 -to GPIOC[5]
+set_location_assignment PIN_H14 -to GPIOC[4]
+set_location_assignment PIN_A15 -to GPIOC[3]
+set_location_assignment PIN_B15 -to GPIOC[2]
+set_location_assignment PIN_E15 -to GPIOC[1]
+set_location_assignment PIN_C15 -to GPIOC[0]
+set_location_assignment PIN_F15 -to GPIOA[0]
+set_location_assignment PIN_G15 -to GPIOB[0]
+set_location_assignment PIN_B16 -to GPIOA[1]
+set_location_assignment PIN_E16 -to GPIOB[1]
+set_location_assignment PIN_C16 -to GPIOA[2]
+set_location_assignment PIN_D17 -to GPIOB[2]
+set_location_assignment PIN_G17 -to GPIOA[3]
+set_location_assignment PIN_G18 -to GPIOB[3]
+set_location_assignment PIN_G16 -to GPIOA[4]
+set_location_assignment PIN_H18 -to GPIOB[4]
+set_location_assignment PIN_J18 -to GPIOA[5]
+set_location_assignment PIN_J19 -to GPIOB[5]
+set_location_assignment PIN_J17 -to GPIOA[6]
+set_location_assignment PIN_K22 -to GPIOB[6]
+set_location_assignment PIN_K21 -to GPIOA[7]
+set_location_assignment PIN_K19 -to GPIOB[7]
+set_location_assignment PIN_K20 -to GPIOA[8]
+set_location_assignment PIN_K17 -to GPIOB[8]
+set_location_assignment PIN_K16 -to GPIOA[9]
+set_location_assignment PIN_L22 -to GPIOB[9]
+set_location_assignment PIN_L19 -to GPIOA[10]
+set_location_assignment PIN_L18 -to GPIOB[10]
+set_location_assignment PIN_L17 -to GPIOA[11]
+set_location_assignment PIN_M22 -to GPIOB[11]
+set_location_assignment PIN_M21 -to GPIOA[12]
+set_location_assignment PIN_M18 -to GPIOB[12]
+set_location_assignment PIN_M20 -to GPIOA[13]
+set_location_assignment PIN_M16 -to GPIOB[13]
+set_location_assignment PIN_N21 -to GPIOA[14]
+set_location_assignment PIN_N19 -to GPIOB[14]
+set_location_assignment PIN_N20 -to GPIOA[15]
+set_location_assignment PIN_N16 -to GPIOB[15]
+set_location_assignment PIN_P22 -to GPIOA[16]
+set_location_assignment PIN_P18 -to GPIOB[16]
+set_location_assignment PIN_P19 -to GPIOA[17]
+set_location_assignment PIN_P17 -to GPIOB[17]
+set_location_assignment PIN_P16 -to GPIOA[18]
+set_location_assignment PIN_R22 -to GPIOB[18]
+set_location_assignment PIN_R21 -to GPIOA[19]
+set_location_assignment PIN_R17 -to GPIOB[19]
+set_location_assignment PIN_R16 -to GPIOA[20]
+set_location_assignment PIN_T22 -to GPIOB[20]
+set_location_assignment PIN_T19 -to GPIOA[21]
+set_location_assignment PIN_T20 -to GPIOB[21]
+set_location_assignment PIN_T18 -to GPIOA[22]
+set_location_assignment PIN_T17 -to GPIOB[22]
+set_location_assignment PIN_U22 -to GPIOA[23]
+set_location_assignment PIN_U21 -to GPIOB[23]
+set_location_assignment PIN_U20 -to GPIOA[24]
+set_location_assignment PIN_V21 -to GPIOB[24]
+set_location_assignment PIN_V19 -to GPIOA[25]
+set_location_assignment PIN_V20 -to GPIOB[25]
+set_location_assignment PIN_W22 -to GPIOA[26]
+set_location_assignment PIN_W21 -to GPIOB[26]
+set_location_assignment PIN_Y22 -to GPIOA[27]
+set_location_assignment PIN_Y21 -to GPIOB[27]
+set_location_assignment PIN_AA22 -to GPIOA[28]
+set_location_assignment PIN_AB22 -to GPIOB[28]
+set_location_assignment PIN_AB21 -to GPIOA[29]
+set_location_assignment PIN_AB20 -to GPIOB[29]
+set_location_assignment PIN_AA20 -to GPIOA[30]
+set_location_assignment PIN_Y20 -to GPIOB[30]
+set_location_assignment PIN_AA19 -to GPIOA[31]
+set_location_assignment PIN_W19 -to GPIOB[31]
+set_location_assignment PIN_Y19 -to GPIOA[32]
+set_location_assignment PIN_AB18 -to GPIOB[32]
+set_location_assignment PIN_AA18 -to GPIOA[33]
+set_location_assignment PIN_V18 -to GPIOB[33]
+set_location_assignment PIN_AB17 -to GPIOA[34]
+set_location_assignment PIN_AA17 -to GPIOB[34]
+set_location_assignment PIN_U17 -to GPIOA[35]
+set_location_assignment PIN_Y17 -to GPIOB[35]
+set_location_assignment PIN_Y16 -to GPIOC[35]
+set_location_assignment PIN_V16 -to GPIOC[34]
+set_location_assignment PIN_W16 -to GPIOC[33]
+set_location_assignment PIN_U16 -to GPIOC[32]
+set_location_assignment PIN_AB15 -to GPIOC[31]
+set_location_assignment PIN_AA15 -to GPIOC[30]
+set_location_assignment PIN_V15 -to GPIOC[29]
+set_location_assignment PIN_Y15 -to GPIOC[28]
+set_location_assignment PIN_U15 -to GPIOC[27]
+set_location_assignment PIN_T15 -to GPIOC[26]
+set_location_assignment PIN_AA14 -to GPIOC[25]
+set_location_assignment PIN_V14 -to GPIOC[24]
+set_location_assignment PIN_Y14 -to GPIOC[23]
+set_location_assignment PIN_T14 -to GPIOC[22]
+set_location_assignment PIN_R14 -to GPIOC[21]
+set_location_assignment PIN_AB13 -to GPIOC[20]
+set_location_assignment PIN_AA13 -to GPIOC[19]
+set_location_assignment PIN_V13 -to GPIOC[18]
+set_location_assignment PIN_U13 -to SD_WRITEPROTECT
+set_location_assignment PIN_T13 -to SD_DETECT
+set_location_assignment PIN_AB12 -to SD_DAT1
+set_location_assignment PIN_AA12 -to SD_DAT0
+set_location_assignment PIN_U12 -to SD_CLK
+set_location_assignment PIN_T12 -to SD_CMD
+set_location_assignment PIN_R12 -to SD_DAT3
+set_location_assignment PIN_AB11 -to SD_DAT2
+set_location_assignment PIN_U11 -to PS2CLK
+set_location_assignment PIN_Y11 -to PS2DAT
+set_location_assignment PIN_R11 -to USB2DM
+set_location_assignment PIN_AB10 -to USB2DP
+set_location_assignment PIN_AA10 -to USB1DM
+set_location_assignment PIN_V10 -to USB1DP
+set_location_assignment PIN_Y10 -to DRAM_ADDR[4]
+set_location_assignment PIN_U10 -to DRAM_ADDR[5]
+set_location_assignment PIN_T10 -to DRAM_ADDR[6]
+set_location_assignment PIN_AA9 -to DRAM_ADDR[7]
+set_location_assignment PIN_W9 -to DRAM_ADDR[8]
+set_location_assignment PIN_Y9 -to DRAM_ADDR[9]
+set_location_assignment PIN_V9 -to DRAM_ADDR[11]
+set_location_assignment PIN_T9 -to DRAM_ADDR[12]
+set_location_assignment PIN_AB8 -to DRAM_CKE
+set_location_assignment PIN_AA8 -to DRAM_CLK
+set_location_assignment PIN_U8 -to DRAM_UDQM
+set_location_assignment PIN_W8 -to DRAM_DQ[8]
+set_location_assignment PIN_T8 -to DRAM_DQ[9]
+set_location_assignment PIN_AB7 -to DRAM_DQ[10]
+set_location_assignment PIN_AA7 -to DRAM_DQ[11]
+set_location_assignment PIN_U7 -to DRAM_DQ[12]
+set_location_assignment PIN_AB6 -to DRAM_DQ[13]
+set_location_assignment PIN_V6 -to DRAM_DQ[14]
+set_location_assignment PIN_AB5 -to DRAM_DQ[15]
+set_location_assignment PIN_U6 -to DRAM_ADDR[3]
+set_location_assignment PIN_T7 -to DRAM_ADDR[2]
+set_location_assignment PIN_R5 -to DRAM_ADDR[1]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_location_assignment PIN_R7 -to DRAM_ADDR[10]
+set_location_assignment PIN_P6 -to DRAM_BA_1
+set_location_assignment PIN_P7 -to DRAM_BA_0
+set_location_assignment PIN_P8 -to DRAM_CS_N
+set_location_assignment PIN_N6 -to DRAM_RAS_N
+set_location_assignment PIN_N8 -to DRAM_CAS_N
+set_location_assignment PIN_N9 -to DRAM_WE_N
+set_location_assignment PIN_M6 -to DRAM_LDQM
+set_location_assignment PIN_M7 -to DRAM_DQ[7]
+set_location_assignment PIN_M8 -to DRAM_DQ[6]
+set_location_assignment PIN_L7 -to DRAM_DQ[5]
+set_location_assignment PIN_L8 -to DRAM_DQ[4]
+set_location_assignment PIN_K7 -to DRAM_DQ[0]
+set_location_assignment PIN_K9 -to DRAM_DQ[1]
+set_location_assignment PIN_J7 -to DRAM_DQ[2]
+set_location_assignment PIN_J8 -to DRAM_DQ[3]
+set_location_assignment PIN_H6 -to ADC_SDA
+set_location_assignment PIN_G6 -to ADC_SCL
Index: eclaireXL/atari800core_eclaireXL.qws
===================================================================
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Property changes on: eclaireXL/atari800core_eclaireXL.qws
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+application/octet-stream
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Index: eclaireXL/atari800core_eclaireXL.sdc
===================================================================
--- eclaireXL/atari800core_eclaireXL.sdc	(nonexistent)
+++ eclaireXL/atari800core_eclaireXL.sdc	(revision 381)
@@ -0,0 +1,3 @@
+create_clock -period 50MHz [get_ports CLOCK_5]
+derive_pll_clocks
+
Index: eclaireXL/atari800core_eclaireXL.vhd
===================================================================
--- eclaireXL/atari800core_eclaireXL.vhd	(nonexistent)
+++ eclaireXL/atari800core_eclaireXL.vhd	(revision 381)
@@ -0,0 +1,776 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_eclaireXL IS 
+	GENERIC
+	(
+		TV : integer; -- 1 = PAL, 0=NTSC
+		GPIO : integer  -- 1 = OLD GPIO LAYOUT, 2=NEW GPIO LAYOUT (WIP)
+	);
+	PORT
+	(
+		CLOCK_5 :  IN  STD_LOGIC;
+
+		PS2CLK :  IN  STD_LOGIC;
+		PS2DAT :  IN  STD_LOGIC;
+
+		GPIOA :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIOB :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIOC:  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_WRITEPROTECT : IN STD_LOGIC;
+		SD_DETECT : IN STD_LOGIC;
+		--SD_DAT1 : IN STD_LOGIC;
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC;
+		--SD_DAT2 : IN STD_LOGIC;
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+		VGA_BLANK_N : OUT STD_LOGIC;
+		VGA_CLK : OUT STD_LOGIC;
+		
+		AUDIO_LEFT : OUT STD_LOGIC;
+		AUDIO_RIGHT : OUT STD_LOGIC;
+
+		USB2DM: INOUT STD_LOGIC;
+		USB2DP: INOUT STD_LOGIC;
+		USB1DM: INOUT STD_LOGIC;
+		USB1DP: INOUT STD_LOGIC;
+		
+		ADC_SDA: INOUT STD_LOGIC;
+		ADC_SCL: INOUT STD_LOGIC
+	);
+END atari800core_eclaireXL;
+
+ARCHITECTURE vhdl OF atari800core_eclaireXL IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+	-- SYSTEM
+	SIGNAL CLK : STD_LOGIC;
+	SIGNAL CLK_SDRAM : STD_LOGIC;
+	SIGNAL RESET_N : STD_LOGIC;
+	signal SDRAM_RESET_N : std_logic;
+	SIGNAL PLL_LOCKED : STD_LOGIC;
+
+	-- PIA
+	SIGNAL	CA1_IN :  STD_LOGIC;
+	SIGNAL	CB1_IN:  STD_LOGIC;
+	SIGNAL	CA2_OUT :  STD_LOGIC;
+	SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+	SIGNAL	CB2_OUT :  STD_LOGIC;
+	SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+	SIGNAL	CA2_IN:  STD_LOGIC;
+	SIGNAL	CB2_IN:  STD_LOGIC;
+	SIGNAL	PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	--SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- GTIA
+	signal GTIA_TRIG : std_logic_vector(3 downto 0);
+	
+	-- ANTIC
+	signal ANTIC_LIGHTPEN : std_logic;
+	
+	-- CARTRIDGE ACCESS
+	SIGNAL	CART_RD4 :  STD_LOGIC;
+	SIGNAL	CART_RD5 :  STD_LOGIC;
+	SIGNAL	CART_S4_n :  STD_LOGIC;
+	SIGNAL	CART_S5_n :  STD_LOGIC;
+	SIGNAL	CART_CCTL_n :  STD_LOGIC;
+	
+	-- PBI
+	SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
+	SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
+	
+	-- INTERNAL ROM/RAM
+	SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+	SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+	SIGNAL	RAM_REQUEST :  STD_LOGIC;
+	SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+	SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+	
+	SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+	SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	ROM_REQUEST :  STD_LOGIC;
+	SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+
+	-- SDRAM
+	signal SDRAM_REQUEST : std_logic;
+	signal SDRAM_REQUEST_COMPLETE : std_logic;
+	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal SDRAM_WRITE_ENABLE : std_logic;
+	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	signal SDRAM_REFRESH : std_logic;
+	
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL CONSOL_START : std_logic;
+	SIGNAL CONSOL_SELECT : std_logic;
+	SIGNAL CONSOL_OPTION : std_logic;
+	
+	-- SIO
+	SIGNAL SIO_RXD : std_logic;
+	SIGNAL SIO_COMMAND : std_logic;
+	SIGNAL SIO_TXD : std_logic;
+
+	SIGNAL GPIO_SIO_RXD : std_logic;
+
+	SIGNAL SIO_CLOCKOUT : std_logic;
+	SIGNAL SIO_CLOCKIN : std_logic;
+
+	-- VIDEO
+	signal VGA_VS_RAW : std_logic;
+	signal VGA_HS_RAW : std_logic;
+	signal VGA_CS_RAW : std_logic;
+	signal VGA_BLANK : std_logic;
+
+	-- AUDIO
+	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+	signal emulated_cartridge_select: std_logic_vector(5 downto 0);
+
+	-- GPIO
+	signal GPIOA_DIR_OUT : std_logic_vector(35 downto 0);
+	signal GPIOA_OUT : std_logic_vector(35 downto 0);
+	signal GPIOB_DIR_OUT : std_logic_vector(35 downto 0);
+	signal GPIOB_OUT : std_logic_vector(35 downto 0);
+	signal TRIGGERS : std_logic_vector(3 downto 0);
+
+	signal POT_RESET : std_logic;
+	signal POT_IN : std_logic_vector(7 downto 0);
+
+	signal GPIO_KEYBOARD_RESPONSE  : std_logic_vector(1 downto 0);
+	signal PS2_KEYBOARD_RESPONSE  : std_logic_vector(1 downto 0);
+
+	signal PBI_WRITE_ENABLE : std_logic;
+	signal PBI_ADDRESS : std_logic_vector(15 downto 0);
+
+	signal cart_request : std_logic;
+	signal cart_request_complete : std_logic;
+	signal cart_data : std_logic_vector(7 downto 0);
+
+	signal pbi_addr : std_logic_vector(15 downto 0);
+
+	signal enable_179_early : std_logic;
+
+	-- scandoubler
+	signal half_scandouble_enable_reg : std_logic;
+	signal half_scandouble_enable_next : std_logic;
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+	signal freezer_enable : std_logic;
+	signal freezer_activate: std_logic;
+
+	signal freezer_state: std_logic_vector(2 downto 0);
+
+	signal pbi_enable: std_logic;
+
+	signal pal : std_logic;
+
+	signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
+	signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
+BEGIN 
+
+	-- TODO
+	pbi_enable <= '1'; --SW(4);
+	PAL <= '1';-- SW(8);
+
+-- ANYTHING NOT CONNECTED...
+--GPIOA(0) <= 'Z';
+--GPIOA(35 downto 2) <= (others=>'Z');
+--GPIOB(35 downto 0) <= (others=>'Z');
+
+sdram_adaptor : entity work.sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N =>  RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => PBI_WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => PBI_WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => PBI_WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => PBI_WRITE_DATA(31 downto 0),
+		 SDRAM_DQ => DRAM_DQ,
+		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR(11 downto 0),
+		 reset_client_n => SDRAM_RESET_N
+		 );
+
+-- PIA mapping
+-- emulate pull-up on command line
+SIO_COMMAND <= CB2_OUT when CB2_DIR_OUT='1' else '1';
+-- SIO_COMMAND <= CB2_OUT;
+--PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+--PORTA_IN <= (not (porta_dir_out)) or (porta_dir_out and porta_out);
+PORTB_IN <= PORTB_OUT;
+
+-- GTIA triggers
+--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
+GTIA_TRIG <= "11"&TRIGGERS(1 downto 0);
+
+-- Cartridge not inserted
+--CART_RD4 <= '0';
+--CART_RD5 <= '0';
+
+-- Internal rom/ram
+internalromram1 : entity work.internalromram
+	GENERIC MAP
+	(
+		internal_rom => 0,
+		internal_ram => 0
+	)
+	PORT MAP (
+ 		clock   => CLK,
+		reset_n => RESET_N,
+
+		ROM_ADDR => ROM_ADDR,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_DATA => ROM_DO,
+		
+		RAM_ADDR => RAM_ADDR,
+		RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
+		RAM_REQUEST_COMPLETE => open,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_DATA => open
+	);
+
+GPIOA_gen:
+   for I in 0 to 35 generate
+		GPIOA(I) <= GPIOA_out(I) when GPIOA_dir_out(I)='1' else 'Z';
+   end generate GPIOA_gen;
+
+GPIO1_gen:
+   for I in 0 to 35 generate
+		GPIOB(I) <= GPIOB_out(I) when GPIOB_dir_out(I)='1' else 'Z';
+   end generate GPIO1_gen;
+
+gen_old_gpio : if gpio=1 generate
+GPIO1 : entity work.gpio
+GENERIC MAP(
+		cartridge_cycle_length => 26
+)
+PORT MAP(clk => CLK,
+	reset_n => reset_n,
+		 gpio_enable => pbi_enable,
+		 pot_reset => pot_reset,
+		 pbi_write_enable => pbi_write_enable,
+		 enable_179_early => enable_179_early,
+		 cart_request => cart_request,
+		 cart_complete => cart_request_complete,
+		 cart_data_read => cart_data,
+		 s4_n => cart_s4_n,
+		 s5_n => cart_s5_n,
+		 cctl_n => cart_cctl_n,
+		 cart_data_write => pbi_write_data(7 downto 0),
+		 GPIO_0_IN => GPIOA,
+		 GPIO_0_OUT => GPIOA_OUT,
+		 GPIO_0_DIR_OUT => GPIOA_DIR_OUT,
+		 GPIO_1_IN => GPIOB,
+		 GPIO_1_OUT => GPIOB_OUT,
+		 GPIO_1_DIR_OUT => GPIOB_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => pbi_addr,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 lightpen => ANTIC_LIGHTPEN,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 keyboard_response => GPIO_KEYBOARD_RESPONSE,
+		 porta_in => PORTA_IN,
+		 pot_in => pot_in,
+		 trig_in => TRIGGERS,
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => open,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => open,
+		 SIO_IN => GPIO_SIO_RXD,
+		 SIO_OUT => SIO_TXD
+		 );
+
+	CA1_IN <= '1';
+	CB1_IN <= '1';
+	CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
+	CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
+end generate gen_old_gpio;
+
+gen_new_gpio : if gpio=2 generate
+gpio2 : entity work.gpiov2
+GENERIC MAP(
+		cartridge_cycle_length => 26
+)
+PORT MAP(clk => CLK,
+	reset_n => reset_n,
+		 gpio_enable => pbi_enable,
+		 pot_reset => pot_reset,
+		 pbi_write_enable => pbi_write_enable,
+		 enable_179_early => enable_179_early,
+		 cart_request => cart_request,
+		 cart_complete => cart_request_complete,
+		 cart_data_read => cart_data,
+		 s4_n => cart_s4_n,
+		 s5_n => cart_s5_n,
+		 cctl_n => cart_cctl_n,
+		 cart_data_write => pbi_write_data(7 downto 0),
+		 GPIO_0_IN => GPIOA,
+		 GPIO_0_OUT => GPIOA_OUT,
+		 GPIO_0_DIR_OUT => GPIOA_DIR_OUT,
+		 GPIO_1_IN => GPIOB,
+		 GPIO_1_OUT => GPIOB_OUT,
+		 GPIO_1_DIR_OUT => GPIOB_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => pbi_addr,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 lightpen => ANTIC_LIGHTPEN,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 keyboard_response => GPIO_KEYBOARD_RESPONSE,
+		 porta_in => PORTA_IN,
+		 pot_in => pot_in,
+		 trig_in => TRIGGERS,
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => CA2_IN,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => CB2_IN,
+		 SIO_IN => GPIO_SIO_RXD,
+		 SIO_OUT => SIO_TXD,
+		 SIO_CLOCKIN => SIO_CLOCKIN,
+		 SIO_CLOCKOUT => SIO_CLOCKOUT
+		 );
+end generate gen_new_gpio;
+
+	process(clk,RESET_N,SDRAM_RESET_N,reset_atari)
+	begin
+		if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then
+			half_scandouble_enable_reg <= '0';
+		elsif (clk'event and clk='1') then
+			half_scandouble_enable_reg <= half_scandouble_enable_next;
+		end if;
+	end process;
+
+	half_scandouble_enable_next <= not(half_scandouble_enable_reg);
+
+scandoubler : entity work.scandoubler
+GENERIC MAP
+(
+	video_bits=>8
+)
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+		 VGA => '0', -- TODO SW(7),
+		 COMPOSITE_ON_HSYNC => '1', -- SW(6),
+		 colour_enable => half_scandouble_enable_reg,
+		 doubled_enable => '1',
+	 	 scanlines_on => '0', -- SW(5),
+		 vsync_in => VGA_VS_RAW,
+		 hsync_in => VGA_HS_RAW,
+		 csync_in => VGA_CS_RAW,
+		 pal => PAL,
+		 colour_in => VIDEO_B,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+VGA_BLANK_N <= NOT(VGA_BLANK);
+-- TODO VGA_CLK <= '0';
+
+--gen_ntsc_pll : if tv=0 generate
+--pll : entity work.pll_ntsc
+--PORT MAP(inclk0 => CLOCK_27(0),
+--		 c0 => CLK_SDRAM,
+--		 c1 => CLK,
+--		 c2 => DRAM_CLK,
+--		 locked => PLL_LOCKED);
+--end generate;
+--
+--gen_pal_pll : if tv=1 generate
+--pll : entity work.pll_pal
+--PORT MAP(inclk0 => CLOCK_27(0),
+--		 c0 => CLK_SDRAM,
+--		 c1 => CLK,
+--		 c2 => DRAM_CLK,
+--		 locked => PLL_LOCKED);
+--end generate;
+--
+--gen_old_pll : if tv=2 generate
+pll : entity work.pll
+PORT MAP(inclk0 => CLOCK_5, -- new PLL!
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+--end generate;
+
+RESET_N <= PLL_LOCKED;
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari800
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2clk,
+		PS2_DAT => ps2dat,
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => PS2_KEYBOARD_RESPONSE,
+
+		CONSOL_START => CONSOL_START,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_OPTION => CONSOL_OPTION,
+		
+		FKEYS => FKEYS,
+		FREEZER_ACTIVATE => freezer_activate,
+
+		PS2_KEYS_NEXT_OUT => ps2_keys_next,
+		PS2_KEYS => ps2_keys
+	);
+
+KEYBOARD_RESPONSE <= PS2_KEYBOARD_RESPONSE and GPIO_KEYBOARD_RESPONSE;
+
+-- SIO
+-- TODO combine
+--SIO_RXD <= UART_RXD;
+--UART_TXD <= SIO_TXD;
+--GPIOA(1) <= SIO_COMMAND;
+
+zpu_sio_command <= SIO_COMMAND;
+zpu_sio_rxd <= SIO_TXD;
+SIO_RXD <= zpu_sio_txd and GPIO_SIO_RXD;
+
+-- VIDEO
+--VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+--VGA_VS <= not(VGA_VS_RAW);
+
+atari800 : entity work.atari800core
+	GENERIC MAP
+	(
+		cycle_length => 32,
+		video_bits => 8,
+		palette => 0
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+
+		VIDEO_VS => VGA_VS_RAW,
+		VIDEO_HS => VGA_HS_RAW,
+		VIDEO_CS => VGA_CS_RAW,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => open,
+		VIDEO_R => open,
+		VIDEO_BLANK => VGA_BLANK,
+		VIDEO_BURST => open,
+		VIDEO_START_OF_FIELD => open,
+		VIDEO_ODD_LINE => open,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		CA1_IN => CA1_IN,
+		CB1_IN => CB1_IN,
+		CA2_IN => CA2_IN,
+		CA2_OUT => CA2_OUT,
+		CA2_DIR_OUT => CA2_DIR_OUT,
+		CB2_IN => CB2_IN,
+		CB2_OUT => CB2_OUT,
+		CB2_DIR_OUT => CB2_DIR_OUT,
+		PORTA_IN => PORTA_IN and not("0000"&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)),
+		PORTA_DIR_OUT => PORTA_DIR_OUT,
+		PORTA_OUT => PORTA_OUT,
+		PORTB_IN => PORTB_IN,
+		PORTB_DIR_OUT => open,--PORTB_DIR_OUT,
+		PORTB_OUT => PORTB_OUT,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		POT_IN => POT_IN,
+		POT_RESET => POT_RESET,
+		
+		ENABLE_179_EARLY => ENABLE_179_EARLY,
+		PBI_ADDR => PBI_ADDR,
+		PBI_WRITE_ENABLE => PBI_WRITE_ENABLE,
+		PBI_SNOOP_DATA => open,
+		PBI_WRITE_DATA => PBI_WRITE_DATA,
+		PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
+		PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
+		PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
+
+		PBI_ROM_DO => CART_DATA,
+		PBI_REQUEST => CART_REQUEST,
+		PBI_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+
+		CART_RD4 => CART_RD4,
+		CART_RD5 => CART_RD5,
+		CART_S4_n => CART_S4_n,
+		CART_S5_N => CART_S5_n,
+		CART_CCTL_N => CART_CCTL_n,
+
+		SIO_RXD => SIO_RXD,
+		SIO_TXD => SIO_TXD,
+
+		SIO_CLOCKIN => SIO_CLOCKIN,
+		SIO_CLOCKOUT => SIO_CLOCKOUT,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START=> CONSOL_START,
+		GTIA_TRIG => GTIA_TRIG and not("000"&ps2_keys(16#127#)),
+		
+		ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
+
+		SDRAM_REQUEST => SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => SDRAM_ADDR,
+		SDRAM_DO => SDRAM_DO,
+
+		ANTIC_REFRESH => SDRAM_REFRESH,
+
+		RAM_ADDR => RAM_ADDR,
+		RAM_DO => RAM_DO,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
+		
+		ROM_ADDR => ROM_ADDR,
+		ROM_DO => ROM_DO,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		--DMA_MEMORY_DATA => dma_memory_data,  
+		PBI_SNOOP_DATA => DMA_MEMORY_DATA,
+
+		RAM_SELECT => ram_select,
+		CART_EMULATION_SELECT => emulated_cartridge_select,
+		PAL => PAL,
+		USE_SDRAM => '1', --SW(9),
+		ROM_IN_RAM => '1',
+		THROTTLE_COUNT_6502 => speed_6502,
+		HALT => pause_atari,
+
+		freezer_enable => freezer_enable,
+		freezer_activate => freezer_activate,
+		freezer_state_out => freezer_state,
+
+		pbi_enable => pbi_enable
+	);
+
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_reset_n,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_dat0,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_dat3,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"000"&
+			"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+			FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	emulated_cartridge_select <= zpu_out1(22 downto 17);
+
+	freezer_enable <= zpu_out1(25);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>32) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => AUDIO_LEFT
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => AUDIO_RIGHT
+);
+
+END vhdl;
Index: eclaireXL/build.sh
===================================================================
--- eclaireXL/build.sh	(nonexistent)
+++ eclaireXL/build.sh	(revision 381)
@@ -0,0 +1,82 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+my $name="eclaireXL";
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $RGB = 1; # i.e. not scandoubled
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+#	"PAL" => 
+#	{
+#		"TV" => $PAL
+#	},
+#	"NTSC" =>
+#	{
+#		"TV" => $NTSC
+#	},
+	"BOTH" =>
+	{
+		"TV" => 2,
+		"GPIO" => 1
+	},
+	"PRIVATE" =>
+	{
+		"TV" => 2,
+		"GPIO" => 2
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant of $name\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari800core_eclaireXL.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp *.v $dir`;
+	`cp *.vhd* $dir`;
+	`cp atari800core*.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+
+	chdir $dir;
+	`../makeqsf ../atari800core_eclaireXL.qsf ./common/a8core ./common/components ./common/zpu`;
+	`cat ../atari800core_eclaireXL.qsf_$variant >> atari800core_eclaireXL.qsf`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari800core_eclaireXL.qsf`;
+	}
+
+#	`quartus_sh --flow compile atari800core > build.log 2> build.err`;
+#
+#	`quartus_cpf --convert ../output_file.cof`;
+	
+	chdir "..";
+}
+

Property changes on: eclaireXL/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL/gpio.vhd
===================================================================
--- eclaireXL/gpio.vhd	(nonexistent)
+++ eclaireXL/gpio.vhd	(revision 381)
@@ -0,0 +1,436 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+generic
+(
+	cartridge_cycle_length : in integer := 32
+);
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	enable_179_early : in std_logic;
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal bus_data_in : std_logic_vector(7 downto 0);
+	signal bus_data_out : std_logic_vector(7 downto 0);
+	signal bus_data_oe : std_logic;
+	signal bus_addr_out : std_logic_vector(15 downto 0);
+	signal bus_addr_oe : std_logic;
+	signal bus_write_n : std_logic;
+	signal bus_s4_n : std_logic;
+	signal bus_s5_n : std_logic;
+	signal bus_cctl_n : std_logic;
+	signal bus_control_oe : std_logic;
+	signal phi2 : std_logic;
+
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= 'Z';
+	GPIO_0_OUT(4) <= '0'; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '1';
+	GPIO_0_OUT(35) <= phi2;
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= bus_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(33) <= bus_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(32) <= bus_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and bus_data_oe; -- d7
+	GPIO_0_OUT(31) <= bus_data_out(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and bus_data_oe; -- d3
+	GPIO_0_OUT(30) <= bus_data_out(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(29) <= bus_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(28) <= bus_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(27) <= bus_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(26) <= bus_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(25) <= bus_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(24) <= bus_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(23) <= bus_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable and bus_control_oe;
+	GPIO_0_OUT(21) <= bus_s4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(20) <= bus_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(19) <= bus_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(18) <= bus_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(17) <= bus_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and bus_data_oe; -- d4
+	GPIO_0_OUT(16) <= bus_data_out(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and bus_data_oe; -- d5
+	GPIO_0_OUT(15) <= bus_data_out(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and bus_data_oe; -- d2
+	GPIO_0_OUT(14) <= bus_data_out(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and bus_data_oe; -- d1
+	GPIO_0_OUT(13) <= bus_data_out(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and bus_data_oe; -- d0
+	GPIO_0_OUT(12) <= bus_data_out(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
+	GPIO_0_OUT(11) <= bus_data_out(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable and bus_control_oe;
+	GPIO_0_OUT(10) <= bus_s5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable and bus_control_oe; -- cart control
+	GPIO_0_OUT(8) <= bus_cctl_n; -- cart control
+
+-- PBI: A13-A15
+	GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(7) <= bus_addr_out(15);
+	GPIO_0_DIR_OUT(6) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(6) <= bus_addr_out(14);
+	GPIO_0_DIR_OUT(5) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(5) <= bus_addr_out(13);
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0);
+		
+	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_1_IN(7)& GPIO_1_IN(6));
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	keyboard_response <= keyboard_response_gpio;
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+
+
+bus_adaptor : ENTITY work.timing6502
+GENERIC MAP
+(
+	CYCLE_LENGTH => cartridge_cycle_length,
+	CONTROl_BITS => 3
+)
+PORT MAP
+( 
+	CLK => clk,
+	RESET_N => reset_n,
+
+	-- FPGA side
+	ENABLE_179_EARLY =>enable_179_early,
+
+	REQUEST => cart_request,
+	ADDR_IN => pbi_addr_out,
+	DATA_IN => cart_data_write,
+	WRITE_IN => pbi_write_enable,
+	CONTROL_N_IN => s4_n&s5_n&cctl_n,
+
+	DATA_OUT => cart_data_read,
+	COMPLETE => cart_complete,
+
+	-- 6502 side
+	BUS_DATA_IN => bus_data_in,
+	
+	BUS_PHI1 => open,
+	BUS_PHI2 => phi2,
+	BUS_SUBCYCLE => open,
+	BUS_ADDR_OUT => bus_addr_out,
+	BUS_ADDR_OE => bus_addr_oe,
+	BUS_DATA_OUT => bus_data_out,
+	BUS_DATA_OE => bus_data_oe,
+	BUS_WRITE_N => bus_write_n,
+	BUS_CONTROL_N(2) => bus_s4_n,
+	BUS_CONTROL_N(1) => bus_s5_n,
+	BUS_CONTROL_N(0) => bus_cctl_n,
+	BUS_CONTROL_OE => bus_control_oe
+);
+
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	bus_data_in <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+--	cart_data0_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+--	cart_data1_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+--	cart_data2_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+--	cart_data3_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+--	cart_data4_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+--	cart_data5_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+--	cart_data6_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+--	cart_data7_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: eclaireXL/gpio.vhd_org
===================================================================
--- eclaireXL/gpio.vhd_org	(nonexistent)
+++ eclaireXL/gpio.vhd_org	(revision 381)
@@ -0,0 +1,436 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+generic
+(
+	cartridge_cycle_length : in integer := 32
+);
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	enable_179_early : in std_logic;
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal bus_data_in : std_logic_vector(7 downto 0);
+	signal bus_data_out : std_logic_vector(7 downto 0);
+	signal bus_data_oe : std_logic;
+	signal bus_addr_out : std_logic_vector(15 downto 0);
+	signal bus_addr_oe : std_logic;
+	signal bus_write_n : std_logic;
+	signal bus_s4_n : std_logic;
+	signal bus_s5_n : std_logic;
+	signal bus_cctl_n : std_logic;
+	signal bus_control_oe : std_logic;
+	signal phi2 : std_logic;
+
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= 'Z';
+	GPIO_0_OUT(4) <= '0'; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '1';
+	GPIO_0_OUT(35) <= phi2;
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= bus_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(33) <= bus_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(32) <= bus_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and bus_data_oe; -- d7
+	GPIO_0_OUT(31) <= bus_data_out(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and bus_data_oe; -- d3
+	GPIO_0_OUT(30) <= bus_data_out(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(29) <= bus_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(28) <= bus_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(27) <= bus_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(26) <= bus_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(25) <= bus_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(24) <= bus_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(23) <= bus_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable and bus_control_oe;
+	GPIO_0_OUT(21) <= bus_s4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(20) <= bus_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(19) <= bus_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(18) <= bus_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(17) <= bus_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and bus_data_oe; -- d4
+	GPIO_0_OUT(16) <= bus_data_out(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and bus_data_oe; -- d5
+	GPIO_0_OUT(15) <= bus_data_out(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and bus_data_oe; -- d2
+	GPIO_0_OUT(14) <= bus_data_out(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and bus_data_oe; -- d1
+	GPIO_0_OUT(13) <= bus_data_out(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and bus_data_oe; -- d0
+	GPIO_0_OUT(12) <= bus_data_out(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and bus_data_oe; -- d6
+	GPIO_0_OUT(11) <= bus_data_out(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable and bus_control_oe;
+	GPIO_0_OUT(10) <= bus_s5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable and bus_control_oe; -- cart control
+	GPIO_0_OUT(8) <= bus_cctl_n; -- cart control
+
+-- PBI: A13-A15
+	GPIO_0_DIR_OUT(7) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(7) <= bus_addr_out(15);
+	GPIO_0_DIR_OUT(6) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(6) <= bus_addr_out(14);
+	GPIO_0_DIR_OUT(5) <= gpio_enable and bus_addr_oe;
+	GPIO_0_OUT(5) <= bus_addr_out(13);
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0);
+		
+	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_1_IN(7)& GPIO_1_IN(6));
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	keyboard_response <= keyboard_response_gpio;
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+
+
+bus_adaptor : ENTITY work.timing6502
+GENERIC MAP
+(
+	CYCLE_LENGTH => cartridge_cycle_length,
+	CONTROl_BITS => 3
+)
+PORT MAP
+( 
+	CLK => clk,
+	RESET_N => reset_n,
+
+	-- FPGA side
+	ENABLE_179_EARLY =>enable_179_early,
+
+	REQUEST => cart_request,
+	ADDR_IN => pbi_addr_out,
+	DATA_IN => cart_data_write,
+	WRITE_IN => pbi_write_enable,
+	CONTROL_N_IN => s4_n&s5_n&cctl_n,
+
+	DATA_OUT => cart_data_read,
+	COMPLETE => cart_complete,
+
+	-- 6502 side
+	BUS_DATA_IN => bus_data_in,
+	
+	BUS_PHI1 => open,
+	BUS_PHI2 => phi2,
+	BUS_SUBCYCLE => open,
+	BUS_ADDR_OUT => bus_addr_out,
+	BUS_ADDR_OE => bus_addr_oe,
+	BUS_DATA_OUT => bus_data_out,
+	BUS_DATA_OE => bus_data_oe,
+	BUS_WRITE_N => bus_write_n,
+	BUS_CONTROL_N(2) => bus_s4_n,
+	BUS_CONTROL_N(1) => bus_s5_n,
+	BUS_CONTROL_N(0) => bus_cctl_n,
+	BUS_CONTROL_OE => bus_control_oe
+);
+
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	bus_data_in <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+--	cart_data0_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+--	cart_data1_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+--	cart_data2_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+--	cart_data3_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+--	cart_data4_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+--	cart_data5_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+--	cart_data6_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+--	cart_data7_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: eclaireXL/gpiov2.vhd
===================================================================
--- eclaireXL/gpiov2.vhd	(nonexistent)
+++ eclaireXL/gpiov2.vhd	(revision 381)
@@ -0,0 +1,439 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpiov2 is
+generic
+(
+	cartridge_cycle_length : in integer := 32
+);
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA1_IN : OUT STD_LOGIC;
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB1_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	SIO_CLOCKIN : OUT STD_LOGIC;
+	SIO_CLOCKOUT : IN STD_LOGIC;
+	
+	-- cartridge
+	enable_179_early : in std_logic;
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpiov2;
+
+architecture vhdl of gpiov2 is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal bus_data_in : std_logic_vector(7 downto 0);
+	signal bus_data_out : std_logic_vector(7 downto 0);
+	signal bus_data_oe : std_logic;
+	signal bus_addr_out : std_logic_vector(15 downto 0);
+	signal bus_addr_oe : std_logic;
+	signal bus_write_n : std_logic;
+	signal bus_s4_n : std_logic;
+	signal bus_s5_n : std_logic;
+	signal bus_cctl_n : std_logic;
+	signal bus_control_oe : std_logic;
+	signal phi2 : std_logic;
+
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	--GPIO_0_DIR_OUT(35 downto 4) <= (others=>'0');
+	GPIO_0_OUT(35 downto 2) <= (others=>'0');
+	GPIO_0_OUT(1) <= '0' when gpio_enable='1' else CB2_OUT;
+	GPIO_0_OUT(0) <= '0';
+
+	-- sio
+	--CB1=SIO_IRQ
+	--CB2=SIO_COMMAND
+	--CA1=SIO_PROCEED
+	--CA2=SIO_MOTOR_RAW
+
+	GPIO_0_DIR_OUT(0) <= '0';
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out and not(CB2_OUT) when gpio_enable='1' else '1';
+	GPIO_0_DIR_OUT(2) <= '0';
+	GPIO_0_DIR_OUT(3) <= CA2_dir_out and not(CA2_OUT) and gpio_enable;
+	GPIO_0_DIR_OUT(4) <= not(SIO_OUT) and gpio_enable;
+	GPIO_0_DIR_OUT(5) <= '0';
+	GPIO_0_DIR_OUT(6) <= not(SIO_CLOCKOUT) and gpio_enable;
+	GPIO_0_DIR_OUT(7) <= '0';
+	
+	CB1_in <= GPIO_0_IN(0) when gpio_enable='1' else '1';
+	CB2_in <= GPIO_0_IN(1) when gpio_enable='1' else '1';
+	CA1_in <= GPIO_0_IN(2) when gpio_enable='1' else '1';
+	CA2_in <= GPIO_0_IN(3) when gpio_enable='1' else '1';
+	SIO_IN <= GPIO_0_IN(5) when gpio_enable='1' else '1';
+	SIO_CLOCKIN <= GPIO_0_IN(7) when gpio_enable='1' else '1';
+	
+	-- sticks
+	-- PORTA7,6,5,4,TRIG1,POT3,2,1,0,PORTA3,2,1,0,TRIG0
+	GPIO_0_DIR_OUT(8) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick
+	GPIO_0_DIR_OUT(9) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick
+	GPIO_0_DIR_OUT(10) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick
+	GPIO_0_DIR_OUT(11) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick
+	GPIO_0_DIR_OUT(17) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick
+	GPIO_0_DIR_OUT(18) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick
+	GPIO_0_DIR_OUT(19) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick
+	GPIO_0_DIR_OUT(20) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick
+
+	GPIO_0_DIR_OUT(12) <= '0'; -- trig
+	GPIO_0_DIR_OUT(21) <= '0'; -- trig
+
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pot_reset;
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pot_reset;
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pot_reset;
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pot_reset;
+
+	-- ext
+	GPIO_0_DIR_OUT(22) <= '0';
+	GPIO_0_DIR_OUT(23) <= '0';
+	GPIO_0_DIR_OUT(24) <= '0';
+	GPIO_0_DIR_OUT(25) <= '0';
+	GPIO_0_DIR_OUT(26) <= '0';
+	GPIO_0_DIR_OUT(27) <= '0';
+	
+	-- keyboard
+	GPIO_0_DIR_OUT(28) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_0_DIR_OUT(29) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_0_DIR_OUT(30) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	GPIO_0_DIR_OUT(31) <= '0'; -- keyboard response 1
+	GPIO_0_DIR_OUT(32) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_0_DIR_OUT(33) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_0_DIR_OUT(34) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_0_DIR_OUT(35) <= '0'; -- keyboard response 2
+	
+	-- cart
+	GPIO_1_DIR_OUT(0) <= gpio_enable and bus_control_oe; -- cart control
+	GPIO_1_OUT(0) <= bus_cctl_n; -- cart control
+	GPIO_1_DIR_OUT(1) <= '1';
+	GPIO_1_OUT(1) <= phi2;
+	GPIO_1_DIR_OUT(2) <= '0'; -- RD5 rom present
+	GPIO_1_OUT(2) <= '0'; -- RD5 rom present
+	GPIO_1_DIR_OUT(3) <= gpio_enable; 
+	GPIO_1_OUT(3) <= bus_write_n; 
+	GPIO_1_DIR_OUT(4) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(4) <= bus_addr_out(10);
+	GPIO_1_DIR_OUT(5) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(5) <= bus_addr_out(11);
+	GPIO_1_DIR_OUT(6) <= gpio_enable and bus_control_oe;
+	GPIO_1_OUT(6) <= bus_s5_n;
+	GPIO_1_DIR_OUT(7) <= gpio_enable and bus_data_oe; -- d7
+	GPIO_1_OUT(7) <= bus_data_out(7); -- d7
+	GPIO_1_DIR_OUT(8) <= gpio_enable and bus_data_oe; -- d6
+	GPIO_1_OUT(8) <= bus_data_out(6); -- d6
+	GPIO_1_DIR_OUT(9) <= gpio_enable and bus_data_oe; -- d3
+	GPIO_1_OUT(9) <= bus_data_out(3); -- d3
+	GPIO_1_DIR_OUT(10) <= gpio_enable and bus_data_oe; -- d0
+	GPIO_1_OUT(10) <= bus_data_out(0); -- d0
+	GPIO_1_DIR_OUT(11) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(11) <= bus_addr_out(12);
+	GPIO_1_DIR_OUT(12) <= gpio_enable and bus_data_oe; -- d1
+	GPIO_1_OUT(12) <= bus_data_out(1); -- d1
+	GPIO_1_DIR_OUT(13) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(13) <= bus_addr_out(9);
+	GPIO_1_DIR_OUT(14) <= gpio_enable and bus_data_oe; -- d2
+	GPIO_1_OUT(14) <= bus_data_out(2); -- d2
+	GPIO_1_DIR_OUT(15) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(15) <= bus_addr_out(8);
+	GPIO_1_DIR_OUT(16) <= gpio_enable and bus_data_oe; -- d5
+	GPIO_1_OUT(16) <= bus_data_out(5); -- d5
+	GPIO_1_DIR_OUT(17) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(17) <= bus_addr_out(7);
+	GPIO_1_DIR_OUT(18) <= gpio_enable and bus_data_oe; -- d4
+	GPIO_1_OUT(18) <= bus_data_out(4); -- d4
+	GPIO_1_DIR_OUT(19) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(19) <= bus_addr_out(6);
+	GPIO_1_DIR_OUT(20) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(20) <= bus_addr_out(0);
+	GPIO_1_DIR_OUT(21) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(21) <= bus_addr_out(5);
+	GPIO_1_DIR_OUT(22) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(22) <= bus_addr_out(1);
+	GPIO_1_DIR_OUT(23) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(23) <= bus_addr_out(4);
+	GPIO_1_DIR_OUT(24) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(24) <= bus_addr_out(2);
+	GPIO_1_DIR_OUT(25) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(25) <= bus_addr_out(3);
+	GPIO_1_DIR_OUT(26) <= '0'; -- RD4 rom present
+	GPIO_1_OUT(26) <= '0'; -- RD4 rom present
+	GPIO_1_DIR_OUT(27) <= gpio_enable and bus_control_oe;
+	GPIO_1_OUT(27) <= bus_s4_n;
+
+-- PBI: EXTSEL_N,A13-A15
+	GPIO_1_DIR_OUT(28) <= '0'; -- TODO, EXTSEL_N
+	GPIO_1_OUT(28) <= '0';
+	GPIO_1_DIR_OUT(29) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(29) <= bus_addr_out(13);
+	GPIO_1_DIR_OUT(30) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(30) <= bus_addr_out(14);
+	GPIO_1_DIR_OUT(31) <= gpio_enable and bus_addr_oe;
+	GPIO_1_OUT(31) <= bus_addr_out(15);
+	GPIO_1_DIR_OUT(32) <= '0'; -- TODO, MPD_N
+	GPIO_1_OUT(32) <= '0';
+	GPIO_1_DIR_OUT(33) <= '0'; -- TODO, REF_N
+	GPIO_1_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(34) <= '0'; -- TODO, IRQ_N
+	GPIO_1_OUT(34) <= '0';
+	GPIO_1_DIR_OUT(35) <= '0'; -- TODO, RST_N
+	GPIO_1_OUT(35) <= '0';
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_0_IN(13)&GPIO_0_IN(14)&
+					GPIO_0_IN(15)&GPIO_0_IN(16));
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+	porta_in_async <= 
+					GPIO_0_IN(8)&GPIO_0_IN(9)&GPIO_0_IN(10)&GPIO_0_IN(11)& 
+					GPIO_0_IN(17)&GPIO_0_IN(18)&GPIO_0_IN(19)&GPIO_0_IN(20); 
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 0) <= porta_in_gpio(7 downto 0);
+		
+	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_0_IN(12)&GPIO_0_IN(21)));
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= not(gpio_enable&gpio_enable) or (GPIO_0_IN(35)& GPIO_0_IN(31));
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	keyboard_response <= keyboard_response_gpio;
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+
+
+bus_adaptor : ENTITY work.timing6502
+GENERIC MAP
+(
+	CYCLE_LENGTH => cartridge_cycle_length,
+	CONTROl_BITS => 3
+)
+PORT MAP
+( 
+	CLK => clk,
+	RESET_N => reset_n,
+
+	-- FPGA side
+	ENABLE_179_EARLY =>enable_179_early,
+
+	REQUEST => cart_request,
+	ADDR_IN => pbi_addr_out,
+	DATA_IN => cart_data_write,
+	WRITE_IN => pbi_write_enable,
+	CONTROL_N_IN => s4_n&s5_n&cctl_n,
+
+	DATA_OUT => cart_data_read,
+	COMPLETE => cart_complete,
+
+	-- 6502 side
+	BUS_DATA_IN => bus_data_in,
+	
+	BUS_PHI1 => open,
+	BUS_PHI2 => phi2,
+	BUS_SUBCYCLE => open,
+	BUS_ADDR_OUT => bus_addr_out,
+	BUS_ADDR_OE => bus_addr_oe,
+	BUS_DATA_OUT => bus_data_out,
+	BUS_DATA_OE => bus_data_oe,
+	BUS_WRITE_N => bus_write_n,
+	BUS_CONTROL_N(2) => bus_s4_n,
+	BUS_CONTROL_N(1) => bus_s5_n,
+	BUS_CONTROL_N(0) => bus_cctl_n,
+	BUS_CONTROL_OE => bus_control_oe
+);
+
+	rd4_async <= gpio_enable and GPIO_1_IN(26);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_1_IN(2);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	bus_data_in <= GPIO_1_IN(7)&GPIO_1_IN(8)&GPIO_1_IN(16)&GPIO_1_IN(18)&GPIO_1_IN(9)&GPIO_1_IN(14)&GPIO_1_IN(12)&GPIO_1_IN(10);	
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: eclaireXL/makeqsf
===================================================================
--- eclaireXL/makeqsf	(nonexistent)
+++ eclaireXL/makeqsf	(revision 381)
@@ -0,0 +1,40 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+print QSF_OUT "\n";
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: eclaireXL/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL/pincalc/connect.xml
===================================================================
--- eclaireXL/pincalc/connect.xml	(nonexistent)
+++ eclaireXL/pincalc/connect.xml	(revision 381)
@@ -0,0 +1,193 @@
+<connect gate="G$1" pin="P$20" pad="A10"/>
+<connect gate="G$1" pin="P$30" pad="A12"/>
+<connect gate="G$1" pin="P$35" pad="A13"/>
+<connect gate="G$1" pin="P$41" pad="A14"/>
+<connect gate="G$1" pin="P$45" pad="A15"/>
+<connect gate="G$1" pin="P$1" pad="A5"/>
+<connect gate="G$1" pin="P$6" pad="A7"/>
+<connect gate="G$1" pin="P$11" pad="A8"/>
+<connect gate="G$1" pin="P$15" pad="A9"/>
+<connect gate="G$1" pin="P$151" pad="AA10"/>
+<connect gate="G$1" pin="P$142" pad="AA12"/>
+<connect gate="G$1" pin="P$137" pad="AA13"/>
+<connect gate="G$1" pin="P$131" pad="AA14"/>
+<connect gate="G$1" pin="P$126" pad="AA15"/>
+<connect gate="G$1" pin="P$118" pad="AA17"/>
+<connect gate="G$1" pin="P$115" pad="AA18"/>
+<connect gate="G$1" pin="P$111" pad="AA19"/>
+<connect gate="G$1" pin="P$109" pad="AA20"/>
+<connect gate="G$1" pin="P$105" pad="AA22"/>
+<connect gate="G$1" pin="P$167" pad="AA7"/>
+<connect gate="G$1" pin="P$162" pad="AA8"/>
+<connect gate="G$1" pin="P$156" pad="AA9"/>
+<connect gate="G$1" pin="P$150" pad="AB10"/>
+<connect gate="G$1" pin="P$146" pad="AB11"/>
+<connect gate="G$1" pin="P$141" pad="AB12"/>
+<connect gate="G$1" pin="P$136" pad="AB13"/>
+<connect gate="G$1" pin="P$125" pad="AB15"/>
+<connect gate="G$1" pin="P$117" pad="AB17"/>
+<connect gate="G$1" pin="P$114" pad="AB18"/>
+<connect gate="G$1" pin="P$108" pad="AB20"/>
+<connect gate="G$1" pin="P$107" pad="AB21"/>
+<connect gate="G$1" pin="P$106" pad="AB22"/>
+<connect gate="G$1" pin="P$171" pad="AB5"/>
+<connect gate="G$1" pin="P$169" pad="AB6"/>
+<connect gate="G$1" pin="P$166" pad="AB7"/>
+<connect gate="G$1" pin="P$161" pad="AB8"/>
+<connect gate="G$1" pin="P$21" pad="B10"/>
+<connect gate="G$1" pin="P$25" pad="B11"/>
+<connect gate="G$1" pin="P$31" pad="B12"/>
+<connect gate="G$1" pin="P$36" pad="B13"/>
+<connect gate="G$1" pin="P$46" pad="B15"/>
+<connect gate="G$1" pin="P$51" pad="B16"/>
+<connect gate="G$1" pin="P$2" pad="B5"/>
+<connect gate="G$1" pin="P$3" pad="B6"/>
+<connect gate="G$1" pin="P$7" pad="B7"/>
+<connect gate="G$1" pin="P$27" pad="C11"/>
+<connect gate="G$1" pin="P$38" pad="C13"/>
+<connect gate="G$1" pin="P$48" pad="C15"/>
+<connect gate="G$1" pin="P$53" pad="C16"/>
+<connect gate="G$1" pin="P$5" pad="C6"/>
+<connect gate="G$1" pin="P$13" pad="C8"/>
+<connect gate="G$1" pin="P$17" pad="C9"/>
+<connect gate="G$1" pin="P$32" pad="D12"/>
+<connect gate="G$1" pin="P$37" pad="D13"/>
+<connect gate="G$1" pin="P$54" pad="D17"/>
+<connect gate="G$1" pin="P$4" pad="D6"/>
+<connect gate="G$1" pin="P$9" pad="D7"/>
+<connect gate="G$1" pin="P$16" pad="D9"/>
+<connect gate="G$1" pin="P$22" pad="E10"/>
+<connect gate="G$1" pin="P$33" pad="E12"/>
+<connect gate="G$1" pin="P$42" pad="E14"/>
+<connect gate="G$1" pin="P$47" pad="E15"/>
+<connect gate="G$1" pin="P$52" pad="E16"/>
+<connect gate="G$1" pin="P$8" pad="E7"/>
+<connect gate="G$1" pin="P$18" pad="E9"/>
+<connect gate="G$1" pin="P$23" pad="F10"/>
+<connect gate="G$1" pin="P$34" pad="F12"/>
+<connect gate="G$1" pin="P$39" pad="F13"/>
+<connect gate="G$1" pin="P$43" pad="F14"/>
+<connect gate="G$1" pin="P$49" pad="F15"/>
+<connect gate="G$1" pin="P$10" pad="F7"/>
+<connect gate="G$1" pin="P$19" pad="F9"/>
+<connect gate="G$1" pin="P$24" pad="G10"/>
+<connect gate="G$1" pin="P$26" pad="G11"/>
+<connect gate="G$1" pin="P$40" pad="G13"/>
+<connect gate="G$1" pin="P$50" pad="G15"/>
+<connect gate="G$1" pin="P$57" pad="G16"/>
+<connect gate="G$1" pin="P$55" pad="G17"/>
+<connect gate="G$1" pin="P$56" pad="G18"/>
+<connect gate="G$1" pin="P$193" pad="G6"/>
+<connect gate="G$1" pin="P$12" pad="G8"/>
+<connect gate="G$1" pin="P$28" pad="H11"/>
+<connect gate="G$1" pin="P$44" pad="H14"/>
+<connect gate="G$1" pin="P$58" pad="H18"/>
+<connect gate="G$1" pin="P$192" pad="H6"/>
+<connect gate="G$1" pin="P$14" pad="H8"/>
+<connect gate="G$1" pin="P$29" pad="J11"/>
+<connect gate="G$1" pin="P$61" pad="J17"/>
+<connect gate="G$1" pin="P$59" pad="J18"/>
+<connect gate="G$1" pin="P$60" pad="J19"/>
+<connect gate="G$1" pin="P$190" pad="J7"/>
+<connect gate="G$1" pin="P$191" pad="J8"/>
+<connect gate="G$1" pin="P$67" pad="K16"/>
+<connect gate="G$1" pin="P$66" pad="K17"/>
+<connect gate="G$1" pin="P$64" pad="K19"/>
+<connect gate="G$1" pin="P$65" pad="K20"/>
+<connect gate="G$1" pin="P$63" pad="K21"/>
+<connect gate="G$1" pin="P$62" pad="K22"/>
+<connect gate="G$1" pin="P$188" pad="K7"/>
+<connect gate="G$1" pin="P$189" pad="K9"/>
+<connect gate="G$1" pin="P$71" pad="L17"/>
+<connect gate="G$1" pin="P$70" pad="L18"/>
+<connect gate="G$1" pin="P$69" pad="L19"/>
+<connect gate="G$1" pin="P$68" pad="L22"/>
+<connect gate="G$1" pin="P$186" pad="L7"/>
+<connect gate="G$1" pin="P$187" pad="L8"/>
+<connect gate="G$1" pin="P$76" pad="M16"/>
+<connect gate="G$1" pin="P$74" pad="M18"/>
+<connect gate="G$1" pin="P$75" pad="M20"/>
+<connect gate="G$1" pin="P$73" pad="M21"/>
+<connect gate="G$1" pin="P$72" pad="M22"/>
+<connect gate="G$1" pin="P$183" pad="M6"/>
+<connect gate="G$1" pin="P$184" pad="M7"/>
+<connect gate="G$1" pin="P$185" pad="M8"/>
+<connect gate="G$1" pin="P$80" pad="N16"/>
+<connect gate="G$1" pin="P$78" pad="N19"/>
+<connect gate="G$1" pin="P$79" pad="N20"/>
+<connect gate="G$1" pin="P$77" pad="N21"/>
+<connect gate="G$1" pin="P$180" pad="N6"/>
+<connect gate="G$1" pin="P$181" pad="N8"/>
+<connect gate="G$1" pin="P$182" pad="N9"/>
+<connect gate="G$1" pin="P$85" pad="P16"/>
+<connect gate="G$1" pin="P$84" pad="P17"/>
+<connect gate="G$1" pin="P$82" pad="P18"/>
+<connect gate="G$1" pin="P$83" pad="P19"/>
+<connect gate="G$1" pin="P$81" pad="P22"/>
+<connect gate="G$1" pin="P$177" pad="P6"/>
+<connect gate="G$1" pin="P$178" pad="P7"/>
+<connect gate="G$1" pin="P$179" pad="P8"/>
+<connect gate="G$1" pin="P$149" pad="R11"/>
+<connect gate="G$1" pin="P$145" pad="R12"/>
+<connect gate="G$1" pin="P$135" pad="R14"/>
+<connect gate="G$1" pin="P$89" pad="R16"/>
+<connect gate="G$1" pin="P$88" pad="R17"/>
+<connect gate="G$1" pin="P$87" pad="R21"/>
+<connect gate="G$1" pin="P$86" pad="R22"/>
+<connect gate="G$1" pin="P$174" pad="R5"/>
+<connect gate="G$1" pin="P$175" pad="R6"/>
+<connect gate="G$1" pin="P$176" pad="R7"/>
+<connect gate="G$1" pin="P$155" pad="T10"/>
+<connect gate="G$1" pin="P$144" pad="T12"/>
+<connect gate="G$1" pin="P$140" pad="T13"/>
+<connect gate="G$1" pin="P$134" pad="T14"/>
+<connect gate="G$1" pin="P$130" pad="T15"/>
+<connect gate="G$1" pin="P$94" pad="T17"/>
+<connect gate="G$1" pin="P$93" pad="T18"/>
+<connect gate="G$1" pin="P$91" pad="T19"/>
+<connect gate="G$1" pin="P$92" pad="T20"/>
+<connect gate="G$1" pin="P$90" pad="T22"/>
+<connect gate="G$1" pin="P$173" pad="T7"/>
+<connect gate="G$1" pin="P$165" pad="T8"/>
+<connect gate="G$1" pin="P$160" pad="T9"/>
+<connect gate="G$1" pin="P$154" pad="U10"/>
+<connect gate="G$1" pin="P$147" pad="U11"/>
+<connect gate="G$1" pin="P$143" pad="U12"/>
+<connect gate="G$1" pin="P$139" pad="U13"/>
+<connect gate="G$1" pin="P$129" pad="U15"/>
+<connect gate="G$1" pin="P$124" pad="U16"/>
+<connect gate="G$1" pin="P$119" pad="U17"/>
+<connect gate="G$1" pin="P$97" pad="U20"/>
+<connect gate="G$1" pin="P$96" pad="U21"/>
+<connect gate="G$1" pin="P$95" pad="U22"/>
+<connect gate="G$1" pin="P$172" pad="U6"/>
+<connect gate="G$1" pin="P$168" pad="U7"/>
+<connect gate="G$1" pin="P$163" pad="U8"/>
+<connect gate="G$1" pin="P$152" pad="V10"/>
+<connect gate="G$1" pin="P$138" pad="V13"/>
+<connect gate="G$1" pin="P$132" pad="V14"/>
+<connect gate="G$1" pin="P$127" pad="V15"/>
+<connect gate="G$1" pin="P$122" pad="V16"/>
+<connect gate="G$1" pin="P$116" pad="V18"/>
+<connect gate="G$1" pin="P$99" pad="V19"/>
+<connect gate="G$1" pin="P$100" pad="V20"/>
+<connect gate="G$1" pin="P$98" pad="V21"/>
+<connect gate="G$1" pin="P$170" pad="V6"/>
+<connect gate="G$1" pin="P$159" pad="V9"/>
+<connect gate="G$1" pin="P$123" pad="W16"/>
+<connect gate="G$1" pin="P$112" pad="W19"/>
+<connect gate="G$1" pin="P$102" pad="W21"/>
+<connect gate="G$1" pin="P$101" pad="W22"/>
+<connect gate="G$1" pin="P$164" pad="W8"/>
+<connect gate="G$1" pin="P$157" pad="W9"/>
+<connect gate="G$1" pin="P$153" pad="Y10"/>
+<connect gate="G$1" pin="P$148" pad="Y11"/>
+<connect gate="G$1" pin="P$133" pad="Y14"/>
+<connect gate="G$1" pin="P$128" pad="Y15"/>
+<connect gate="G$1" pin="P$121" pad="Y16"/>
+<connect gate="G$1" pin="P$120" pad="Y17"/>
+<connect gate="G$1" pin="P$113" pad="Y19"/>
+<connect gate="G$1" pin="P$110" pad="Y20"/>
+<connect gate="G$1" pin="P$104" pad="Y21"/>
+<connect gate="G$1" pin="P$103" pad="Y22"/>
+<connect gate="G$1" pin="P$158" pad="Y9"/>
Index: eclaireXL/pincalc/connecttopins.pl
===================================================================
--- eclaireXL/pincalc/connecttopins.pl	(nonexistent)
+++ eclaireXL/pincalc/connecttopins.pl	(revision 381)
@@ -0,0 +1,93 @@
+#!/usr/bin/perl -w
+use strict;
+
+my %pinusage;
+open (PINS,"pinusage");
+	my $pincount = 1;
+	while (<PINS>)
+	{
+		chomp;
+		my @entry = split /,/;
+		if (1==scalar @entry)
+		{
+			$pinusage{$pincount} = $entry[0];
+			$pincount = $pincount+1;
+		}
+		if (3==scalar @entry)
+		{
+			my $base = $entry[0];
+			my $start = $entry[1];
+			my $end = $entry[2];
+			if ($end>=$start) {$end=$end+1};
+			if ($end<=$start) {$end=$end-1};
+			while ($start != $end)
+			{
+				$pinusage{$pincount} = "${base}[$start]";
+				if ($end>$start)
+				{
+					$start = $start+1;
+				}
+				else
+				{
+					$start = $start-1;
+				}
+				$pincount = $pincount+1;
+			}
+		}
+		if (4==scalar @entry)
+		{
+			my $base = $entry[0];
+			my $base2 = $entry[1];
+			my $start = $entry[2];
+			my $end = $entry[3];
+			if ($end>=$start) {$end=$end+1};
+			if ($end<=$start) {$end=$end-1};
+			while ($start != $end)
+			{
+				$pinusage{$pincount} = "${base}[$start]";
+				$pincount = $pincount+1;
+				$pinusage{$pincount} = "${base2}[$start]";
+				$pincount = $pincount+1;
+				if ($end>$start)
+				{
+					$start = $start+1;
+				}
+				else
+				{
+					$start = $start-1;
+				}
+			}
+		}
+	}
+close (PINS);
+
+#foreach my $pin (sort {$a<=>$b} keys %pinusage)
+#{
+#	my $func = $pinusage{$pin};
+#	print "$pin,$func\n";
+#}
+
+#<connect gate="G$1" pin="P$20" pad="A10"/>
+my %pintopad;
+while (<>)
+{
+	/connect.*pin=\"P\$(.*?)\" pad=\"(.*?)\"/;
+	my $pin=$1;
+	my $pad=$2;
+	$pintopad{$pin}=$pad;
+}
+
+
+#From,To,Assignment Name,Value,Enabled
+#,GPIO_0[0],Location,PIN_A13,Yes
+
+#print "From,To,Assignment Name,Value,Enabled\n";
+foreach my $pin (sort {$a<=>$b} keys %pintopad)
+{
+	my $pad = $pintopad{$pin};
+	my $func = $pinusage{$pin};
+#	print ",$func,P\$$pin,PIN_$pad,Yes\n";
+	print "set_location_assignment PIN_$pad -to $func\n";
+}
+
+

Property changes on: eclaireXL/pincalc/connecttopins.pl
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL/pincalc/pin.csv
===================================================================
--- eclaireXL/pincalc/pin.csv	(nonexistent)
+++ eclaireXL/pincalc/pin.csv	(revision 381)
@@ -0,0 +1,194 @@
+From,To,Assignment Name,Value,Enabled
+,VGA_R_0,P$1,PIN_A5,Yes
+,VGA_R_1,P$2,PIN_B5,Yes
+,VGA_R_2,P$3,PIN_B6,Yes
+,VGA_R_3,P$4,PIN_D6,Yes
+,VGA_R_4,P$5,PIN_C6,Yes
+,VGA_R_5,P$6,PIN_A7,Yes
+,VGA_R_6,P$7,PIN_B7,Yes
+,VGA_R_7,P$8,PIN_E7,Yes
+,VGA_G_0,P$9,PIN_D7,Yes
+,VGA_G_1,P$10,PIN_F7,Yes
+,VGA_G_2,P$11,PIN_A8,Yes
+,VGA_G_3,P$12,PIN_G8,Yes
+,VGA_G_4,P$13,PIN_C8,Yes
+,VGA_G_5,P$14,PIN_H8,Yes
+,VGA_G_6,P$15,PIN_A9,Yes
+,VGA_G_7,P$16,PIN_D9,Yes
+,VGA_BLANK_N,P$17,PIN_C9,Yes
+,VGA_B_0,P$18,PIN_E9,Yes
+,VGA_B_1,P$19,PIN_F9,Yes
+,VGA_B_2,P$20,PIN_A10,Yes
+,VGA_B_3,P$21,PIN_B10,Yes
+,VGA_B_4,P$22,PIN_E10,Yes
+,VGA_B_5,P$23,PIN_F10,Yes
+,VGA_B_6,P$24,PIN_G10,Yes
+,VGA_B_7,P$25,PIN_B11,Yes
+,VGA_CLK,P$26,PIN_G11,Yes
+,VGA_HSYNC,P$27,PIN_C11,Yes
+,VGA_VSYNC,P$28,PIN_H11,Yes
+,AUDIO_LEFT,P$29,PIN_J11,Yes
+,AUDIO_RIGHT,P$30,PIN_A12,Yes
+,GPIOC_17,P$31,PIN_B12,Yes
+,GPIOC_16,P$32,PIN_D12,Yes
+,GPIOC_15,P$33,PIN_E12,Yes
+,GPIOC_14,P$34,PIN_F12,Yes
+,GPIOC_13,P$35,PIN_A13,Yes
+,GPIOC_12,P$36,PIN_B13,Yes
+,GPIOC_11,P$37,PIN_D13,Yes
+,GPIOC_10,P$38,PIN_C13,Yes
+,GPIOC_9,P$39,PIN_F13,Yes
+,GPIOC_8,P$40,PIN_G13,Yes
+,GPIOC_7,P$41,PIN_A14,Yes
+,GPIOC_6,P$42,PIN_E14,Yes
+,GPIOC_5,P$43,PIN_F14,Yes
+,GPIOC_4,P$44,PIN_H14,Yes
+,GPIOC_3,P$45,PIN_A15,Yes
+,GPIOC_2,P$46,PIN_B15,Yes
+,GPIOC_1,P$47,PIN_E15,Yes
+,GPIOC_0,P$48,PIN_C15,Yes
+,GPIOA_0,P$49,PIN_F15,Yes
+,GPIOB_0,P$50,PIN_G15,Yes
+,GPIOA_1,P$51,PIN_B16,Yes
+,GPIOB_1,P$52,PIN_E16,Yes
+,GPIOA_2,P$53,PIN_C16,Yes
+,GPIOB_2,P$54,PIN_D17,Yes
+,GPIOA_3,P$55,PIN_G17,Yes
+,GPIOB_3,P$56,PIN_G18,Yes
+,GPIOA_4,P$57,PIN_G16,Yes
+,GPIOB_4,P$58,PIN_H18,Yes
+,GPIOA_5,P$59,PIN_J18,Yes
+,GPIOB_5,P$60,PIN_J19,Yes
+,GPIOA_6,P$61,PIN_J17,Yes
+,GPIOB_6,P$62,PIN_K22,Yes
+,GPIOA_7,P$63,PIN_K21,Yes
+,GPIOB_7,P$64,PIN_K19,Yes
+,GPIOA_8,P$65,PIN_K20,Yes
+,GPIOB_8,P$66,PIN_K17,Yes
+,GPIOA_9,P$67,PIN_K16,Yes
+,GPIOB_9,P$68,PIN_L22,Yes
+,GPIOA_10,P$69,PIN_L19,Yes
+,GPIOB_10,P$70,PIN_L18,Yes
+,GPIOA_11,P$71,PIN_L17,Yes
+,GPIOB_11,P$72,PIN_M22,Yes
+,GPIOA_12,P$73,PIN_M21,Yes
+,GPIOB_12,P$74,PIN_M18,Yes
+,GPIOA_13,P$75,PIN_M20,Yes
+,GPIOB_13,P$76,PIN_M16,Yes
+,GPIOA_14,P$77,PIN_N21,Yes
+,GPIOB_14,P$78,PIN_N19,Yes
+,GPIOA_15,P$79,PIN_N20,Yes
+,GPIOB_15,P$80,PIN_N16,Yes
+,GPIOA_16,P$81,PIN_P22,Yes
+,GPIOB_16,P$82,PIN_P18,Yes
+,GPIOA_17,P$83,PIN_P19,Yes
+,GPIOB_17,P$84,PIN_P17,Yes
+,GPIOA_18,P$85,PIN_P16,Yes
+,GPIOB_18,P$86,PIN_R22,Yes
+,GPIOA_19,P$87,PIN_R21,Yes
+,GPIOB_19,P$88,PIN_R17,Yes
+,GPIOA_20,P$89,PIN_R16,Yes
+,GPIOB_20,P$90,PIN_T22,Yes
+,GPIOA_21,P$91,PIN_T19,Yes
+,GPIOB_21,P$92,PIN_T20,Yes
+,GPIOA_22,P$93,PIN_T18,Yes
+,GPIOB_22,P$94,PIN_T17,Yes
+,GPIOA_23,P$95,PIN_U22,Yes
+,GPIOB_23,P$96,PIN_U21,Yes
+,GPIOA_24,P$97,PIN_U20,Yes
+,GPIOB_24,P$98,PIN_V21,Yes
+,GPIOA_25,P$99,PIN_V19,Yes
+,GPIOB_25,P$100,PIN_V20,Yes
+,GPIOA_26,P$101,PIN_W22,Yes
+,GPIOB_26,P$102,PIN_W21,Yes
+,GPIOA_27,P$103,PIN_Y22,Yes
+,GPIOB_27,P$104,PIN_Y21,Yes
+,GPIOA_28,P$105,PIN_AA22,Yes
+,GPIOB_28,P$106,PIN_AB22,Yes
+,GPIOA_29,P$107,PIN_AB21,Yes
+,GPIOB_29,P$108,PIN_AB20,Yes
+,GPIOA_30,P$109,PIN_AA20,Yes
+,GPIOB_30,P$110,PIN_Y20,Yes
+,GPIOA_31,P$111,PIN_AA19,Yes
+,GPIOB_31,P$112,PIN_W19,Yes
+,GPIOA_32,P$113,PIN_Y19,Yes
+,GPIOB_32,P$114,PIN_AB18,Yes
+,GPIOA_33,P$115,PIN_AA18,Yes
+,GPIOB_33,P$116,PIN_V18,Yes
+,GPIOA_34,P$117,PIN_AB17,Yes
+,GPIOB_34,P$118,PIN_AA17,Yes
+,GPIOA_35,P$119,PIN_U17,Yes
+,GPIOB_35,P$120,PIN_Y17,Yes
+,GPIOC_35,P$121,PIN_Y16,Yes
+,GPIOC_34,P$122,PIN_V16,Yes
+,GPIOC_33,P$123,PIN_W16,Yes
+,GPIOC_32,P$124,PIN_U16,Yes
+,GPIOC_31,P$125,PIN_AB15,Yes
+,GPIOC_30,P$126,PIN_AA15,Yes
+,GPIOC_29,P$127,PIN_V15,Yes
+,GPIOC_28,P$128,PIN_Y15,Yes
+,GPIOC_27,P$129,PIN_U15,Yes
+,GPIOC_26,P$130,PIN_T15,Yes
+,GPIOC_25,P$131,PIN_AA14,Yes
+,GPIOC_24,P$132,PIN_V14,Yes
+,GPIOC_23,P$133,PIN_Y14,Yes
+,GPIOC_22,P$134,PIN_T14,Yes
+,GPIOC_21,P$135,PIN_R14,Yes
+,GPIOC_20,P$136,PIN_AB13,Yes
+,GPIOC_19,P$137,PIN_AA13,Yes
+,GPIOC_18,P$138,PIN_V13,Yes
+,SD_WRITEPROTECT,P$139,PIN_U13,Yes
+,SD_DETECT,P$140,PIN_T13,Yes
+,SD_DAT1,P$141,PIN_AB12,Yes
+,SD_MISO,P$142,PIN_AA12,Yes
+,SD_SCK,P$143,PIN_U12,Yes
+,SD_MOSI,P$144,PIN_T12,Yes
+,SD_CS,P$145,PIN_R12,Yes
+,SD_DAT2,P$146,PIN_AB11,Yes
+,PS2CLK,P$147,PIN_U11,Yes
+,PS2DAT,P$148,PIN_Y11,Yes
+,USB2DM,P$149,PIN_R11,Yes
+,USB2DP,P$150,PIN_AB10,Yes
+,USB1DM,P$151,PIN_AA10,Yes
+,USB1DP,P$152,PIN_V10,Yes
+,SDRAM_A_4,P$153,PIN_Y10,Yes
+,SDRAM_A_5,P$154,PIN_U10,Yes
+,SDRAM_A_6,P$155,PIN_T10,Yes
+,SDRAM_A_7,P$156,PIN_AA9,Yes
+,SDRAM_A_8,P$157,PIN_W9,Yes
+,SDRAM_A_9,P$158,PIN_Y9,Yes
+,SDRAM_A_11,P$159,PIN_V9,Yes
+,SDRAM_A_12,P$160,PIN_T9,Yes
+,SDRAM_CKE,P$161,PIN_AB8,Yes
+,SDRAM_CLK,P$162,PIN_AA8,Yes
+,SDRAM_UDQM,P$163,PIN_U8,Yes
+,SDRAM_DQ_8,P$164,PIN_W8,Yes
+,SDRAM_DQ_9,P$165,PIN_T8,Yes
+,SDRAM_DQ_10,P$166,PIN_AB7,Yes
+,SDRAM_DQ_11,P$167,PIN_AA7,Yes
+,SDRAM_DQ_12,P$168,PIN_U7,Yes
+,SDRAM_DQ_13,P$169,PIN_AB6,Yes
+,SDRAM_DQ_14,P$170,PIN_V6,Yes
+,SDRAM_DQ_15,P$171,PIN_AB5,Yes
+,SDRAM_A_3,P$172,PIN_U6,Yes
+,SDRAM_A_2,P$173,PIN_T7,Yes
+,SDRAM_A_1,P$174,PIN_R5,Yes
+,SDRAM_A_0,P$175,PIN_R6,Yes
+,SDRAM_A10,P$176,PIN_R7,Yes
+,SDRAM_B_1,P$177,PIN_P6,Yes
+,SDRAM_B_0,P$178,PIN_P7,Yes
+,SDRAM_CS_N,P$179,PIN_P8,Yes
+,SDRAM_RAS_N,P$180,PIN_N6,Yes
+,SDRAM_CAS_N,P$181,PIN_N8,Yes
+,SDRAM_WE_N,P$182,PIN_N9,Yes
+,SDRAM_LDQM,P$183,PIN_M6,Yes
+,SDRAM_DQ_7,P$184,PIN_M7,Yes
+,SDRAM_DQ_6,P$185,PIN_M8,Yes
+,SDRAM_DQ_5,P$186,PIN_L7,Yes
+,SDRAM_DQ_4,P$187,PIN_L8,Yes
+,SDRAM_DQ_0,P$188,PIN_K7,Yes
+,SDRAM_DQ_1,P$189,PIN_K9,Yes
+,SDRAM_DQ_2,P$190,PIN_J7,Yes
+,SDRAM_DQ_3,P$191,PIN_J8,Yes
+,ADC_SDA,P$192,PIN_H6,Yes
+,ADC_SCL,P$193,PIN_G6,Yes
Index: eclaireXL/pincalc/pins.csv_example
===================================================================
--- eclaireXL/pincalc/pins.csv_example	(nonexistent)
+++ eclaireXL/pincalc/pins.csv_example	(revision 381)
@@ -0,0 +1,3 @@
+From,To,Assignment Name,Value,Enabled
+,GPIO_0[0],Location,PIN_A13,Yes
+
Index: eclaireXL/pincalc/pinusage
===================================================================
--- eclaireXL/pincalc/pinusage	(nonexistent)
+++ eclaireXL/pincalc/pinusage	(revision 381)
@@ -0,0 +1,45 @@
+VGA_R,0,7
+VGA_G,0,7
+VGA_BLANK_N
+VGA_B,0,7
+VGA_CLK
+VGA_HS
+VGA_VS
+AUDIO_LEFT
+AUDIO_RIGHT
+GPIOC,17,0
+GPIOA,GPIOB,0,35
+GPIOC,35,18
+SD_WRITEPROTECT,
+SD_DETECT
+SD_DAT1
+SD_DAT0
+SD_CLK
+SD_CMD
+SD_DAT3
+SD_DAT2
+PS2CLK
+PS2DAT
+USB2DM
+USB2DP
+USB1DM
+USB1DP
+DRAM_ADDR,4,9
+DRAM_ADDR,11,12
+DRAM_CKE
+DRAM_CLK
+DRAM_UDQM
+DRAM_DQ,8,15
+DRAM_ADDR,3,0
+DRAM_ADDR[10]
+DRAM_BA_1
+DRAM_BA_0
+DRAM_CS_N
+DRAM_RAS_N
+DRAM_CAS_N
+DRAM_WE_N
+DRAM_LDQM
+DRAM_DQ,7,4
+DRAM_DQ,0,3
+ADC_SDA
+ADC_SCL
Index: eclaireXL/pll.cmp
===================================================================
--- eclaireXL/pll.cmp	(nonexistent)
+++ eclaireXL/pll.cmp	(revision 381)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: eclaireXL/pll.ppf
===================================================================
--- eclaireXL/pll.ppf	(nonexistent)
+++ eclaireXL/pll.ppf	(revision 381)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: eclaireXL/pll.qip
===================================================================
--- eclaireXL/pll.qip	(nonexistent)
+++ eclaireXL/pll.qip	(revision 381)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: eclaireXL/pll.vhd
===================================================================
--- eclaireXL/pll.vhd	(nonexistent)
+++ eclaireXL/pll.vhd	(revision 381)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 10,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 20,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 10,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: eclaireXL/zpu_rom.vhdl
===================================================================
--- eclaireXL/zpu_rom.vhdl	(nonexistent)
+++ eclaireXL/zpu_rom.vhdl	(revision 381)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80f7",
+X"80738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80fb",
+X"d00c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580f4",
+X"ae2d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580f3ed",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"80ddfc04",
+X"fd3d0d75",
+X"705254ae",
+X"a33f83e0",
+X"80081453",
+X"72742e92",
+X"38ff1370",
+X"33535371",
+X"af2e0981",
+X"06ee3881",
+X"13537283",
+X"e0800c85",
+X"3d0d04fd",
+X"3d0d7577",
+X"70535454",
+X"c73f83e0",
+X"8008732e",
+X"a13883e0",
+X"80087331",
+X"52ff1252",
+X"71ff2e8f",
+X"38727081",
+X"05543374",
+X"70810556",
+X"34eb39ff",
+X"14548074",
+X"34853d0d",
+X"04803d0d",
+X"7251ff90",
+X"3f823d0d",
+X"047183e0",
+X"800c0480",
+X"3d0d7251",
+X"80713481",
+X"0bbc120c",
+X"800b80c0",
+X"120c823d",
+X"0d04800b",
+X"83e2c008",
+X"248a38b4",
+X"f43fff0b",
+X"83e2c00c",
+X"800b83e0",
+X"800c04ff",
+X"3d0d7352",
+X"83e09c08",
+X"722e8d38",
+X"d93f7151",
+X"96993f71",
+X"83e09c0c",
+X"833d0d04",
+X"f43d0d7e",
+X"60625c5a",
+X"558154bc",
+X"15088191",
+X"387451cf",
+X"3f795880",
+X"7a2580f7",
+X"3883e2f0",
+X"0870892a",
+X"5783ff06",
+X"78848072",
+X"31565657",
+X"73782583",
+X"38735575",
+X"83e2c008",
+X"2e8438ff",
+X"893f83e2",
+X"c0088025",
+X"a6387589",
+X"2b5198dc",
+X"3f83e2f0",
+X"088f3dfc",
+X"11555c54",
+X"8152f81b",
+X"5196c63f",
+X"761483e2",
+X"f00c7583",
+X"e2c00c74",
+X"53765278",
+X"51b3a53f",
+X"83e08008",
+X"83e2f008",
+X"1683e2f0",
+X"0c787631",
+X"761b5b59",
+X"56778024",
+X"ff8b3861",
+X"7a710c54",
+X"75547580",
+X"2e833881",
+X"547383e0",
+X"800c8e3d",
+X"0d04fc3d",
+X"0dfe9b3f",
+X"7651feaf",
+X"3f863dfc",
+X"05537852",
+X"775195e9",
+X"3f797571",
+X"0c5483e0",
+X"80085483",
+X"e0800880",
+X"2e833881",
+X"547383e0",
+X"800c863d",
+X"0d04fe3d",
+X"0d7583e2",
+X"c0085353",
+X"80722489",
+X"3871732e",
+X"8438fdd6",
+X"3f7451fd",
+X"ea3f7251",
+X"97ae3f83",
+X"e0800852",
+X"83e08008",
+X"802e8338",
+X"81527183",
+X"e0800c84",
+X"3d0d0480",
+X"3d0d7280",
+X"c0110883",
+X"e0800c51",
+X"823d0d04",
+X"803d0d72",
+X"bc110883",
+X"e0800c51",
+X"823d0d04",
+X"80c40b83",
+X"e0800c04",
+X"fd3d0d75",
+X"77715470",
+X"535553a9",
+X"fb3f82c8",
+X"1308bc15",
+X"0c82c013",
+X"0880c015",
+X"0cfceb3f",
+X"735193ab",
+X"3f7383e0",
+X"9c0c83e0",
+X"80085383",
+X"e0800880",
+X"2e833881",
+X"537283e0",
+X"800c853d",
+X"0d04fd3d",
+X"0d757755",
+X"53fcbf3f",
+X"72802ea5",
+X"38bc1308",
+X"527351a9",
+X"853f83e0",
+X"80088f38",
+X"77527251",
+X"ff9a3f83",
+X"e0800853",
+X"8a3982cc",
+X"130853d8",
+X"39815372",
+X"83e0800c",
+X"853d0d04",
+X"fe3d0dff",
+X"0b83e2c0",
+X"0c7483e0",
+X"a00c7583",
+X"e2bc0caf",
+X"d93f83e0",
+X"800881ff",
+X"06528153",
+X"71993883",
+X"e2d8518e",
+X"943f83e0",
+X"80085283",
+X"e0800880",
+X"2e833872",
+X"52715372",
+X"83e0800c",
+X"843d0d04",
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+X"7451ff93",
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+X"80567476",
+X"25863874",
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+X"3f83e080",
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+X"800c873d",
+X"0d04fa3d",
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+X"3f72812e",
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+X"881208d8",
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+X"8c120881",
+X"2e098106",
+X"ffb23884",
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+X"ff00ffff",
+X"ffff00ff",
+X"ffffff00",
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+X"a8a9aaab",
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+X"b8b9babb",
+X"bcbdbebf",
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+X"c8c9cacb",
+X"cccdcecf",
+X"d0d1d2d3",
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+X"d8d9dadb",
+X"dcdddedf",
+X"e0e1e2e3",
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+X"ecedeeef",
+X"f0f1f2f3",
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+X"2852616d",
+X"626f2900",
+X"314d4200",
+X"344d4200",
+X"53650000",
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+X"0d310040",
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+X"0f040010",
+X"110c0080",
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+X"1a280010",
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+X"1c2a0040",
+X"1d2b0080",
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+X"02020241",
+X"00060000",
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+X"00003c84",
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+X"00003ca4",
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+X"07954435",
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+X"f0caca10",
+X"ec3006e6",
+X"45d002e6",
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+X"a2018144",
+X"b545d543",
+X"d0edca10",
+X"f720d207",
+X"4c9407a9",
+X"038d0fd2",
+X"6ce202ad",
+X"8e07cd7f",
+X"07d0abee",
+X"0a03d003",
+X"ee0b03ad",
+X"7d070d7e",
+X"07d08e20",
+X"d2076ce0",
+X"0220da07",
+X"8de00220",
+X"da078de1",
+X"022de002",
+X"c9fff0ed",
+X"a9008d8e",
+X"07f08200",
+X"00000028",
+X"00000006",
+X"00000005",
+X"00000004",
+X"00000003",
+X"00000002",
+X"00000001",
+X"00000000",
+X"00003d8c",
+X"00003d98",
+X"00003da0",
+X"00003da8",
+X"00003db0",
+X"00003db8",
+X"00003dc0",
+X"00003dc8",
+X"2f617461",
+X"72693830",
+X"302f726f",
+X"6d000000",
+X"2f617461",
+X"72693830",
+X"302f7573",
+X"65720000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
