Index: ultimate_cart/veronica/veronica.sdc
===================================================================
--- ultimate_cart/veronica/veronica.sdc	(nonexistent)
+++ ultimate_cart/veronica/veronica.sdc	(revision 438)
@@ -0,0 +1,13 @@
+create_clock -period 40MHz [get_ports CLK]
+derive_pll_clocks
+derive_clock_uncertainty
+
+create_clock -period 14MHz -name sram_clk
+set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_ADDR[*]]
+set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_ADDR[*]] 
+
+set_output_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
+set_output_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]] 
+set_input_delay -clock sram_clk -max 60.0 [get_ports EXT_SRAM_DATA[*]]
+set_input_delay -clock sram_clk -min 0.0 [get_ports EXT_SRAM_DATA[*]] 
+
Index: ultimate_cart/veronica/simulate_sram.sh
===================================================================
--- ultimate_cart/veronica/simulate_sram.sh	(nonexistent)
+++ ultimate_cart/veronica/simulate_sram.sh	(revision 438)
@@ -0,0 +1,67 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=sram
+
+
+
+#. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+export XILINX=C:\Xilinx\14.7\ISE_DS\ISE
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_sram/* .
+
+        # copy source files
+	cp ../sram_mux.vhd .
+#	cp `find ../a8core/ -iname "*.vhd"` .
+#	cp `find ../a8core/ -iname "*.vhdl"` .
+#	cp `find ../components/ -iname "*.vhd"` .
+#	cp `find ../components/ -iname "*.vhdl"` .
+#
+        # set up project definition file
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat > $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        /drives/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64/fuse.exe -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: ultimate_cart/veronica/simulate_sram.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/BCDMath.v
===================================================================
--- ultimate_cart/veronica/BCDMath.v	(nonexistent)
+++ ultimate_cart/veronica/BCDMath.v	(revision 438)
@@ -0,0 +1,316 @@
+`timescale 1ns / 1ps
+//=============================================================================
+//        __
+//   \\__/ o\    (C) 2012  Robert Finch
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//  
+//	BCDMath.v
+//
+//  
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+//
+//=============================================================================
+//
+module BCDAdd(ci,a,b,o,c);
+input ci;		// carry input
+input [7:0] a;
+input [7:0] b;
+output [7:0] o;
+output c;
+
+wire c0,c1;
+
+wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
+wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
+
+BCDAddAdjust u1 (hsN0,o[3:0],c0);
+BCDAddAdjust u2 (hsN1,o[7:4],c);
+
+endmodule
+
+module BCDAdd4(ci,a,b,o,c,c8);
+input ci;		// carry input
+input [15:0] a;
+input [15:0] b;
+output [15:0] o;
+output c;
+output c8;
+
+wire c0,c1,c2;
+assign c8 = c1;
+
+wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
+wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
+wire [4:0] hsN2 = a[11:8] + b[11:8] + c1;
+wire [4:0] hsN3 = a[15:12] + b[15:12] + c2;
+
+BCDAddAdjust u1 (hsN0,o[3:0],c0);
+BCDAddAdjust u2 (hsN1,o[7:4],c1);
+BCDAddAdjust u3 (hsN2,o[11:8],c2);
+BCDAddAdjust u4 (hsN3,o[15:12],c);
+
+endmodule
+
+module BCDSub(ci,a,b,o,c);
+input ci;		// carry input
+input [7:0] a;
+input [7:0] b;
+output [7:0] o;
+output c;
+
+wire c0,c1;
+
+wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
+wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
+
+BCDSubAdjust u1 (hdN0,o[3:0],c0);
+BCDSubAdjust u2 (hdN1,o[7:4],c);
+
+endmodule
+
+module BCDSub4(ci,a,b,o,c,c8);
+input ci;		// carry input
+input [15:0] a;
+input [15:0] b;
+output [15:0] o;
+output c;
+output c8;
+
+wire c0,c1,c2;
+assign c8 = c1;
+
+wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
+wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
+wire [4:0] hdN2 = a[11:8] - b[11:8] - c1;
+wire [4:0] hdN3 = a[15:12] - b[15:12] - c2;
+
+BCDSubAdjust u1 (hdN0,o[3:0],c0);
+BCDSubAdjust u2 (hdN1,o[7:4],c1);
+BCDSubAdjust u3 (hdN2,o[11:8],c2);
+BCDSubAdjust u4 (hdN3,o[15:12],c);
+
+endmodule
+
+module BCDAddAdjust(i,o,c);
+input [4:0] i;
+output [3:0] o;
+reg [3:0] o;
+output c;
+reg c;
+always @(i)
+case(i)
+5'h0: begin o = 4'h0; c = 1'b0; end
+5'h1: begin o = 4'h1; c = 1'b0; end
+5'h2: begin o = 4'h2; c = 1'b0; end
+5'h3: begin o = 4'h3; c = 1'b0; end
+5'h4: begin o = 4'h4; c = 1'b0; end
+5'h5: begin o = 4'h5; c = 1'b0; end
+5'h6: begin o = 4'h6; c = 1'b0; end
+5'h7: begin o = 4'h7; c = 1'b0; end
+5'h8: begin o = 4'h8; c = 1'b0; end
+5'h9: begin o = 4'h9; c = 1'b0; end
+5'hA: begin o = 4'h0; c = 1'b1; end
+5'hB: begin o = 4'h1; c = 1'b1; end
+5'hC: begin o = 4'h2; c = 1'b1; end
+5'hD: begin o = 4'h3; c = 1'b1; end
+5'hE: begin o = 4'h4; c = 1'b1; end
+5'hF: begin o = 4'h5; c = 1'b1; end
+5'h10:	begin o = 4'h6; c = 1'b1; end
+5'h11:	begin o = 4'h7; c = 1'b1; end
+5'h12:	begin o = 4'h8; c = 1'b1; end
+5'h13:	begin o = 4'h9; c = 1'b1; end
+default:	begin o = 4'h9; c = 1'b1; end
+endcase
+endmodule
+
+module BCDSubAdjust(i,o,c);
+input [4:0] i;
+output [3:0] o;
+reg [3:0] o;
+output c;
+reg c;
+always @(i)
+case(i)
+5'h0: begin o = 4'h0; c = 1'b0; end
+5'h1: begin o = 4'h1; c = 1'b0; end
+5'h2: begin o = 4'h2; c = 1'b0; end
+5'h3: begin o = 4'h3; c = 1'b0; end
+5'h4: begin o = 4'h4; c = 1'b0; end
+5'h5: begin o = 4'h5; c = 1'b0; end
+5'h6: begin o = 4'h6; c = 1'b0; end
+5'h7: begin o = 4'h7; c = 1'b0; end
+5'h8: begin o = 4'h8; c = 1'b0; end
+5'h9: begin o = 4'h9; c = 1'b0; end
+5'h16: begin o = 4'h0; c = 1'b1; end
+5'h17: begin o = 4'h1; c = 1'b1; end
+5'h18: begin o = 4'h2; c = 1'b1; end
+5'h19: begin o = 4'h3; c = 1'b1; end
+5'h1A: begin o = 4'h4; c = 1'b1; end
+5'h1B: begin o = 4'h5; c = 1'b1; end
+5'h1C: begin o = 4'h6; c = 1'b1; end
+5'h1D: begin o = 4'h7; c = 1'b1; end
+5'h1E: begin o = 4'h8; c = 1'b1; end
+5'h1F: begin o = 4'h9; c = 1'b1; end
+default: begin o = 4'h9; c = 1'b1; end
+endcase
+endmodule
+
+// Multiply two BCD digits
+// Method used is table lookup
+module BCDMul1(a,b,o);
+input [3:0] a;
+input [3:0] b;
+output [7:0] o;
+reg [7:0] o;
+
+always @(a or b)
+casex({a,b})
+8'h00: o = 8'h00;
+8'h01: o = 8'h00;
+8'h02: o = 8'h00;
+8'h03: o = 8'h00;
+8'h04: o = 8'h00;
+8'h05: o = 8'h00;
+8'h06: o = 8'h00;
+8'h07: o = 8'h00;
+8'h08: o = 8'h00;
+8'h09: o = 8'h00;
+8'h10: o = 8'h00;
+8'h11: o = 8'h01;
+8'h12: o = 8'h02;
+8'h13: o = 8'h03;
+8'h14: o = 8'h04;
+8'h15: o = 8'h05;
+8'h16: o = 8'h06;
+8'h17: o = 8'h07;
+8'h18: o = 8'h08;
+8'h19: o = 8'h09;
+8'h20: o = 8'h00;
+8'h21: o = 8'h02;
+8'h22: o = 8'h04;
+8'h23: o = 8'h06;
+8'h24: o = 8'h08;
+8'h25: o = 8'h10;
+8'h26: o = 8'h12;
+8'h27: o = 8'h14;
+8'h28: o = 8'h16;
+8'h29: o = 8'h18;
+8'h30: o = 8'h00;
+8'h31: o = 8'h03;
+8'h32: o = 8'h06;
+8'h33: o = 8'h09;
+8'h34: o = 8'h12;
+8'h35: o = 8'h15;
+8'h36: o = 8'h18;
+8'h37: o = 8'h21;
+8'h38: o = 8'h24;
+8'h39: o = 8'h27;
+8'h40: o = 8'h00;
+8'h41: o = 8'h04;
+8'h42: o = 8'h08;
+8'h43: o = 8'h12;
+8'h44: o = 8'h16;
+8'h45: o = 8'h20;
+8'h46: o = 8'h24;
+8'h47: o = 8'h28;
+8'h48: o = 8'h32;
+8'h49: o = 8'h36;
+8'h50: o = 8'h00;
+8'h51: o = 8'h05;
+8'h52: o = 8'h10;
+8'h53: o = 8'h15;
+8'h54: o = 8'h20;
+8'h55: o = 8'h25;
+8'h56: o = 8'h30;
+8'h57: o = 8'h35;
+8'h58: o = 8'h40;
+8'h59: o = 8'h45;
+8'h60: o = 8'h00;
+8'h61: o = 8'h06;
+8'h62: o = 8'h12;
+8'h63: o = 8'h18;
+8'h64: o = 8'h24;
+8'h65: o = 8'h30;
+8'h66: o = 8'h36;
+8'h67: o = 8'h42;
+8'h68: o = 8'h48;
+8'h69: o = 8'h54;
+8'h70: o = 8'h00;
+8'h71: o = 8'h07;
+8'h72: o = 8'h14;
+8'h73: o = 8'h21;
+8'h74: o = 8'h28;
+8'h75: o = 8'h35;
+8'h76: o = 8'h42;
+8'h77: o = 8'h49;
+8'h78: o = 8'h56;
+8'h79: o = 8'h63;
+8'h80: o = 8'h00;
+8'h81: o = 8'h08;
+8'h82: o = 8'h16;
+8'h83: o = 8'h24;
+8'h84: o = 8'h32;
+8'h85: o = 8'h40;
+8'h86: o = 8'h48;
+8'h87: o = 8'h56;
+8'h88: o = 8'h64;
+8'h89: o = 8'h72;
+8'h90: o = 8'h00;
+8'h91: o = 8'h09;
+8'h92: o = 8'h18;
+8'h93: o = 8'h27;
+8'h94: o = 8'h36;
+8'h95: o = 8'h45;
+8'h96: o = 8'h54;
+8'h97: o = 8'h63;
+8'h98: o = 8'h72;
+8'h99: o = 8'h81;
+default:	o = 8'h00;
+endcase
+endmodule
+
+
+// Multiply two pairs of BCD digits
+// handles from 0x0 to 99x99
+module BCDMul2(a,b,o);
+input [7:0] a;
+input [7:0] b;
+output [15:0] o;
+
+wire [7:0] p1,p2,p3,p4;
+wire [15:0] s1;
+
+BCDMul1 u1 (a[3:0],b[3:0],p1);
+BCDMul1 u2 (a[7:4],b[3:0],p2);
+BCDMul1 u3 (a[3:0],b[7:4],p3);
+BCDMul1 u4 (a[7:4],b[7:4],p4);
+
+BCDAdd4 u5 (1'b0,{p4,p1},{4'h0,p2,4'h0},s1);
+BCDAdd4 u6 (1'b0,s1,{4'h0,p3,4'h0},o);
+
+endmodule
+
+module BCDMul_tb();
+
+wire [15:0] o1,o2,o3,o4;
+
+BCDMul2 u1 (8'h00,8'h00,o1);
+BCDMul2 u2 (8'h99,8'h99,o2);
+BCDMul2 u3 (8'h25,8'h18,o3);
+BCDMul2 u4 (8'h37,8'h21,o4);
+
+endmodule
Index: ultimate_cart/veronica/sram_mux.vhd
===================================================================
--- ultimate_cart/veronica/sram_mux.vhd	(nonexistent)
+++ ultimate_cart/veronica/sram_mux.vhd	(revision 438)
@@ -0,0 +1,98 @@
+	LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY sram_mux IS
+	PORT (
+				clk : in std_logic;
+				clk7x : in std_logic;
+				reset_n : in std_logic;
+				
+				sram_addr : out std_logic_vector(19 downto 0);
+				sram_data_out : out std_logic_vector(7 downto 0);
+				sram_drive_data : out std_logic;
+				sram_we_n : out std_logic;
+
+				atari_bus_request : in std_logic;
+				atari_sram_select : in std_logic;
+				atari_address : in std_logic_vector(16 downto 0);
+				atari_w_n : in std_logic;
+				atari_write_data : in std_logic_vector(7 downto 0);
+				
+				veronica_address : in std_logic_vector(16 downto 0);
+				veronica_sram_select : in std_logic;
+				veronica_w_n : in std_logic;
+				veronica_write_data : in std_logic_vector(7 downto 0)
+			);
+END sram_mux;
+
+ARCHITECTURE vhdl OF sram_mux IS
+	signal sram_we_next : std_logic;
+	signal sram_we_reg : std_logic;
+	
+	signal tick_next : std_logic;
+	signal tick_reg : std_logic;
+	
+	signal tick_fast_next : std_logic_vector(6 downto 0);
+	signal tick_fast_reg : std_logic_vector(6 downto 0);
+	
+	signal tick_mask : std_logic_vector(6 downto 0);
+begin
+
+	-- Back to back writes from 65816?
+	process(veronica_address, veronica_write_data, veronica_w_n, veronica_sram_select,
+			atari_bus_request, atari_address,atari_write_data, atari_w_n, atari_sram_select)
+	begin
+		sram_addr <= (others=>'0');
+		sram_data_out <= (others=>'0');
+		sram_drive_data <= '0';
+	
+		if (atari_bus_request='1') then
+			sram_addr(16 downto 0) <= atari_address;
+			sram_data_out <= atari_write_data;
+			sram_we_next <= (atari_w_n or not(atari_sram_select));
+			sram_drive_data <= not(atari_w_n);
+		else
+			sram_addr(16 downto 0) <= veronica_address;
+			sram_data_out <= veronica_write_data;
+			sram_we_next <= (veronica_w_n or not(veronica_sram_select));
+			sram_drive_data <= not(veronica_w_n);
+		end if;
+	end process;
+	
+	-- 
+	-- 12345
+	-- 01111
+	-- 00000
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			tick_reg <= '0';
+		elsif (clk'event and clk='1') then
+			tick_reg <= tick_next;
+		end if;
+	end process;	
+	tick_next <= not(tick_reg);
+	
+	process(clk7x,reset_n)
+	begin
+		if (reset_n='0') then
+			tick_fast_reg <= (others=>'0');
+			sram_we_reg <= '1';
+		elsif (clk7x'event and clk7x='1') then
+			tick_fast_reg <= tick_fast_next;
+			sram_we_reg <= sram_we_next;
+		end if;
+	end process;
+	tick_fast_next <= tick_fast_reg(5 downto 0)&tick_reg;
+	
+	tick_mask <= (tick_reg&tick_reg&tick_reg&tick_reg&tick_reg&tick_reg&tick_reg) xor tick_fast_reg; --1000000 1000000 1000000 (raise WE - how long must WE be high?)
+ 
+	-- 55 addr, 45 write pulse, 20 we -> drive
+	-- 71.4 total -> 7x clock-> about 10ns
+	-- 10 (we high), 60 (we low) 1 000 000
+	-- 30 (no drive), 40 (drive) 0 001 111
+	
+	sram_we_n <= sram_we_reg;
+
+end vhdl;

Property changes on: ultimate_cart/veronica/sram_mux.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/tb_sram/sram_tb.vhd
===================================================================
--- ultimate_cart/veronica/tb_sram/sram_tb.vhd	(nonexistent)
+++ ultimate_cart/veronica/tb_sram/sram_tb.vhd	(revision 438)
@@ -0,0 +1,157 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity sram_tb is
+end;
+
+architecture rtl of sram_tb is
+
+  constant CLK_PERIOD : time := 1 us / (14);
+  constant CLK_FAST_PERIOD : time := 1 us / (14*7);
+
+  signal reset_n : std_logic;
+  signal clk : std_logic;
+  signal clk_fast : std_logic;
+
+	signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
+	signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
+	signal EXT_SRAM_CE: std_logic;
+	signal EXT_SRAM_OE: std_logic;
+	signal EXT_SRAM_WE: std_logic;
+
+	-- 65816 bus
+	signal veronica_address : std_logic_vector(23 downto 0);
+	signal veronica_read_data : std_logic_vector(7 downto 0);
+	signal veronica_write_data : std_logic_vector(7 downto 0);
+	signal veronica_w_n : std_logic;
+	signal veronica_config_w_n : std_logic;
+	
+	-- 6502 bus
+	signal atari_bus_request : std_logic;	
+	signal atari_address : std_logic_vector(12 downto 0);
+	signal atari_data_bus : std_logic_vector(7 downto 0);
+	signal atari_read_data : std_logic_vector(7 downto 0);
+	signal atari_write_data : std_logic_vector(7 downto 0);
+	signal atari_w_n : std_logic;
+	signal atari_config_w_n : std_logic;
+	signal atari_s4 : std_logic;
+	signal atari_s5 : std_logic;
+	signal atari_ctl : std_logic;
+	
+	-- address decode
+	signal veronica_config_select : std_logic;	
+	signal veronica_sram_select : std_logic;
+	signal veronica_sram_address: std_logic_vector(16 downto 0);	
+	signal atari_config_select : std_logic;
+	signal atari_sram_select : std_logic;	
+	signal atari_sram_address: std_logic_vector(16 downto 0);
+
+	-- veronica config
+	signal veronica_window_address : std_logic;
+	signal veronica_bank_half_select : std_logic;	
+	signal veronica_config_data : std_logic_vector(7 downto 0);
+	
+	-- atari config
+	signal atari_banka_enable : std_logic;
+	signal atari_bank8_enable : std_logic;
+	signal atari_bank_half_select : std_logic;
+	signal atari_config_data : std_logic_vector(7 downto 0);
+
+	-- common config
+	signal common_sem : std_logic;	
+	signal common_bank_select : std_logic;
+	
+	-- cart driving
+	signal cart_bus_data_out : std_logic_vector(7 downto 0);
+	signal cart_bus_drive : std_logic;
+	
+	-- sram driving
+	signal sram_write_data : std_logic_vector(7 downto 0);
+	signal sram_drive_data : std_logic;
+	signal sram_read_data : std_logic_vector(7 downto 0);
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk <= '1';
+	wait for CLK_PERIOD/2;
+	clk <= '0';
+	wait for CLK_PERIOD - (CLK_PERIOD/2 );
+	end process;
+
+	p_clk_gen_b : process
+	begin
+	clk_fast <= '1';
+	wait for CLK_FAST_PERIOD/2;
+	clk_fast <= '0';
+	wait for CLK_FAST_PERIOD - (CLK_FAST_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+	process_setup_sram : process
+	begin
+	atari_bus_request <= '0';
+	atari_sram_select <= '0';
+	atari_address <= (others=>'0');
+	atari_w_n <= '1';
+	atari_write_data <= (others=>'0');
+	
+	veronica_address <= (others=>'0');
+	veronica_sram_select <= '0';
+	veronica_w_n <= '1';
+	veronica_write_data <= (others=>'0');
+
+	wait for 1100ns;
+
+	wait until clk'event and clk = '1';
+	atari_w_n <= '0';
+	atari_address<= '0'&x"402";
+	atari_write_data <= x"56";
+
+	wait until clk'event and clk = '1';
+	atari_w_n <= '0';
+	atari_address<= '0'&x"313";
+	atari_write_data <= x"65";
+
+	wait until clk'event and clk = '1';
+	atari_w_n <= '0';
+	atari_address<= '0'&x"402";
+	atari_write_data <= x"56";
+
+	wait for 100000000us;
+
+	end process;
+
+	glue6: entity work.sram_mux
+	port map
+	(
+		clk => clk,
+		clk7x => clk_fast,
+		reset_n => reset_n,
+		
+		sram_addr => EXT_SRAM_ADDR,
+		sram_data_out => sram_write_data,
+		sram_drive_data => sram_drive_data,
+		sram_we_n => EXT_SRAM_WE,
+
+		atari_bus_request => atari_bus_request,
+		atari_sram_select => atari_sram_select,
+		atari_address => atari_sram_address,
+		atari_w_n => atari_w_n,
+		atari_write_data => atari_write_data,
+		
+		veronica_address => veronica_sram_address,
+		veronica_sram_select => veronica_sram_select,
+		veronica_w_n => veronica_w_n,
+		veronica_write_data => veronica_write_data
+	);
+
+end rtl;
+
Index: ultimate_cart/veronica/veronica.qsf
===================================================================
--- ultimate_cart/veronica/veronica.qsf	(nonexistent)
+++ ultimate_cart/veronica/veronica.qsf	(revision 438)
@@ -0,0 +1,220 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 08:06:31  April 05, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		veronica_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M08SAE144C8G
+set_global_assignment -name TOP_LEVEL_ENTITY veronica
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:06:31  APRIL 05, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_location_assignment PIN_27 -to CLK
+set_location_assignment PIN_120 -to LED[0]
+set_location_assignment PIN_61 -to CART_RD5
+set_location_assignment PIN_58 -to CART_S5
+set_location_assignment PIN_25 -to CART_RD4
+set_location_assignment PIN_28 -to CART_S4
+set_location_assignment PIN_39 -to CART_ADDR[0]
+set_location_assignment PIN_33 -to CART_ADDR[1]
+set_location_assignment PIN_30 -to CART_ADDR[2]
+set_location_assignment PIN_29 -to CART_ADDR[3]
+set_location_assignment PIN_32 -to CART_ADDR[4]
+set_location_assignment PIN_38 -to CART_ADDR[5]
+set_location_assignment PIN_41 -to CART_ADDR[6]
+set_location_assignment PIN_44 -to CART_ADDR[7]
+set_location_assignment PIN_46 -to CART_ADDR[8]
+set_location_assignment PIN_48 -to CART_ADDR[9]
+set_location_assignment PIN_60 -to CART_ADDR[10]
+set_location_assignment PIN_59 -to CART_ADDR[11]
+set_location_assignment PIN_52 -to CART_ADDR[12]
+set_location_assignment PIN_54 -to CART_DATA[0]
+set_location_assignment PIN_50 -to CART_DATA[1]
+set_location_assignment PIN_47 -to CART_DATA[2]
+set_location_assignment PIN_55 -to CART_DATA[3]
+set_location_assignment PIN_57 -to CART_DATA[7]
+set_location_assignment PIN_56 -to CART_DATA[6]
+set_location_assignment PIN_45 -to CART_DATA[5]
+set_location_assignment PIN_43 -to CART_DATA[4]
+set_location_assignment PIN_65 -to SD_CARD_cs
+set_location_assignment PIN_69 -to SD_CARD_sclk
+set_location_assignment PIN_66 -to SD_CARD_mosi
+set_location_assignment PIN_70 -to SD_CARD_miso
+set_location_assignment PIN_93 -to EXT_SRAM_DATA[0]
+set_location_assignment PIN_92 -to EXT_SRAM_DATA[1]
+set_location_assignment PIN_91 -to EXT_SRAM_DATA[2]
+set_location_assignment PIN_90 -to EXT_SRAM_DATA[3]
+set_location_assignment PIN_75 -to EXT_SRAM_DATA[4]
+set_location_assignment PIN_74 -to EXT_SRAM_DATA[5]
+set_location_assignment PIN_113 -to EXT_SRAM_DATA[6]
+set_location_assignment PIN_112 -to EXT_SRAM_DATA[7]
+set_location_assignment PIN_96 -to EXT_SRAM_ADDR[0]
+set_location_assignment PIN_97 -to EXT_SRAM_ADDR[1]
+set_location_assignment PIN_98 -to EXT_SRAM_ADDR[2]
+set_location_assignment PIN_99 -to EXT_SRAM_ADDR[3]
+set_location_assignment PIN_100 -to EXT_SRAM_ADDR[4]
+set_location_assignment PIN_105 -to EXT_SRAM_ADDR[5]
+set_location_assignment PIN_102 -to EXT_SRAM_ADDR[6]
+set_location_assignment PIN_101 -to EXT_SRAM_ADDR[7]
+set_location_assignment PIN_111 -to EXT_SRAM_ADDR[8]
+set_location_assignment PIN_76 -to EXT_SRAM_ADDR[9]
+set_location_assignment PIN_77 -to EXT_SRAM_ADDR[10]
+set_location_assignment PIN_78 -to EXT_SRAM_ADDR[11]
+set_location_assignment PIN_79 -to EXT_SRAM_ADDR[12]
+set_location_assignment PIN_80 -to EXT_SRAM_ADDR[13]
+set_location_assignment PIN_81 -to EXT_SRAM_ADDR[14]
+set_location_assignment PIN_84 -to EXT_SRAM_ADDR[15]
+set_location_assignment PIN_85 -to EXT_SRAM_ADDR[16]
+set_location_assignment PIN_86 -to EXT_SRAM_ADDR[17]
+set_location_assignment PIN_87 -to EXT_SRAM_ADDR[18]
+set_location_assignment PIN_88 -to EXT_SRAM_ADDR[19]
+set_location_assignment PIN_110 -to EXT_SRAM_CE
+set_location_assignment PIN_106 -to EXT_SRAM_OE
+set_location_assignment PIN_89 -to EXT_SRAM_WE
+set_location_assignment PIN_64 -to CART_CTL
+set_location_assignment PIN_26 -to CART_PHI2
+set_location_assignment PIN_62 -to CART_RW
+set_global_assignment -name VHDL_FILE synchronizer_vector.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VERILOG_FILE BCDMath.v
+set_global_assignment -name VHDL_FILE veronica.vhd
+set_global_assignment -name VERILOG_FILE FT816.v
+set_global_assignment -name QIP_FILE pll_veronica.qip
+set_global_assignment -name VHDL_FILE config_regs_veronica.vhd
+set_global_assignment -name VHDL_FILE config_regs_6502.vhd
+set_global_assignment -name VHDL_FILE slave_timing_6502.vhd
+set_global_assignment -name VHDL_FILE veronica_address_decoder.vhd
+set_global_assignment -name VHDL_FILE atari_address_decoder.vhd
+set_global_assignment -name VHDL_FILE sram_mux.vhd
+set_global_assignment -name VHDL_FILE output_mux.vhd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CARD_miso
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CARD_mosi
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CARD_sclk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_RD5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_S5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_RD4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_S4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_OE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_WE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_SRAM_CE
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to CART_PHI2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_CTL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CART_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CART_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CARD_cs
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

Property changes on: ultimate_cart/veronica/veronica.qsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/veronica.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: ultimate_cart/veronica/veronica.qws
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: ultimate_cart/veronica/veronica_address_decoder.vhd
===================================================================
--- ultimate_cart/veronica/veronica_address_decoder.vhd	(nonexistent)
+++ ultimate_cart/veronica/veronica_address_decoder.vhd	(revision 438)
@@ -0,0 +1,39 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+
+ENTITY veronica_address_decoder IS
+	PORT (
+				addr_in: in std_logic_vector(15 downto 0);
+				window_address : in std_logic;
+				bank_half_select : in std_logic;
+				bank_select : in std_logic;
+				
+				config_select : out std_logic;
+				sram_select : out std_logic;
+				sram_address : out std_logic_vector(16 downto 0)
+			);
+END veronica_address_decoder;
+
+ARCHITECTURE vhdl OF veronica_address_decoder IS
+	signal bank_access : std_logic;
+	signal config_select_int : std_logic;
+begin
+	-- window_address 0=0xc0000->0xffff, 1=0x4000->0x7fff
+	-- config_address 0x200->0x20f
+	bank_access <= (window_address xor addr_in(15)) and addr_in(14);
+	process(bank_access,bank_select,bank_half_select,addr_in)
+	begin
+		sram_address <= '0'&addr_in;
+		if (bank_access='1') then
+			sram_address(16 downto 14) <= '1'&not(bank_select)&bank_half_select;
+		end if;
+	end process;
+
+	config_select_int <= not(or_reduce(addr_in(15 downto 10)&addr_in(8 downto 4))) and addr_in(9);	
+	config_select <= config_select_int;
+	sram_select <= not(config_select_int);
+	
+end vhdl;

Property changes on: ultimate_cart/veronica/veronica_address_decoder.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/FT816.v
===================================================================
--- ultimate_cart/veronica/FT816.v	(nonexistent)
+++ ultimate_cart/veronica/FT816.v	(revision 438)
@@ -0,0 +1,2238 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2013, 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816.v
+//  - 16 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+`define TRUE		1'b1
+`define FALSE		1'b0
+
+`define DEBUG		1'b1
+
+`define SUPPORT_ICACHE	1'b1
+`define ICACHE_4K		1'b1
+//`define ICACHE_16K		1'b1
+//`define ICACHE_2WAY		1'b1
+//`define SUPPORT_DCACHE	1'b1
+`define SUPPORT_BCD		1'b1
+`define SUPPORT_DIVMOD		1'b1
+`define SUPPORT_EM8		1'b1
+`define SUPPORT_816		1'b1
+//`define SUPPORT_EXEC	1'b1
+`define SUPPORT_BERR	1'b1
+`define SUPPORT_STRING	1'b1
+`define SUPPORT_SHIFT	1'b1
+//`define SUPPORT_CGI		1'b1			// support the control giveaway interrupt
+
+`define BRK_VECTNO	9'd0
+`define SLP_VECTNO	9'd1
+`define BYTE_RST_VECT	24'h00FFFC
+`define BYTE_NMI_VECT	24'h00FFFA
+`define BYTE_IRQ_VECT	24'h00FFFE
+`define BYTE_ABT_VECT	24'h00FFF8
+`define BYTE_COP_VECT	24'h00FFF4
+`define RST_VECT_816	24'h00FFFC
+`define IRQ_VECT_816	24'h00FFEE
+`define NMI_VECT_816	24'h00FFEA
+`define ABT_VECT_816	24'h00FFE8
+`define BRK_VECT_816	24'h00FFE6
+`define COP_VECT_816	24'h00FFE4
+
+`define BRK			9'h00
+`define RTI			9'h40
+`define RTS			9'h60
+`define PHP			9'h08
+`define CLC			9'h18
+`define PLP			9'h28
+`define SEC			9'h38
+`define PHA			9'h48
+`define CLI			9'h58
+`define PLA			9'h68
+`define SEI			9'h78
+`define DEY			9'h88
+`define TYA			9'h98
+`define TAY			9'hA8
+`define CLV			9'hB8
+`define INY			9'hC8
+`define CLD			9'hD8
+`define INX			9'hE8
+`define SED			9'hF8
+`define ROR_ACC		9'h6A
+`define TXA			9'h8A
+`define TXS			9'h9A
+`define TAX			9'hAA
+`define TSX			9'hBA
+`define DEX			9'hCA
+`define NOP			9'hEA
+`define TXY			9'h9B
+`define TYX			9'hBB
+`define TAS			9'h1B
+`define TSA			9'h3B
+`define TRS			9'h8B
+`define TSR			9'hAB
+`define TCD			9'h5B
+`define TDC			9'h7B
+`define STP			9'hDB
+`define NAT			9'hFB
+`define EMM			9'hFB
+`define XCE			9'hFB
+`define INA			9'h1A
+`define DEA			9'h3A
+`define SEP			9'hE2
+`define REP			9'hC2
+`define PEA			9'hF4
+`define PEI			9'hD4
+`define PER			9'h62
+`define WDM			9'h42
+
+// CMP = SUB r0,....
+
+`define ADC_IMM		9'h69
+`define ADC_ZP		9'h65
+`define ADC_ZPX		9'h75
+`define ADC_IX		9'h61
+`define ADC_IY		9'h71
+`define ADC_IYL		9'h77
+`define ADC_ABS		9'h6D
+`define ADC_ABSX	9'h7D
+`define ADC_ABSY	9'h79
+`define ADC_I		9'h72
+`define ADC_IL		9'h67
+`define ADC_AL		9'h6F
+`define ADC_ALX		9'h7F
+`define ADC_DSP		9'h63
+`define ADC_DSPIY	9'h73
+
+`define SBC_IMM		9'hE9
+`define SBC_ZP		9'hE5
+`define SBC_ZPX		9'hF5
+`define SBC_IX		9'hE1
+`define SBC_IY		9'hF1
+`define SBC_IYL		9'hF7
+`define SBC_ABS		9'hED
+`define SBC_ABSX	9'hFD
+`define SBC_ABSY	9'hF9
+`define SBC_I		9'hF2
+`define SBC_IL		9'hE7
+`define SBC_AL		9'hEF
+`define SBC_ALX		9'hFF
+`define SBC_DSP		9'hE3
+`define SBC_DSPIY	9'hF3
+
+`define CMP_IMM		9'hC9
+`define CMP_ZP		9'hC5
+`define CMP_ZPX		9'hD5
+`define CMP_IX		9'hC1
+`define CMP_IY		9'hD1
+`define CMP_IYL		8'hD7
+`define CMP_ABS		9'hCD
+`define CMP_ABSX	9'hDD
+`define CMP_ABSY	9'hD9
+`define CMP_I		9'hD2
+`define CMP_IL		9'hC7
+`define CMP_AL		9'hCF
+`define CMP_ALX		9'hDF
+`define CMP_DSP		9'hC3
+`define CMP_DSPIY	9'hD3
+
+`define LDA_IMM8	9'hA5
+`define LDA_IMM16	9'hB9
+`define LDA_IMM32	9'hA9
+
+`define AND_IMM		9'h29
+`define AND_ZP		9'h25
+`define AND_ZPX		9'h35
+`define AND_IX		9'h21
+`define AND_IY		9'h31
+`define AND_IYL		9'h37
+`define AND_ABS		9'h2D
+`define AND_ABSX	9'h3D
+`define AND_ABSY	9'h39
+`define AND_RIND	9'h32
+`define AND_I		9'h32
+`define AND_IL		9'h27
+`define AND_DSP		9'h23
+`define AND_DSPIY	9'h33
+`define AND_AL		9'h2F
+`define AND_ALX		9'h3F
+
+`define ORA_IMM		9'h09
+`define ORA_ZP		9'h05
+`define ORA_ZPX		9'h15
+`define ORA_IX		9'h01
+`define ORA_IY		9'h11
+`define ORA_IYL		9'h17
+`define ORA_ABS		9'h0D
+`define ORA_ABSX	9'h1D
+`define ORA_ABSY	9'h19
+`define ORA_I		9'h12
+`define ORA_IL		9'h07
+`define ORA_AL		9'h0F
+`define ORA_ALX		9'h1F
+`define ORA_DSP		9'h03
+`define ORA_DSPIY	9'h13
+
+`define EOR_IMM		9'h49
+`define EOR_ZP		9'h45
+`define EOR_ZPX		9'h55
+`define EOR_IX		9'h41
+`define EOR_IY		9'h51
+`define EOR_IYL		9'h57
+`define EOR_ABS		9'h4D
+`define EOR_ABSX	9'h5D
+`define EOR_ABSY	9'h59
+`define EOR_RIND	9'h52
+`define EOR_I		9'h52
+`define EOR_IL		9'h47
+`define EOR_DSP		9'h43
+`define EOR_DSPIY	9'h53
+`define EOR_AL		9'h4F
+`define EOR_ALX		9'h5F
+
+//`define LDB_RIND	9'hB2	// Conflict with LDX #imm16
+
+`define LDA_IMM		9'hA9
+`define LDA_ZP		9'hA5
+`define LDA_ZPX		9'hB5
+`define LDA_IX		9'hA1
+`define LDA_IY		9'hB1
+`define LDA_IYL		9'hB7
+`define LDA_ABS		9'hAD
+`define LDA_ABSX	9'hBD
+`define LDA_ABSY	9'hB9
+`define LDA_I		9'hB2
+`define LDA_IL		9'hA7
+`define LDA_AL		9'hAF
+`define LDA_ALX		9'hBF
+`define LDA_DSP		9'hA3
+`define LDA_DSPIY	9'hB3
+
+`define STA_ZP		9'h85
+`define STA_ZPX		9'h95
+`define STA_IX		9'h81
+`define STA_IY		9'h91
+`define STA_IYL		9'h97
+`define STA_ABS		9'h8D
+`define STA_ABSX	9'h9D
+`define STA_ABSY	9'h99
+`define STA_I		9'h92
+`define STA_IL		9'h87
+`define STA_AL		9'h8F
+`define STA_ALX		9'h9F
+`define STA_DSP		9'h83
+`define STA_DSPIY	9'h93
+
+`define ASL_ACC		9'h0A
+`define ASL_ZP		9'h06
+`define ASL_RR		9'h06
+`define ASL_ZPX		9'h16
+`define ASL_ABS		9'h0E
+`define ASL_ABSX	9'h1E
+
+`define ROL_ACC		9'h2A
+`define ROL_ZP		9'h26
+`define ROL_RR		9'h26
+`define ROL_ZPX		9'h36
+`define ROL_ABS		9'h2E
+`define ROL_ABSX	9'h3E
+
+`define LSR_ACC		9'h4A
+`define LSR_ZP		9'h46
+`define LSR_RR		9'h46
+`define LSR_ZPX		9'h56
+`define LSR_ABS		9'h4E
+`define LSR_ABSX	9'h5E
+
+`define ROR_RR		9'h66
+`define ROR_ZP		9'h66
+`define ROR_ZPX		9'h76
+`define ROR_ABS		9'h6E
+`define ROR_ABSX	9'h7E
+
+`define DEC_RR		9'hC6
+`define DEC_ZP		9'hC6
+`define DEC_ZPX		9'hD6
+`define DEC_ABS		9'hCE
+`define DEC_ABSX	9'hDE
+`define INC_RR		9'hE6
+`define INC_ZP		9'hE6
+`define INC_ZPX		9'hF6
+`define INC_ABS		9'hEE
+`define INC_ABSX	9'hFE
+
+`define BIT_IMM		9'h89
+`define BIT_ZP		9'h24
+`define BIT_ZPX		9'h34
+`define BIT_ABS		9'h2C
+`define BIT_ABSX	9'h3C
+
+// CMP = SUB r0,...
+// BIT = AND r0,...
+`define BPL			9'h10
+`define BVC			9'h50
+`define BCC			9'h90
+`define BNE			9'hD0
+`define BMI			9'h30
+`define BVS			9'h70
+`define BCS			9'hB0
+`define BEQ			9'hF0
+`define BRL			9'h82
+`define BRA			9'h80
+
+`define JML			9'h5C
+`define JMP			9'h4C
+`define JMP_IND		9'h6C
+`define JMP_INDX	9'h7C
+`define JMP_RIND	9'hD2
+`define JSR			9'h20
+`define JSL			9'h22
+`define JSR_IND		9'h2C
+`define JSR_INDX	9'hFC
+`define JSR_RIND	9'hC2
+`define RTS			9'h60
+`define RTL			9'h6B
+`define BSR			9'h62
+`define NOP			9'hEA
+
+`define BRK			9'h00
+`define PLX			9'hFA
+`define PLY			9'h7A
+`define PHX			9'hDA
+`define PHY			9'h5A
+`define WAI			9'hCB
+`define PUSH		9'h0B
+`define POP			9'h2B
+`define PHB			9'h8B
+`define PHD			9'h0B
+`define PHK			9'h4B
+`define XBA			9'hEB
+`define COP			9'h02
+`define PLB			9'hAB
+`define PLD			9'h2B
+`define PSHR4		9'h0F
+`define POPR4		9'h2F
+
+`define LDX_IMM		9'hA2
+`define LDX_ZP		9'hA6
+`define LDX_ZPX		9'hB6
+`define LDX_ZPY		9'hB6
+`define LDX_ABS		9'hAE
+`define LDX_ABSY	9'hBE
+
+`define LDX_IMM32	9'hA2
+`define LDX_IMM16	9'hB2
+`define LDX_IMM8	9'hA6
+
+`define LDY_IMM		9'hA0
+`define LDY_ZP		9'hA4
+`define LDY_ZPX		9'hB4
+`define LDY_IMM32	9'hA0
+`define LDY_IMM8	9'hA1
+`define LDY_ABS		9'hAC
+`define LDY_ABSX	9'hBC
+
+`define STX_ZP		9'h86
+`define STX_ZPX		9'h96
+`define STX_ZPY		9'h96
+`define STX_ABS		9'h8E
+
+`define STY_ZP		9'h84
+`define STY_ZPX		9'h94
+`define STY_ABS		9'h8C
+
+`define STZ_ZP		9'h64
+`define STZ_ZPX		9'h74
+`define STZ_ABS		9'h9C
+`define STZ_ABSX	9'h9E
+
+`define CPX_IMM		9'hE0
+`define CPX_IMM32	9'hE0
+`define CPX_IMM8	9'hE2
+`define CPX_ZP		9'hE4
+`define CPX_ZPX		9'hE4
+`define CPX_ABS		9'hEC
+`define CPY_IMM		9'hC0
+`define CPY_IMM32	9'hC0
+`define CPY_IMM8	9'hC1
+`define CPY_ZP		9'hC4
+`define CPY_ZPX		9'hC4
+`define CPY_ABS		9'hCC
+
+`define TRB_ZP		9'h14
+`define TRB_ZPX		9'h14
+`define TRB_ABS		9'h1C
+`define TSB_ZP		9'h04
+`define TSB_ZPX		9'h04
+`define TSB_ABS		9'h0C
+
+`define MVP			9'h44
+`define MVN			9'h54
+`define STS			9'h64
+
+// Page Two Opcodes
+`define PG2			9'h42
+
+`define ICOFF		9'h108
+`define ICON		9'h128
+`define TOFF		9'h118
+`define TON			9'h138
+`define MUL_IMM8	9'h105
+`define MUL_IMM16	9'h119
+`define MUL_IMM32	9'h109
+`define MULS_IMM8	9'h125
+`define MULS_IMM16	9'h139
+`define MULS_IMM32	9'h129
+`define DIV_IMM8	9'h145
+`define DIV_IMM16	9'h159
+`define DIV_IMM32	9'h149
+`define DIVS_IMM8	9'h165
+`define DIVS_IMM16	9'h179
+`define DIVS_IMM32	9'h169
+`define MOD_IMM8	9'h185
+`define MOD_IMM16	9'h199
+`define MOD_IMM32	9'h189
+`define MODS_IMM8	9'h1A5
+`define MODS_IMM16	9'h1B9
+`define MODS_IMM32	9'h1A9
+`define PUSHA		9'h10B
+`define POPA		9'h12B
+`define BMS_ZPX		9'h106
+`define BMS_ABS		9'h10E
+`define BMS_ABSX	9'h11E
+`define BMC_ZPX		9'h126
+`define BMC_ABS		9'h12E
+`define BMC_ABSX	9'h13E
+`define BMF_ZPX		9'h146
+`define BMF_ABS		9'h14E
+`define BMF_ABSX	9'h15E
+`define BMT_ZPX		9'h166
+`define BMT_ABS		9'h16E
+`define BMT_ABSX	9'h17E
+`define HOFF		9'h158
+`define CMPS		9'h144
+`define SPL_ABS		9'h18E
+`define SPL_ABSX	9'h19E
+
+`define LEA_ZPX		9'h1D5
+`define LEA_IX		9'h1C1
+`define LEA_IY		9'h1D1
+`define LEA_ABS		9'h1CD
+`define LEA_ABSX	9'h1DD
+`define LEA_RIND	9'h1D2
+`define LEA_I		9'h1D2
+`define LEA_DSP		9'h1C3
+
+`define NOTHING		5'd0
+`define SR_70		5'd1
+`define SR_310		5'd2
+`define BYTE_70		5'd3
+`define WORD_310	5'd4
+`define PC_70		5'd5
+`define PC_158		5'd6
+`define PC_2316		5'd7
+`define PC_3124		5'd8
+`define PC_310		5'd9
+`define WORD_311	5'd10
+`define IA_310		5'd11
+`define IA_70		5'd12
+`define IA_158		5'd13
+`define BYTE_71		5'd14
+`define WORD_312	5'd15
+`define WORD_313	5'd16
+`define WORD_314	5'd17
+`define IA_2316		5'd18
+`define HALF_70		5'd19
+`define HALF_158	5'd20
+`define HALF_71		5'd21
+`define HALF_159	5'd22
+`define HALF_71S	5'd23
+`define HALF_159S	5'd24
+`define BYTE_72		5'd25
+`define TRIP_2316	5'd26
+
+`define STW_DEF		6'h0
+`define STW_RES8	6'd14
+`define STW_R4		6'd15
+`define STW_ACC8	6'd16
+`define STW_X8		6'd17
+`define STW_Y8		6'd18
+`define STW_PC3124	6'd19
+`define STW_PC2316	6'd20
+`define STW_PC158	6'd21
+`define STW_PC70	6'd22
+`define STW_SR70	6'd23
+`define STW_Z8		6'd24
+`define STW_DEF8	6'd25
+`define STW_DEF70	6'd26
+`define STW_DEF158	6'd27
+`define STW_DEF2316	6'd28
+
+`define STW_ACC70	6'd32
+`define STW_ACC158	6'd33
+`define STW_X70		6'd34
+`define STW_X158	6'd35
+`define STW_Y70		6'd36
+`define STW_Y158	6'd37
+`define STW_Z70		6'd38
+`define STW_Z158	6'd39
+`define STW_DBR		6'd40
+`define STW_DPR158	6'd41
+`define STW_DPR70	6'd42
+`define STW_TMP158	6'd43
+`define STW_TMP70	6'd44
+`define STW_IA158	6'd45
+`define STW_IA70	6'd46
+`define STW_BRA		6'd47
+
+// Input Frequency is 32 times the 00 clock
+
+module FT816(rst, clk, clko, cyc, phi11, phi12, phi81, phi82, nmi, irq, abort, e, mx, rdy, be, vpa, vda, mlb, vpb, rw, ad, db, dw, err_i, rty_i);
+parameter SUPPORT_TRIBYTES = 1'b0;
+parameter STORE_SKIPPING = 1'b1;
+parameter EXTRA_LONG_BRANCHES = 1'b1;
+parameter RESET1 = 6'd0;
+parameter IFETCH1 = 6'd1;
+parameter IFETCH2 = 6'd2;
+parameter IFETCH3 = 6'd3;
+parameter IFETCH4 = 6'd4;
+parameter DECODE1 = 6'd5;
+parameter DECODE2 = 6'd6;
+parameter DECODE3 = 6'd7;
+parameter DECODE4 = 6'd8;
+parameter STORE1 = 6'd9;
+parameter STORE2 = 6'd10;
+parameter JSR161 = 6'd11;
+parameter RTS1 = 6'd12;
+parameter IY3 = 6'd13;
+parameter BSR1 = 6'd14;
+parameter BYTE_IX5 = 6'd15;
+parameter BYTE_IY5 = 6'd16;
+parameter WAIT_DHIT = 6'd17;
+parameter BYTE_CALC = 6'd18;
+parameter BUS_ERROR = 6'd19;
+parameter LOAD_MAC1 = 6'd20;
+parameter LOAD_MAC2 = 6'd21;
+parameter LOAD_MAC3 = 6'd22;
+parameter MVN3 = 6'd23;
+parameter IFETCH0 = 6'd24;
+parameter LOAD_DCACHE = 6'd26;
+parameter LOAD_ICACHE = 6'd27;
+parameter LOAD_IBUF1 = 6'd28;
+parameter LOAD_IBUF2 = 6'd29;
+parameter LOAD_IBUF3 = 6'd30;
+parameter ICACHE1 = 6'd31;
+parameter IBUF1 = 6'd32;
+parameter DCACHE1 = 6'd33;
+parameter HALF_CALC = 6'd35;
+parameter MVN816 = 6'd36;
+
+input rst;
+input clk;
+output clko;
+output reg [4:0] cyc;
+output phi11;
+output phi12;
+output phi81;
+output phi82;
+input nmi;
+input irq;
+input abort;
+output e;
+output mx;
+input rdy;
+input be;
+output reg vpa;
+output reg vda;
+output reg mlb;
+output reg vpb;
+output tri rw;
+output tri [23:0] ad;
+input [7:0] db;
+output[7:0] dw;
+input err_i;
+input rty_i;
+
+parameter TRUE = 1'b1;
+parameter FALSE = 1'b0;
+
+reg [31:0] phi1r,phi2r;
+reg rwo;
+reg [23:0] ado;
+reg [7:0] dbo;
+
+reg [7:0] dbi;
+reg pg2;
+reg [5:0] state;
+reg [5:0] retstate;
+reg [31:0] ir;
+wire [8:0] ir9 = {pg2,ir[7:0]};
+reg [23:0] pc,opc;
+reg [15:0] dpr;		// direct page register
+reg [7:0] dbr;		// data bank register
+reg [15:0] x,y,acc,sp;
+reg [15:0] tmp;
+wire [15:0] acc16 = acc;
+wire [7:0] acc8=acc[7:0];
+wire [7:0] x8=x[7:0];
+wire [7:0] y8=y[7:0];
+wire [15:0] x16 = x[15:0];
+wire [15:0] y16 = y[15:0];
+wire [15:0] acc_dec = acc - 16'd1;
+wire [15:0] acc_inc = acc + 16'd1;
+wire [15:0] x_dec = x - 16'd1;
+wire [15:0] x_inc = x + 16'd1;
+wire [15:0] y_dec = y - 16'd1;
+wire [15:0] y_inc = y + 16'd1;
+wire [15:0] sp_dec = sp - 16'd1;
+wire [15:0] sp_inc = sp + 16'd1;
+wire [15:0] sp_dec2 = sp - 16'd2;
+reg gie;	// global interrupt enable (set when sp is loaded)
+reg hwi;	// hardware interrupt indicator
+reg im;
+reg cf,vf,nf,zf,df,em,bf;
+reg m816;
+reg x_bit,m_bit;
+wire m16 = m816 & ~m_bit;
+wire xb16 = m816 & ~x_bit;
+wire [7:0] sr8 = m816 ? {nf,vf,m_bit,x_bit,df,im,zf,cf} : {nf,vf,1'b0,bf,df,im,zf,cf};
+reg nmi1,nmi_edge;
+reg wai;
+reg [7:0] b8;
+reg [15:0] b16;
+reg [7:0] b24;
+reg [8:0] res8;
+reg [16:0] res16;
+wire resc8 = res8[8];
+wire resc16 = res16[16];
+wire resz8 = ~|res8[7:0];
+wire resz16 = ~|res16[15:0];
+wire resn8 = res8[7];
+wire resn16 = res16[15];
+reg [23:0] radr;
+reg [23:0] wadr;
+reg [23:0] wdat;
+wire [7:0] rdat;
+reg [4:0] load_what;
+reg [5:0] store_what;
+reg [15:0] tmp16;
+reg first_ifetch;
+reg [23:0] derr_address;
+
+reg [8:0] intno;
+reg isBusErr;
+reg isBrk,isMove,isSts;
+reg isMove816;
+reg isRTI,isRTL,isRTS;
+reg isRMW;
+reg isSub;
+reg isJsrIndx,isJsrInd;
+reg isIY,isIY24,isI24;
+reg isTribyte;
+
+wire isCmp = ir9==`CPX_ZPX || ir9==`CPX_ABS ||
+			 ir9==`CPY_ZPX || ir9==`CPY_ABS;
+wire isRMW8 =
+			 ir9==`ASL_ZP || ir9==`ROL_ZP || ir9==`LSR_ZP || ir9==`ROR_ZP || ir9==`INC_ZP || ir9==`DEC_ZP ||
+			 ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
+			 ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
+			 ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
+			 ir9==`TRB_ZP || ir9==`TRB_ZPX || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ZPX || ir9==`TSB_ABS;
+wire isBranch = ir9==`BRA || ir9==`BEQ || ir9==`BNE || ir9==`BVS || ir9==`BVC || ir9==`BMI || ir9==`BPL || ir9==`BCS || ir9==`BCC;
+
+// Registerable decodes
+// The following decodes can be registered because they aren't needed until at least the cycle after
+// the DECODE stage.
+
+always @(posedge clk)
+	if (state==RESET1)
+		isBrk <= `TRUE;
+	else if (state==DECODE1||state==DECODE2||state==DECODE3||state==DECODE4) begin
+		isRMW <= isRMW8;
+		isRTI <= ir9==`RTI;
+		isRTL <= ir9==`RTL;
+		isRTS <= ir9==`RTS;
+		isBrk <= ir9==`BRK || ir9==`COP;
+		isMove <= ir9==`MVP || ir9==`MVN;
+		isJsrIndx <= ir9==`JSR_INDX;
+		isJsrInd <= ir9==`JSR_IND;
+	end
+
+assign mx = clk ? m_bit : x_bit;
+assign e = ~m816;
+
+wire [15:0] bcaio;
+wire [15:0] bcao;
+wire [15:0] bcsio;
+wire [15:0] bcso;
+wire bcaico,bcaco,bcsico,bcsco;
+wire bcaico8,bcaco8,bcsico8,bcsco8;
+
+`ifdef SUPPORT_BCD
+BCDAdd4 ubcdai1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcaio),.c(bcaico),.c8(bcaico8));
+BCDAdd4 ubcda2 (.ci(cf),.a(acc16),.b(b8),.o(bcao),.c(bcaco),.c8(bcaco8));
+BCDSub4 ubcdsi1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcsio),.c(bcsico),.c8(bcsico8));
+BCDSub4 ubcds2 (.ci(cf),.a(acc16),.b(b8),.o(bcso),.c(bcsco),.c8(bcsco8));
+`endif
+
+wire [7:0] dati = db;
+
+// Evaluate branches
+// 
+reg takb;
+always @(ir9 or cf or vf or nf or zf)
+case(ir9)
+`BEQ:	takb <= zf;
+`BNE:	takb <= !zf;
+`BPL:	takb <= !nf;
+`BMI:	takb <= nf;
+`BCS:	takb <= cf;
+`BCC:	takb <= !cf;
+`BVS:	takb <= vf;
+`BVC:	takb <= !vf;
+`BRA:	takb <= 1'b1;
+`BRL:	takb <= 1'b1;
+default:	takb <= 1'b0;
+endcase
+
+reg [23:0] ia;
+wire [23:0] mvnsrc_address	= {ir[23:16],x16};
+wire [23:0] mvndst_address	= {ir[15: 8],y16};
+wire [23:0] iapy8 			= ia + y16;		// Don't add in abs8, already included with ia
+wire [23:0] zp_address 		= {8'h00,ir[15:8]} + dpr;
+wire [23:0] zpx_address 	= {{16'h00,ir[15:8]} + x16} + dpr;
+wire [23:0] zpy_address	 	= {{16'h00,ir[15:8]} + y16} + dpr;
+wire [23:0] abs_address 	= {dbr,ir[23:8]};
+wire [23:0] absx_address 	= {dbr,ir[23:8] + x16};	// simulates 64k bank wrap-around
+wire [23:0] absy_address 	= {dbr,ir[23:8] + y16};
+wire [23:0] al_address		= {ir[31:8]};
+wire [23:0] alx_address		= {ir[31:8] + x16};
+
+wire [23:0] dsp_address = m816 ? {8'h00,sp + ir[15:8]} : {16'h0001,sp[7:0]+ir[15:8]};
+reg [23:0] vect;
+
+assign rw = be ? rwo : 1'bz;
+assign ad = be ? ado : {24{1'bz}};
+assign dw = rwo ? {8{1'bz}} : be ? dbo : {8{1'bz}};
+
+reg [31:0] phi11r,phi12r,phi81r,phi82r;
+assign phi11 = phi11r[31];
+assign phi12 = phi12r[31];
+assign phi81 = phi81r[31];
+assign phi82 = phi82r[31];
+
+always @(posedge clk)
+if (~rst) begin
+	cyc <= 5'd0;
+	phi11r <= 32'b01111111111111100000000000000000;
+	phi12r <= 32'b00000000000000000111111111111110;
+	phi81r <= 32'b01110000011100000111000001110000;
+	phi82r <= 32'b00000111000001110000011100000111;
+end
+else begin
+	cyc <= cyc + 5'd1;
+	phi11r <= {phi11r[30:0],phi11r[31]};
+	phi12r <= {phi12r[30:0],phi12r[31]};
+	phi81r <= {phi81r[30:0],phi81r[31]};
+	phi82r <= {phi82r[30:0],phi82r[31]};
+end
+
+// Detect a single byte opcode
+function isOneByte;
+input [7:0] ir;
+casex(ir)
+8'hx8:	isOneByte = TRUE;
+8'hxA:	isOneByte = TRUE;
+8'hxB: isOneByte = TRUE;
+`RTI,`RTS:	isOneByte = TRUE;
+default:	isOneByte = FALSE;
+endcase
+endfunction
+
+// Detect double byte opcode
+function isTwoBytes;
+input [7:0] ir;
+input m16;
+input xb16;
+casex(ir)
+`BRK,`COP:	isTwoBytes = TRUE;
+8'hx1:	isTwoBytes = TRUE;
+8'hx3:	isTwoBytes = TRUE;
+8'hx5:	isTwoBytes = TRUE;
+8'hx6:	isTwoBytes = TRUE;
+8'hx7:	isTwoBytes = TRUE;
+`BPL,`BMI,`BVS,`BVC,`BCS,`BCC,`BEQ,`BNE,`BRA:	isTwoBytes = TRUE;
+`LDY_IMM,`CPY_IMM,`CPX_IMM,`LDX_IMM:			isTwoBytes = !xb16;
+`ORA_I,`AND_I,`EOR_I,`LDA_I,`CMP_I,`STA_I,`ADC_I,`SBC_I,`PEI:
+			isTwoBytes = TRUE;
+`REP,`SEP:	isTwoBytes = TRUE;
+`TSB_ZPX,`TRB_ZPX,`BIT_ZP,`BIT_ZPX,`STZ_ZP,`STZ_ZPX,`STY_ZP,`STY_ZPX,
+`LDY_ZP,`LDY_ZPX,`CPY_ZP,`CPX_ZP:
+			isTwoBytes = TRUE;
+`ORA_IMM,`AND_IMM,`EOR_IMM,`ADC_IMM,`SBC_IMM,`CMP_IMM,`LDA_IMM,`BIT_IMM:
+			isTwoBytes = !m16;
+default:	isTwoBytes = FALSE;
+endcase
+endfunction
+
+function isThreeBytes;
+input [7:0] ir;
+input m16;
+input xb16;
+casex(ir)
+`JSR:	isThreeBytes = TRUE;
+`PER,`BRL:	isThreeBytes = TRUE;
+`MVP,`MVN,`PEA:	isThreeBytes = TRUE;
+`LDY_IMM,`CPY_IMM,`CPX_IMM,`LDX_IMM:			isThreeBytes = xb16;
+`ORA_IMM,`AND_IMM,`EOR_IMM,`ADC_IMM,`SBC_IMM,`CMP_IMM,`LDA_IMM,`BIT_IMM:
+			isThreeBytes = m16;
+8'bxxx11001:	isThreeBytes = TRUE;
+`TSB_ABS,`TRB_ABS,`BIT_ABS,`BIT_ABSX,
+`JMP,`JMP_IND,`JMP_INDX,`STY_ABS,`STZ_ABS,`LDY_ABS,`LDY_ABSX,`CPY_ABS,
+`CPX_ABS,`JSR_INDX:	isThreeBytes = TRUE;
+8'hxD,8'hxE:	isThreeBytes = TRUE;
+default:	isThreeBytes = FALSE;
+endcase
+endfunction
+
+//-----------------------------------------------------------------------------
+// Clock control
+// - reset or NMI reenables the clock
+// - this circuit must be under the clk_i domain
+//-----------------------------------------------------------------------------
+//
+reg cpu_clk_en;
+reg clk_en;
+wire clkx;
+//FIXME TODO XXX BUFGCE u20 (.CE(cpu_clk_en), .I(clk), .O(clkx) );
+assign clkx = clk;
+assign clko = clkx;
+//assign clkx = clk;
+
+always @(posedge clk)
+if (~rst) begin
+	cpu_clk_en <= 1'b1;
+	nmi1 <= 1'b0;
+end
+else begin
+	nmi1 <= nmi;
+	if (nmi)
+		cpu_clk_en <= 1'b1;
+	else
+		cpu_clk_en <= clk_en;
+end
+
+reg abort1;
+reg abort_edge;
+reg [2:0] imcd;	// interrupt mask enable count down
+
+always @(posedge clkx)
+if (~rst) begin
+	vpa <= `FALSE;
+	vda <= `FALSE;
+	vpb <= `TRUE;
+	rwo <= `TRUE;
+	ado <= 24'h000000;
+	dbo <= 8'h00;
+	nmi_edge <= 1'b0;
+	wai <= 1'b0;
+	pg2 <= 1'b0;
+	ir <= 8'hEA;
+	cf <= 1'b0;
+	df <= 1'b0;
+	m816 <= 1'b0;
+	m_bit <= 1'b1;
+	x_bit <= 1'b1;
+	pc <= 24'h00FFF0;		// set high-order pc to zero
+	vect <= `BYTE_RST_VECT;
+	state <= RESET1;
+	em <= 1'b1;
+	dbr <= 8'h00;
+	dpr <= 16'h0000;
+	clk_en <= 1'b1;
+	im <= `TRUE;
+	gie <= 1'b0;
+	isIY <= 1'b0;
+	isIY24 <= 1'b0;
+	isI24 <= `FALSE;
+	load_what <= `NOTHING;
+	abort_edge <= 1'b0;
+	abort1 <= 1'b0;
+	imcd <= 3'b111;
+end
+else begin
+abort1 <= abort;
+if (~abort & abort1)
+	abort_edge <= 1'b1;
+if (~nmi & nmi1)
+	nmi_edge <= 1'b1;
+if (~nmi|~nmi1)
+	clk_en <= 1'b1;
+case(state)
+RESET1:
+	begin
+		radr <= `BYTE_RST_VECT;
+		load_what <= `PC_70;
+		state <= LOAD_MAC1;
+	end
+IFETCH0:
+	moveto_ifetch();
+IFETCH1:
+	if (rdy) begin
+		if (imcd != 3'b111)
+			imcd <= {imcd[1:0],1'b0};
+		if (imcd == 3'b000) begin
+			imcd <= 3'b111;
+			im <= 1'b0;
+		end
+		vect <= m816 ? `BRK_VECT_816 : `BYTE_IRQ_VECT;
+		hwi <= `FALSE;
+		isBusErr <= `FALSE;
+		pg2 <= `FALSE;
+		isIY <= `FALSE;
+		isIY24 <= `FALSE;
+		isTribyte <= `FALSE;
+		store_what <= m16 ? `STW_DEF70 : `STW_DEF;
+		ir[7:0] <= db;
+		opc <= pc;
+		if (nmi_edge | ~irq)
+			wai <= 1'b0;
+		if (abort_edge) begin
+			pc <= opc;
+			ir[7:0] <= `BRK;
+			abort_edge <= 1'b0;
+			hwi <= `TRUE;
+			vect <= m816 ? `ABT_VECT_816 : `BYTE_ABT_VECT;
+			vect[23:16] <= 8'h00;
+			next_state(DECODE2);
+		end
+		else if (nmi_edge & gie) begin
+			ir[7:0] <= `BRK;
+			nmi_edge <= 1'b0;
+			hwi <= `TRUE;
+			vect <= m816 ? `NMI_VECT_816 : `BYTE_NMI_VECT;
+			vect[23:16] <= 8'h00;
+			next_state(DECODE2);
+		end
+		else if (~irq & gie & ~im) begin
+			ir[7:0] <= `BRK;
+			hwi <= `TRUE;
+			if (m816)
+				vect <= `IRQ_VECT_816;
+			next_state(DECODE2);
+		end
+		else if (!wai) begin
+			ado <= pc + 24'd1;
+			pc <= pc + 24'd1;
+			// Is it more than one byte ?
+			if (!isOneByte(db)) begin
+				vpa <= TRUE;
+				next_state(IFETCH2);
+			end
+			else begin
+				vpa <= FALSE;
+				next_state(DECODE1);
+			end
+			vda <= FALSE;
+		end
+		else
+			next_state(IFETCH1);
+		if (!abort_edge) begin
+		case(ir[7:0])
+		// Note the break flag is not affected by SEP/REP
+		// Setting the index registers to eight bit zeros out the upper part of the register.
+		`SEP:
+			begin
+				cf <= cf | ir[8];
+				zf <= zf | ir[9];
+				im <= im | ir[10];
+				df <= df | ir[11];
+				if (m816) begin
+					x_bit <= x_bit | ir[12];
+					m_bit <= m_bit | ir[13];
+					//if (ir[13]) acc[31:8] <= 24'd0;
+					if (ir[12]) begin
+						x[15:8] <= 8'd0;
+						y[15:8] <= 8'd0;
+					end
+				end
+				vf <= vf | ir[14];
+				nf <= nf | ir[15];
+			end
+		`REP:
+			begin
+				cf <= cf & ~ir[8];
+				zf <= zf & ~ir[9];
+				im <= im & ~ir[10];
+				df <= df & ~ir[11];
+				if (m816) begin
+					x_bit <= x_bit & ~ir[12];
+					m_bit <= m_bit & ~ir[13];
+				end
+				vf <= vf & ~ir[14];
+				nf <= nf & ~ir[15];
+			end
+		`XBA:
+			begin
+				acc[15:0] <= res16[15:0];
+				nf <= resn8;
+				zf <= resz8;
+			end
+		`TAY,`TXY,`DEY,`INY:		if (xb16) begin y[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end	else begin y[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`TAX,`TYX,`TSX,`DEX,`INX:	if (xb16) begin x[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end else begin x[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`TSA,`TYA,`TXA,`INA,`DEA:	if (m16) begin acc[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end else begin acc[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`TAS,`TXS: begin if (m816) sp <= res16[15:0]; else sp <= {8'h01,res8[7:0]}; gie <= `TRUE; end
+		`TCD:	begin dpr <= res16[15:0]; end
+		`TDC:	begin acc[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end
+		`ADC_IMM:
+			begin
+				if (m16) begin
+					acc[15:0] <= df ? bcaio : res16[15:0];
+					cf <= df ? bcaico : resc16;
+//						vf <= resv8;
+					vf <= (res16[15] ^ b16[15]) & (1'b1 ^ acc[15] ^ b16[15]);
+					nf <= df ? bcaio[15] : resn16;
+					zf <= df ? bcaio==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcaio[7:0] : res8[7:0];
+					cf <= df ? bcaico8 : resc8;
+//						vf <= resv8;
+					vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
+					nf <= df ? bcaio[7] : resn8;
+					zf <= df ? bcaio[7:0]==8'h00 : resz8;
+				end
+			end
+		`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_IYL,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I,`ADC_IL,`ADC_AL,`ADC_ALX,`ADC_DSP,`ADC_DSPIY:
+			begin
+				if (m16) begin
+					acc[15:0] <= df ? bcao : res16[15:0];
+					cf <= df ? bcaco : resc16;
+					vf <= (res16[15] ^ b16[15]) & (1'b1 ^ acc[15] ^ b16[15]);
+					nf <= df ? bcao[15] : resn16;
+					zf <= df ? bcao==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcao[7:0] : res8[7:0];
+					cf <= df ? bcaco8 : resc8;
+					vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
+					nf <= df ? bcao[7] : resn8;
+					zf <= df ? bcao[7:0]==8'h00 : resz8;
+				end
+			end
+		`SBC_IMM:
+			begin
+				if (m16) begin
+					acc[15:0] <= df ? bcsio : res16[15:0];
+					cf <= ~(df ? bcsico : resc16);
+					vf <= (1'b1 ^ res16[15] ^ b16[15]) & (acc[15] ^ b16[15]);
+					nf <= df ? bcsio[15] : resn16;
+					zf <= df ? bcsio==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcsio[7:0] : res8[7:0];
+					cf <= ~(df ? bcsico8 : resc8);
+					vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
+					nf <= df ? bcsio[7] : resn8;
+					zf <= df ? bcsio[7:0]==8'h00 : resz8;
+				end
+			end
+		`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_IYL,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I,`SBC_IL,`SBC_AL,`SBC_ALX,`SBC_DSP,`SBC_DSPIY:
+			begin
+				if (m16) begin
+					acc[15:0] <= df ? bcso : res16[15:0];
+					vf <= (1'b1 ^ res16[15] ^ b16[15]) & (acc[15] ^ b16[15]);
+					cf <= ~(df ? bcsco : resc16);
+					nf <= df ? bcso[15] : resn16;
+					zf <= df ? bcso==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcso[7:0] : res8[7:0];
+					vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
+					cf <= ~(df ? bcsco8 : resc8);
+					nf <= df ? bcso[7] : resn8;
+					zf <= df ? bcso[7:0]==8'h00 : resz8;
+				end
+			end
+		`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_IYL,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,`CMP_IL,`CMP_AL,`CMP_ALX,`CMP_DSP,`CMP_DSPIY:
+				if (m16) begin cf <= ~resc16; nf <= resn16; zf <= resz16; end else begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
+		`CPX_IMM,`CPX_ZP,`CPX_ABS,
+		`CPY_IMM,`CPY_ZP,`CPY_ABS:
+				if (xb16) begin cf <= ~resc16; nf <= resn16; zf <= resz16; end else begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
+		`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
+				if (m16) begin nf <= b16[15]; vf <= b16[14]; zf <= resz16; end else begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
+		`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
+			if (m16) begin zf <= resz16; end else begin zf <= resz8; end
+		`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_IYL,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,`LDA_IL,`LDA_AL,`LDA_ALX,`LDA_DSP,`LDA_DSPIY,
+		`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_IYL,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,`AND_IL,`AND_AL,`AND_ALX,`AND_DSP,`AND_DSPIY,
+		`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_IYL,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,`ORA_IL,`ORA_AL,`ORA_ALX,`ORA_DSP,`ORA_DSPIY,
+		`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_IYL,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I,`EOR_IL,`EOR_AL,`EOR_ALX,`EOR_DSP,`EOR_DSPIY:
+			if (m16) begin acc[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end
+			else begin acc[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`ASL_ACC:	if (m16) begin acc[15:0] <= res16[15:0]; cf <= resc16; nf <= resn16; zf <= resz16; end else begin acc[7:0] <= res8[7:0]; cf <= resc8; nf <= resn8; zf <= resz8; end
+		`ROL_ACC:	if (m16) begin acc[15:0] <= res16[15:0]; cf <= resc16; nf <= resn16; zf <= resz16; end else begin acc[7:0] <= res8[7:0]; cf <= resc8; nf <= resn8; zf <= resz8; end
+		`LSR_ACC:	if (m16) begin acc[15:0] <= res16[15:0]; cf <= resc16; nf <= resn16; zf <= resz16; end else begin acc[7:0] <= res8[7:0]; cf <= resc8; nf <= resn8; zf <= resz8; end
+		`ROR_ACC:	if (m16) begin acc[15:0] <= res16[15:0]; cf <= resc16; nf <= resn16; zf <= resz16; end else begin acc[7:0] <= res8[7:0]; cf <= resc8; nf <= resn8; zf <= resz8; end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: if (m16) begin cf <= resc16; nf <= resn16; zf <= resz16; end else begin cf <= resc8; nf <= resn8; zf <= resz8; end
+		`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: if (m16) begin cf <= resc16; nf <= resn16; zf <= resz16; end else begin cf <= resc8; nf <= resn8; zf <= resz8; end
+		`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: if (m16) begin cf <= resc16; nf <= resn16; zf <= resz16; end else begin cf <= resc8; nf <= resn8; zf <= resz8; end
+		`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: if (m16) begin cf <= resc16; nf <= resn16; zf <= resz16; end else begin cf <= resc8; nf <= resn8; zf <= resz8; end
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: if (m16) begin nf <= resn16; zf <= resz16; end else begin nf <= resn8; zf <= resz8; end
+		`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: if (m16) begin nf <= resn16; zf <= resz16; end else begin nf <= resn8; zf <= resz8; end
+		`PLA:	if (m16) begin acc[15:0] <= res16[15:0]; zf <= resz16; nf <= resn16; end else begin acc[7:0] <= res8[7:0]; zf <= resz8; nf <= resn8; end
+		`PLX:	if (xb16) begin x[15:0] <= res16[15:0]; zf <= resz16; nf <= resn16; end else begin x[7:0] <= res8[7:0]; zf <= resz8; nf <= resn8; end
+		`PLY:	if (xb16) begin y[15:0] <= res16[15:0]; zf <= resz16; nf <= resn16; end else begin y[7:0] <= res8[7:0]; zf <= resz8; nf <= resn8; end
+		`PLB:	begin dbr <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`PLD:	begin dpr <= res16[15:0]; nf <= resn16; zf <= resz16; end
+		`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:	if (xb16) begin x[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end else begin x[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:	if (xb16) begin y[15:0] <= res16[15:0]; nf <= resn16; zf <= resz16; end else begin y[7:0] <= res8[7:0]; nf <= resn8; zf <= resz8; end
+		endcase
+		end	// abort_edge
+	end
+IFETCH2:
+	if (rdy) begin
+		ir[15:8] <= db;
+		ado <= pc + 24'd1;
+		pc <= pc + 24'd1;
+		if ((isBranch && db==8'hFF && EXTRA_LONG_BRANCHES) ||
+		   (!isTwoBytes(ir,m16,xb16))) begin
+			vpa <= TRUE;
+			next_state(IFETCH3);
+		end
+		else begin
+			vpa <= FALSE;
+			next_state(DECODE2);
+		end
+		vda <= FALSE;
+	end
+IFETCH3:
+	if (rdy) begin
+		ir[23:16] <= db;
+		ado <= pc + 24'd1;
+		pc <= pc + 24'd1;
+		if (!isThreeBytes(ir,m16,xb16)) begin
+			vpa <= TRUE;
+			next_state(IFETCH4);
+		end
+		else begin
+			vpa <= FALSE;
+			next_state(DECODE3);
+		end
+		vda <= FALSE;
+	end
+IFETCH4:
+	if (rdy) begin
+		ir[31:24] <= db;
+		ado <= pc + 24'd1;
+		pc <= pc + 24'd1;
+		next_state(DECODE4);
+		vpa <= FALSE;
+		vda <= FALSE;
+	end
+
+// Decode single byte opcodes
+DECODE1:
+	if (rdy) begin
+		next_state(IFETCH1);
+		opcode_read();
+		case(ir[7:0])
+		`SEP:	;	// see byte_ifetch
+		`REP:	;
+		// XBA cannot be done in the ifetch stage because it'd repeat when there
+		// was a cache miss, causing the instruction to be done twice.
+		`XBA:	
+			begin
+				res16 <= {acc[7:0],acc[15:8]};
+				res8 <= acc[15:8];	// for flag settings
+			end
+		`STP:	begin clk_en <= 1'b0; end
+		// Switching the processor mode always zeros out the upper part of the index registers.
+		// switching to emulation mode sets 8 bit memory/indexes
+		`XCE:	begin
+					m816 <= ~cf;
+					cf <= ~m816;
+					if (cf) begin		
+						m_bit <= 1'b1;
+						x_bit <= 1'b1;
+						sp[15:8] <= 8'h01;
+					end
+					x[15:8] <= 8'd0;
+					y[15:8] <= 8'd0;
+				end
+//		`NOP:	;	// may help routing
+		`CLC:	begin cf <= 1'b0; end
+		`SEC:	begin cf <= 1'b1; end
+		`CLV:	begin vf <= 1'b0; end
+		`CLI:	begin imcd <= 3'b110; end
+		`SEI:	begin im <= 1'b1; end
+		`CLD:	begin df <= 1'b0; end
+		`SED:	begin df <= 1'b1; end
+		`WAI:	begin wai <= 1'b1; end
+		`DEX:	begin res8 <= x_dec[7:0]; res16 <= x_dec[15:0]; end
+		`INX:	begin res8 <= x_inc[7:0]; res16 <= x_inc[15:0]; end
+		`DEY:	begin res8 <= y_dec[7:0]; res16 <= y_dec[15:0]; end
+		`INY:	begin res8 <= y_inc[7:0]; res16 <= y_inc[15:0]; end
+		`DEA:	begin res8 <= acc_dec[7:0]; res16 <= acc_dec[15:0]; end
+		`INA:	begin res8 <= acc_inc[7:0]; res16 <= acc_inc[15:0]; end
+		`TSX,`TSA:	begin res8 <= sp[7:0]; res16 <= sp[15:0]; end
+		`TXS,`TXA,`TXY:	begin res8 <= x[7:0]; res16 <= xb16 ? x[15:0] : {8'h00,x8}; end
+		`TAX,`TAY:	begin res8 <= acc[7:0]; res16 <= m16 ? acc[15:0] : {8'h00,acc8}; end
+		`TAS:	begin res8 <= acc[7:0]; res16 <= acc[15:0]; end
+		`TYA,`TYX:	begin res8 <= y[7:0]; res16 <= xb16 ? y[15:0] : {8'h00,y8}; end
+		`TDC:		begin res16 <= dpr; end
+		`TCD:		begin res16 <= acc[15:0]; end
+		`ASL_ACC:	begin res8 <= {acc8,1'b0}; res16 <= {acc16,1'b0}; end
+		`ROL_ACC:	begin res8 <= {acc8,cf}; res16 <= {acc16,cf}; end
+		`LSR_ACC:	begin res8 <= {acc8[0],1'b0,acc8[7:1]}; res16 <= {acc16[0],1'b0,acc16[15:1]}; end
+		`ROR_ACC:	begin res8 <= {acc8[0],cf,acc8[7:1]}; res16 <= {acc16[0],cf,acc16[15:1]}; end
+		`RTS,`RTL:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				data_nack();
+				load_what <= `PC_70;
+				state <= LOAD_MAC1;
+			end
+		`RTI:	begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				data_nack();
+				load_what <= `SR_70;
+				state <= LOAD_MAC1;
+				end
+		`PHP:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				data_nack();
+				store_what <= `STW_SR70;
+				state <= STORE1;
+			end
+		`PHA:
+begin
+	if (m816) begin
+		if (m16) begin
+			radr <= {8'h00,sp_dec[15:0]};
+			wadr <= {8'h00,sp_dec[15:0]};
+			store_what <= `STW_ACC70;
+			sp <= sp_dec2;
+		end
+		else begin
+			radr <= {8'h00,sp[15:0]};
+			wadr <= {8'h00,sp[15:0]};
+			store_what <= `STW_ACC8;
+			sp <= sp_dec;
+		end
+	end
+	else begin
+		radr <= {16'h01,sp[7:0]};
+		wadr <= {16'h01,sp[7:0]};
+		store_what <= `STW_ACC8;
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+	state <= STORE1;
+end
+//		tsk_push(`STW_ACC8,`STW_ACC70,m16);
+		`PHX:	tsk_push(`STW_X8,`STW_X70,xb16);
+		`PHY:	tsk_push(`STW_Y8,`STW_Y70,xb16);
+		`PLP:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				load_what <= `SR_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`PLA:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				load_what <= m16 ? `HALF_71S : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`PLX,`PLY:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				load_what <= xb16 ? `HALF_71S : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`PHB:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= `STW_DBR;
+				data_nack();
+				state <= STORE1;
+			end
+		`PHD:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= `STW_DPR158;
+				data_nack();
+				state <= STORE1;
+			end
+		`PHK:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= `STW_PC2316;
+				data_nack();
+				state <= STORE1;
+			end
+		`PLB:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				load_what <= `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`PLD:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end				load_what <= `HALF_71S;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		default:
+			begin
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		endcase
+	end
+
+// Decode 2-byte opcodes
+DECODE2:
+	if (rdy) begin
+		case(ir[7:0])
+		// Handle # mode
+		`LDA_IMM:
+			begin
+				res8 <= ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`LDX_IMM,`LDY_IMM:
+			begin
+				res8 <= ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`ADC_IMM:
+			begin
+				res8 <= acc8 + ir[15:8] + {7'b0,cf};
+				b8 <= ir[15:8];		// for overflow calc
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`SBC_IMM:
+			begin
+				res8 <= acc8 - ir[15:8] - {7'b0,~cf};
+				$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
+				b8 <= ir[15:8];		// for overflow calc
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`AND_IMM,`BIT_IMM:
+			begin
+				res8 <= acc8 & ir[15:8];
+				b8 <= ir[15:8];	// for bit flags
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`ORA_IMM:
+			begin
+				res8 <= acc8 | ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`EOR_IMM:
+			begin
+				res8 <= acc8 ^ ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CMP_IMM:
+			begin
+				res8 <= acc8 - ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CPX_IMM:
+			begin
+				res8 <= x8 - ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CPY_IMM:
+			begin
+				res8 <= y8 - ir[15:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		// Handle zp mode
+		`LDA_ZP:
+			begin
+				data_nack();
+				radr <= zp_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				state <= LOAD_MAC1;
+			end
+		`LDX_ZP,`LDY_ZP:
+			begin
+				radr <= zp_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
+		`BIT_ZP,
+		`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`TRB_ZP,`TSB_ZP:
+			begin
+				radr <= zp_address;
+				wadr <= zp_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`INC_ZP,`DEC_ZP:
+			begin
+				radr <= zp_address;
+				wadr <= zp_address;
+				isTribyte <= zp_address[23:4]==16'h2 && SUPPORT_TRIBYTES;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`CPX_ZP,`CPY_ZP:
+			begin
+				radr <= zp_address;
+				load_what <= xb16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ZP:
+			begin
+				wadr <= zp_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STX_ZP:
+			begin
+				wadr <= zp_address;
+				store_what <= xb16 ? `STW_X70 : `STW_X8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STY_ZP:
+			begin
+				wadr <= zp_address;
+				store_what <= xb16 ? `STW_Y70 : `STW_Y8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STZ_ZP:
+			begin
+				wadr <= zp_address;
+				store_what <= m16 ? `STW_Z70 : `STW_Z8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle zp,x mode
+		`LDA_ZPX:
+			begin
+				radr <= zpx_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`LDY_ZPX:
+			begin
+				radr <= zpx_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
+		`BIT_ZPX,
+		`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
+			begin
+				radr <= zpx_address;
+				wadr <= zpx_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ZPX:
+			begin
+				wadr <= zpx_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STY_ZPX:
+			begin
+				wadr <= zpx_address;
+				store_what <= xb16 ? `STW_Y70 : `STW_Y8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STZ_ZPX:
+			begin
+				wadr <= zpx_address;
+				store_what <= m16 ? `STW_Z70 : `STW_Z8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle zp,y
+		`LDX_ZPY:
+			begin
+				radr <= zpy_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STX_ZPY:
+			begin
+				wadr <= zpy_address;
+				store_what <= xb16 ? `STW_X70 : `STW_X8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle (zp,x)
+		`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
+			begin
+				radr <= zpx_address;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		// Handle (zp),y
+		`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
+			begin
+				radr <= zp_address;
+				isIY <= `TRUE;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		// Handle d,sp
+		`LDA_DSP:
+			begin
+				radr <= dsp_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_DSP,`SBC_DSP,`CMP_DSP,`ORA_DSP,`AND_DSP,`EOR_DSP:
+			begin
+				radr <= dsp_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_DSP:
+			begin
+				wadr <= dsp_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle (d,sp),y
+		`ADC_DSPIY,`SBC_DSPIY,`CMP_DSPIY,`ORA_DSPIY,`AND_DSPIY,`EOR_DSPIY,`LDA_DSPIY,`STA_DSPIY:
+			begin
+				radr <= dsp_address;
+				isIY <= `TRUE;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		// Handle [zp],y
+		`ADC_IYL,`SBC_IYL,`AND_IYL,`ORA_IYL,`EOR_IYL,`CMP_IYL,`LDA_IYL,`STA_IYL:
+			begin
+				radr <= zp_address;
+				isIY24 <= `TRUE;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		// Handle [zp]
+		`ADC_IL,`SBC_IL,`AND_IL,`ORA_IL,`EOR_IL,`CMP_IL,`LDA_IL,`STA_IL:
+			begin
+				isI24 <= `TRUE;
+				radr <= zp_address;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		// Handle (zp)
+		`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I,`PEI:
+			begin
+				radr <= zp_address;
+				load_what <= `IA_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`BRK:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
+				data_nack();
+				state <= STORE1;
+				bf <= !hwi;
+			end
+		`COP:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
+				state <= STORE1;
+				vect <= m816 ? `COP_VECT_816 : `BYTE_COP_VECT;
+				data_nack();
+			end
+		`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
+				begin
+					vpa <= `TRUE;
+					vda <= `TRUE;
+					if (takb) begin
+						pc <= pc + {{16{ir[15]}},ir[15:8]};
+						ado <= pc + {{16{ir[15]}},ir[15:8]};
+					end
+					next_state(IFETCH1);
+				end
+			//end
+		default:
+			begin
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		endcase
+	end
+
+DECODE3:
+	if (rdy) begin
+		case(ir[7:0])
+		// Handle # mode
+		`LDA_IMM:
+			begin
+				res16 <= ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`LDX_IMM,`LDY_IMM:
+			begin
+				res16 <= ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`ADC_IMM:
+			begin
+				res16 <= acc16 + ir[23:8] + {15'b0,cf};
+				b16 <= ir[23:8];		// for overflow calc
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`SBC_IMM:
+			begin
+				res16 <= acc16 - ir[23:8] - {15'b0,~cf};
+				b16 <= ir[23:8];		// for overflow calc
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`AND_IMM,`BIT_IMM:
+			begin
+				res16 <= acc16 & ir[23:8];
+				b16 <= ir[23:8];	// for bit flags
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`ORA_IMM:
+			begin
+				res16 <= acc16 | ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`EOR_IMM:
+			begin
+				res16 <= acc16 ^ ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CMP_IMM:
+			begin
+				res16 <= acc16 - ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CPX_IMM:
+			begin
+				res16 <= x16 - ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		`CPY_IMM:
+			begin
+				res16 <= y16 - ir[23:8];
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		// Handle abs
+		`LDA_ABS:
+			begin
+				radr <= abs_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`LDX_ABS,`LDY_ABS:
+			begin
+				radr <= abs_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
+		`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
+		`BIT_ABS:
+			begin
+				radr <= abs_address;
+				wadr <= abs_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`CPX_ABS,`CPY_ABS:
+			begin
+				radr <= abs_address;
+				load_what <= xb16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ABS:
+			begin
+				wadr <= abs_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STX_ABS:
+			begin
+				wadr <= abs_address;
+				store_what <= xb16 ? `STW_X70 : `STW_X8;
+				data_nack();
+				state <= STORE1;
+			end	
+		`STY_ABS:
+			begin
+				wadr <= abs_address;
+				store_what <= xb16 ? `STW_Y70 : `STW_Y8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STZ_ABS:
+			begin
+				wadr <= abs_address;
+				store_what <= m16 ? `STW_Z70 : `STW_Z8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle abs,x
+		`LDA_ABSX:
+			begin
+				radr <= absx_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,
+		`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX:
+			begin
+				radr <= absx_address;
+				wadr <= absx_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`LDY_ABSX:
+			begin
+				radr <= absx_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ABSX:
+			begin
+				wadr <= absx_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`STZ_ABSX:
+			begin
+				wadr <= absx_address;
+				store_what <= m16 ? `STW_Z70 : `STW_Z8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle abs,y
+		`LDA_ABSY:
+			begin
+				radr <= absy_address;
+				load_what <= m16 ? `HALF_71	: `BYTE_71;
+				state <= LOAD_MAC1;
+				data_nack();
+			end
+		`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY:
+			begin
+				radr <= absy_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`LDX_ABSY:
+			begin
+				radr <= absy_address;
+				load_what <= xb16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ABSY:
+			begin
+				wadr <= absy_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`JMP:
+			begin
+				vpa <= `TRUE;
+				vda <= `TRUE;
+				pc[15:0] <= ir[23:8];
+				ado[15:0] <= ir[23:8];
+				next_state(IFETCH1);
+			end
+		`JMP_IND:
+			begin
+				radr <= abs_address;
+				load_what <= `PC_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`JMP_INDX:
+			begin
+				radr <= absx_address;
+				load_what <= `PC_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end	
+		`JSR,`JSR_INDX:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				pc <= pc - 24'd1;
+				store_what <= `STW_PC158;
+				data_nack();
+				state <= STORE1;
+			end
+		`BRL:
+			begin
+				vpa <= `TRUE;
+				vda <= `TRUE;
+				pc <= pc + {{8{ir[23]}},ir[23:8]};
+				ado <= pc + {{8{ir[23]}},ir[23:8]};
+				next_state(IFETCH1);
+			end
+		`PEA:
+			begin
+				tmp16 <= ir[23:8];
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= `STW_TMP158;
+				data_nack();
+				state <= STORE1;
+			end
+		`PER:
+			begin
+				tmp16 <= pc[15:0] + ir[23:8] + 16'd3;
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				store_what <= `STW_TMP158;
+				data_nack();
+				state <= STORE1;
+			end
+		`MVN,`MVP:
+			begin
+				radr <= mvnsrc_address;
+				load_what <= `BYTE_72;
+				pc <= pc - 24'd3;	// override increment above
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		default:
+			begin
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		endcase
+	end
+
+DECODE4:
+	if (rdy) begin
+		first_ifetch <= `TRUE;
+		next_state(IFETCH1);
+		case(ir[7:0])
+		`WDM:	if (ir[15:8]==`XCE) begin
+					em <= 1'b0;
+					next_state(IFETCH1);
+					pc <= pc + 32'd2;
+				end
+		// Handle al
+		`LDA_AL:
+			begin
+				radr <= al_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_AL,`SBC_AL,`AND_AL,`ORA_AL,`EOR_AL,`CMP_AL:
+			begin
+				radr <= al_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_AL:
+			begin
+				wadr <= al_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		// Handle alx
+		`LDA_ALX:
+			begin
+				radr <= alx_address;
+				load_what <= m16 ? `HALF_71 : `BYTE_71;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`ADC_ALX,`SBC_ALX,`AND_ALX,`ORA_ALX,`EOR_ALX,`CMP_ALX:
+			begin
+				radr <= alx_address;
+				load_what <= m16 ? `HALF_70 : `BYTE_70;
+				data_nack();
+				state <= LOAD_MAC1;
+			end
+		`STA_ALX:
+			begin
+				wadr <= alx_address;
+				store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+				data_nack();
+				state <= STORE1;
+			end
+		`JML:
+			begin
+				vpa <= `TRUE;
+				vda <= `TRUE;
+				pc[23:0] <= ir[31:8];
+				ado[23:0] <= ir[31:8];
+				next_state(IFETCH1);
+			end
+		`JSL:
+			begin
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end				pc <= pc - 24'd1;
+				store_what <= `STW_PC2316;
+				data_nack();
+				state <= STORE1;
+			end
+		`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
+			begin
+				vpa <= `TRUE;
+				vda <= `TRUE;
+				if (takb) begin
+					pc <= pc + {{8{ir[31]}},ir[31:16]};
+					ado <= pc + {{8{ir[31]}},ir[31:16]};
+				end
+				next_state(IFETCH1);
+			end
+		default:
+			begin
+				opcode_read();
+				next_state(IFETCH1);
+			end
+		endcase
+	end
+
+`include "load_mac.v"
+`include "store.v"
+//`include "half_calc.v"
+`include "byte_calc.v"
+HALF_CALC:
+	begin
+		moveto_ifetch();
+		store_what <= `STW_DEF70;
+		case(ir[7:0])
+		`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_IYL,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_AL,`ADC_ALX,`ADC_I,`ADC_IL,`ADC_DSP,`ADC_DSPIY:	begin res16 <= acc16 + b16 + {15'd0,cf}; end
+		`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_IYL,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_AL,`SBC_ALX,`SBC_I,`SBC_IL,`SBC_DSP,`SBC_DSPIY:	begin res16 <= acc16 - b16 - {15'd0,~cf}; end
+		`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_IYL,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_AL,`CMP_ALX,`CMP_I,`CMP_IL,`CMP_DSP,`CMP_DSPIY:	begin res16 <= acc16 - b16; end
+		`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_IYL,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_AL,`AND_ALX,`AND_I,`AND_IL,`AND_DSP,`AND_DSPIY:	begin res16 <= acc16 & b16; end
+		`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_IYL,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_AL,`ORA_ALX,`ORA_I,`ORA_IL,`ORA_DSP,`ORA_DSPIY:	begin res16 <= acc16 | b16; end
+		`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_IYL,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_AL,`EOR_ALX,`EOR_I,`EOR_IL,`EOR_DSP,`EOR_DSPIY:	begin res16 <= acc16 ^ b16; end
+		`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_IYL,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_AL,`LDA_ALX,`LDA_I,`LDA_IL,`LDA_DSP,`LDA_DSPIY:	begin res16 <= b16; end
+		`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:	begin res16 <= acc16 & b16; end
+		`TRB_ZP,`TRB_ABS:	begin res16 <= ~acc16 & b16; wdat <= ~acc16 & b16; state <= STORE1; data_nack(); end
+		`TSB_ZP,`TSB_ABS:	begin res16 <= acc16 | b16; wdat <= acc16 | b16; state <= STORE1; data_nack(); end
+		`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:	begin res16 <= b16; end
+		`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:	begin res16 <= b16; end
+		`CPX_IMM,`CPX_ZP,`CPX_ABS:	begin res16 <= x16 - b16; end
+		`CPY_IMM,`CPY_ZP,`CPY_ABS:	begin res16 <= y16 - b16; end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX:	begin res16 <= {b16,1'b0}; wdat <= {b16[14:0],1'b0}; state <= STORE1; data_nack(); end
+		`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX:	begin res16 <= {b16,cf}; wdat <= {b16[14:0],cf}; state <= STORE1; data_nack(); end
+		`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX:	begin res16 <= {b16[0],1'b0,b16[15:1]}; wdat <= {1'b0,b16[15:1]}; state <= STORE1; data_nack(); end
+		`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX:	begin res16 <= {b16[0],cf,b16[15:1]}; wdat <= {cf,b16[15:1]}; state <= STORE1; data_nack(); end
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX:	begin res16 <= {b24,b16} + 24'd1; wdat <= {{b24,b16}+24'd1}; state <= STORE1; data_nack(); end
+		`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX:	begin res16 <= {b24,b16} - 24'd1; wdat <= {{b24,b16}-24'd1}; state <= STORE1; data_nack(); end
+		endcase
+	end
+
+MVN816:
+	begin
+		moveto_ifetch();
+		if (&acc[15:0]) begin
+			pc <= pc + 24'd3;
+			ado <= pc + 24'd3;
+			dbr <= ir[15:8];
+		end
+	end
+endcase
+end
+
+`include "bus_task.v"
+`include "misc_task.v"
+
+task next_state;
+input [5:0] nxt;
+begin
+	state <= nxt;
+end
+endtask
+
+function [127:0] fnStateName;
+input [5:0] state;
+case(state)
+RESET1:	fnStateName = "RESET1     ";
+IFETCH1:	fnStateName = "IFETCH1    ";
+IFETCH2:	fnStateName = "IFETCH2    ";
+IFETCH3:	fnStateName = "IFETCH3    ";
+IFETCH4:	fnStateName = "IFETCH4    ";
+STORE1:	fnStateName = "STORE1     ";
+STORE2:	fnStateName = "STORE2     ";
+RTS1:	fnStateName = "RTS1       ";
+IY3:	fnStateName = "IY3        ";
+BYTE_IX5:	fnStateName = "BYTE_IX5   ";
+BYTE_IY5:	fnStateName = "BYTE_IY5   ";
+DECODE1:	fnStateName = "DECODE1    ";
+DECODE2:	fnStateName = "DECODE2    ";
+DECODE3:	fnStateName = "DECODE3    ";
+DECODE4:	fnStateName = "DECODE4    ";
+BYTE_CALC:	fnStateName = "BYTE_CALC  ";
+BUS_ERROR:	fnStateName = "BUS_ERROR  ";
+LOAD_MAC1:	fnStateName = "LOAD_MAC1  ";
+LOAD_MAC2:	fnStateName = "LOAD_MAC2  ";
+LOAD_MAC3:	fnStateName = "LOAD_MAC3  ";
+MVN3:		fnStateName = "MVN3       ";
+LOAD_DCACHE:	fnStateName = "LOAD_DCACHE";
+LOAD_ICACHE:	fnStateName = "LOAD_ICACHE";
+LOAD_IBUF1:		fnStateName = "LOAD_IBUF1 ";
+LOAD_IBUF2:		fnStateName = "LOAD_IBUF2 ";
+LOAD_IBUF3:		fnStateName = "LOAD_IBUF3 ";
+ICACHE1:		fnStateName = "ICACHE1    ";
+IBUF1:			fnStateName = "IBUF1      ";
+DCACHE1:		fnStateName = "DCACHE1    ";
+HALF_CALC:		fnStateName = "HALF_CALC  ";
+MVN816:			fnStateName = "MVN816     ";
+default:		fnStateName = "UNKNOWN    ";
+endcase
+endfunction
+
+endmodule
+
Index: ultimate_cart/veronica/FT816Float.v
===================================================================
--- ultimate_cart/veronica/FT816Float.v	(nonexistent)
+++ ultimate_cart/veronica/FT816Float.v	(revision 438)
@@ -0,0 +1,687 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816Float.v
+//  - Triple precision floating point accelerator
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// 1600 LUTs 350 FF's
+// 140 MHz
+// ============================================================================
+//
+`define SIMULATION	1'b1
+
+module FT816Float(rst, clk, vda, rw, ad, db, rdy);
+parameter pIOAddress = 24'hFEA200;
+parameter EMSB = 15;
+parameter FMSB = 79;
+parameter TRUE = 1'b1;
+parameter FALSE = 1'b0;
+parameter FADD = 8'd1;
+parameter FSUB = 8'd2;
+parameter FMUL = 8'd3;
+parameter FDIV = 8'd4;
+parameter FIX2FLT = 8'd5;
+parameter FLT2FIX = 8'd6;
+parameter FABS = 8'd7;
+parameter ABS = 8'd7;
+parameter NABS = 8'd8;
+parameter FNABS = 8'd8;
+parameter MD1 = 8'd10;
+parameter ABSSWP = 8'd11;
+parameter ABSSWP1 = 8'd12;
+parameter NORM1 = 8'd13;
+parameter NORM = 8'd14;
+parameter ADD = 8'd15;
+parameter FCOMPL = 8'd16;
+parameter FNEG = 8'd16;
+parameter SWAP = 8'd17;
+parameter FIXED_ADD = 8'h81;
+parameter FIXED_SUB = 8'h82;
+parameter FIXED_MUL = 8'h83;
+parameter FIXED_DIV = 8'h84;
+parameter FIXED_ABS = 8'h87;
+parameter FIXED_NEG = 8'h90;
+parameter SWPALG = 8'd18;
+parameter ADDEND = 8'd19;
+parameter ALGNSW = 8'd20;
+parameter RTLOG = 8'd22;
+parameter FMUL1 = 8'd24;
+parameter FMUL2 = 8'd25;
+parameter MUL1 = 8'd26;
+parameter FMUL3 = 8'd27;
+parameter MUL2 = 8'd28;
+parameter MDEND = 8'd29;
+parameter FDIV1 = 8'd30;
+parameter MD2 = 8'd31;
+parameter MD3 = 8'd32;
+parameter OVCHK = 8'd34;
+parameter OVFL = 8'd35;
+parameter DIV1 = 8'd36;
+parameter IDLE = 8'd62;
+parameter RESET = 8'd63;
+
+input rst;
+input clk;
+input vda;
+input rw;
+input [23:0] ad;
+inout tri [7:0] db;
+output rdy;
+
+reg [7:0] cmd;
+reg [7:0] state;
+reg [5:0] state_stk [3:0];
+//reg [3:0] sp;
+reg [1:0] sign;
+reg [EMSB:0] acc;
+reg [7:0] y;
+reg [EMSB+FMSB+1:0] FAC1;
+reg [EMSB+FMSB+1:0] FAC2;
+reg [FMSB:0] E;
+wire [EMSB:0] FAC1_exp = FAC1[EMSB+FMSB+1:FMSB+1];
+wire [FMSB:0] FAC1_man = FAC1[FMSB:0];
+wire [EMSB:0] FAC2_exp = FAC2[EMSB+FMSB+1:FMSB+1];
+wire [FMSB:0] FAC2_man = FAC2[FMSB:0];
+
+reg addOrSub;
+wire [FMSB+1:0] sum = addOrSub ? FAC2_man - FAC1_man : FAC2_man + FAC1_man;
+wire [FMSB+1:0] dif = FAC2_man - E;
+wire [FMSB+1:0] neg = {FMSB+1{1'b0}} - FAC1_man;
+wire [EMSB+1:0] expdif = FAC2_exp - FAC1_exp;
+// Note the carry flag must be extended manually!
+reg cf,vf,nf;
+wire [EMSB+1:0] exp_sum = acc + FAC1_exp + {15'd0,cf};	// FMUL
+wire [EMSB+1:0] exp_dif = acc - FAC1_exp - {15'd0,~cf};	// FDIV
+reg [FMSB:0] rem;
+reg isRTAR;
+reg busy;
+reg shiftBy16;
+reg isFixedPoint;
+reg [7:0] dbo;
+
+wire eq = FAC1==FAC2;
+wire gt = (FAC1[FMSB]^FAC2[FMSB]) ? FAC2[FMSB] : // If the signs are different, whichever one is positive
+		   FAC1_exp==FAC2_exp ? (FAC1_man > FAC2_man) :	// if exponents are equal check mantissa
+		   FAC1_exp > FAC2_exp;	// else compare exponents
+wire lt = !(gt|eq);
+wire zf = ~|FAC1;
+
+wire cs = vda && (ad[23:8]==pIOAddress[23:8]);
+reg rdy1,rdy2;
+always @(posedge clk)
+if (rst) begin
+	rdy1 <= 1'b1;
+	rdy2 <= 1'b1;
+end
+else begin
+	rdy1 <= cs & ~rdy1;
+	rdy2 <= cs & rdy1;
+end
+assign rdy = cs ? (rw ? rdy2 : 1'b1) : 1'b1;
+assign db = cs & rw ? dbo : {8{1'bz}};
+
+// This is a clock cycle counter used in simulation to determine the number of
+// cycles a given operation takes to complete.
+reg [11:0] cyccnt;
+
+always @(posedge clk)
+if (rst) begin
+	next_state(RESET);
+`ifdef SIMULATION
+	FAC1 <= 96'd0;	// for simulation
+	FAC2 <= 96'd0;
+`endif
+end
+else begin
+`ifdef SIMULATION
+	cyccnt <= cyccnt + 1;
+`endif
+	cmd <= 8'h00;
+	if (cs & ~rw)
+		case(ad[7:0])
+		8'h00:	FAC1[7:0] <= db;
+		8'h01:	FAC1[15:8] <= db;
+		8'h02:	FAC1[23:16] <= db;
+		8'h03:	FAC1[31:24] <= db;
+		8'h04:	FAC1[39:32] <= db;
+		8'h05:	FAC1[47:40] <= db;
+		8'h06:	FAC1[55:48] <= db;
+		8'h07:	FAC1[63:56] <= db;
+		8'h08:	FAC1[71:64] <= db;
+		8'h09:	FAC1[79:72] <= db;
+		8'h0A:	FAC1[87:80] <= db;
+		8'h0B:	FAC1[95:88] <= db;
+		8'h0E:	cmd <= db;
+		8'h10:	FAC2[7:0] <= db;
+		8'h11:	FAC2[15:8] <= db;
+		8'h12:	FAC2[23:16] <= db;
+		8'h13:	FAC2[31:24] <= db;
+		8'h14:	FAC2[39:32] <= db;
+		8'h15:	FAC2[47:40] <= db;
+		8'h16:	FAC2[55:48] <= db;
+		8'h17:	FAC2[63:56] <= db;
+		8'h18:	FAC2[71:64] <= db;
+		8'h19:	FAC2[79:72] <= db;
+		8'h1A:	FAC2[87:80] <= db;
+		8'h1B:	FAC2[95:88] <= db;
+		endcase
+
+	case(ad[7:0])
+	8'h00:	dbo <= FAC1[7:0];
+	8'h01:	dbo <= FAC1[15:8];
+	8'h02:	dbo <= FAC1[23:16];
+	8'h03:	dbo <= FAC1[31:24];
+	8'h04:	dbo <= FAC1[39:32];
+	8'h05:	dbo <= FAC1[47:40];
+	8'h06:	dbo <= FAC1[55:48];
+	8'h07:	dbo <= FAC1[63:56];
+	8'h08:	dbo <= FAC1[71:64];
+	8'h09:	dbo <= FAC1[79:72];
+	8'h0A:	dbo <= FAC1[87:80];
+	8'h0B:	dbo <= FAC1[95:88];
+	8'h0E:	dbo <= {busy,2'b00,lt,eq,gt,zf,vf};
+	8'h10:	dbo <= FAC2[7:0];
+	8'h11:	dbo <= FAC2[15:8];
+	8'h12:	dbo <= FAC2[23:16];
+	8'h13:	dbo <= FAC2[31:24];
+	8'h14:	dbo <= FAC2[39:32];
+	8'h15:	dbo <= FAC2[47:40];
+	8'h16:	dbo <= FAC2[55:48];
+	8'h17:	dbo <= FAC2[63:56];
+	8'h18:	dbo <= FAC2[71:64];
+	8'h19:	dbo <= FAC2[79:72];
+	8'h1A:	dbo <= FAC2[87:80];
+	8'h1B:	dbo <= FAC2[95:88];
+	endcase
+
+case(state)
+RESET:
+	begin
+//		sp <= 4'h0;
+		next_state(IDLE);
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+IDLE:
+	begin
+`ifdef SIMULATION
+		if (cyccnt > 0)
+			$display("Cycle Count=%d", cyccnt);
+		cyccnt <= 12'h0;
+`endif
+		busy <= 1'b0;
+//		sp <= 4'h0;
+		isFixedPoint <= FALSE;
+		case(cmd)
+		FADD:	begin push_state(IDLE); next_state(FADD); busy <= 1'b1; addOrSub <= 1'b0; end
+		FSUB:	begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; addOrSub <= 1'b0; end
+		FMUL:	begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; addOrSub <= 1'b0; end 
+		FDIV:	begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; end
+		FIX2FLT:	begin push_state(IDLE); next_state(FIX2FLT); busy <= 1'b1; end
+		FLT2FIX:	begin push_state(IDLE); next_state(FLT2FIX); busy <= 1'b1; end
+		FNEG:		begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; end
+		FABS:		begin push_state(IDLE); next_state(ABS); busy <= 1'b1; end
+		FNABS:		begin push_state(IDLE); next_state(NABS); busy <= 1'b1; end
+		SWAP:		begin push_state(IDLE); next_state(SWAP); busy <= 1'b1; end
+		// Fixed point operations
+		FIXED_ADD:	begin push_state(IDLE); next_state(FADD); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
+		FIXED_SUB:	begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
+		FIXED_MUL:	begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
+		FIXED_DIV:	begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; isFixedPoint <= TRUE; end
+		FIXED_NEG:	begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; isFixedPoint <= TRUE; end
+		FIXED_ABS:	begin push_state(IDLE); next_state(ABS); busy <= 1'b1; isFixedPoint <= TRUE; end
+		endcase
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+MD1:
+	begin
+		$display("MD1");
+		sign <= {sign[1:0],1'b0};
+		next_state(ABSSWP);
+		push_state(ABSSWP);
+	end
+ABSSWP:
+	begin
+		if (~FAC1_man[FMSB]) begin
+			next_state(ABSSWP1);
+		end
+		else begin
+			push_state(ABSSWP1);
+			sign <= sign + 2'd1;
+			next_state(FCOMPL);
+		end
+	end
+ABSSWP1:
+	begin
+		cf <= 1'b1;
+		next_state(SWAP);
+	end
+
+
+//-----------------------------------------------------------------------------
+// Take the absolute value of FAC1
+//-----------------------------------------------------------------------------
+
+ABS:
+	begin
+		if (FAC1_man[FMSB])
+			next_state(FCOMPL);
+		else
+			pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Take the negative absolute value of FAC1
+//-----------------------------------------------------------------------------
+
+NABS:
+	begin
+		if (~FAC1_man[FMSB])
+			next_state(FCOMPL);
+		else
+			pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Normalize
+// - Decrement exponent and shift left
+// - Normalization is normally the last step of an operation.
+// - If possible the FAC is shifted by 16 bits at a time. This helps with
+//   the many small constants that are usually present.
+//-----------------------------------------------------------------------------
+NORM:
+	begin
+	if (isFixedPoint)	// nothing to do for fixed point
+		pop_state();
+	else begin
+	$display("Normalize FAC1H %h", FAC1[FMSB:FMSB-15]);
+	if (FAC1[FMSB]!=FAC1[FMSB-1] || ~|FAC1_exp) begin
+		$display("Normal: %h",FAC1);
+		pop_state();
+	end
+	// If the mantissa is zero, set the the exponent to zero. Otherwise 
+	// normalization could spin for thousands of clock cycles decrementing
+	// the exponent to zero.
+	else if (~|FAC1_man) begin
+		FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h0;
+		pop_state();
+	end
+	else if (FAC1[FMSB:FMSB-15]=={16{FAC1[FMSB]}}) begin
+		$display("shift by 16");
+		FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd16;
+		FAC1[FMSB:0] <= {FAC1[FMSB-16:0],16'h0};
+	end
+	else begin
+		FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd1;
+		FAC1[FMSB:0] <= {FAC1[FMSB-1:0],1'b0};
+	end
+	end
+	end
+
+//-----------------------------------------------------------------------------
+// Add mantissa's and compute carry and overflow.
+// This is used by both ADD and MUL.
+//-----------------------------------------------------------------------------
+
+ADD:
+	begin
+		FAC1[FMSB:0] <= sum[FMSB:0];
+		cf <= sum[FMSB+1];
+		vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);
+		pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Negate
+//-----------------------------------------------------------------------------
+
+// Complement FAC1
+FCOMPL:
+	begin
+		$display("FCOMPL");
+		FAC1[FMSB:0] <= neg[FMSB:0];
+		cf <= ~neg[FMSB+1];
+		vf <= neg[FMSB]==FAC1[FMSB];
+		if (isFixedPoint)
+			pop_state();
+		else
+			next_state(ADDEND);
+	end
+
+//-----------------------------------------------------------------------------
+// Swap FAC1 and FAC2
+//-----------------------------------------------------------------------------
+
+SWAP:
+	begin
+		$display("Swapping FAC1 and FAC2");
+		FAC1 <= FAC2;
+		FAC2 <= FAC1;
+		E <= FAC2[FMSB:0];
+		acc <= FAC1_exp;
+		pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Subtract
+// - subtract first complements the FAC then performs an ADD operation.
+//-----------------------------------------------------------------------------
+
+FSUB:
+	begin
+//		if (isFixedPoint)
+//			push_state(FADD);
+//		else
+//			push_state(SWPALG);
+		push_state(FADD);
+		next_state(FCOMPL);
+	end
+SWPALG:
+	begin
+		push_state(FADD);
+		next_state(ALGNSW);
+	end
+
+//-----------------------------------------------------------------------------
+// Addition
+//-----------------------------------------------------------------------------
+
+FADD:
+	begin
+		cf <= ~expdif[EMSB+1];	// Must set carry flag from compare
+		// If the exponents are too different then one of the values will
+		// become zero, so the result is just the larger value. This check
+		// is to prevent shifting thousands of times.
+		if (expdif[15] ? expdif < 16'hFFB0 : expdif[15:0] > 16'h0050) begin
+			FAC1 <= expdif[15] ? FAC2 : FAC1;
+			pop_state();
+		end
+		else if (|expdif[15:0] & !isFixedPoint)
+			next_state(SWPALG);
+		else begin
+			if (!isFixedPoint) push_state(ADDEND);
+			next_state(ADD);
+		end
+	end
+ADDEND:
+	begin
+		if (!vf)
+			next_state(NORM);
+		else begin
+			isRTAR <= FALSE;
+			next_state(RTLOG);
+		end
+	end
+ALGNSW:
+	begin
+		if (!cf)
+			next_state(SWAP);
+		else begin
+			isRTAR <= TRUE;
+			next_state(RTLOG);
+		end
+	end
+
+//-----------------------------------------------------------------------------
+// Right shift, logical or arithmetic.
+//-----------------------------------------------------------------------------
+
+RTLOG:
+	begin
+		FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] + 16'd1;
+		if (FAC1[EMSB+FMSB+1:FMSB+1]==16'hFFFF)
+			next_state(OVFL);
+		else begin
+			FAC1[FMSB:0] <= {isRTAR ? FAC1_man[FMSB] : cf,FAC1[FMSB:1]};
+			E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};
+			cf <= E[0];
+			pop_state();
+		end
+	end
+
+//-----------------------------------------------------------------------------
+// Mulyiply
+//-----------------------------------------------------------------------------
+
+FMUL:
+	begin
+		next_state(MD1);
+		push_state(FMUL1);
+	end
+FMUL1:
+	begin
+		acc <= exp_sum[EMSB:0];
+		cf <= exp_sum[EMSB+1];
+		push_state(MUL1);
+		next_state(MD2);
+	end
+MUL1:
+	begin
+		// inline RTLOG1 code
+		FAC1[FMSB:0] <= {1'b0,FAC1[FMSB:1]};
+		E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};
+		cf <= E[0];
+		next_state(FMUL3);
+		//push_state(FMUL3);
+		//next_state(RTLOG1);
+	end
+FMUL3:
+	begin
+		if (cf) begin
+			FAC1[FMSB:0] <= sum[FMSB:0];
+			cf <= sum[FMSB+1];
+			vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);
+		end
+		y <= y - 8'd1;
+		if (y==8'd0)
+			next_state(MDEND);
+		else
+			next_state(MUL1);
+	end
+MDEND:
+	begin
+		sign <= {1'b0,sign[1]};
+		if (~sign[0])
+			next_state(NORM);
+		else
+			next_state(FCOMPL);
+	end
+
+//-----------------------------------------------------------------------------
+// Divide
+//-----------------------------------------------------------------------------
+FDIV:
+	begin
+		push_state(FDIV1);
+		next_state(MD1);
+	end
+FDIV1:
+	begin
+		acc <= exp_dif[EMSB:0];
+		cf <= ~exp_dif[EMSB+1];
+		$display("acc=%h %h %h", exp_dif, acc, FAC1_exp);
+		push_state(DIV1);
+		next_state(MD2);
+	end
+DIV1:
+	begin
+		$display("FAC1=%h, FAC2=%h, E=%h", FAC1, FAC2, E);
+		y <= y - 8'd1;
+		FAC1[FMSB:0] <= {FAC1[FMSB:0],~dif[FMSB+1]};
+		if (dif[FMSB+1]) begin
+			FAC2[FMSB:0] <= {FAC2[FMSB-1:0],1'b0};
+			if (FAC2[FMSB]) begin
+				next_state(OVFL);
+			end
+			else if (y!=8'd1)
+				next_state(DIV1);
+			else begin
+				rem <= dif;
+				next_state(MDEND);
+			end
+		end
+		else begin
+			FAC2[FMSB:0] <= {dif[FMSB-1:0],1'b0};
+			if (dif[FMSB]) begin
+				next_state(OVFL);
+			end
+			else if (y!=8'd1)
+				next_state(DIV1);
+			else begin
+				rem <= dif;
+				next_state(MDEND);
+			end
+		end
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+MD2:
+	begin
+		FAC1[FMSB:0] <= 80'h0;
+		if (isFixedPoint) begin
+			y <= 8'h4F;
+			pop_state();
+		end
+		else if (cf)
+			next_state(OVCHK);
+		else if (acc[EMSB])
+			next_state(MD3);
+		else begin
+			pop_state();
+			next_state(NORM);
+		end
+	end
+MD3:
+	begin
+		acc[EMSB] <= ~acc[EMSB];
+		FAC1[EMSB+FMSB+1:FMSB+1] <= {~acc[EMSB],acc[EMSB-1:0]};
+		y <= 8'h4F;
+		pop_state();
+	end
+OVCHK:
+	begin
+		if (~acc[EMSB])
+			next_state(MD3);
+		else
+			next_state(OVFL);
+	end
+OVFL:
+	begin
+		vf <= 1'b1;
+		next_state(IDLE);
+	end
+
+//-----------------------------------------------------------------------------
+// FIX2FLT
+// - convert 64 bit fixed point number to floating point
+//-----------------------------------------------------------------------------
+
+FIX2FLT:
+	begin
+		FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h804E;	// exponent = 78
+		next_state(NORM);
+	end
+
+//-----------------------------------------------------------------------------
+// FLT2FIX
+// - convert floating point number to fixed point.
+//-----------------------------------------------------------------------------
+
+FLT2FIX:
+	begin
+		// If the exponent is too small then no amount of shifting will
+		// result in a non-zero number. In this case we just set the 
+		// FAC to zero. Otherwise FLT2FIX would spin for thousands of cycles
+		// until the exponent incremented finally to 803Eh.
+		if (FAC1_exp < 16'h7FB0) begin
+			FAC1[79:0] <= 80'd0;
+			FAC1[95:80] <= 16'h804E;
+			pop_state();
+		end
+		// If the exponent is too large, we can't right shift and the value
+		// would overflow a 64-bit integer, so we just set it to the max.
+		else if (FAC1_exp > 16'h804E) begin
+			vf <= 1'b1;
+			FAC1[95:80] <= 16'h804E;
+			FAC1[79:0] <= FAC1[79] ? 80'h80000000000000000000 : 80'h7FFFFFFFFFFFFFFFFFFF;
+			pop_state();
+		end
+		else if (FAC1_exp==16'h804E)
+			pop_state();
+		else begin
+			push_state(FLT2FIX);
+			isRTAR <= TRUE;
+			next_state(RTLOG);
+		end
+	end
+endcase
+end
+
+/*
+DIVBY10:
+	begin
+		FAC2[EMSB+FMSB+1:FMSB+1] <= 16'h8003;
+		FAC2[FMSB] <= 1'b0;		// +ve
+		FAC2[FMSB-1:75] <= 4'hA;	// 10
+		FAC2[74:0] <= 75'd0;
+		next_state(FDIV);
+	end
+*/
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+task push_state;
+input [5:0] st;
+begin
+	state_stk[0] <= st;
+	state_stk[1] <= state_stk[0];
+	state_stk[2] <= state_stk[1];
+	state_stk[3] <= state_stk[2];
+//	state_stk[sp-4'd1] <= st;
+//	sp <= sp - 4'd1;
+end
+endtask
+
+task pop_state;
+begin
+	state <= state_stk[0];
+	state_stk[0] <= state_stk[1];
+	state_stk[1] <= state_stk[2];
+	state_stk[2] <= state_stk[3];
+	state_stk[3] <= IDLE;
+//	next_state(state_stk[sp]);
+//	sp <= sp + 4'd1;
+end
+endtask
+
+task next_state;
+input [7:0] st;
+begin
+	state <= st;
+end
+endtask
+
+endmodule
Index: ultimate_cart/veronica/FT816FloatSingle.v
===================================================================
--- ultimate_cart/veronica/FT816FloatSingle.v	(nonexistent)
+++ ultimate_cart/veronica/FT816FloatSingle.v	(revision 438)
@@ -0,0 +1,537 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816FloatSingle.v
+//  - Single precision (40 bit) floating point accelerator
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//
+// SEEEEEEE SM.MMMMMM MMMMMMMM MMMMMMMM MMMMMMMM
+//                                                                         
+// 850 LUTs 188 FF's
+// 170 MHz
+// ============================================================================
+//
+module FT816FloatSingle(rst, clk, vda, rw, ad, db, rdy);
+parameter pIOAddress = 24'hFEA200;
+parameter FADD = 8'd1;
+parameter FSUB = 8'd2;
+parameter FMUL = 8'd3;
+parameter FDIV = 8'd4;
+parameter FIX2FLT = 8'd5;
+parameter FLT2FIX = 8'd6;
+parameter MD1 = 8'd10;
+parameter ABSSWP = 8'd11;
+parameter ABSSWP1 = 8'd12;
+parameter NORM1 = 8'd13;
+parameter NORM = 8'd14;
+parameter ADD = 8'd15;
+parameter FCOMPL = 8'd16;
+parameter FNEG = 8'd16;
+parameter SWAP = 8'd17;
+parameter SWPALG = 8'd18;
+parameter ADDEND = 8'd19;
+parameter ALGNSW = 8'd20;
+parameter RTAR = 8'd21;
+parameter RTLOG = 8'd22;
+parameter RTLOG1 = 8'd23;
+parameter FMUL1 = 8'd24;
+parameter FMUL2 = 8'd25;
+parameter MUL1 = 8'd26;
+parameter FMUL3 = 8'd27;
+parameter MUL2 = 8'd28;
+parameter MDEND = 8'd29;
+parameter FDIV1 = 8'd30;
+parameter MD2 = 8'd31;
+parameter MD3 = 8'd32;
+parameter OVCHK = 8'd34;
+parameter OVFL = 8'd35;
+parameter DIV1 = 8'd36;
+parameter IDLE = 8'd62;
+parameter RESET = 8'd63;
+
+input rst;
+input clk;
+input vda;
+input rw;
+input [23:0] ad;
+inout tri [7:0] db;
+output rdy;
+
+reg [7:0] cmd;
+reg [7:0] state;
+reg [5:0] state_stk [31:0];
+reg [4:0] sp;
+reg [3:0] sign;
+reg [15:0] acc;
+reg [5:0] y;
+reg [39:0] FAC1;
+reg [39:0] FAC2;
+
+reg [31:0] E;
+wire [7:0] FAC1_exp = FAC1[39:32];
+wire [31:0] FAC1_man = FAC1[31:0];
+wire [7:0] FAC2_exp = FAC2[39:32];
+wire [31:0] FAC2_man = FAC2[31:0];
+
+wire [32:0] sum = FAC1_man + FAC2_man;
+wire [32:0] dif = FAC2_man - E;
+wire [32:0] neg = 32'h0 - FAC1_man;
+// Note the carry flag must be extended manually!
+wire [8:0] exp_sum = acc + FAC1_exp + {7'd0,cf};	// FMUL
+wire [8:0] exp_dif = acc - FAC1_exp - {7'd0,~cf};	// FDIV
+reg [39:0] rem;
+
+reg cf,vf,nf;
+reg busy;
+reg [7:0] dbo;
+
+wire eq = FAC1==FAC2;
+wire gt = (FAC1[31]^FAC2[31]) ? FAC2[31] : // If the signs are different, whichever one is positive
+		   FAC1_exp==FAC2_exp ? (FAC1_man > FAC2_man) ^ FAC1[31] :	// if exponents are equal check mantissa
+		   FAC1_exp > FAC2_exp;	// else compare exponents
+wire lt = !(gt|eq);
+wire zf = ~|FAC1;
+
+wire cs = vda && (ad[23:8]==pIOAddress[23:8]);
+reg rdy1;
+always @(posedge clk)
+if (rst)
+	rdy1 <= 1'b1;
+else
+	rdy1 <= cs & ~rdy1;
+assign rdy = cs ? (rw ? rdy1 : 1'b1) : 1'b1;
+assign db = cs & rw ? dbo : {8{1'bz}};
+
+always @(posedge clk)
+if (rst) begin
+	next_state(RESET);
+end
+else begin
+	cmd <= 8'h00;
+	if (cs & ~rw)
+		case(ad[7:0])
+		8'h00:	FAC1[7:0] <= db;
+		8'h01:	FAC1[15:8] <= db;
+		8'h02:	FAC1[23:16] <= db;
+		8'h03:	FAC1[31:24] <= db;
+		8'h04:	FAC1[39:32] <= db;
+		8'h0F:	cmd <= db;
+		8'h10:	FAC2[7:0] <= db;
+		8'h11:	FAC2[15:8] <= db;
+		8'h12:	FAC2[23:16] <= db;
+		8'h13:	FAC2[31:24] <= db;
+		8'h14:	FAC2[39:32] <= db;
+		endcase
+
+	case(ad[7:0])
+	8'h00:	dbo <= FAC1[7:0];
+	8'h01:	dbo <= FAC1[15:8];
+	8'h02:	dbo <= FAC1[23:16];
+	8'h03:	dbo <= FAC1[31:24];
+	8'h04:	dbo <= FAC1[39:32];
+	8'h0F:	dbo <= {busy,2'b00,lt,eq,gt,zf,vf};
+	8'h10:	dbo <= FAC2[7:0];
+	8'h11:	dbo <= FAC2[15:8];
+	8'h12:	dbo <= FAC2[23:16];
+	8'h13:	dbo <= FAC2[31:24];
+	8'h14:	dbo <= FAC2[39:32];
+	endcase
+
+case(state)
+RESET:
+	begin
+		sp <= 5'h00;
+		next_state(IDLE);
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+IDLE:
+	begin
+		busy <= 1'b0;
+		sp <= 5'h00;
+		case(cmd)
+		FADD:	begin push_state(IDLE); next_state(FADD); busy <= 1'b1; end
+		FSUB:	begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; end
+		FMUL:	begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; end
+		FDIV:	begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; end
+		FIX2FLT:	begin push_state(IDLE); next_state(FIX2FLT); busy <= 1'b1; end
+		FLT2FIX:	begin push_state(IDLE); next_state(FLT2FIX); busy <= 1'b1; end
+		FNEG:		begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; end
+		SWAP:		begin push_state(IDLE); next_state(SWAP); busy <= 1'b1; end
+		endcase
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+MD1:
+	begin
+		$display("MD1");
+		sign <= {sign[2:0],1'b0};
+		next_state(ABSSWP);
+		push_state(ABSSWP);
+	end
+ABSSWP:
+	begin
+		if (~FAC1_man[31]) begin
+			next_state(ABSSWP1);
+		end
+		else begin
+			push_state(ABSSWP1);
+			sign <= sign + 4'd1;
+			next_state(FCOMPL);
+		end
+	end
+ABSSWP1:
+	begin
+		cf <= 1'b1;
+		next_state(SWAP);
+	end
+
+//-----------------------------------------------------------------------------
+// Normalize
+// - Decrement exponent and shift left
+// - Normalization is normally the last step of an operation so it is used
+//   to set a couple of result flags.
+//-----------------------------------------------------------------------------
+NORM1:
+	begin
+	FAC1[39:32] <= FAC1[39:32] - 16'd1;
+	FAC1[31:0] <= {FAC1[30:0],1'b0};
+	next_state(NORM);
+	end
+NORM:
+	begin
+	$display("Normalize");
+	if (FAC1[31]!=FAC1[30] || FAC1_exp==8'h00) begin
+		$display("Normal: %h",FAC1);
+		pop_state();
+	end
+	// If the mantissa is zero, set the the exponent to zero. Otherwise 
+	// normalization could spin for thousands of clock cycles decrementing
+	// the exponent to zero.
+	else if (~|FAC1_man) begin
+		FAC1[39:32] <= 8'h0;
+		pop_state();
+	end
+	else
+		next_state(NORM1);
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+ADD:
+	begin
+		FAC1[31:0] <= sum[31:0];
+		cf <= sum[32];
+		vf <= (sum[31] ^ FAC2[31]) & (1'b1 ^ FAC1[31] ^ FAC2[31]);
+		pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Negate
+//-----------------------------------------------------------------------------
+
+// Complement FAC1
+FCOMPL:
+	begin
+		$display("FCOMPL");
+		FAC1[31:0] <= neg[31:0];
+		cf <= ~neg[32];
+		vf <= neg[31]==FAC1[31];
+		next_state(ADDEND);
+	end
+
+//-----------------------------------------------------------------------------
+// Swap FAC1 and FAC2
+//-----------------------------------------------------------------------------
+
+SWAP:
+	begin
+		$display("Swapping FAC1 and FAC2");
+		FAC1 <= FAC2;
+		FAC2 <= FAC1;
+		E <= FAC2[31:0];
+		acc <= FAC1_exp;
+		pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Subtract
+//-----------------------------------------------------------------------------
+
+FSUB:
+	begin
+		push_state(SWPALG);
+		next_state(FCOMPL);
+	end
+SWPALG:
+	begin
+		push_state(FADD);
+		next_state(ALGNSW);
+	end
+
+//-----------------------------------------------------------------------------
+// Addition
+//-----------------------------------------------------------------------------
+
+FADD:
+	begin
+		if (FAC1_exp != FAC2_exp)
+			next_state(SWPALG);
+		else begin
+			push_state(ADDEND);
+			next_state(ADD);
+		end
+	end
+ADDEND:
+	begin
+		if (!vf)
+			next_state(NORM);
+		else
+			next_state(RTLOG);
+	end
+ALGNSW:
+	begin
+		if (!cf)
+			next_state(SWAP);
+		else
+			next_state(RTAR);
+	end
+RTAR:
+	begin
+		cf <= FAC1_man[31];
+		next_state(RTLOG);
+	end
+RTLOG:
+	begin
+		FAC1[39:32] <= FAC1[39:32] + 16'd1;
+		if (FAC1[39:32]==8'hFF)
+			next_state(OVFL);
+		else
+			next_state(RTLOG1);
+	end
+RTLOG1:
+	begin
+		FAC1[31:0] <= {FAC1[31],FAC1[31:1]};
+		E[31:0] <= {FAC1[0],E[30:1]};
+		cf <= E[0];
+		pop_state();
+	end
+
+//-----------------------------------------------------------------------------
+// Mulyiply
+//-----------------------------------------------------------------------------
+
+FMUL:
+	begin
+		next_state(MD1);
+		push_state(FMUL1);
+	end
+FMUL1:
+	begin
+		acc <= exp_sum[7:0];
+		cf <= exp_sum[8];
+		push_state(FMUL2);
+		next_state(MD2);
+	end
+FMUL2:
+	begin
+		cf <= 1'b0;
+		next_state(MUL1);
+	end
+MUL1:
+	begin
+		push_state(FMUL3);
+		next_state(RTLOG1);
+	end
+FMUL3:
+	begin
+		if (!cf)
+			next_state(MUL2);
+		else begin
+			push_state(MUL2);
+			next_state(ADD);
+		end
+	end
+MUL2:
+	begin
+		y <= y - 6'd1;
+		if (y!=6'd0)
+			next_state(MUL1);
+		else
+			next_state(MDEND);
+	end
+MDEND:
+	begin
+		sign <= {1'b0,sign[3:1]};
+		if (~sign[0])
+			next_state(NORM);
+		else
+			next_state(FCOMPL);
+	end
+
+//-----------------------------------------------------------------------------
+// Divide
+//-----------------------------------------------------------------------------
+FDIV:
+	begin
+		push_state(FDIV1);
+		next_state(MD1);
+	end
+FDIV1:
+	begin
+		acc <= exp_dif[7:0];
+		cf <= ~exp_dif[8];
+		$display("acc=%h %h %h", exp_dif, acc, FAC1_exp);
+		push_state(DIV1);
+		next_state(MD2);
+	end
+DIV1:
+	begin
+		$display("FAC1=%h, FAC2=%h, E=%h", FAC1, FAC2, E);
+		y <= y - 8'd1;
+		FAC1[31:0] <= {FAC1[31:0],~dif[32]};
+		if (dif[32]) begin
+			FAC2[31:0] <= {FAC2[30:0],1'b0};
+			if (FAC2[31]) begin
+				next_state(OVFL);
+			end
+			else if (y!=8'd1)
+				next_state(DIV1);
+			else begin
+				rem <= dif;
+				next_state(MDEND);
+			end
+		end
+		else begin
+			FAC2[31:0] <= {dif[30:0],1'b0};
+			if (dif[31]) begin
+				next_state(OVFL);
+			end
+			else if (y!=6'd1)
+				next_state(DIV1);
+			else begin
+				rem <= dif;
+				next_state(MDEND);
+			end
+		end
+	end
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+MD2:
+	begin
+		FAC1[31:0] <= 32'h0;
+		if (cf)
+			next_state(OVCHK);
+		else if (acc[15])
+			next_state(MD3);
+		else begin
+			pop_state();
+			next_state(NORM);
+		end
+	end
+MD3:
+	begin
+		acc[7] <= ~acc[7];
+		FAC1[39:32] <= {~acc[7],acc[6:0]};
+		y <= 6'h1F;
+		pop_state();
+	end
+OVCHK:
+	begin
+		if (~acc[7])
+			next_state(MD3);
+		else
+			next_state(OVFL);
+	end
+OVFL:
+	begin
+		vf <= 1'b1;
+		next_state(IDLE);
+	end
+
+//-----------------------------------------------------------------------------
+// FIX2FLT
+// - convert 64 bit fixed point number to floating point
+//-----------------------------------------------------------------------------
+
+FIX2FLT:
+	begin
+		FAC1[39:32] <= 8'h9E;	// exponent = 30
+		next_state(NORM);
+	end
+
+//-----------------------------------------------------------------------------
+// FLT2FIX
+// - convert floating point number to fixed point.
+//-----------------------------------------------------------------------------
+
+FLT2FIX:
+	begin
+		if (FAC1_exp==8'h9E)
+			pop_state();
+		else begin
+			push_state(FLT2FIX);
+			next_state(RTAR);
+		end
+	end
+endcase
+end
+
+/*
+DIVBY10:
+	begin
+		FAC2[39:32] <= 16'h8003;
+		FAC2[31] <= 1'b0;		// +ve
+		FAC2[30:75] <= 4'hA;	// 10
+		FAC2[74:0] <= 75'd0;
+		next_state(FDIV);
+	end
+*/
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+task push_state;
+input [5:0] st;
+begin
+	state_stk[sp-5'd1] <= st;
+	sp <= sp - 5'd1;
+end
+endtask
+
+task pop_state;
+begin
+	next_state(state_stk[sp]);
+	sp <= sp + 5'd1;
+end
+endtask
+
+task next_state;
+input [7:0] st;
+begin
+	state <= st;
+end
+endtask
+
+endmodule
Index: ultimate_cart/veronica/FT816Float_tb.v
===================================================================
--- ultimate_cart/veronica/FT816Float_tb.v	(nonexistent)
+++ ultimate_cart/veronica/FT816Float_tb.v	(revision 438)
@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816Float_tb.v
+//  - Test Bench for triple precision floating point accelerator
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+module FT816Float_tb();
+
+reg clk;
+reg rst;
+reg vda;
+reg rw;
+reg [23:0] ad;
+wire [7:0] db;
+reg [7:0] dbo;
+wire rdy;
+reg [7:0] state;
+reg [7:0] retstate;
+reg fix2flt;
+reg [95:0] value;
+
+initial begin
+	#1 clk <= 1'b0;
+	#5 rst <= 1'b1;
+	#100 rst <= 1'b0;
+end
+
+always #5 clk <= ~clk;
+
+assign db = rw ? {8{1'bz}} : dbo;
+
+FT816Float u1 (
+	.rst(rst),
+	.clk(clk),
+	.vda(vda),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.rdy(rdy)
+);
+
+
+always @(posedge clk)
+if (rst)
+	state <= 8'h00;
+else begin
+state <= state + 8'd1;
+case(state)
+8'h00:	begin
+			value <= 96'h00000000000000004D20000;	// MAXINT
+			fix2flt <= 1'b1;
+			state <= 8'h80;
+			retstate <= 8'h01;
+			 b_write(24'hFEA20F,8'd17); 	// prime bus
+		end
+8'h01:  if (rdy) b_write(24'hFEA20F,8'd17); else state <= state;// SWAP
+8'h03:  if (rdy) b_read(24'hFEA20F); else state <= state;
+8'h04:	if (rdy) begin
+			if (db[7]) state <= state - 1;
+		end
+		else
+			state <= state;
+8'h05:	begin
+			value <= 96'h000000000000000004D20000;	// MAXINT
+			fix2flt <= 1'b1;
+			state <= 8'h80;
+			retstate <= 8'h06;
+		end
+8'h06:  if (rdy) b_write(24'hFEA20F,8'h06); else state <= state;// MUL
+8'h08:  if (rdy) b_read(24'hFEA20F); else state <= state;
+8'h09:	if (rdy) begin
+			if (db[7]) state <= state - 1;
+		end
+		else
+			state <= state;
+8'h20:	state <= state;
+// This subroutine writes a value to FAC1.
+8'h80:	if (rdy) b_write(24'hFEA200,value[7:0]); else state <= state;
+8'h81:  if (rdy) b_write(24'hFEA201,value[15:8]); else state <= state;
+8'h82:  if (rdy) b_write(24'hFEA202,value[23:16]); else state <= state;
+8'h83:  if (rdy) b_write(24'hFEA203,value[31:24]); else state <= state;
+8'h84:  if (rdy) b_write(24'hFEA204,value[39:32]); else state <= state;
+8'h85:  if (rdy) b_write(24'hFEA205,value[47:40]); else state <= state;
+8'h86:  if (rdy) b_write(24'hFEA206,value[55:48]); else state <= state;
+8'h87:  if (rdy) b_write(24'hFEA207,value[63:56]); else state <= state;
+8'h88:  if (rdy) b_write(24'hFEA208,value[71:64]); else state <= state;
+8'h89:  if (rdy) b_write(24'hFEA209,value[79:72]); else state <= state;
+8'h8A:  if (rdy) b_write(24'hFEA20A,value[87:80]); else state <= state;
+8'h8B:  if (rdy) begin b_write(24'hFEA20B,value[95:88]); if (fix2flt) state <= 8'h90; else state <= retstate; end else state <= state;
+8'h90:  if (rdy) b_write(24'hFEA20F,8'h05); else state <= state;// FIX2FLT
+8'h92:  if (rdy) b_read(24'hFEA20F); else state <= state;
+8'h93:	if (rdy) begin
+			if (db[7]) state <= state - 1;
+			else state <= retstate;
+		end
+		else
+			state <= state;
+endcase
+end
+
+task b_write;
+input [23:0] adr;
+input [7:0] dat;
+begin
+	vda <= 1'b1;
+	rw <= 1'b0;
+	ad <= adr;
+	dbo <= dat;
+end
+endtask
+
+task b_read;
+input [23:0] adr;
+begin
+	vda <= 1'b1;
+	rw <= 1'b1;
+	ad <= adr;
+end
+endtask
+
+endmodule
Index: ultimate_cart/veronica/FT816Sys.v
===================================================================
--- ultimate_cart/veronica/FT816Sys.v	(nonexistent)
+++ ultimate_cart/veronica/FT816Sys.v	(revision 438)
@@ -0,0 +1,145 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816Sys.v
+//  - Top Module for 16 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+`define TRUE 	1'b1
+`define FALSE	1'b0
+
+module FT816Sys(btn, xclk, Led, sw);
+input [5:0] btn;
+input xclk;
+output [7:0] Led;
+reg [7:0] Led;
+input [7:0] sw;
+
+wire xreset = ~btn[0];
+wire irq = btn[1];
+reg [32:0] rommem [2047:0];
+reg [7:0] rammem [8191:0];
+wire rw;
+wire [23:0] ad;
+tri [7:0] db;
+wire cs0,cs1,cs4,cs6;
+
+initial begin
+`include "..\..\software\asm\test816.ver"
+end
+
+wire locked;
+wire clk200u,clk85u,clk;
+BUFG bg5 (.I(clk85u), .O(clk) );
+
+DCM dcm0(
+	.RST(xreset),
+	.PSCLK(gnd),
+	.PSEN(gnd),
+	.PSINCDEC(gnd),
+	.DSSEN(gnd),
+	.CLKIN(xclk),
+	.CLKFB(clk200u),	// 200.000 MHz
+	.CLKDV(),
+	.CLKFX(clk85u),		// 85.714 MHz unbuffered
+	.CLKFX180(),
+	.CLK0(),
+	.CLK2X(clk200u),	// 200.xxx MHz
+	.CLK2X180(),
+	.CLK90(),
+	.CLK180(),
+	.CLK270(),
+	.LOCKED(locked),
+	.PSDONE(),
+	.STATUS()
+);
+defparam dcm0.CLK_FEEDBACK = "2x";
+defparam dcm0.CLKDV_DIVIDE = 5.0;
+defparam dcm0.CLKFX_DIVIDE = 25;	// (16/25)*100 = 64 MHz
+defparam dcm0.CLKFX_MULTIPLY = 16;
+defparam dcm0.CLKIN_DIVIDE_BY_2 = "FALSE";
+defparam dcm0.CLKIN_PERIOD = 10.000;
+defparam dcm0.CLKOUT_PHASE_SHIFT = "NONE";
+defparam dcm0.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+defparam dcm0.DFS_FREQUENCY_MODE = "LOW";
+defparam dcm0.DLL_FREQUENCY_MODE = "LOW";
+defparam dcm0.DUTY_CYCLE_CORRECTION = "FALSE";
+//	defparam dcm0.FACTORY_JF = 16'h8080;
+defparam dcm0.PHASE_SHIFT = 0;
+defparam dcm0.STARTUP_WAIT = "FALSE";
+
+always @(posedge clk)
+if (~locked)
+	Led <= 8'h00;
+else begin
+	if (~cs0 && ~rw && ad[7:0]==8'h00)
+		Led <= db;
+end
+
+always @(posedge clk)
+	if (~cs6 & ~rw)
+		rammem[ad[12:0]] <= db;
+
+reg [7:0] ro;
+always @*
+case(ad[1:0])
+2'd0:	ro <= rommem[ad[12:2]][7:0];
+2'd1:	ro <= rommem[ad[12:2]][15:8];
+2'd2:	ro <= rommem[ad[12:2]][23:16];
+2'd3:	ro <= rommem[ad[12:2]][31:24];
+endcase
+
+assign db = rw & ~cs1 ? sw : {8{1'bz}};
+assign db = rw & ~cs4 ? ro : {8{1'bz}};
+assign db = rw & ~cs6 ? rammem[ad[12:0]] : {8{1'bz}};
+
+FT816mpu u1
+(
+	.rst(~locked),
+	.clk(clk),
+	.phi11(),
+	.phi12(),
+	.phi81(),
+	.phi82(),
+	.rdy(1'b1),
+	.e(),
+	.mx(),
+	.nmi(1'b0),
+	.irq(btn[1]),
+	.be(1'b1),
+	.vpa(),
+	.vda(),
+	.mlb(),
+	.vpb(),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.cs0(cs0),
+	.cs1(cs1),
+	.cs2(),
+	.cs3(),
+	.cs4(cs4),
+	.cs5(),
+	.cs6(cs6)
+);
+
+endmodule
Index: ultimate_cart/veronica/FT816Sys2.v
===================================================================
--- ultimate_cart/veronica/FT816Sys2.v	(nonexistent)
+++ ultimate_cart/veronica/FT816Sys2.v	(revision 438)
@@ -0,0 +1,266 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816Sys2.v
+//  - Top Module for 16 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+`define TRUE 	1'b1
+`define FALSE	1'b0
+
+module FT816Sys2(btn, xclk, Led, sw, kclk, kd,
+	HDMIOUTCLKP, HDMIOUTCLKN,
+	HDMIOUTD0P,HDMIOUTD0N,
+	HDMIOUTD1P,HDMIOUTD1N,
+	HDMIOUTD2P,HDMIOUTD2N,
+	HDMIOUTSCL,HDMIOUTSDA
+);
+input [5:0] btn;
+input xclk;
+output [7:0] Led;
+reg [7:0] Led;
+input [7:0] sw;
+inout kclk;
+tri kclk;
+inout kd;
+tri kd;
+output HDMIOUTCLKP;
+output HDMIOUTCLKN;
+output HDMIOUTD0P;
+output HDMIOUTD0N;
+output HDMIOUTD1P;
+output HDMIOUTD1N;
+output HDMIOUTD2P;
+output HDMIOUTD2N;
+inout HDMIOUTSCL;
+inout HDMIOUTSDA;
+tri HDMIOUTSCL;
+tri HDMIOUTSDA;
+
+wire xreset = ~btn[0];
+wire irq = btn[1];
+reg [32:0] rommem [4095:0];
+reg [7:0] rammem [16383:0];
+wire rw;
+wire vda;
+wire [23:0] ad;
+tri [7:0] db;
+wire cs0,cs1,cs4,cs6;
+wire rst;
+wire vclk,vclk2,vclk10;
+wire hsync,vsync,blank,border;
+wire [24:0] tc_rgb;
+
+wire [3:0] TMDS;
+wire [3:0] TMDSB;
+assign HDMIOUTCLKP = TMDS[3];
+assign HDMIOUTCLKN = TMDSB[3];
+assign HDMIOUTD0P = TMDS[0];
+assign HDMIOUTD0N = TMDSB[0];
+assign HDMIOUTD1P = TMDS[1];
+assign HDMIOUTD1N = TMDSB[1];
+assign HDMIOUTD2P = TMDS[2];
+assign HDMIOUTD2N = TMDSB[2];
+//assign HDMIOUTSCL = 1'b0;
+//assign HDMIOUTSDA = 1'b0;
+
+
+initial begin
+`include "..\..\software\asm\FTBios816.ver"
+end
+
+wire locked;
+wire clk200u,clk85u,clk,sys_clk;
+
+clkgen1366x768 u2
+(
+	.xreset(xreset),
+	.xclk(xclk),
+	.rst(rst),
+	.clk100(),
+	.clk25(),
+	.clk200(),
+	.clk125(),		// ETHERMAC clock
+	.vclk(vclk),		// 85.7MHz
+	.vclk2(vclk2),
+	.vclk10(vclk10),
+	.bmp_clk(),
+	.sys_clk(sys_clk),
+	.dram_clk(),
+	.locked(locked),
+	.pulse1000Hz(),
+	.pulse100Hz()
+);
+assign clk = sys_clk;
+
+dvi_out_native u3
+(
+	.reset(rst),
+	.pll_lckd(locked),
+	.clkin(vclk),                // pixel clock, from bufg
+	.clkx2in(vclk2),             // pixel clock x2, from bufg
+	.clkx10in(vclk10),           // pixel clock x10, unbuffered
+	.blue_din(tc_rgb[7:0]),       // Blue data in
+	.green_din(tc_rgb[15:8]),      // Green data in
+	.red_din(tc_rgb[23:16]),        // Red data in
+	.hsync(hsync),          // hsync data
+	.vsync(vsync),          // vsync data
+	.de(!blank),             // data enable
+  
+	.TMDS(TMDS),
+	.TMDSB(TMDSB)
+);
+
+//VGASyncGen640x480_60Hz u4
+WXGASyncGen1366x768_60Hz u4
+(
+	.rst(rst),
+	.clk(vclk),
+	.hSync(hsync),
+	.vSync(vsync),
+	.blank(blank),
+	.border(border)
+);
+
+wire tc_rdy;
+rtfTextController816 tc1
+(
+	.rst(rst),
+	.clk(clk),
+	.rdy(tc_rdy),
+	.rw(rw),
+	.vda(vda),
+	.ad(ad),
+	.db(db),
+	.vclk(vclk),
+	.hsync(hsync),
+	.vsync(vsync),
+	.blank(blank),
+	.border(border),
+	.rgbIn(25'h0),
+	.rgbOut(tc_rgb)
+);
+
+wire kbd_rst;
+wire kbd_rdy;
+PS2KbdToAscii #(.pIOAddress(32'h00FEA110)) u_kbd
+(
+	.rst_i(rst),
+	.clk_i(clk),
+	.cyc_i(vda),
+	.stb_i(vda),
+	.ack_o(kbd_rdy),
+	.we_i(~rw),
+	.adr_i({8'h00,ad}),
+	.dat_i(db),
+	.dat_o(),
+	.db(db),
+	.kclk(kclk),
+	.kd(kd),
+	.irq(),
+	.rst_o(kbd_rst)
+);
+
+PRNG u_prng
+(
+	.rst(rst),
+	.clk(clk),
+	.vda(vda),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.rdy(prng_rdy)
+);
+
+always @(posedge clk)
+if (~locked)
+	Led <= 8'h00;
+else begin
+	if (~cs0 && ~rw && ad[7:0]==8'h00)
+		Led <= db;
+end
+
+always @(posedge clk)
+	if (~cs6 & ~rw && ad[23:15]==17'h0000)
+		rammem[ad[13:0]] <= db;
+
+reg [7:0] ro;
+always @(posedge clk)
+case(ad[1:0])
+2'd0:	ro <= rommem[ad[13:2]][7:0];
+2'd1:	ro <= rommem[ad[13:2]][15:8];
+2'd2:	ro <= rommem[ad[13:2]][23:16];
+2'd3:	ro <= rommem[ad[13:2]][31:24];
+endcase
+/*
+always @(posedge clk)
+if (~cs4 & ~rw)
+	case(ad[1:0])
+	2'd0:	rommem[ad[13:2]][7:0] <= db;
+	2'd0:	rommem[ad[13:2]][15:8] <= db;
+	2'd0:	rommem[ad[13:2]][23:16] <= db;
+	2'd0:	rommem[ad[13:2]][31:24] <= db;
+	endcase
+*/
+reg [7:0] ramo;
+reg ramrdy;
+always @(posedge clk)
+ramo <= rammem[ad[13:0]];
+always @(posedge clk)
+ramrdy <= ~cs6;
+assign db = rw & ~cs1 ? sw : {8{1'bz}};
+assign db = rw & ~cs4 ? ro : {8{1'bz}};
+assign db = (rw & ~cs6 && ad[23:15]==17'h0000) ? ramo : {8{1'bz}};
+wire ram_rdy = ~cs6 ? (~rw ? 1'b1 : ramrdy) : 1'b1;
+
+FT816mpu u1
+(
+	.rst(~rst),
+	.clk(clk),
+	.phi11(),
+	.phi12(),
+	.phi81(),
+	.phi82(),
+	.rdy(prng_rdy & tc_rdy & ram_rdy),
+	.e(),
+	.mx(),
+	.nmi(~kbd_rst),
+	.irq(~btn[1]),
+	.abort(1'b1),
+	.be(1'b1),
+	.vpa(),
+	.vda(vda),
+	.mlb(),
+	.vpb(),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.cs0(cs0),
+	.cs1(cs1),
+	.cs2(),
+	.cs3(),
+	.cs4(cs4),
+	.cs5(),
+	.cs6(cs6)
+);
+
+endmodule
Index: ultimate_cart/veronica/FT816_tb.v
===================================================================
--- ultimate_cart/veronica/FT816_tb.v	(nonexistent)
+++ ultimate_cart/veronica/FT816_tb.v	(revision 438)
@@ -0,0 +1,35 @@
+
+module FT816_tb();
+
+reg [5:0] btn;
+reg [5:0] prev_state;
+reg clk;
+always #10 clk <= ~clk;
+
+initial begin
+	#1 clk <= 1'b0;
+	#50 btn <= 6'h00;
+	#50 btn <= 6'h3D;
+	#20000 btn[1] <= 1'b1;
+	#2000 btn[1] <= 1'b0;
+end
+
+FT816Sys2 u1
+(
+	.btn(btn),
+	.xclk(clk),
+	.Led(),
+	.sw(8'h00)
+);
+
+always @(posedge clk)
+begin
+	prev_state <= u1.u1.u1.state;
+	if (prev_state != u1.u1.u1.state) begin
+	$display("%d %c ad=%h db=%h pc=%h ir=%h %s", $time, u1.u1.u1.rw ? " " : "W",
+		u1.u1.u1.ad, u1.u1.u1.db,
+		u1.u1.u1.pc, u1.u1.u1.ir, u1.u1.u1.fnStateName(u1.u1.u1.state));
+	end
+end
+
+endmodule
Index: ultimate_cart/veronica/FT816mpu.v
===================================================================
--- ultimate_cart/veronica/FT816mpu.v	(nonexistent)
+++ ultimate_cart/veronica/FT816mpu.v	(revision 438)
@@ -0,0 +1,327 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT816mpu.v
+//  - 16 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+`define TRUE 	1'b1
+`define FALSE	1'b0
+
+module FT816mpu(rst, clk, phi11, phi12, phi81, phi82, rdy, e, mx, nmi, irq, abort, be, vpa, vda, mlb, vpb, rw, ad, db, cs0, cs1, cs2, cs3, cs4, cs5, cs6, ct0, ct1, ct2);
+parameter pIOAddress = 24'h00F000;
+parameter pZPAddress = 24'h000010;
+input rst;
+input clk;
+output phi11;
+output phi12;
+output phi81;
+output phi82;
+input rdy;
+output e;
+output mx;
+input nmi;
+input irq;
+input abort;
+input be;
+output vpa;
+output vda;
+output mlb;
+output vpb;
+output tri rw;
+output tri [23:0] ad;
+inout tri [7:0] db;
+output cs0;
+output cs1;
+output cs2;
+output cs3;
+output cs4;
+output cs5;
+output cs6;
+input ct0;
+input ct1;
+input ct2;
+
+wire ivda;
+wire [4:0] cycle;
+reg [15:0] dec_cs0;
+reg [15:0] dec_cs1;
+reg [15:0] dec_cs2;
+reg [15:0] dec_cs3;
+reg [8:0] dec_cs4;
+reg [8:0] dec_cs5;
+reg [7:0] mh1, mh8, mh32;
+reg isRegEnabled;
+reg cntIrq0,cntIrqEn0;
+reg cntIrq1,cntIrqEn1;
+reg cntIrq2,cntIrqEn2;
+reg cntUp0,cntUp1,cntUp2;
+reg [23:0] cntLimit0;
+reg [23:0] realCnt0;
+reg autoCnt0,cntTrig0;
+reg [23:0] cntLimit1;
+reg [23:0] realCnt1;
+reg autoCnt1,cntTrig1;
+reg [23:0] cntLimit2;
+reg [23:0] realCnt2;
+reg autoCnt2,cntTrig2;
+reg [1:0] cntSrc0,cntSrc1,cntSrc2;
+reg [7:0] zp_shadow [15:0];
+
+reg phi1d;
+always @(posedge clk)
+	phi1d <= phi11;
+
+wire match_cs0 = ad[23:8]==dec_cs0;
+wire match_cs1 = ad[23:8]==dec_cs1;
+wire match_cs2 = ad[23:8]==dec_cs2;
+wire match_cs3 = ad[23:8]==dec_cs3;
+wire match_cs4 = ad[23:15]==dec_cs4;
+wire match_cs5 = ad[23:15]==dec_cs5;
+
+wire dec_match1 = (match_cs0 & mh1[0]) |
+				  (match_cs1 & mh1[1]) |
+				  (match_cs2 & mh1[2]) |
+				  (match_cs3 & mh1[3]) |
+				  (match_cs4 & mh1[4]) |
+				  (match_cs5 & mh1[5])
+				  ;
+wire dec_match8 = (match_cs0 & mh8[0]) |
+				  (match_cs1 & mh8[1]) |
+				  (match_cs2 & mh8[2]) |
+				  (match_cs3 & mh8[3]) |
+				  (match_cs4 & mh8[4]) |
+				  (match_cs5 & mh8[5])
+				  ;
+wire dec_match32 = (match_cs0 & mh32[0]) |
+				  (match_cs1 & mh32[1]) |
+				  (match_cs2 & mh32[2]) |
+				  (match_cs3 & mh32[3]) |
+				  (match_cs4 & mh32[4]) |
+				  (match_cs5 & mh32[5])
+				  ;
+
+
+wire iirq = !((cntIrqEn0 & cntIrq0) || 
+			(cntIrqEn1 & cntIrq1) || 
+			(cntIrqEn2 & cntIrq2)) &&
+			irq
+			;
+
+reg [7:0] shadow_ram [31:0];
+
+always @(posedge clk)
+if (~rst) begin
+	isRegEnabled <= `TRUE;
+	dec_cs0 <= 16'h00D0;
+	dec_cs1 <= 16'h00D1;
+	dec_cs2 <= 16'h00D2;
+	dec_cs3 <= 16'h00D3;
+	dec_cs4 <= 9'h01;
+	dec_cs5 <= 9'h02;
+	mh1 <= 8'h0F;
+	mh8 <= 8'h30;
+	mh32 <= 8'h00;
+	cntIrqEn0 <= 1'b0;
+	cntIrqEn1 <= 1'b0;
+	cntIrqEn2 <= 1'b0;
+	cntIrq0 <= 1'b0;
+	cntIrq1 <= 1'b0;
+	cntIrq2 <= 1'b0;
+	cntSrc0 <= 2'b00;
+	cntSrc1 <= 2'b00;
+	cntSrc2 <= 2'b00;
+	cntTrig0 <= 1'b0;
+	cntTrig1 <= 1'b0;
+	cntTrig2 <= 1'b0;
+	cntUp0 <= 1'b1;
+	cntUp1 <= 1'b1;
+	cntUp2 <= 1'b1;
+end
+else begin
+	cntTrig0 <= 1'b0;
+	cntTrig1 <= 1'b0;
+	cntTrig2 <= 1'b0;
+	if (cntSrc0==2'b01 || cntTrig0 || (cntSrc0==2'b10 && ct0))
+		realCnt0 <= cntUp0 ? realCnt0 + 24'd1 : realCnt0 - 24'd1;
+	if (cntSrc1==2'b01 || cntTrig1 || (cntSrc1==2'b10 && ct1))
+		realCnt1 <= cntUp1 ? realCnt1 + 24'd1 : realCnt1 - 24'd1;
+	if (cntSrc2==2'b01 || cntTrig2 || (cntSrc2==2'b10 && ct2))
+		realCnt2 <= cntUp2 ? realCnt2 + 24'd1 : realCnt2 - 24'd1;
+	if (((cntUp0 && realCnt0==cntLimit0) || (!cntUp0 && realCnt0==24'd0)) && cntIrqEn0)
+		cntIrq0 <= 1'b1;
+	if (((cntUp0 && realCnt0==cntLimit0) || (!cntUp0 && realCnt0==24'd0)))
+		realCnt0 <= cntUp0 ? 24'd0 : cntLimit0;
+	if (((cntUp1 && realCnt1==cntLimit1) || (!cntUp1 && realCnt1==24'd0)) && cntIrqEn1)
+		cntIrq1 <= 1'b1;
+	if (((cntUp1 && realCnt1==cntLimit1) || (!cntUp1 && realCnt1==24'd0)))
+		realCnt1 <= cntUp1 ? 24'd0 : cntLimit1;
+	if (((cntUp2 && realCnt2==cntLimit2) || (!cntUp2 && realCnt2==24'd0)) && cntIrqEn2)
+		cntIrq2 <= 1'b1;
+	if (((cntUp2 && realCnt2==cntLimit2) || (!cntUp2 && realCnt2==24'd0)))
+		realCnt2 <= cntUp2 ? 24'd0 : cntLimit2;
+	if (ivda && ad[23:8]==pIOAddress[23:8] && isRegEnabled && ~rw) begin
+		shadow_ram[ad[4:0]] <= db;
+		case(ad[4:0])
+		5'h00:	dec_cs0[7:0] <= db;
+		5'h01:	dec_cs0[15:8] <= db;
+		5'h02:	dec_cs1[7:0] <= db;
+		5'h03:	dec_cs1[15:8] <= db;
+		5'h04:	dec_cs2[7:0] <= db;
+		5'h05:	dec_cs2[15:8] <= db;
+		5'h06:	dec_cs3[7:0] <= db;
+		5'h07:	dec_cs3[15:8] <= db;
+		5'h08:	dec_cs4[7:0] <= db;
+		5'h09:	dec_cs4[8] <= db[0];
+		5'h0A:	dec_cs5[7:0] <= db;
+		5'h0B:	dec_cs5[8] <= db[0];
+		5'h0C:	mh1 <= db;
+		5'h0D:	mh8 <= db;
+		5'h0E:	mh32 <= db;
+		5'h0F:	if (db==8'hE0)
+					isRegEnabled <= `FALSE;
+		5'h10:	cntLimit0[7:0] <= db;
+		5'h11:	cntLimit0[15:8] <= db;
+		5'h12:	cntLimit0[23:16] <= db;
+		5'h13:	begin
+				cntIrqEn0 <= db[0];
+				cntIrq0 <= 1'b0;
+				cntSrc0 <= db[3:2];
+				cntUp0 <= db[4];
+				end
+		5'h14:	cntLimit1[7:0] <= db;
+		5'h15:	cntLimit1[15:8] <= db;
+		5'h16:	cntLimit1[23:16] <= db;
+		5'h17:	begin
+				cntIrqEn1 <= db[0];
+				cntIrq1 <= 1'b0;
+				cntSrc1 <= db[3:2];
+				cntUp1 <= db[4];
+				end
+		5'h18:	cntLimit2[7:0] <= db;
+		5'h19:	cntLimit2[15:8] <= db;
+		5'h1A:	cntLimit2[23:16] <= db;
+		5'h1B:	begin
+				cntIrqEn2 <= db[0];
+				cntIrq2 <= 1'b0;
+				cntSrc2 <= db[3:2];
+				cntUp2 <= db[4];
+				end
+		5'h1C:	cntTrig0 <= 1'b1;
+		5'h1D:	cntTrig1 <= 1'b1;
+		5'h1E:	cntTrig2 <= 1'b1;
+		endcase
+	end
+	if (ivda && ad[23:4]==pZPAddress[23:4] && ~rw) begin
+		zp_shadow[ad[3:0]] <= db;
+		case(ad[3:0])
+		4'h0:	realCnt0[7:0] <= db;
+		4'h1:	realCnt0[15:8] <= db;
+		4'h2:	realCnt0[23:16] <= db;
+		4'h4:	realCnt1[7:0] <= db;
+		4'h5:	realCnt1[15:8] <= db;
+		4'h6:	realCnt1[23:16] <= db;
+		4'h8:	realCnt2[7:0] <= db;
+		4'h9:	realCnt2[15:8] <= db;
+		4'hA:	realCnt2[23:16] <= db;
+		endcase
+	end
+end
+
+reg [7:0] dbo;
+always @*
+case(ad[3:0])
+4'h0:	dbo <= realCnt0[7:0];
+4'h1:	dbo <= realCnt0[15:8];
+4'h2:	dbo <= realCnt0[23:16];
+4'h4:	dbo <= realCnt1[7:0];
+4'h5:	dbo <= realCnt1[15:8];
+4'h6:	dbo <= realCnt1[23:16];
+4'h8:	dbo <= realCnt2[7:0];
+4'h9:	dbo <= realCnt2[15:8];
+4'hA:	dbo <= realCnt2[23:16];
+default:	dbo <= zp_shadow[ad[3:0]];
+endcase
+
+wire cs_mpu = (ivda && ad[23:4]==pZPAddress[23:4]) || (ivda && ad[23:8]==pIOAddress[23:8]);
+assign db = (ivda && ad[23:4]==pZPAddress[23:4] && rw) ? dbo : {8{1'bz}};
+assign db =	(ivda && ad[23:8]==pIOAddress[23:8] && rw) ? (
+	ad[4:0]==5'h1F ? {cntIrq2,cntIrq1,cntIrq0} :
+	shadow_ram[ad[4:0]] ) :
+	{8{1'bz}};
+assign vda = !cs_mpu & ivda;
+
+reg trig1;
+reg trig8;
+always @(posedge clk)
+begin
+	if (cycle==5'd0 & dec_match1 & (vpa | vda))
+		trig1 <= `TRUE;
+	if (cycle==5'd30 && rdy)
+		trig1 <= `FALSE;
+	if ((cycle==5'd0 || cycle==5'd8 || cycle==5'd16 || cycle==5'd24) & dec_match8 & (vpa | vda))
+		trig8 <= `TRUE;
+	if ((cycle==5'd6 || cycle==5'd14 || cycle==5'd22 || cycle==5'd30) && rdy)
+		trig8 <= `FALSE;
+end
+
+assign cs0 = !((trig1 & match_cs0 & mh1[0]) | (trig8 & match_cs0 & mh8[0]) | (match_cs0 & mh32[0]));
+assign cs1 = !((trig1 & match_cs1 & mh1[1]) | (trig8 & match_cs1 & mh8[1]) | (match_cs0 & mh32[1]));
+assign cs2 = !((trig1 & match_cs2 & mh1[2]) | (trig8 & match_cs2 & mh8[2]) | (match_cs0 & mh32[2]));
+assign cs3 = !((trig1 & match_cs3 & mh1[3]) | (trig8 & match_cs3 & mh8[3]) | (match_cs0 & mh32[3]));
+assign cs4 = !((trig1 & match_cs4 & mh1[4]) | (trig8 & match_cs4 & mh8[4]) | (match_cs0 & mh32[4]));
+assign cs5 = !((trig1 & match_cs5 & mh1[5]) | (trig8 & match_cs5 & mh8[5]) | (match_cs0 & mh32[5]));
+assign cs6 = !(!(match_cs0 | match_cs1 | match_cs2 | match_cs3 | match_cs4 | match_cs5) & (vda | vpa));
+
+wire rdy816 = (vda|vpa) ? (
+			  dec_match1 ? trig1 && (cycle==5'd30) && rdy :
+			  dec_match8 ? trig8 && (cycle==5'd30 || cycle==5'd22 || cycle==5'd14 || cycle==5'd6) && rdy :
+				rdy) : 1'b1;
+
+FT816 u1
+(
+	.rst(rst),
+	.clk(clk),
+	.nmi(nmi),
+	.irq(iirq),
+	.abort(abort),
+	.e(e),
+	.mx(mx),
+	.cyc(cycle),
+	.phi11(phi11),
+	.phi12(phi12),
+	.phi81(phi81),
+	.phi82(phi82),
+	.mlb(mlb),
+	.vpb(vpb),
+	.rdy(rdy816),
+	.be(be),
+	.vpa(vpa),
+	.vda(ivda),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.err_i(1'b0),
+	.rty_i(1'b0)
+);
+
+endmodule
Index: ultimate_cart/veronica/FT832.v
===================================================================
--- ultimate_cart/veronica/FT832.v	(nonexistent)
+++ ultimate_cart/veronica/FT832.v	(revision 438)
@@ -0,0 +1,5850 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2013-2015  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT832.v
+//  - 8/16/32 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//
+// Approx 10561 LUTs   (16900 LC's)
+// 9 block rams                                                                       
+// ============================================================================
+//
+`define TRUE		1'b1
+`define FALSE		1'b0
+
+`define DEBUG		1'b1
+
+// Comment out the SUPPORT_xxx definitions to remove a core feature.
+`define SUPPORT_TASK	1'b1
+`define TASK_MEM        512
+`define TASK_MEM_ABIT   8
+`define TASK_BL         1'b1                // core uses back link register rather than stack
+`define SUPPORT_SEG     1'b1
+`define ICACHE_4K		1'b1
+//`define ICACHE_16K		1'b1
+//`define ICACHE_2WAY		1'b1
+`define SUPPORT_BCD		1'b1
+//`define SUPPORT_CGI		1'b1			// support the control giveaway interrupt
+`define SUPPORT_NEW_INSN    1'b1
+
+`define BYTE_RST_VECT	32'h0000FFFC
+`define BYTE_NMI_VECT	32'h0000FFFA
+`define BYTE_IRQ_VECT	32'h0000FFFE
+`define BYTE_ABT_VECT	32'h0000FFF8
+`define BYTE_COP_VECT	32'h0000FFF4
+`define RST_VECT_816	32'h0000FFFC
+`define IRQ_VECT_816	32'h0000FFEE
+`define NMI_VECT_816	32'h0000FFEA
+`define ABT_VECT_816	32'h0000FFE8
+`define BRK_VECT_816	32'h0000FFE6
+`define COP_VECT_816	32'h0000FFE4
+
+`define RST_VECT_832	32'h0000FFFC
+`define IRQ_VECT_832	32'h0000FFDE
+`define NMI_VECT_832	32'h0000FFDA
+`define ABT_VECT_832	32'h0000FFD8
+`define BRK_VECT_832	32'h0000FFD6
+`define COP_VECT_832	32'h0000FFD4
+`define ADV_VECT_832    32'h0000FFD2    // address violation
+
+`define BRK			9'h00
+`define BRK2		9'h100
+`define RTI			9'h40
+`define RTS			9'h60
+`define PHP			9'h08
+`define CLC			9'h18
+`define CMC         9'h118
+`define PLP			9'h28
+`define SEC			9'h38
+`define PHA			9'h48
+`define CLI			9'h58
+`define PLA			9'h68
+`define SEI			9'h78
+`define DEY			9'h88
+`define DEY4		9'h188
+`define TYA			9'h98
+`define TAY			9'hA8
+`define CLV			9'hB8
+`define SEV			9'h1B8
+`define INY			9'hC8
+`define INY4		9'h1C8
+`define CLD			9'hD8
+`define INX			9'hE8
+`define INX4		9'h1E8
+`define SED			9'hF8
+`define ROR_ACC		9'h6A
+`define TXA			9'h8A
+`define TXS			9'h9A
+`define TAX			9'hAA
+`define TSX			9'hBA
+`define DEX			9'hCA
+`define DEX4		9'h1CA
+`define NOP			9'hEA
+`define NOP2		9'h1EA
+`define TXY			9'h9B
+`define TYX			9'hBB
+`define TAS			9'h1B
+`define TSA			9'h3B
+`define TCD			9'h5B
+`define TDC			9'h7B
+`define STP			9'hDB
+`define XCE			9'hFB
+`define INA			9'h1A
+`define DEA			9'h3A
+`define SEP			9'hE2
+`define SEP16       9'h1E2
+`define REP			9'hC2
+`define REP16       9'h1C2
+`define PEA			9'hF4
+`define PEI			9'hD4
+`define PER			9'h62
+`define WDM			9'h42
+`define PEAxl       9'h1F4
+`define CS          9'h11B
+`define SS          9'h16A
+`define SEG         9'h13B
+`define SEG0        9'h15B
+`define IOS         9'h17B
+`define PHDS        9'h10B
+`define PLDS        9'h12B
+`define PHCS        9'h14B
+`define PCHIST      9'h1F0
+`define CACHE       9'h1E0
+`define BYT         9'h18B
+`define UBT         9'h19B
+`define HAF         9'h1AB
+`define UHF         9'h1BB
+`define WRD         9'h19A
+`define INF         9'h14A
+`define AAX         9'h18A
+`define RA          9'h1F8
+`define CR          9'h1D8
+`define TASS        9'h15A
+`define TSSA        9'h17A
+`define SDU         9'h1BA
+
+`define ADC_IMM		9'h69
+`define ADC_ZP		9'h65
+`define ADC_ZPX		9'h75
+`define ADC_IX		9'h61
+`define ADC_IY		9'h71
+`define ADC_IYL		9'h77
+`define ADC_ABS		9'h6D
+`define ADC_ABSX	9'h7D
+`define ADC_ABSY	9'h79
+`define ADC_I		9'h72
+`define ADC_IL		9'h67
+`define ADC_AL		9'h6F
+`define ADC_ALX		9'h7F
+`define ADC_DSP		9'h63
+`define ADC_DSPIY	9'h73
+`define ADC_XDSPIY	9'h173
+`define ADC_XIYL	9'h177
+`define ADC_XIL		9'h167
+`define ADC_XABS	9'h16D
+`define ADC_XABSX	9'h17D
+`define ADC_XABSY	9'h179
+
+`define SBC_IMM		9'hE9
+`define SBC_ZP		9'hE5
+`define SBC_ZPX		9'hF5
+`define SBC_IX		9'hE1
+`define SBC_IY		9'hF1
+`define SBC_IYL		9'hF7
+`define SBC_ABS		9'hED
+`define SBC_ABSX	9'hFD
+`define SBC_ABSY	9'hF9
+`define SBC_I		9'hF2
+`define SBC_IL		9'hE7
+`define SBC_AL		9'hEF
+`define SBC_ALX		9'hFF
+`define SBC_DSP		9'hE3
+`define SBC_DSPIY	9'hF3
+`define SBC_XDSPIY	9'h1F3
+`define SBC_XIYL	9'h1F7
+`define SBC_XIL		9'h1E7
+`define SBC_XABS	9'h1ED
+`define SBC_XABSX	9'h1FD
+`define SBC_XABSY	9'h1F9
+
+`define CMP_IMM		9'hC9
+`define CMP_ZP		9'hC5
+`define CMP_ZPX		9'hD5
+`define CMP_IX		9'hC1
+`define CMP_IY		9'hD1
+`define CMP_IYL		8'hD7
+`define CMP_ABS		9'hCD
+`define CMP_ABSX	9'hDD
+`define CMP_ABSY	9'hD9
+`define CMP_I		9'hD2
+`define CMP_IL		9'hC7
+`define CMP_AL		9'hCF
+`define CMP_ALX		9'hDF
+`define CMP_DSP		9'hC3
+`define CMP_DSPIY	9'hD3
+`define CMP_XDSPIY	9'h1D3
+`define CMP_XIYL	8'h1D7
+`define CMP_XIL		9'h1C7
+`define CMP_XABS	9'h1CD
+`define CMP_XABSX	9'h1DD
+`define CMP_XABSY	9'h1D9
+
+`define LDA_IMM8	9'hA5
+`define LDA_IMM16	9'hB9
+`define LDA_IMM32	9'hA9
+
+`define AND_IMM		9'h29
+`define AND_ZP		9'h25
+`define AND_ZPX		9'h35
+`define AND_IX		9'h21
+`define AND_IY		9'h31
+`define AND_IYL		9'h37
+`define AND_ABS		9'h2D
+`define AND_ABSX	9'h3D
+`define AND_ABSY	9'h39
+`define AND_RIND	9'h32
+`define AND_I		9'h32
+`define AND_IL		9'h27
+`define AND_DSP		9'h23
+`define AND_DSPIY	9'h33
+`define AND_AL		9'h2F
+`define AND_ALX		9'h3F
+`define AND_XDSPIY	9'h133
+`define AND_XIL		9'h127
+`define AND_XIYL	9'h137
+`define AND_XABS	9'h12D
+`define AND_XABSX	9'h13D
+`define AND_XABSY	9'h139
+
+`define ORA_IMM		9'h09
+`define ORA_ZP		9'h05
+`define ORA_ZPX		9'h15
+`define ORA_IX		9'h01
+`define ORA_IY		9'h11
+`define ORA_IYL		9'h17
+`define ORA_ABS		9'h0D
+`define ORA_ABSX	9'h1D
+`define ORA_ABSY	9'h19
+`define ORA_I		9'h12
+`define ORA_IL		9'h07
+`define ORA_AL		9'h0F
+`define ORA_ALX		9'h1F
+`define ORA_DSP		9'h03
+`define ORA_DSPIY	9'h13
+`define ORA_XDSPIY	9'h113
+`define ORA_XIL		9'h107
+`define ORA_XIYL	9'h117
+`define ORA_XABS	9'h10D
+`define ORA_XABSX	9'h11D
+`define ORA_XABSY	9'h119
+
+`define EOR_IMM		9'h49
+`define EOR_ZP		9'h45
+`define EOR_ZPX		9'h55
+`define EOR_IX		9'h41
+`define EOR_IY		9'h51
+`define EOR_IYL		9'h57
+`define EOR_ABS		9'h4D
+`define EOR_ABSX	9'h5D
+`define EOR_ABSY	9'h59
+`define EOR_RIND	9'h52
+`define EOR_I		9'h52
+`define EOR_IL		9'h47
+`define EOR_DSP		9'h43
+`define EOR_DSPIY	9'h53
+`define EOR_AL		9'h4F
+`define EOR_ALX		9'h5F
+`define EOR_XDSPIY	9'h153
+`define EOR_XIL		9'h147
+`define EOR_XIYL	9'h157
+`define EOR_XABS	9'h14D
+`define EOR_XABSX	9'h15D
+`define EOR_XABSY	9'h159
+
+//`define LDB_RIND	9'hB2	// Conflict with LDX #imm16
+
+`define LDA_IMM		9'hA9
+`define LDA_ZP		9'hA5
+`define LDA_ZPX		9'hB5
+`define LDA_IX		9'hA1
+`define LDA_IY		9'hB1
+`define LDA_IYL		9'hB7
+`define LDA_ABS		9'hAD
+`define LDA_ABSX	9'hBD
+`define LDA_ABSY	9'hB9
+`define LDA_I		9'hB2
+`define LDA_IL		9'hA7
+`define LDA_AL		9'hAF
+`define LDA_ALX		9'hBF
+`define LDA_DSP		9'hA3
+`define LDA_DSPIY	9'hB3
+`define LDA_XDSPIY	9'h1B3
+`define LDA_XIL		9'h1A7
+`define LDA_XIYL	9'h1B7
+`define LDA_XABS	9'h1AD
+`define LDA_XABSX	9'h1BD
+`define LDA_XABSY	9'h1B9
+
+`define STA_ZP		9'h85
+`define STA_ZPX		9'h95
+`define STA_IX		9'h81
+`define STA_IY		9'h91
+`define STA_IYL		9'h97
+`define STA_ABS		9'h8D
+`define STA_ABSX	9'h9D
+`define STA_ABSY	9'h99
+`define STA_I		9'h92
+`define STA_IL		9'h87
+`define STA_AL		9'h8F
+`define STA_ALX		9'h9F
+`define STA_DSP		9'h83
+`define STA_DSPIY	9'h93
+`define STA_XDSPIY	9'h193
+`define STA_XIL		9'h187
+`define STA_XIYL	9'h197
+`define STA_XABS	9'h18D
+`define STA_XABSX	9'h19D
+`define STA_XABSY	9'h199
+
+`define ASL_ACC		9'h0A
+`define ASR_ACC		9'h10A
+`define ASL_ZP		9'h06
+`define ASL_RR		9'h06
+`define ASL_ZPX		9'h16
+`define ASL_ABS		9'h0E
+`define ASL_ABSX	9'h1E
+`define ASL_XABS	9'h10E
+`define ASL_XABSX	9'h11E
+
+`define ROL_ACC		9'h2A
+`define ROL_ZP		9'h26
+`define ROL_RR		9'h26
+`define ROL_ZPX		9'h36
+`define ROL_ABS		9'h2E
+`define ROL_ABSX	9'h3E
+`define ROL_XABS	9'h12E
+`define ROL_XABSX	9'h13E
+
+`define LSR_ACC		9'h4A
+`define LSR_ZP		9'h46
+`define LSR_RR		9'h46
+`define LSR_ZPX		9'h56
+`define LSR_ABS		9'h4E
+`define LSR_ABSX	9'h5E
+`define LSR_XABS	9'h14E
+`define LSR_XABSX	9'h15E
+
+`define ROR_ZP		9'h66
+`define ROR_ZPX		9'h76
+`define ROR_ABS		9'h6E
+`define ROR_ABSX	9'h7E
+`define ROR_XABS	9'h16E
+`define ROR_XABSX	9'h17E
+
+`define DEC_RR		9'hC6
+`define DEC_ZP		9'hC6
+`define DEC_ZPX		9'hD6
+`define DEC_ABS		9'hCE
+`define DEC_ABSX	9'hDE
+`define DEC_XABS	9'h1CE
+`define DEC_XABSX	9'h1DE
+`define INC_RR		9'hE6
+`define INC_ZP		9'hE6
+`define INC_ZPX		9'hF6
+`define INC_ABS		9'hEE
+`define INC_ABSX	9'hFE
+`define INC_XABS	9'h1EE
+`define INC_XABSX	9'h1FE
+`define INC_IMM     9'h1E9
+
+`define BIT_IMM		9'h89
+`define BIT_ZP		9'h24
+`define BIT_ZPX		9'h34
+`define BIT_ABS		9'h2C
+`define BIT_ABSX	9'h3C
+`define BIT_XABS	9'h12C
+`define BIT_XABSX	9'h13C
+
+// CMP = SUB r0,...
+// BIT = AND r0,...
+`define BPL			9'h10
+`define BVC			9'h50
+`define BCC			9'h90
+`define BNE			9'hD0
+`define BMI			9'h30
+`define BVS			9'h70
+`define BCS			9'hB0
+`define BEQ			9'hF0
+`define BRL			9'h82
+`define BRA			9'h80
+`define BGT         9'h110
+`define BLT         9'h130
+`define BGE         9'h190
+`define BLE         8'h1B0
+
+`define JML			9'h5C
+`define JML_IND     9'hDC
+`define JML_XIND    9'h1DC
+`define JMF			9'h15C
+`define JMP			9'h4C
+`define JMP_IND		9'h6C
+`define JMP_INDX	9'h7C
+`define JML_XINDX   9'h17C
+`define JSR			9'h20
+`define JSL			9'h22
+`define JSL_XINDX   9'h1FC
+`define JSF			9'h122
+`define JSR_INDX	9'hFC
+`define RTS			9'h60
+`define RTT         9'h160
+`define RTL			9'h6B
+`define RTF			9'h16B
+`define NOP			9'hEA
+`define NOP2        9'h1EA
+`define RTS_IMM     9'h1C0
+`define RTL_IMM     9'h168
+`define BSR         9'h128
+`define BSL         9'h148
+
+`define PLX			9'hFA
+`define PLY			9'h7A
+`define PHX			9'hDA
+`define PHY			9'h5A
+`define WAI			9'hCB
+`define PHB			9'h8B
+`define PHD			9'h0B
+`define PHK			9'h4B
+`define XBA			9'hEB
+`define XBAW        9'h1EB
+`define COP			9'h02
+`define PLB			9'hAB
+`define PLD			9'h2B
+`define MUL         9'h12A
+
+`define LDX_IMM		9'hA2
+`define LDX_ZP		9'hA6
+`define LDX_ZPX		9'hB6
+`define LDX_ZPY		9'hB6
+`define LDX_ABS		9'hAE
+`define LDX_ABSY	9'hBE
+`define LDX_XABS	9'h1AE
+`define LDX_XABSY	9'h1BE
+
+`define LDX_IMM32	9'hA2
+`define LDX_IMM16	9'hB2
+`define LDX_IMM8	9'hA6
+
+`define LDY_IMM		9'hA0
+`define LDY_ZP		9'hA4
+`define LDY_ZPX		9'hB4
+`define LDY_IMM32	9'hA0
+`define LDY_IMM8	9'hA1
+`define LDY_ABS		9'hAC
+`define LDY_ABSX	9'hBC
+`define LDY_XABS	9'h1AC
+`define LDY_XABSX	9'h1BC
+
+`define STX_ZP		9'h86
+`define STX_ZPX		9'h96
+`define STX_ZPY		9'h96
+`define STX_ABS		9'h8E
+`define STX_XABS	9'h18E
+
+`define STY_ZP		9'h84
+`define STY_ZPX		9'h94
+`define STY_ABS		9'h8C
+`define STY_XABS	9'h18C
+
+`define STZ_ZP		9'h64
+`define STZ_ZPX		9'h74
+`define STZ_ABS		9'h9C
+`define STZ_ABSX	9'h9E
+`define STZ_XABS	9'h19C
+`define STZ_XABSX	9'h19E
+
+`define CPX_IMM		9'hE0
+`define CPX_IMM32	9'hE0
+`define CPX_IMM8	9'hE2
+`define CPX_ZP		9'hE4
+`define CPX_ZPX		9'hE4
+`define CPX_ABS		9'hEC
+`define CPX_XABS	9'h1EC
+`define CPY_IMM		9'hC0
+`define CPY_IMM32	9'hC0
+`define CPY_IMM8	9'hC1
+`define CPY_ZP		9'hC4
+`define CPY_ZPX		9'hC4
+`define CPY_ABS		9'hCC
+`define CPY_XABS	9'h1CC
+
+`define TRB_ZP		9'h14
+`define TRB_ABS		9'h1C
+`define TRB_XABS	9'h11C
+`define TSB_ZP		9'h04
+`define TSB_ABS		9'h0C
+`define TSB_XABS	9'h10C
+
+`define MVP			9'h44
+`define MVN			9'h54
+`define FILL		9'h144
+
+`define TSK_IMM     9'h1A2
+`define TSK_ACC     9'h13A
+`define LDT_XABSX   9'h14C
+`define LDT_XABS    9'h16C
+`define FORK_IMM    9'h1A0
+`define FORK_ACC    9'h1AA
+`define TTA         9'h11A
+`define TASB        9'h19A
+`define TSBA        9'h1BA
+`define JCR         9'h120
+`define JCL         9'h182
+`define JCF         9'h162
+`define RTC         9'h140 
+`define JCI         9'h180
+`define TJ          9'h1CB
+
+// Page Two Opcodes
+`define PG2			9'h42
+
+`define NOTHING		6'd0
+`define SR_70		6'd1
+`define SR_158		6'd2
+`define WORD_310	6'd4
+`define PC_70		6'd5
+`define PC_158		6'd6
+`define PC_2316		6'd7
+`define PC_3124		6'd8
+`define PC_310		6'd9
+`define WORD_311	6'd10
+`define IA_310		6'd11
+`define IA_70		6'd12
+`define IA_158		6'd13
+`define WORD_312	6'd15
+`define WORD_313	6'd16
+`define WORD_314	6'd17
+`define IA_2316		6'd18
+`define BYTE_72		6'd25
+`define TRIP_2316	6'd26
+`define WORD_71S    6'd27
+`define LOAD_70     6'd28
+`define LOAD_158    6'd29
+`define LOAD_2316   6'd30
+`define LOAD_3124   6'd31
+`define WORD_159S   6'd36
+`define WORD_2317S  6'd37
+`define WORD_3125S  6'd38
+`define IA_3124     6'd39
+`define CS_70       6'd40
+`define CS_158      6'd41
+`define CS_2316     6'd42
+`define CS_3124     6'd43
+`define LDW_TR70    6'd44
+`define LDW_TR158   6'd45
+`define CPY_BUF     6'd46
+`define LDW_TR70S   6'd47
+`define LDW_TR158S  6'd48
+
+`define STW_DEF		6'h1
+`define STW_SR158   6'd2
+`define STW_CS3124  6'd4
+`define STW_CS2316  6'd5
+`define STW_CS158   6'd6
+`define STW_CS70    6'd7
+`define STW_DS3124  6'd8
+`define STW_DS2316  6'd9
+`define STW_DS158   6'd10
+`define STW_DS70    6'd11
+`define STW_ACC3124 6'd12
+`define STW_ACC2316 6'd13
+`define STW_RES8	6'd14
+`define STW_TR70    6'd15
+`define STW_TR158   6'd16
+`define STW_PC3124	6'd19
+`define STW_PC2316	6'd20
+`define STW_PC158	6'd21
+`define STW_PC70	6'd22
+`define STW_SR70	6'd23
+`define STW_Z8		6'd24
+`define STW_DEF8	6'd25
+`define STW_DEF70	6'd26
+`define STW_DEF158	6'd27
+`define STW_DEF2316	6'd28
+`define STW_DEF3124 6'd29
+
+`define STW_ACC70	6'd32
+`define STW_ACC158	6'd33
+`define STW_X70		6'd34
+`define STW_X158	6'd35
+`define STW_Y70		6'd36
+`define STW_Y158	6'd37
+`define STW_Z70		6'd38
+`define STW_Z158	6'd39
+`define STW_DBR		6'd40
+`define STW_DPR158	6'd41
+`define STW_DPR70	6'd42
+`define STW_TMP158	6'd43
+`define STW_TMP70	6'd44
+`define STW_IA158	6'd45
+`define STW_IA70	6'd46
+`define STW_BRA		6'd47
+
+`define STW_X3124   6'd48
+`define STW_X2316   6'd49
+`define STW_Y3124   6'd50
+`define STW_Y2316   6'd51
+`define STW_Z3124   6'd52
+`define STW_Z2316   6'd53
+`define STW_IA2316  6'd54
+`define STW_IA3124  6'd55
+`define STW_TMP3124 6'd56
+`define STW_TMP2316 6'd57
+`define STW_CPY_BUF 6'd58
+
+// Input Frequency is 32 times the 00 clock
+
+module FT832(corenum, rst, clk, clko, cyc, phi11, phi12, phi81, phi82, nmi, irq, abort, e, mx, rdy, be, vpa, vda, mlb, vpb,
+    rw, ad, db, err_i, rty_i);
+parameter STORE_SKIPPING = 1'b1;        // set to 1 to skip the store operation if the value didn't change during a RMW instruction
+parameter EXTRA_LONG_BRANCHES = 1'b1;   // set to 1 to use an illegal branch displacement ($FF) to indicate a long branch
+parameter IO_SEGMENT = 32'hFFD00000;    // set to determine the segment value of the IOS: prefix
+parameter PC24 = 1'b1;                  // set if PC is to be true 24 bits (generates slightly more hardware).
+parameter POPBF = 1'b0;                 // set to 1 if popping the break flag from the stack is desired
+parameter TASK_VECTORING = 1'b1;        // controls whether the core uses task vectors or regular interrupt vectors
+//parameter DEAD_CYCLE = 1'b1;            // insert dead cycles between each memory access
+
+// There parameters are not meant to be altered.
+parameter RESET1 = 6'd0;
+parameter IFETCH = 6'd1;
+parameter LDT1 = 6'd2;
+parameter TSK1 = 6'd3;
+parameter TSK2 = 6'd4;
+parameter DECODE = 6'd5;
+parameter INF1 = 6'd6;
+parameter SSM1 = 6'd7;
+parameter TSK3 = 6'd8;
+parameter STORE1 = 6'd9;
+parameter STORE2 = 6'd10;
+parameter JSR161 = 6'd11;
+parameter RTS1 = 6'd12;
+parameter IY3 = 6'd13;
+parameter BSR1 = 6'd14;
+parameter BYTE_IX5 = 6'd15;
+parameter BYTE_IY5 = 6'd16;
+parameter WAIT_DHIT = 6'd17;
+parameter TSK4 = 6'd18;
+parameter BUS_ERROR = 6'd19;
+parameter LOAD_MAC1 = 6'd20;
+parameter LOAD_MAC2 = 6'd21;
+parameter LOAD_MAC3 = 6'd22;
+parameter LOAD_DCACHE = 6'd26;
+parameter LOAD_ICACHE = 6'd27;
+parameter LOAD_IBUF1 = 6'd28;
+parameter LOAD_IBUF2 = 6'd29;
+parameter LOAD_IBUF3 = 6'd30;
+parameter ICACHE1 = 6'd31;
+parameter IBUF1 = 6'd32;
+parameter DCACHE1 = 6'd33;
+parameter MVN816 = 6'd36;
+parameter JMF1 = 6'd37;
+parameter PLDS1 = 6'd38;
+parameter PLDS2 = 6'd39;
+parameter TASS1 = 6'd40;
+parameter ICACHE2 = 6'd43;
+parameter CALC = 6'd44;
+parameter ICACHE3 = 6'd45;
+
+parameter SEGF_NONE = 6'd0;
+parameter SEGF_EXEC = 6'd1;
+parameter SEGF_WRITE = 6'd2;
+parameter SEGF_BOUND = 6'd3;
+
+input [31:0] corenum;
+input rst;
+input clk;
+output clko;
+output reg [4:0] cyc;
+output phi11;
+output phi12;
+output phi81;
+output phi82;
+input nmi;
+input irq;
+input abort;
+output e;
+output mx;
+input rdy;
+input be;
+output reg vpa;
+output reg vda;
+output reg mlb;
+output reg vpb;
+output tri rw;
+output tri [31:0] ad;
+inout tri [7:0] db;
+input err_i;
+input rty_i;
+
+parameter TRUE = 1'b1;
+parameter FALSE = 1'b0;
+
+reg [31:0] phi1r,phi2r;
+reg [31:0] ado1;
+
+reg rwo;
+reg [7:0] dbo;
+reg [31:0] ado;
+reg [7:0] dbi;
+reg pg2;
+reg [5:0] state;    // machine state number
+reg [5:0] retstate; // return state - allows 1 level of state subroutine call
+reg [7:0] cnt;      // icache counter / general counter
+reg [7:0] maxcnt;
+reg [127:0] ir;     // the instruction register
+wire [8:0] ir9 = {pg2,ir[7:0]}; // The first byte of the instruction
+reg [23:0] pc,opc,npc;
+reg pc_cap;                 // pc history capture flag
+`ifdef SUPPORT_SEG
+reg [15:0] ds;              // data segment
+reg [15:0] cs;              // code segment
+reg [15:0] ss;          // stack segment
+reg [31:0] cs_base, cs_limit;
+reg [31:0] ds_base, ds_limit;
+reg [31:0] ss_base, ss_limit;
+reg ds_wr;              // data segment is writable
+reg ss_wr;              // writability of stack segment
+reg cs_wr;              // writability of code segment
+reg mem_wr;             // memory is writable
+reg [31:0] lmt;         // segment limit
+reg [3:0] seg_fault_val;
+wire [31:0] cspc = cs_base + pc;
+`else
+wire [31:0] cspc = pc;
+`endif
+reg [15:0] dpr;		        // direct page register
+reg [7:0] dbr;		        // data bank register
+reg [31:0] x,y,acc,sp;      // programming model registers
+reg [23:0] stack_page = 24'd1;    // The default stack page for eight bit emulation
+reg [15:0] stack_bank = 16'd0;    // The default stack bank for sixteen bit emulation
+reg [1:0] stksz;            // size of stack 00=256,01=4095,10=65536,11=16777216
+reg [15:0] tmp;
+wire [15:0] acc16 = acc[15:0];  // convenience wires
+wire [7:0] acc8=acc[7:0];
+wire [7:0] x8=x[7:0];
+wire [7:0] y8=y[7:0];
+wire [15:0] x16 = x[15:0];
+wire [15:0] y16 = y[15:0];
+wire [15:0] sp16 = sp[15:0];
+wire [31:0] acc_dec = acc - 32'd1;
+wire [31:0] acc_inc = acc + 32'd1;
+wire [31:0] x_dec = x - 32'd1;
+wire [31:0] x_inc = x + 32'd1;
+wire [31:0] y_dec = y - 32'd1;
+wire [31:0] y_inc = y + 32'd1;
+reg gie;	// global interrupt enable (set when sp is loaded)
+reg hwi;	// hardware interrupt indicator
+reg im;
+reg cf,vf,nf,zf,df,em,bf;
+reg m816,m832;
+reg x_bit,m_bit;
+reg m16,m32;
+reg xb16,xb32;
+reg mxb16,mxb32;
+reg mib;
+reg ssm;
+wire DEAD_CYCLE = FALSE;//(vda|vpa) && ado >= 32'h10000;
+
+//wire m16 = m816 & ~m_bit;
+//wire xb16 = m816 & ~x_bit;
+always @(m816,m832,m_bit,x_bit)
+begin
+    case ({~m832,~m816,m_bit,x_bit})
+    4'b0000:    begin m32 = `FALSE; m16 = `TRUE; xb32 = `TRUE; xb16 = `FALSE; end
+    4'b0001:    begin m32 = `FALSE; m16 = `TRUE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b0010:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `TRUE; xb16 = `FALSE; end
+    4'b0011:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b0100:    begin m32 = `TRUE; m16 = `FALSE; xb32 = `TRUE; xb16 = `FALSE; end
+    4'b0101:    begin m32 = `TRUE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b0110:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `TRUE; xb16 = `FALSE; end
+    4'b0111:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1000:    begin m32 = `FALSE; m16 = `TRUE; xb32 = `FALSE; xb16 = `TRUE; end
+    4'b1001:    begin m32 = `FALSE; m16 = `TRUE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1010:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `TRUE; end
+    4'b1011:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1100:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1101:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1110:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    4'b1111:    begin m32 = `FALSE; m16 = `FALSE; xb32 = `FALSE; xb16 = `FALSE; end
+    endcase 
+end
+wire [31:0] acc32 = m32 ? acc : m16 ? {16'h0000,acc[15:0]} : {24'h000000,acc[7:0]}; // for multiply
+wire [31:0] x32 = xb32 ? x : xb16 ? {16'h0000,x[15:0]} : {24'h000000,x[7:0]};
+wire [31:0] y32 = xb32 ? y : xb16 ? {16'h0000,y[15:0]} : {24'h000000,y[7:0]};
+wire [7:0] sr8 = (m816|m832) ? {nf,vf,m_bit,x_bit,df,im,zf,cf} : {nf,vf,1'b0,bf,df,im,zf,cf};
+wire [7:0] srx = {3'b0,ssm,1'b0,mib,m832,m816};
+reg nmi1,nmi_edge;
+reg wai;
+reg [31:0] a32,b32;
+wire [15:0] b16 = b32[15:0];
+wire [7:0] b8 = b32[7:0];
+reg [32:0] res32;
+reg [63:0] prod64;
+wire resc8 = res32[8];
+wire resc16 = res32[16];
+wire resc32 = res32[32];
+wire resz8 = res32[7:0]==8'h00;
+wire resz16 = res32[15:0]==16'h0000;
+wire resz32 = res32[31:0]==32'd0;
+wire resn8 = res32[7];
+wire resn16 = res32[15];
+wire resn32 = res32[31];
+reg [31:0] radr;
+reg [31:0] wadr;
+reg [31:0] wdat;
+wire [7:0] rdat;
+reg [5:0] load_what;
+reg [5:0] store_what;
+reg s8,s16,s32,lds;
+reg sop;                // size override prefix
+reg [31:0] tmp32;
+reg first_ifetch;
+reg [31:0] derr_address;
+
+reg [8:0] intno;
+reg isBusErr;
+reg isBrk,isMove,isSts;
+reg isMove816;
+reg isRTI,isRTL,isRTS,isRTF;
+reg isRMW;
+reg isSub;
+reg isJsrIndx,isJsrInd,isJLInd;
+reg isIY,isIY24,isI24,isIY32,isI32;
+reg isDspiy;
+reg tj_prefix;
+
+wire isCmp = ir9==`CPX_ZPX || ir9==`CPX_ABS || ir9==`CPX_XABS ||
+			 ir9==`CPY_ZPX || ir9==`CPY_ABS || ir9==`CPY_XABS;
+wire isRMW8 =
+			 ir9==`ASL_ZP || ir9==`ROL_ZP || ir9==`LSR_ZP || ir9==`ROR_ZP || ir9==`INC_ZP || ir9==`DEC_ZP ||
+			 ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
+			 ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
+			 ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
+			 ir9==`ASL_XABS || ir9==`ROL_XABS || ir9==`LSR_XABS || ir9==`ROR_XABS || ir9==`INC_XABS || ir9==`DEC_XABS ||
+             ir9==`ASL_XABSX || ir9==`ROL_XABSX || ir9==`LSR_XABSX || ir9==`ROR_XABSX || ir9==`INC_XABSX || ir9==`DEC_XABSX ||
+			 ir9==`TRB_ZP || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ABS ||
+			 ir9==`TRB_XABS || ir9==`TSB_XABS
+			 ;
+wire isBranch = ir9==`BRA || ir9==`BEQ || ir9==`BNE || ir9==`BVS || ir9==`BVC || ir9==`BMI || ir9==`BPL || ir9==`BCS || ir9==`BCC ||
+                ir9==`BGT || ir9==`BGE || ir9==`BLT || ir9==`BLE;
+
+// This function needed to make the processor adhere to the page and bank 
+// wrapping characteristics of the 65xx. The stack will wrap around within
+// page 1 for eight bit emulation, and within bank 0 for 16 bit emulation.
+// Direct page addressimg wraps around within bank 0 for 16 bit emulation.
+
+reg bank_wrap;
+reg page_wrap;
+function [31:0] inc_adr;
+input [31:0] adr;
+begin
+    if (page_wrap)
+        inc_adr = {adr[31:8],adr[7:0] + 8'd1};
+    else if (bank_wrap)
+        inc_adr = {adr[31:16],adr[15:0] + 16'd1};
+    else
+        inc_adr = adr + 32'd1;
+end
+endfunction
+
+
+// Instruction cache.
+// The cache is organized as 256 lines of 16 bytes each, for a total of
+// 4kB. The processor has access to a window of 16 bytes into the cache
+// from the current program counter.
+
+reg wr_icache;
+wire [127:0] insn;
+ft832_icachemem uicm1
+(
+    .wclk(clk),
+    .wce(rdy),
+    .wr(vpa&wr_icache),
+    .wa(ado[11:0]),
+    .i(db),
+    .rclk(~clk),
+    .rce(1'b1),
+    .pc(cspc[11:0]),
+    .insn(insn)
+);
+
+reg inv_icache;
+reg wr_itag;
+wire hit0,hit1;
+reg prc_hit0,prc_hit1;
+reg inv_iline;
+
+ft832_itagmem uitm1
+(
+    .wclk(clk),
+    .wce(1'b1),
+    .wr(wr_itag),
+    .wa(ado1),
+    .invalidate(inv_icache),
+    .invalidate_line(inv_iline),
+    .rclk(~clk),
+    .rce(1'b1),
+    .pc(cspc),
+    .hit0(hit0),
+    .hit1(hit1)
+);
+
+`ifdef SUPPORT_TASK
+reg [`TASK_MEM_ABIT:0] tr, otr;
+reg [7:0] tsk_pres;                 // register value preservation flags
+reg tskm_we;
+reg tskm_wr;
+reg [`TASK_MEM_ABIT:0] tskm_wa;
+
+wire [15:0] cs_o;
+wire [15:0] ds_o;
+wire [15:0] ss_o;
+wire [23:0] pc_o;
+wire [31:0] acc_o;
+wire [31:0] x_o;
+wire [31:0] y_o;
+wire [31:0] sp_o;
+wire [7:0] sr_o;
+wire [7:0] srx_o;
+wire [7:0] dbr_o;
+wire [15:0] dpr_o;
+wire [`TASK_MEM_ABIT:0] bl_o;
+reg [15:0] cs_i;
+reg [15:0] ds_i;
+reg [15:0] ss_i;
+reg [23:0] pc_i;
+reg [31:0] acc_i;
+reg [31:0] x_i;
+reg [31:0] y_i;
+reg [31:0] sp_i;
+reg [7:0] sr_i;
+reg [7:0] srx_i;
+reg [7:0] dbr_i;
+reg [15:0] dpr_i;
+reg [`TASK_MEM_ABIT:0] bl_i;
+reg [`TASK_MEM_ABIT:0] back_link;
+
+task_mem utskm1
+(
+    .wclk(clk),
+    .wce(tskm_we),
+    .wr(tskm_wr),
+    .wa(tskm_wa),
+    .cs_i(cs_i),
+    .ds_i(ds_i),
+    .ss_i(ss_i),
+    .pc_i(pc_i),
+    .acc_i(acc_i),
+    .x_i(x_i),
+    .y_i(y_i),
+    .sp_i(sp_i),
+    .sr_i(sr_i),
+    .srx_i(srx_i),
+    .db_i(dbr_i),
+    .dpr_i(dpr_i),
+    .bl_i(bl_i),
+    .rclk(~clk),
+    .rce(1'b1),
+    .ra(tr),
+    .cs_o(cs_o),
+    .ds_o(ds_o),
+    .ss_o(ss_o),
+    .pc_o(pc_o),
+    .acc_o(acc_o),
+    .x_o(x_o),
+    .y_o(y_o),
+    .sp_o(sp_o),
+    .sr_o(sr_o),
+    .srx_o(srx_o),
+    .db_o(dbr_o),
+    .dpr_o(dpr_o),
+    .bl_o(bl_o)
+);
+
+`endif
+
+reg wr_sdt;
+reg [11:0] sdt_wa;
+reg [11:0] sdt_ra;
+reg [7:0] acr_i;
+reg [3:0] size_i;
+reg [31:0] base_i;
+wire [7:0] acr_o;
+wire [3:0] size_o;
+wire [31:0] base_o;
+
+SegDescTbl usdt1
+(
+    .wclk(clk),
+    .wce(1'b1),
+    .wr(wr_sdt),
+    .wa(sdt_wa),
+    .acr_i(acr_i),
+    .size_i(size_i),
+    .base_i(base_i),
+    .rclk(~clk),
+    .rce(1'b1),
+    .ra(sdt_ra),
+    .acr_o(acr_o),
+    .size_o(size_o),
+    .base_o(base_o)
+);
+
+reg  [7:0] cpybuf [63:0];   // stack copy buffer
+
+// Registerable decodes
+// The following decodes can be registered because they aren't needed until at least the cycle after
+// the DECODE stage.
+
+always @(posedge clk)
+	if (state==RESET1)
+		isBrk <= `TRUE;
+	else if (state==DECODE) begin
+		isRMW <= isRMW8;
+		isRTI <= ir9==`RTI;
+		isRTL <= ir9==`RTL || ir9==`RTL_IMM;
+		isRTS <= ir9==`RTS || ir9==`RTS_IMM;
+		isRTF <= ir9==`RTF;
+		isBrk <= ir9==`BRK || ir9==`COP;
+		isMove <= ir9==`MVP || ir9==`MVN;
+		isJsrIndx <= ir9==`JSR_INDX;
+		isJLInd <= ir9==`JML_IND || ir9==`JML_XIND || ir9==`JSL_XINDX || ir9==`JML_XINDX;
+		isDspiy <= ir9[4:0]==5'h13;
+	end
+
+assign mx = clk ? m_bit : x_bit;
+assign e = ~(m816|m832);
+
+wire [15:0] bcaio;
+wire [15:0] bcao;
+wire [15:0] bcsio;
+wire [15:0] bcso;
+wire bcaico,bcaco,bcsico,bcsco;
+wire bcaico8,bcaco8,bcsico8,bcsco8;
+
+`ifdef SUPPORT_BCD
+BCDAdd4 ubcdai1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcaio),.c(bcaico),.c8(bcaico8));
+BCDAdd4 ubcda2 (.ci(cf),.a(acc16),.b(b8),.o(bcao),.c(bcaco),.c8(bcaco8));
+BCDSub4 ubcdsi1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcsio),.c(bcsico),.c8(bcsico8));
+BCDSub4 ubcds2 (.ci(cf),.a(acc16),.b(b8),.o(bcso),.c(bcsco),.c8(bcsco8));
+`endif
+
+function carry;
+input op;	// 0=add,1=sub
+input a;
+input b;
+input s;
+begin
+	carry = op? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
+end
+endfunction
+
+
+
+wire [7:0] dati = db;
+
+// Evaluate branches
+// 
+reg takb;
+always @(ir9 or cf or vf or nf or zf)
+case(ir9)
+`BEQ:	takb <= zf;
+`BNE:	takb <= !zf;
+`BPL:	takb <= !nf;
+`BMI:	takb <= nf;
+`BCS:	takb <= cf;
+`BCC:	takb <= !cf;
+`BVS:	takb <= vf;
+`BVC:	takb <= !vf;
+`BRA:	takb <= 1'b1;
+`BRL:	takb <= 1'b1;
+`BGT:   takb <= !nf & !zf;//(nf & vf & !zf) | (!nf & !vf & !zf);
+//`BGE:   takb <= !nf;//(nf & vf) | (!nf & !vf);
+`BLE:   takb <= zf | nf;//zf | (nf & !vf) | (!nf & vf);
+//`BLT:   takb <= nf;//(nf & !vf) | (!nf & vf);
+default:	takb <= 1'b0;
+endcase
+
+// Address generation
+reg [7:0] mvndst_bank;
+reg [7:0] mvnsrc_bank;
+reg [31:0] seg;
+reg [31:0] ia;
+wire [15:0] dpr_zp = {16'h00,ir[15:8]} + dpr;
+wire [15:0] dpr_zpx = {{16'h00,ir[15:8]} + x32} + dpr;
+wire [15:0] dpr_zpy = {{16'h00,ir[15:8]} + y32} + dpr;
+wire [31:0] dpr_zp32 = {16'h00,ir[15:8]} + dpr;
+wire [31:0] dpr_zpx32 = {{16'h00,ir[15:8]} + x32} + dpr;
+wire [31:0] dpr_zpy32 = {{16'h00,ir[15:8]} + y32} + dpr;
+wire [31:0] mvnsrc_address	= m832 ? x32 : {8'h00,ir[23:16],x32[15:0]};
+wire [31:0] mvndst_address	= m832 ? y32 : {8'h00,ir[15:8],y32[15:0]};
+wire [31:0] iapy8 			= ia + y32;		// Don't add in abs8, already included with ia
+wire [31:0] zp_address 		= (m832 ? dpr_zp32 : dpr_zp);
+wire [31:0] zpx_address 	= (m832 ? dpr_zpx32 : dpr_zpx);
+wire [31:0] zpy_address	 	= (m832 ? dpr_zpy32 : dpr_zpy);
+wire [31:0] abs_address 	= {8'h00,dbr,ir[23:8]};
+wire [31:0] absx_address 	= m832 ? {8'h00,dbr,ir[23:8]} + x32 :
+                                     {8'h00,dbr,ir[23:8] + x16} ;	// simulates 64k bank wrap-around
+wire [31:0] absy_address 	= m832 ? {8'h00,dbr,ir[23:8]} + y32 :
+                                     {8'h00,dbr,ir[23:8] + y16} ;
+wire [31:0] al_address		= {8'h00,ir[31:8]};
+wire [31:0] alx_address		= {8'h00,ir[31:8]} + x32;
+wire [31:0] xal_address		= ir[39:8];
+wire [31:0] xalx_address	= ir[39:8] + x32;
+wire [31:0] xaly_address	= ir[39:8] + y32;
+
+wire [31:0] dsp_address = m832 ? sp + ir[15:8] :
+                          m816 ? {stack_bank,sp16 + ir[15:8]} : {stack_page,sp[7:0]+ir[15:8]};
+reg [31:0] vect;
+
+assign rw = be ? rwo : 1'bz;
+assign ad = be ? ado : {32{1'bz}};
+assign db = rwo ? {8{1'bz}} : be ? dbo : {8{1'bz}};
+
+wire [23:0] pc_hist_o;
+
+vtdl #(.WID(24),.DEP(64)) pc_hist_buf (
+    .clk(clk),
+    .ce(state==IFETCH && hit0 && hit1 && pc_cap),
+    .a(x[5:0]),
+    .d(pc),
+    .q(pc_hist_o)
+);
+/*
+c_shift_ram_0 pc_hist_buf (
+  .A(x[5:0]),      // input wire [5 : 0] A
+  .D({8'h00,pc}),      // input wire [31 : 0] D
+  .CLK(clk),  // input wire CLK
+  .CE(state==IFETCH && hit0 && hit1 && pc_cap),    // input wire CE
+  .Q(pc_hist_o)      // output wire [31 : 0] Q
+);
+*/
+reg [31:0] phi11r,phi12r,phi81r,phi82r;
+assign phi11 = phi11r[31];
+assign phi12 = phi12r[31];
+assign phi81 = phi81r[31];
+assign phi82 = phi82r[31];
+
+always @(posedge clk)
+if (~rst) begin
+	cyc <= 5'd0;
+	phi11r <= 32'b01111111111111100000000000000000;
+	phi12r <= 32'b00000000000000000111111111111110;
+	phi81r <= 32'b01110000011100000111000001110000;
+	phi82r <= 32'b00000111000001110000011100000111;
+end
+else begin
+	cyc <= cyc + 5'd1;
+	phi11r <= {phi11r[30:0],phi11r[31]};
+	phi12r <= {phi12r[30:0],phi12r[31]};
+	phi81r <= {phi81r[30:0],phi81r[31]};
+	phi82r <= {phi82r[30:0],phi82r[31]};
+end
+
+//-----------------------------------------------------------------------------
+// Clock control
+// - reset or NMI reenables the clock
+// - this circuit must be under the clk_i domain
+//-----------------------------------------------------------------------------
+//
+reg cpu_clk_en;
+reg clk_en;
+wire clkx;
+BUFGCE u20 (.CE(cpu_clk_en), .I(clk), .O(clkx) );
+assign clko = clkx;
+//assign clkx = clk;
+
+always @(posedge clk)
+if (~rst) begin
+	cpu_clk_en <= 1'b1;
+	nmi1 <= 1'b0;
+end
+else begin
+	nmi1 <= nmi;
+	if (nmi)
+		cpu_clk_en <= 1'b1;
+	else
+		cpu_clk_en <= clk_en;
+end
+
+reg abort1;
+reg abort_edge;
+reg [2:0] imcd;	// interrupt mask enable count down
+
+always @(posedge clkx)
+if (~rst) begin
+	vpa <= `FALSE;
+	vda <= `FALSE;
+	vpb <= `TRUE;
+	rwo <= `TRUE;
+	ado <= 32'h000000;
+	dbo <= 8'h00;
+	nmi_edge <= 1'b0;
+	wai <= 1'b0;
+	pg2 <= 1'b0;
+	ir <= 8'hEA;
+	cf <= 1'b0;
+	df <= 1'b0;
+	m816 <= 1'b0;
+	m832 <= 1'b0;
+	m_bit <= 1'b1;
+	x_bit <= 1'b1;
+	vect <= `BYTE_RST_VECT;
+	state <= RESET1;
+	em <= 1'b1;
+	pc <= 24'h00FFF0;		// set high-order pc to zero
+	cs <= 16'd0;
+	ds <= 16'd0;
+	ss <= 16'd0;
+	cs_base <= 32'd0;
+	ds_base <= 32'd0;
+	ss_base <= 32'd0;
+	cs_limit <= 32'hFFFFFFFF;
+	ds_limit <= 32'hFFFFFFFF;
+	ss_limit <= 32'hFFFFFFFF;
+	ds_wr <= TRUE;
+	ss_wr <= TRUE;
+	cs_wr <= FALSE;
+	stksz <= 2'b00;        // 256 bytes
+	dpr <= 16'h0000;
+	dbr <= 8'h00;
+	acc <= 32'h0;
+	x <= 32'h0;
+	y <= 32'h0;
+	sp <= 32'h1FF;
+	clk_en <= 1'b1;
+	im <= `TRUE;
+	mib <= `FALSE;
+	gie <= 1'b0;
+	isIY <= 1'b0;
+	isIY24 <= 1'b0;
+	isI24 <= `FALSE;
+	load_what <= `NOTHING;
+	abort_edge <= 1'b0;
+	abort1 <= 1'b0;
+	imcd <= 3'b111;
+	inv_icache <= TRUE;
+	inv_iline <= FALSE;
+	pc_cap <= TRUE;
+	tr <= 8'h00;
+    tskm_we <= FALSE;
+    tskm_wr <= FALSE;
+    wr_sdt <= FALSE;
+    ssm <= FALSE;
+    tj_prefix <= FALSE;
+    seg_fault_val = SEGF_NONE;
+end
+else begin
+abort1 <= abort;
+if (~abort & abort1)
+	abort_edge <= 1'b1;
+if (~nmi & nmi1)
+	nmi_edge <= 1'b1;
+if (~nmi|~nmi1)
+	clk_en <= 1'b1;
+inv_iline <= FALSE;
+`ifdef SUPPORT_TASK
+tskm_we <= FALSE;
+tskm_wr <= FALSE;
+`endif
+wr_itag <= FALSE;
+wr_sdt <= FALSE;
+case(state)
+RESET1:
+	begin
+		radr <= `BYTE_RST_VECT;
+		load_what <= `PC_70;
+`ifdef SUPPORT_SEG
+		cs <= 16'd0;
+		ds <= 16'd0;
+		ss <= 16'd0;
+    	cs_base <= 32'd0;
+        ds_base <= 32'd0;
+        ss_base <= 32'd0;
+    	cs_limit <= 32'hFFFFFFFF;
+        ds_limit <= 32'hFFFFFFFF;
+        ss_limit <= 32'hFFFFFFFF;
+        ds_wr <= TRUE;
+`endif 
+        first_ifetch <= TRUE;
+		seg <= 32'd0;
+		lmt <= 32'hFFFF;
+		mem_wr <= TRUE;
+		inv_icache <= FALSE;
+		state <= LOAD_MAC1;
+	end
+IFETCH:
+    begin
+	vda <= FALSE;
+	if (hit0&hit1) begin
+		if (imcd != 3'b111)
+			imcd <= {imcd[1:0],1'b0};
+		if (imcd == 3'b000) begin
+			imcd <= 3'b111;
+			im <= 1'b0;
+		end
+		vect <= m832 ? `BRK_VECT_832 : m816 ? `BRK_VECT_816 : `BYTE_IRQ_VECT;
+		hwi <= `FALSE;
+		isBusErr <= `FALSE;
+		pg2 <= FALSE;
+		isIY <= `FALSE;
+		isIY24 <= `FALSE;
+		isIY32 <= `FALSE;
+		isI24 <= `FALSE;
+		isI32 <= `FALSE;
+		s8 <= FALSE;
+		s16 <= FALSE;
+		s32 <= FALSE;
+		lds <= FALSE;
+		sop <= FALSE;
+		tj_prefix <= FALSE;
+		bank_wrap <= FALSE;
+		page_wrap <= FALSE;
+`ifdef SUPPORT_SEG
+		seg <= ds_base;
+		lmt <= ds_limit;
+		mem_wr <= ds_wr;
+		seg_fault_val = SEGF_NONE;
+`endif
+		store_what <= (m32 | m16) ? `STW_DEF70 : `STW_DEF;
+	    ir <= insn;
+		opc <= pc;
+		if (nmi_edge | ~irq)
+			wai <= 1'b0;
+		if (abort_edge) begin
+			pc <= opc;
+			ir[7:0] <= `BRK;
+			abort_edge <= 1'b0;
+			hwi <= `TRUE;
+			vect <= m832 ? `ABT_VECT_832 : m816 ? `ABT_VECT_816 : `BYTE_ABT_VECT;
+			vect[23:16] <= 8'h00;
+			seg <= 32'd0;
+			lmt <= 32'hFFFF;
+			mem_wr <= FALSE;
+			next_state(DECODE);
+		end
+		else if (nmi_edge & gie) begin
+			ir[7:0] <= `BRK;
+			nmi_edge <= 1'b0;
+			hwi <= `TRUE;
+			vect <= m832 ? `NMI_VECT_832 : m816 ? `NMI_VECT_816 : `BYTE_NMI_VECT;
+			vect[23:16] <= 8'h00;
+			seg <= 32'd0;
+			lmt <= 32'hFFFF;
+			mem_wr <= FALSE;
+			next_state(DECODE);
+		end
+		else if (~irq & gie & ~im) begin
+			ir[7:0] <= `BRK;
+			hwi <= `TRUE;
+			if (m832)
+			    vect <= `IRQ_VECT_832;
+			else if (m816)
+				vect <= `IRQ_VECT_816;
+			seg <= 32'd0;
+			lmt <= 32'hFFFF;
+			mem_wr <= FALSE;
+			next_state(DECODE);
+		end
+		else if (pc > cs_limit && m832) begin
+			ir[7:0] <= `BRK;
+            hwi <= `TRUE;
+            if (m832)
+                vect <= `IRQ_VECT_832;
+            else if (m816)
+                vect <= `IRQ_VECT_816;
+            seg <= 32'd0;
+            lmt <= 32'hFFFF;
+            mem_wr <= FALSE;
+            next_state(DECODE);
+            seg_fault_val <= SEGF_BOUND;
+		end
+		else if (!wai) begin
+            if (mib) begin
+                set_task_regs(m832 ? 24'd4 : m816 ? 24'd2 : 24'd1);
+                case({m832,m816})
+                2'd0: acc <= insn[7:0];
+                2'd1: acc <= insn[15:0];
+                2'd2: acc <= insn[31:0];
+                2'd3: acc <= insn[31:0];
+                endcase
+                x <= pc;
+                tsk_pres <= 7'h0C;
+                tr <= back_link;
+                retstate <= IFETCH;
+                next_state(TSK1);
+            end
+            else
+			    next_state(DECODE);
+		end
+		else
+			next_state(IFETCH);
+		if (!abort_edge & first_ifetch) begin
+		first_ifetch <= FALSE;
+		case(ir9)
+		// Note the break flag is not affected by SEP/REP
+		// Setting the index registers to eight bit zeros out the upper part of the register.
+		`SEP:
+			begin
+				cf <= cf | ir[8];
+				zf <= zf | ir[9];
+				im <= im | ir[10];
+				df <= df | ir[11];
+				if (m816|m832) begin
+					x_bit <= x_bit | ir[12];
+					m_bit <= m_bit | ir[13];
+					//if (ir[13]) acc[31:8] <= 24'd0;
+					if (ir[12]) begin
+						x[31:8] <= 24'd0;
+						y[31:8] <= 24'd0;
+					end
+				end
+				vf <= vf | ir[14];
+				nf <= nf | ir[15];
+			end
+		`REP:
+			begin
+				cf <= cf & ~ir[8];
+				zf <= zf & ~ir[9];
+				im <= im & ~ir[10];
+				df <= df & ~ir[11];
+				if (m816|m832) begin
+					x_bit <= x_bit & ~ir[12];
+					m_bit <= m_bit & ~ir[13];
+				end
+				vf <= vf & ~ir[14];
+				nf <= nf & ~ir[15];
+			end
+`ifdef SUPPORT_NEW_INSN
+		`SEP16:
+                begin
+                    cf <= cf | ir[8];
+                    zf <= zf | ir[9];
+                    im <= im | ir[10];
+                    df <= df | ir[11];
+                    if (m816|m832) begin
+                        x_bit <= x_bit | ir[12];
+                        m_bit <= m_bit | ir[13];
+                        //if (ir[13]) acc[31:8] <= 24'd0;
+                        if (ir[12]) begin
+                            x[31:8] <= 24'd0;
+                            y[31:8] <= 24'd0;
+                        end
+                    end
+                    vf <= vf | ir[14];
+                    nf <= nf | ir[15];
+                    m816 <= m816 | ir[16];
+                    m832 <= m832 | ir[17];
+                    mib <= mib | ir[18];
+                    ssm <= ssm | ir[20];
+                end
+		`REP16:
+            begin
+                cf <= cf & ~ir[8];
+                zf <= zf & ~ir[9];
+                im <= im & ~ir[10];
+                df <= df & ~ir[11];
+                if (m816|m832) begin
+                    x_bit <= x_bit & ~ir[12];
+                    m_bit <= m_bit & ~ir[13];
+                end
+                vf <= vf & ~ir[14];
+                nf <= nf & ~ir[15];
+                m816 <= m816 & ~ir[16];
+                m832 <= m832 & ~ir[17];
+                mib <= mib & ~ir[18];
+                ssm <= ssm & ~ir[20];
+            end
+        `INF:   begin
+                acc <= res32;
+                nf <= resn32;
+                zf <= resz32;
+                end
+`endif
+		`XBA:
+			begin
+                acc[15:0] <= res32[15:0];
+                nf <= resn8;
+                zf <= resz8;
+            end
+`ifdef SUPPORT_NEW_INSN
+		`XBAW:
+		    begin
+		        acc <= res32;
+		        nf <= resn16;
+		        zf <= resz16;
+		    end
+		`AAX:
+		    begin
+		        if (m32) begin
+    		        acc <= res32;
+	 	            zf <= resz32;
+                    nf <= resn32;
+                    vf <= (res32[31] ^ b32[31]) & (1'b1 ^ a32[31] ^ b32[31]);
+                    cf <= carry(0,a32[31],b32[31],res32[31]);
+		        end
+		        else if (m16) begin
+    		        acc[15:0] <= res32[15:0];
+		            zf <= resz16;
+                    nf <= resn16;
+                    vf <= (res32[15] ^ b32[15]) & (1'b1 ^ a32[15] ^ b32[15]);
+                    cf <= carry(0,a32[15],b32[15],res32[15]);
+		        end
+		        else begin
+    		        acc[7:0] <= res32[7:0];
+		            zf <= resz8;
+		            nf <= resn8;
+                    vf <= (res32[7] ^ b32[7]) & (1'b1 ^ a32[7] ^ b32[7]);
+                    cf <= carry(0,a32[7],b32[7],res32[7]);
+		        end
+		    end
+`endif
+		`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`LDY_XABS,`LDY_XABSX,
+		`TAY,`TXY,`DEY,`INY,`INY4,`DEY4,`PLY:
+			begin
+                if (xb32) begin
+                    y <= res32;
+                    nf <= resn32;
+                    zf <= resz32;
+                end
+                else if (xb16) begin
+                    y <= {16'h0000,res32[15:0]};
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+                else begin
+                    y <= {24'h000000,res32[7:0]};
+                    nf <= resn8;
+                    zf <= resz8;
+                end
+            end
+		`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`LDX_XABS,`LDX_XABSY,
+        `TAX,`TYX,`TSX,`DEX,`INX,`INX4,`DEX4,`PLX:
+			begin
+                if (xb32) begin
+                    x <= res32;
+                    nf <= resn32;
+                    zf <= resz32;
+                end
+                else if (xb16) begin
+                    x <= {16'h0000,res32[15:0]};
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+                else begin
+                    x <= {24'h000000,res32[7:0]};
+                    nf <= resn8;
+                    zf <= resz8;
+                end
+            end
+        `TTA:
+            begin
+                if (m32) begin
+                    acc <= res32;
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+                else if (m16) begin
+                    acc[15:0] <= res32[15:0];
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+                else begin
+                    acc[15:0] <= res32[15:0];
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+            end
+        `TASS:  ss <= res32[15:0];
+		`TSA,`TYA,`TXA,`INA,`DEA,`PLA,`TSSA:
+			begin
+                if (m32) begin
+                    acc <= res32;
+                    nf <= resn32;
+                    zf <= resz32;
+                end
+                else if (m16) begin
+                    acc[15:0] <= {acc[31:16],res32[15:0]};
+                    nf <= resn16;
+                    zf <= resz16;
+                end
+                else begin
+                    acc[7:0] <= {acc[31:8],res32[7:0]};
+                    nf <= resn8;
+                    zf <= resz8;
+                end
+            end
+        `PCHIST:    acc <= res32;
+		`TAS,`TXS:
+		    begin
+		        if (m832) sp <= res32;
+		        else if (m816) sp <= {stack_bank,res32[15:0]};
+		        else sp <= {stack_page,res32[7:0]};
+		        gie <= `TRUE;
+		    end
+		`TCD:	begin dpr <= res32[15:0]; end
+		`TDC:	begin acc <= {16'h0000,res32[15:0]}; nf <= resn16; zf <= resz16; end
+		`ADC_IMM:
+			begin
+			    if (m32) begin
+					acc <= df ? bcaio : res32;
+                    cf <= df ? bcaico : carry(0,a32[31],b32[31],res32[31]);
+    //                        vf <= resv8;
+                    vf <= (res32[31] ^ b32[31]) & (1'b1 ^ a32[31] ^ b32[31]);
+                    nf <= df ? bcaio[15] : resn32;
+                    zf <= df ? bcaio==16'h0000 : resz32;
+			    end
+				else if (m16) begin
+					acc[15:0] <= df ? bcaio : res32[15:0];
+					cf <= df ? bcaico : carry(0,a32[15],b32[15],res32[15]);;
+//						vf <= resv8;
+					vf <= (res32[15] ^ b32[15]) & (1'b1 ^ a32[15] ^ b32[15]);
+					nf <= df ? bcaio[15] : resn16;
+					zf <= df ? bcaio==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcaio[7:0] : res32[7:0];
+					cf <= df ? bcaico8 : carry(0,a32[7],b32[7],res32[7]);
+//						vf <= resv8;
+					vf <= (res32[7] ^ b32[7]) & (1'b1 ^ a32[7] ^ b32[7]);
+					nf <= df ? bcaio[7] : resn8;
+					zf <= df ? bcaio[7:0]==8'h00 : resz8;
+				end
+			end
+		`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_IYL,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I,`ADC_IL,`ADC_AL,`ADC_ALX,`ADC_DSP,`ADC_DSPIY,
+		`ADC_XABS,`ADC_XABSX,`ADC_XABSY,`ADC_XIYL,`ADC_XIL,`ADC_XDSPIY:
+			begin
+			    if (m32) begin
+					acc <= df ? bcao : res32;
+                    cf <= df ? bcaco : carry(0,a32[31],b32[31],res32[31]);
+                    vf <= (res32[31] ^ b32[31]) & (1'b1 ^ a32[31] ^ b32[31]);
+                    nf <= df ? bcao[15] : resn32;
+                    zf <= df ? bcao==16'h0000 : resz32;
+			    end
+				else if (m16) begin
+					acc[15:0] <= df ? bcao : res32[15:0];
+					cf <= df ? bcaco : carry(0,a32[15],b32[15],res32[15]);
+					vf <= (res32[15] ^ b32[15]) & (1'b1 ^ a32[15] ^ b32[15]);
+					nf <= df ? bcao[15] : resn16;
+					zf <= df ? bcao==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcao[7:0] : res32[7:0];
+					cf <= df ? bcaco8 : carry(0,a32[7],b32[7],res32[7]);
+					vf <= (res32[7] ^ b32[7]) & (1'b1 ^ a32[7] ^ b32[7]);
+					nf <= df ? bcao[7] : resn8;
+					zf <= df ? bcao[7:0]==8'h00 : resz8;
+				end
+			end
+		`SBC_IMM:
+			begin
+				if (m32) begin
+                    acc <= df ? bcsio : res32;
+                    cf <= ~(df ? bcsico : carry(1,a32[31],b32[31],res32[31]));
+                    vf <= (1'b1 ^ res32[31] ^ b32[31]) & (a32[31] ^ b32[31]);
+                    nf <= df ? bcsio[15] : resn16;
+                    zf <= df ? bcsio==16'h0000 : resz16;
+                end
+				else if (m16) begin
+					acc[15:0] <= df ? bcsio : res32[15:0];
+					cf <= ~(df ? bcsico : carry(1,a32[15],b32[15],res32[15]));
+					vf <= (1'b1 ^ res32[15] ^ b32[15]) & (a32[15] ^ b32[15]);
+					nf <= df ? bcsio[15] : resn16;
+					zf <= df ? bcsio==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcsio[7:0] : res32[7:0];
+					cf <= ~(df ? bcsico8 : carry(1,a32[7],b32[7],res32[7]));
+					vf <= (1'b1 ^ res32[7] ^ b32[7]) & (a32[7] ^ b32[7]);
+					nf <= df ? bcsio[7] : resn8;
+					zf <= df ? bcsio[7:0]==8'h00 : resz8;
+				end
+			end
+		`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_IYL,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I,`SBC_IL,`SBC_AL,`SBC_ALX,`SBC_DSP,`SBC_DSPIY,
+		`SBC_XABS,`SBC_XABSX,`SBC_XABSY,`SBC_XIYL,`SBC_XIL,`SBC_XDSPIY:
+			begin
+				if (m32) begin
+                    acc <= df ? bcso : res32;
+                    vf <= (1'b1 ^ res32[31] ^ b32[31]) & (a32[31] ^ b32[31]);
+                    cf <= ~(df ? bcsco : carry(1,a32[31],b32[31],res32[31]));
+                    nf <= df ? bcso[15] : resn16;
+                    zf <= df ? bcso==16'h0000 : resz16;
+                end
+				else if (m16) begin
+					acc[15:0] <= df ? bcso : res32[15:0];
+					vf <= (1'b1 ^ res32[15] ^ b32[15]) & (a32[15] ^ b32[15]);
+					cf <= ~(df ? bcsco : carry(1,a32[15],b32[15],res32[15]));
+					nf <= df ? bcso[15] : resn16;
+					zf <= df ? bcso==16'h0000 : resz16;
+				end
+				else begin
+					acc[7:0] <= df ? bcso[7:0] : res32[7:0];
+					vf <= (1'b1 ^ res32[7] ^ b32[7]) & (a32[7] ^ b32[7]);
+					cf <= ~(df ? bcsco8 : carry(1,a32[7],b32[7],res32[7]));
+					nf <= df ? bcso[7] : resn8;
+					zf <= df ? bcso[7:0]==8'h00 : resz8;
+				end
+			end
+		`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_IYL,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,`CMP_IL,`CMP_AL,`CMP_ALX,`CMP_DSP,`CMP_DSPIY,
+		`CMP_XABS,`CMP_XABSX,`CMP_XABSY,`CMP_XIYL,`CMP_XIL,`CMP_XDSPIY:
+		        if (m32) begin cf <= ~carry(1,a32[31],b32[31],res32[31]); nf <= resn32; zf <= resz32; end 
+				else if (m16) begin cf <= ~carry(1,a32[15],b32[15],res32[15]); nf <= resn16; zf <= resz16; end
+				else begin          cf <= ~carry(1,a32[7],b32[7],res32[7]); nf <= resn8; zf <= resz8; end
+		`CPX_IMM,`CPX_ZP,`CPX_ABS,`CPX_XABS:
+		        if (xb32) begin cf <= ~carry(1,a32[31],b32[31],res32[31]); nf <= resn32; zf <= resz32; end 
+                else if (xb16) begin cf <= ~carry(1,a32[15],b32[15],res32[15]); nf <= resn16; zf <= resz16; end
+                else begin           cf <= ~carry(1,a32[7],b32[7],res32[7]); nf <= resn8; zf <= resz8; end
+		`CPY_IMM,`CPY_ZP,`CPY_ABS,`CPY_XABS:
+		        if (xb32) begin cf <= ~carry(1,a32[31],b32[31],res32[31]); nf <= resn32; zf <= resz32; end 
+				else if (xb16) begin cf <= ~carry(1,a32[15],b32[15],res32[15]); nf <= resn16; zf <= resz16; end
+				else begin           cf <= ~carry(1,a32[7],b32[7],res32[7]); nf <= resn8; zf <= resz8; end
+		`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX,`BIT_XABS,`BIT_XABSX:
+		        if (m32) begin nf <= b32[31]; vf <= b32[30]; zf <= resz32; end 
+				else if (m16) begin nf <= b32[15]; vf <= b32[14]; zf <= resz16; end
+				else begin          nf <= b32[7]; vf <= b32[6]; zf <= resz8; end
+		`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS,`TRB_XABS,`TSB_XABS:
+		    if (m32) begin zf <= resz32; end
+			else if (m16) begin zf <= resz16; end
+			else begin          zf <= resz8; end
+		`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_IYL,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,`LDA_IL,`LDA_AL,`LDA_ALX,`LDA_DSP,`LDA_DSPIY,
+		`LDA_XABS,`LDA_XABSX,`LDA_XABSY,`LDA_XIYL,`LDA_XIL,`LDA_XDSPIY,
+		`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_IYL,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,`AND_IL,`AND_AL,`AND_ALX,`AND_DSP,`AND_DSPIY,
+		`AND_XABS,`AND_XABSX,`AND_XABSY,`AND_XIYL,`AND_XIL,`AND_XDSPIY,
+		`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_IYL,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,`ORA_IL,`ORA_AL,`ORA_ALX,`ORA_DSP,`ORA_DSPIY,
+		`ORA_XABS,`ORA_XABSX,`ORA_XABSY,`ORA_XIYL,`ORA_XIL,`ORA_XDSPIY,
+		`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_IYL,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I,`EOR_IL,`EOR_AL,`EOR_ALX,`EOR_DSP,`EOR_DSPIY,
+		`ORA_XABS,`ORA_XABSX,`ORA_XABSY,`ORA_XIYL,`ORA_XIL,`ORA_XDSPIY:
+		    if (m32) begin acc <= res32; nf <= resn32; zf <= resz32; end
+			else if (m16) begin acc[15:0] <= res32[15:0]; nf <= resn16; zf <= resz16; end
+			else begin acc[7:0] <= res32[7:0]; nf <= resn8; zf <= resz8; end
+		`ASR_ACC:
+              if (m32) begin acc <= res32; cf <= a32[0]; nf <= resn32; zf <= resz32; end 
+              else if (m16) begin acc[15:0] <= res32[15:0]; cf <= a32[0]; nf <= resn16; zf <= resz16; end
+              else begin acc[7:0] <= res32[7:0]; cf <= a32[0]; nf <= resn8; zf <= resz8; end
+        `ASL_ACC,
+        `ROL_ACC:
+		      if (m32) begin acc <= res32; cf <= res32[32]; nf <= resn32; zf <= resz32; end 
+		      else if (m16) begin acc[15:0] <= res32[15:0]; cf <= res32[16]; nf <= resn16; zf <= resz16; end
+		      else begin acc[7:0] <= res32[7:0]; cf <= res32[8]; nf <= resn8; zf <= resz8; end
+		`LSR_ACC,
+		`ROR_ACC:
+		      if (m32) begin acc <= res32; cf <= res32[32]; nf <= resn32; zf <= resz32; end 
+		      else if (m16) begin acc[15:0] <= res32[15:0]; cf <= res32[32]; nf <= resn16; zf <= resz16; end
+		      else begin acc[7:0] <= res32[7:0]; cf <= res32[32]; nf <= resn8; zf <= resz8; end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX,`ASL_XABS,`ASL_XABSX,
+		`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX,`ROL_XABS,`ROL_XABSX:
+		     if (m32) begin cf <= b32[31]; nf <= resn32; zf <= resz32; end 
+             else if (m16) begin cf <= b32[15]; nf <= resn16; zf <= resz16; end
+             else begin cf <= b32[7]; nf <= resn8; zf <= resz8; end
+		`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX,`LSR_XABS,`LSR_XABSX,
+		`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX,`ROR_XABS,`ROR_XABSX:
+		      if (m32) begin cf <= b32[0]; nf <= resn32; zf <= resz32; end 
+		      else if (m16) begin cf <= b32[0]; nf <= resn16; zf <= resz16; end
+		      else begin cf <= b32[0]; nf <= resn8; zf <= resz8; end
+		`INC_IMM,
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX,`INC_XABS,`INC_XABSX,
+		`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX,`DEC_XABS,`DEC_XABSX:
+		      if (m32) begin nf <= resn32; zf <= resz32; end 
+		      else if (m16) begin nf <= resn16; zf <= resz16; end
+		      else begin nf <= resn8; zf <= resz8; end
+		`PLB:	begin dbr <= res32[7:0]; nf <= resn8; zf <= resz8; end
+`ifdef SUPPORT_NEW_INSN
+		`MUL:   begin
+		            acc <= prod64[31:0];
+		            x <= prod64[63:32];
+		            zf <= prod64==64'd0;
+		            nf <= prod64[63];
+		            vf <= prod64[63:32]!=32'd0;
+		        end
+`ifdef SUPPORT_SEG
+		`PLDS:	begin ds <= res32[15:0]; nf <= resn16; zf <= resz16; end
+`endif
+`endif
+        `PLD:   begin dpr <= res32[15:0]; nf <= resn16; zf <= resz16; end
+		endcase
+		end	// abort_edge
+	end
+	else begin
+	    prc_hit0 <= FALSE;
+	    prc_hit1 <= FALSE;
+	    next_state(ICACHE1);
+	end
+	end
+
+// Decode
+DECODE:
+    begin
+        first_ifetch <= TRUE;
+		moveto_ifetch();
+        inc_pc(24'd1);
+		case(ir9)
+		`PG2: begin
+		      pg2 <= TRUE;
+		      ir <= {8'h00,ir[127:8]};
+		      next_state(DECODE);
+		      end
+`ifdef SUPPORT_NEW_INSN
+`ifdef SUPPORT_SEG
+		`CS:  begin
+		      seg <= cs_base;
+		      lmt <= cs_limit;
+		      mem_wr <= cs_wr;
+		      ir <= {8'h00,ir[127:8]};
+		      pg2 <= FALSE;
+		      next_state(DECODE);
+		      end
+		`SS:  begin
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                ir <= {8'h00,ir[127:8]};
+                pg2 <= FALSE;
+                next_state(DECODE);
+                end
+		`IOS: begin
+		      seg <= IO_SEGMENT;
+		      lmt <= 32'hFFFFF;
+		      mem_wr <= TRUE;
+		      ir <= {8'h00,ir[127:8]};
+		      pg2 <= FALSE;
+              next_state(DECODE);
+		      end
+		`SEG0:
+   	          begin
+              seg <= 32'd0;
+              lmt <= 32'hFFFFFFFF;
+              mem_wr <= TRUE;
+              ir <= {8'h00,ir[127:8]};
+		      pg2 <= FALSE;
+              next_state(DECODE);
+              end
+         `SEG: begin
+              inc_pc(24'd5);
+		      seg <= ir[39:8];
+		      ir <= {40'h00,ir[127:40]};
+		      pg2 <= FALSE;
+		      next_state(DECODE);
+		      end
+`endif
+        `TJ:  begin tj_prefix <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`BYT: begin sop <= TRUE; lds <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`UBT: begin sop <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`HAF: begin sop <= TRUE; lds <= TRUE; s16 <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`UHF: begin sop <= TRUE; s16 <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`UHF: begin sop <= TRUE; s16 <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`WRD: begin sop <= TRUE; s32 <= TRUE; ir <= {8'h00,ir[127:8]}; pg2 <= FALSE; next_state(DECODE); end
+		`SEP16:	  inc_pc(24'd3);	// see byte_ifetch
+        `REP16:   inc_pc(24'd3);
+`endif
+		`SEP:	inc_pc(24'd2);	// see byte_ifetch
+		`REP:	inc_pc(24'd2);
+		`PCHIST:  res32 <= pc_hist_o;
+		// XBA cannot be done in the ifetch stage because it'd repeat when there
+		// was a cache miss, causing the instruction to be done twice.
+		`XBA:   res32 <= {acc[31:16],acc[7:0],acc[15:8]};
+		`STP:	begin clk_en <= 1'b0; end
+		// Switching the processor mode always zeros out the upper part of the index registers.
+		// switching to native mode sets 8 bit memory/indexes
+		`XCE:	begin
+					m816 <= ~cf;
+					m832 <= ~vf;
+					cf <= ~m816;
+					vf <= ~m832;
+					if (!cf) begin
+					   x_bit <= 1'b1;
+					   m_bit <= 1'b1;
+					end
+				end
+//		`NOP:	;	// may help routing
+		`CLC:	begin cf <= 1'b0; end
+		`SEC:	begin cf <= 1'b1; end
+		`CMC:   cf <= ~cf;
+		`CLV:	begin vf <= 1'b0; end
+		`CLI:	begin imcd <= 3'b110; end
+		`SEI:	begin im <= 1'b1; end
+		`CLD:	begin df <= 1'b0; end
+		`SED:	begin df <= 1'b1; end
+		`WAI:	begin wai <= 1'b1; end
+		`DEX:	begin res32 <= x_dec; end
+		`INX:	begin res32 <= x_inc; end
+		`DEY:	begin res32 <= y_dec; end
+		`INY:	begin res32 <= y_inc; end
+`ifdef SUPPORT_NEW_INSN
+		`XBAW:    res32 <= {acc[15:0],acc[31:16]};
+		`DEX4:    res32 <= x - 32'd4;
+		`DEY4:    res32 <= y - 32'd4;
+		`INX4:    res32 <= x + 32'd4;
+		`INY4:    res32 <= y + 32'd4;
+		`AAX:     begin res32 <= acc32 + x32; a32 <= acc32; b32 <= x32; end
+		`TSSA:    res32 <= ss;
+		`TASS:    begin
+		              res32 <= acc[15:0];
+		              sdt_ra <= acc[11:0];
+		              next_state(TASS1);
+		          end
+`ifdef SUPPORT_TASK
+		`TTA:       res32 <= tr;
+`endif
+`endif
+		`DEA:	res32 <= acc_dec;
+		`INA:	res32 <= acc_inc;
+		`TSX,`TSA:	res32 <= sp;
+		`TXS,`TXA,`TXY:	begin res32 <= x32; end
+		`TAX,`TAY:	begin res32 <= acc; end
+		`TAS:	res32 <= acc;
+		`TYA,`TYX:	begin res32 <= y32; end
+		`TDC:		begin res32 <= dpr; end
+		`TCD:		begin res32 <= acc; end
+		`ASL_ACC:   res32 <= {acc,1'b0};
+		`ROL_ACC:	res32 <= {acc,cf};
+		`LSR_ACC:	if (m32) res32 <= {acc[0],1'b0,acc[31:1]};
+		            else if (m16) res32 <= {acc[0],17'b0,acc[15:1]};
+		            else res32 <= {acc[0],25'b0,acc[7:1]};
+`ifdef SUPPORT_NEW_INSN
+		`ASR_ACC:	begin
+		            a32 <= acc;
+		            if (m32) res32 <= {acc[0],acc[31],acc[31:1]};
+                    else if (m16) res32 <= {acc[0],16'b0,acc[15],acc[15:1]};
+                    else res32 <= {acc[0],24'b0,acc[7],acc[7:1]};
+                    end
+        `MUL:       prod64 <= acc32 * x32;
+        `INF:       begin
+                    otr <= tr;
+                    tr <= x32[15:4];
+                    sdt_ra <= y[11:0];
+                    next_state(INF1);
+                    end
+`endif
+		`ROR_ACC:	if (m32) res32 <= {acc[0],cf,acc[31:1]};
+		            else if (m16) res32 <= {acc[0],16'b0,cf,acc[15:1]};
+		            else res32 <= {acc[0],24'b0,cf,acc[7:1]};
+`ifdef SUPPORT_SEG
+		`RTF,`RTS_IMM,`RTL_IMM:
+			begin
+			    inc_pc(24'd2);
+                inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                load_what <= `PC_70;
+                state <= LOAD_MAC1;
+            end
+`endif
+		`RTS,`RTL:
+			begin
+			    inc_sp();
+			    seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+				load_what <= `PC_70;
+				state <= LOAD_MAC1;
+			end
+		`RTI:	begin
+			    seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+`ifdef SUPPORT_TASK
+		        if (m832) begin
+                    set_task_regs(24'd1);
+`ifdef TASK_BL
+                    begin
+                        tr <= back_link;
+                        tsk_pres <= 7'h0;
+                        retstate <= IFETCH;
+                        next_state(TSK1);
+                    end
+`else
+                    begin
+                        sp_i <= fn_add_to_sp(32'd2);
+                        inc_sp();
+                        seg <= ss_base;
+                        lmt <= ss_limit;
+                        mem_wr <= ss_wr;
+                        tsk_pres <= 7'd0;
+                        load_what <= `LDW_TR70S;
+                        state <= LOAD_MAC1;
+                    end
+`endif
+                end
+                else
+`endif
+                begin
+                    inc_sp();
+                    if (bf) pc_cap <= TRUE;
+                    load_what <= `SR_70;
+                    state <= LOAD_MAC1;
+				end
+				end
+		`PHP:   begin
+		             if (m832)
+		                 tsk_push(`STW_SR158,1,0);
+		             else
+		                 tsk_push(`STW_SR70,0,0);
+		        end
+        `PHA:   tsk_push(`STW_ACC70,m16,m32);
+		`PHX:	tsk_push(`STW_X70,xb16,xb32);
+		`PHY:	tsk_push(`STW_Y70,xb16,xb32);
+//		`PHCS:  tsk_push(`STW_CS0,0,1);
+        `PHK:   tsk_push(`STW_PC2316,0,0);
+		`PHB:   tsk_push(`STW_DBR,0,0);
+		`PHD:   tsk_push(`STW_DPR70,1,0);
+		`PEA:
+            begin
+                inc_pc(24'd3);
+                wdat <= ir[23:8];
+                tsk_push(`STW_DEF70,1,0);
+            end
+`ifdef SUPPORT_NEW_INSN
+        `PEAxl:
+            begin
+                inc_pc(24'd5);
+                wdat <= ir[39:8];
+                tsk_push(`STW_DEF70,0,1);
+            end
+`endif
+        `PER:
+            begin
+                inc_pc(24'd3);
+                wdat <= pc[15:0] + ir[23:8] + 16'd3;
+                tsk_push(`STW_DEF70,1,0);
+            end
+		`PLP:
+			begin
+                inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+				load_what <= `SR_70;
+				state <= LOAD_MAC1;
+			end
+		`PLA:
+			begin
+			    inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                if (m32) s32 <= TRUE;
+                else if (m16) s16 <= TRUE;
+                load_what <= `WORD_71S;
+				state <= LOAD_MAC1;
+				retstate <= ssm ? SSM1:IFETCH;
+			end
+		`PLX,`PLY:
+			begin
+			    inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                if (xb32) s32 <= TRUE;
+                else if (xb16) s16 <= TRUE;
+				load_what <= `WORD_71S;
+				state <= LOAD_MAC1;
+				retstate <= ssm ? SSM1:IFETCH;
+			end
+		`PLB:
+			begin
+			    inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+  				load_what <= `WORD_71S;
+				state <= LOAD_MAC1;
+				retstate <= ssm ? SSM1 : IFETCH;
+			end
+		`PLD:
+			begin
+			    inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+			    s16 <= TRUE;
+  				load_what <= `WORD_71S;
+				state <= LOAD_MAC1;
+				retstate <= ssm ? SSM1 : IFETCH;
+			end
+		// Handle # mode
+        `LDA_IMM:
+            begin
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= ir[39:8];
+            end
+        `LDX_IMM,`LDY_IMM:
+            begin
+                if (xb32) inc_pc(24'd5);
+                else if (xb16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= ir[39:8];
+            end
+            // We don't care what the high order bits of the calculation
+            // are for 8/16 bit results, so we can safely use 32 bits
+            // from the instruction stream. The high order bits will be
+            // invalid, but don't get stored anyway for 8/16 bit ops.
+            // This is to save some hardware.
+        `ADC_IMM:
+            begin
+                a32 <= acc;
+                b32 <= ir[39:8];        // for overflow calc
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= acc + ir[39:8] + {31'b0,cf};
+            end
+        `SBC_IMM:
+            begin
+                a32 <= acc;
+                b32 <= ir[39:8];        // for overflow calc
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= acc - ir[39:8] - {31'b0,~cf};
+            end
+        `AND_IMM,`BIT_IMM:
+            begin
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= acc & ir[39:8];
+                b32 <= ir[39:8];    // for bit flags
+            end
+        `ORA_IMM:
+            begin
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= acc | ir[39:8];
+            end
+        `EOR_IMM:
+            begin
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+                res32 <= acc ^ ir[39:8];
+            end
+        `CMP_IMM:
+            begin
+                a32 <= acc;
+                b32 <= ir[39:8];        // for carry calc
+                res32 <= {1'd0,acc} - {1'd0,ir[39:8]};
+                if (m32) inc_pc(24'd5);
+                else if (m16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+            end
+        `CPX_IMM:
+            begin
+                a32 <= x32;
+                b32 <= ir[39:8];        // for carry calc
+                res32 <= x32 - ir[39:8];
+                if (xb32) inc_pc(24'd5);
+                else if (xb16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+            end
+        `CPY_IMM:
+            begin
+                a32 <= y32;
+                b32 <= ir[39:8];        // for carry calc
+                res32 <= y32 - ir[39:8];
+                if (xb32) inc_pc(24'd5);
+                else if (xb16) inc_pc(24'd3);
+                else inc_pc(24'd2);
+            end
+		// Handle zp mode
+        `LDA_ZP:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `LDX_ZP,`LDY_ZP:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                retstate <= ssm ? SSM1 : IFETCH;
+                state <= LOAD_MAC2;
+                bank_wrap <= !m832;
+            end
+        `ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
+        `BIT_ZP,
+        `ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`TRB_ZP,`TSB_ZP:
+            begin
+                inc_pc(24'd2);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                radr <= zp_address;
+                wadr <= zp_address;
+                data_read(zp_address,1);
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+        `INC_ZP,`DEC_ZP:
+            begin
+                inc_pc(24'd2);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                radr <= zp_address;
+                wadr <= zp_address;
+                data_read(zp_address,1);
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+        `INC_IMM:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                radr <= zp_address;
+                wadr <= zp_address;
+                data_read(zp_address,1);
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+        `CPX_ZP,`CPY_ZP:
+            begin
+                inc_pc(24'd2);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                radr <= zp_address;
+                data_read(zp_address,1);
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+        `STA_ZP:
+            begin
+                inc_pc(24'd2);
+                wadr <= zp_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        `STX_ZP:
+            begin
+                inc_pc(24'd2);
+                wadr <= zp_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_X70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        `STY_ZP:
+            begin
+                inc_pc(24'd2);
+                wadr <= zp_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_Y70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        `STZ_ZP:
+            begin
+                inc_pc(24'd2);
+                wadr <= zp_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+		// Handle zp,x mode
+        `LDA_ZPX:
+            begin
+                inc_pc(24'd2);
+                radr <= zpx_address;
+                data_read(zpx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `LDY_ZPX:
+            begin
+                inc_pc(24'd2);
+                radr <= zpx_address;
+                data_read(zpx_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
+        `BIT_ZPX,
+        `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
+            begin
+                inc_pc(24'd2);
+                radr <= zpx_address;
+                wadr <= zpx_address;
+                data_read(zpx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                retstate <= CALC;
+                state <= LOAD_MAC2;
+                bank_wrap <= !m832;
+            end
+        `STA_ZPX:
+            begin
+                inc_pc(24'd2);
+                wadr <= zpx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        `STY_ZPX:
+            begin
+                inc_pc(24'd2);
+                wadr <= zpx_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_Y70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        `STZ_ZPX:
+            begin
+                inc_pc(24'd2);
+                wadr <= zpx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+        // Handle zp,y
+        `LDX_ZPY:
+            begin
+                inc_pc(24'd2);
+                radr <= zpy_address;
+                data_read(zpy_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `STX_ZPY:
+            begin
+                inc_pc(24'd2);
+                wadr <= zpy_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_X70;
+                state <= STORE1;
+                bank_wrap <= !m832;
+            end
+		// Handle (zp,x)
+		`LDA_IX:
+            begin
+                inc_pc(24'd2);
+                radr <= zpx_address;
+                data_read(zpx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`STA_IX:
+            begin
+                inc_pc(24'd2);
+                radr <= zpx_address;
+                data_read(zpx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+        // Handle (zp),y
+        `LDA_IY:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+		// Handle d,sp
+        `LDA_DSP:
+            begin
+                inc_pc(24'd2);
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                radr <= dsp_address;
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC1;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_DSP,`SBC_DSP,`CMP_DSP,`ORA_DSP,`AND_DSP,`EOR_DSP:
+            begin
+                inc_pc(24'd2);
+                radr <= dsp_address;
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC1;
+                retstate <= CALC;
+            end
+        `STA_DSP:
+            begin
+                inc_pc(24'd2);
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                radr <= dsp_address;
+                wadr <= dsp_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                state <= STORE1;
+            end
+		// Handle (d,sp),y
+		`LDA_DSPIY:
+            begin
+                inc_pc(24'd2);
+                seg <= ss_base;
+                lmt <= ss_limit;
+                radr <= dsp_address;
+                mem_wr <= ss_wr;
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY <= `TRUE;
+                load_what <= `IA_70;
+                retstate <= ssm ? SSM1 : IFETCH;
+                state <= LOAD_MAC1;
+            end
+        `ADC_DSPIY,`SBC_DSPIY,`CMP_DSPIY,`ORA_DSPIY,`AND_DSPIY,`EOR_DSPIY,`STA_DSPIY:
+            begin
+                inc_pc(24'd2);
+                radr <= dsp_address;
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY <= `TRUE;
+                load_what <= `IA_70;
+                retstate <= CALC;
+                state <= LOAD_MAC1;
+            end
+`ifdef SUPPORT_NEW_INSN
+		// Handle {d,sp},y
+	   `LDA_XDSPIY:
+            begin
+               inc_pc(24'd2);
+               seg <= ss_base;
+               lmt <= ss_limit;
+               mem_wr <= ss_wr;
+               radr <= dsp_address;
+               mxb16 <= m16;
+               mxb32 <= m32;
+               isIY32 <= `TRUE;
+               load_what <= `IA_70;
+               state <= LOAD_MAC1;
+               retstate <= ssm ? SSM1 : IFETCH;
+           end
+       `ADC_XDSPIY,`SBC_XDSPIY,`CMP_XDSPIY,`ORA_XDSPIY,`AND_XDSPIY,`EOR_XDSPIY,`STA_XDSPIY:
+            begin
+                inc_pc(24'd2);
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                radr <= dsp_address;
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY32 <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC1;
+                retstate <= CALC;
+            end
+`endif
+        // Handle [zp],y
+        `LDA_IYL:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY24 <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_IYL,`SBC_IYL,`AND_IYL,`ORA_IYL,`EOR_IYL,`CMP_IYL,`STA_IYL:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY24 <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+`ifdef SUPPORT_NEW_INSN
+        // Handle {zp},y
+        `LDA_XIYL:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY32 <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_XIYL,`SBC_XIYL,`AND_XIYL,`ORA_XIYL,`EOR_XIYL,`CMP_XIYL,`STA_XIYL:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                isIY32 <= `TRUE;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+`endif
+		// Handle [zp]
+		`LDA_IL:
+            begin
+                inc_pc(24'd2);
+                isI24 <= `TRUE;
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_IL,`SBC_IL,`AND_IL,`ORA_IL,`EOR_IL,`CMP_IL,`STA_IL:
+            begin
+                inc_pc(24'd2);
+                isI24 <= `TRUE;
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+`ifdef SUPPORT_NEW_INSN
+		// Handle {zp}
+		`LDA_XIL:
+            begin
+                inc_pc(24'd2);
+                isI32 <= `TRUE;
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_XIL,`SBC_XIL,`AND_XIL,`ORA_XIL,`EOR_XIL,`CMP_XIL,`STA_XIL:
+            begin
+                inc_pc(24'd2);
+                isI32 <= `TRUE;
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+`endif
+        // Handle (zp)
+        `LDA_I:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`STA_I,`PEI:
+            begin
+                inc_pc(24'd2);
+                radr <= zp_address;
+                data_read(zp_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                load_what <= `IA_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+                bank_wrap <= !m832;
+            end
+		// Handle abs
+        `LDA_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= abs_address;
+                data_read(abs_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                retstate <= ssm ? SSM1 : IFETCH;
+                state <= LOAD_MAC2;
+            end
+        `LDX_ABS,`LDY_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= abs_address;
+                data_read(abs_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
+        `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
+        `BIT_ABS:
+            begin
+                inc_pc(24'd3);
+                radr <= abs_address;
+                wadr <= abs_address;
+                data_read(abs_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `CPX_ABS,`CPY_ABS:
+            begin
+                inc_pc(24'd3);
+                radr <= abs_address;
+                data_read(abs_address,1);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `STA_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= abs_address;
+                wadr <= abs_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(abs_address,acc[7:0],1);
+                state <= STORE2;
+            end
+        `STX_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= abs_address;
+                wadr <= abs_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_X70;
+                data_write(abs_address,x[7:0],1);
+                state <= STORE2;
+            end    
+        `STY_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= abs_address;
+                wadr <= abs_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_Y70;
+                data_write(abs_address,y[7:0],1);
+                state <= STORE2;
+            end
+        `STZ_ABS:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= abs_address;
+                wadr <= abs_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                data_write(abs_address,8'h00,1);
+                state <= STORE2;
+            end
+`ifdef SUPPORT_NEW_INSN
+		// Handle xlabs
+        `LDA_XABS:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xal_address;
+                data_read(xal_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `LDX_XABS,`LDY_XABS:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= xal_address;
+                data_read(xal_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_XABS,`SBC_XABS,`AND_XABS,`ORA_XABS,`EOR_XABS,`CMP_XABS,
+        `ASL_XABS,`ROL_XABS,`LSR_XABS,`ROR_XABS,`INC_XABS,`DEC_XABS,`TRB_XABS,`TSB_XABS,
+        `BIT_XABS:
+            begin
+                inc_pc(24'd5);
+                radr <= xal_address;
+                wadr <= xal_address;
+                data_read(xal_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `CPX_XABS,`CPY_XABS:
+            begin
+                inc_pc(24'd5);
+                radr <= xal_address;
+                data_read(xal_address,1);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `STA_XABS:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xal_address;
+                wadr <= xal_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(xal_address,acc[7:0],1);
+                state <= STORE2;
+            end
+        `STX_XABS:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= xal_address;
+                wadr <= xal_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_X70;
+                data_write(xal_address,x[7:0],1);
+                state <= STORE2;
+            end    
+        `STY_XABS:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= xal_address;
+                wadr <= xal_address;
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                store_what <= `STW_Y70;
+                data_write(xal_address,y[7:0],1);
+                state <= STORE2;
+            end
+        `STZ_XABS:
+            begin
+                inc_pc(24'd5);
+                radr <= xal_address;
+                wadr <= xal_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                data_write(xal_address,8'h00,1);
+                state <= STORE2;
+            end
+`endif
+        // Handle abs,x
+        `LDA_ABSX:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= absx_address;
+                data_read(absx_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,
+        `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX:
+            begin
+                inc_pc(24'd3);
+                radr <= absx_address;
+                wadr <= absx_address;
+                data_read(absx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `LDY_ABSX:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= absx_address;
+                data_read(absx_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `STA_ABSX:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= absx_address;
+                wadr <= absx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(absx_address,acc[7:0],1);
+                state <= STORE2;
+            end
+        `STZ_ABSX:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= absx_address;
+                wadr <= absx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                data_write(absx_address,8'h00,1);
+                state <= STORE2;
+            end
+`ifdef SUPPORT_NEW_INSN
+        // Handle xlabs,x
+        `LDA_XABSX:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xalx_address;
+                data_read(xalx_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_XABSX,`SBC_XABSX,`AND_XABSX,`ORA_XABSX,`EOR_XABSX,`CMP_XABSX,
+        `ASL_XABSX,`ROL_XABSX,`LSR_XABSX,`ROR_XABSX,`INC_XABSX,`DEC_XABSX,`BIT_XABSX:
+            begin
+                inc_pc(24'd5);
+                radr <= xalx_address;
+                wadr <= xalx_address;
+                data_read(xalx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `LDY_XABSX:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= xalx_address;
+                data_read(xalx_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `STA_XABSX:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xalx_address;
+                wadr <= xalx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(xalx_address,acc[7:0],1);
+                state <= STORE2;
+            end
+        `STZ_XABSX:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xalx_address;
+                wadr <= xalx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_Z70;
+                data_write(xalx_address,8'h00,1);
+                state <= STORE2;
+            end
+`endif
+		// Handle abs,y
+        `LDA_ABSY:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= absy_address;
+                data_read(absy_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+                bank_wrap <= !m832;
+            end
+        `ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY:
+            begin
+                inc_pc(24'd3);
+                radr <= absy_address;
+                data_read(absy_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `LDX_ABSY:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= absy_address;
+                data_read(absy_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `STA_ABSY:
+            begin
+                inc_pc(24'd3);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= absy_address;
+                wadr <= absy_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(absy_address,acc[7:0],1);
+                state <= STORE2;
+            end
+`ifdef SUPPORT_NEW_INSN
+		// Handle xlabs,y
+        `LDA_XABSY:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xaly_address;
+                data_read(xaly_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_XABSY,`SBC_XABSY,`AND_XABSY,`ORA_XABSY,`EOR_XABSY,`CMP_XABSY:
+            begin
+                inc_pc(24'd5);
+                radr <= xaly_address;
+                data_read(xaly_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `LDX_XABSY:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= xb16;
+                mxb32 <= xb32;
+                radr <= xaly_address;
+                data_read(xaly_address,1);
+                if (!sop) begin
+                    if (xb32) s32 <= TRUE;
+                    else if (xb16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `STA_XABSY:
+            begin
+                inc_pc(24'd5);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= xaly_address;
+                wadr <= xaly_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(xaly_address,acc[7:0],1);
+                state <= STORE2;
+            end
+`endif
+		// Handle al
+        `LDA_AL:
+            begin
+                inc_pc(24'd4);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= al_address;
+                data_read(al_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_AL,`SBC_AL,`AND_AL,`ORA_AL,`EOR_AL,`CMP_AL:
+            begin
+                inc_pc(24'd4);
+                radr <= al_address;
+                data_read(al_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `STA_AL:
+            begin
+                inc_pc(24'd4);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= al_address;
+                wadr <= al_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(al_address,acc[7:0],1);
+                state <= STORE2;
+            end
+		// Handle alx
+        `LDA_ALX:
+            begin
+                inc_pc(24'd4);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= alx_address;
+                data_read(alx_address,1);
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= ssm ? SSM1 : IFETCH;
+            end
+        `ADC_ALX,`SBC_ALX,`AND_ALX,`ORA_ALX,`EOR_ALX,`CMP_ALX:
+            begin
+                inc_pc(24'd4);
+                radr <= alx_address;
+                data_read(alx_address,1);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                load_what <= `LOAD_70;
+                state <= LOAD_MAC2;
+                retstate <= CALC;
+            end
+        `STA_ALX:
+            begin
+                inc_pc(24'd4);
+                mxb16 <= m16;
+                mxb32 <= m32;
+                radr <= alx_address;
+                wadr <= alx_address;
+                if (!sop) begin
+                    if (m32) s32 <= TRUE;
+                    else if (m16) s16 <= TRUE;
+                end
+                store_what <= `STW_ACC70;
+                data_write(alx_address,acc[7:0],1);
+                state <= STORE2;
+            end
+        `BRK,`BRK2:
+            begin
+                pc_cap <= FALSE;
+                if (!hwi)
+                    inc_pc(24'd2);
+                else
+                    pc <= pc;   // override increment above
+                if (m832) begin
+`ifdef SUPPORT_TASK
+                    if (TASK_VECTORING) begin
+                        seg <= 32'd0;
+                        lmt <= 32'hFFFF;
+                        mem_wr <= FALSE;
+                        radr <= vect;
+                        otr <= tr;
+                        load_what <= `LDW_TR70;
+                        next_state(LOAD_MAC1);
+                    end
+                    else begin
+                        set_sp();
+                        seg <= ss_base;
+                        lmt <= ss_limit;
+                        mem_wr <= ss_wr;
+                        store_what <= `STW_CS158;
+                        data_nack();
+                        state <= STORE1;
+                    end
+`else
+                    set_sp();
+                    seg <= ss_base;
+                    lmt <= ss_limit;
+                    mem_wr <= ss_wr;
+                    store_what <= `STW_CS158;
+                    data_nack();
+                    state <= STORE1;
+`endif
+                end
+                else begin
+                    set_sp();
+                    seg <= ss_base;
+                    lmt <= ss_limit;
+                    mem_wr <= ss_wr;
+                    store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
+                    data_nack();
+                    state <= STORE1;
+                end
+                bf <= !hwi;
+            end
+		`COP:
+            begin
+                inc_pc(24'd2);
+                set_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                store_what <= m832 ? `STW_CS158 : m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
+                state <= STORE1;
+                vect <= m832 ? `COP_VECT_832 : m816 ? `COP_VECT_816 : `BYTE_COP_VECT;
+            end
+		`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,`BGT,`BGE,`BLT,`BLE:
+            begin
+                if (ir[15:8]==8'hFF) begin
+                    if (takb)
+                        inc_pc({{8{ir[31]}},ir[31:16]} + 24'd4);
+                    else
+                        inc_pc(24'd4);
+                end
+                else begin
+                    if (takb)
+                        inc_pc({{16{ir[15]}},ir[15:8]} + 24'd2);
+                    else
+                        inc_pc(24'd2);
+                end
+            end
+		`JMP:
+            begin
+                pc[15:0] <= ir[23:8];
+            end
+        `JMP_IND:
+            begin
+                radr <= abs_address;
+                load_what <= `PC_70;
+                data_read(abs_address,0);
+                state <= LOAD_MAC2;
+            end
+        `JML_IND:
+            begin
+                radr <= abs_address;
+                load_what <= `PC_70;
+                data_read(abs_address,0);
+                state <= LOAD_MAC2;
+            end
+        `JML_XIND:
+            begin
+                radr <= xal_address;
+                data_read(xal_address,0);
+                load_what <= `PC_70;
+                state <= LOAD_MAC2;
+            end
+`ifdef SUPPORT_NEW_INSN
+        `JML_XINDX:
+            begin
+                radr <= xalx_address;
+                load_what <= `PC_70;
+                data_read(xalx_address,0);
+                state <= LOAD_MAC2;
+            end
+        `JSL_XINDX:
+            begin
+                inc_pc(24'd4);  // Yes this should be one less than the instruction length.
+                set_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                store_what <= `STW_PC2316;
+                state <= STORE1;
+            end
+`endif
+        `JMP_INDX:
+            begin
+                radr <= absx_address;
+                load_what <= `PC_70;
+                data_read(absx_address,0);
+                state <= LOAD_MAC2;
+            end    
+        `BSR,`JSR,`JSR_INDX:
+            begin
+                inc_pc(24'd2);  // Yes this should be one less than the instruction length.
+                set_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                store_what <= `STW_PC158;
+                state <= STORE1;
+            end
+        `BRL:
+            begin
+                inc_pc({{8{ir[23]}},ir[23:8]} + 24'd3);
+            end
+		`JML:
+            begin
+                pc <= ir[31:8];
+            end
+        `BSL,`JSL:
+                begin
+                    inc_pc(24'd3);
+                    set_sp();
+                    seg <= ss_base;
+                    lmt <= ss_limit;
+                    mem_wr <= ss_wr;
+                    store_what <= `STW_PC2316;
+                    state <= STORE1;
+                end
+`ifdef SUPPORT_NEW_INSN
+`ifdef SUPPORT_SEG
+		`PHDS:  tsk_push(`STW_DS70,1,0);
+        `PHCS:
+            begin
+                set_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+//                data_write(fn_get_sp(sp),cs[31:24],0); // new to set the segment in use
+//                mlb <= TRUE;
+                store_what <= `STW_CS158;
+                state <= STORE1;
+            end
+        `PLDS:
+            begin
+                inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                s16 <= TRUE;
+                load_what <= `WORD_71S;
+//                data_read(fn_sp_inc(sp_inc),0);
+                state <= LOAD_MAC1;
+                retstate <= PLDS1;
+            end
+        `SDU:
+            begin
+                base_i <= acc;
+                size_i <= x[3:0];
+                acr_i <= x[11:4];
+                sdt_wa <= y[11:0];
+                wr_sdt <= TRUE;
+            end
+		`JMF:
+            begin
+                pc <= ir[31:8];
+                // Switch modes ?
+                if (ir[63:32]==32'hFFFFFFFF) begin
+                    m832 <= `FALSE;
+                    m816 <= `FALSE;
+                    sdt_ra <= 16'd0;
+                    cs <= 16'd0;
+                    ds <= 16'd0;
+                end
+                else if (ir[63:32]==32'hFFFFFFFE) begin
+                    m832 <= `FALSE;
+                    m816 <= `TRUE;
+                    sdt_ra <= 16'd0;
+                    cs <= 16'd0;
+                    ds <= 16'd0;
+                    x_bit <= 1'b1;
+                    m_bit <= 1'b1;
+                end
+                else begin
+                    sdt_ra <= ir[47:32];
+                    cs <= ir[47:32];
+                end
+                next_state(JMF1);
+            end
+        `JSF:
+            begin
+                inc_pc(24'd5);
+                set_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                radr <= sp;
+                wadr <= sp;
+                state <= STORE1;
+            end
+`endif
+`ifdef SUPPORT_TASK
+        `TSK_IMM:
+            begin
+                inc_pc(24'd3);
+                if (tr != ir[`TASK_MEM_ABIT+8:8]) begin
+                    set_task_regs(24'd3);
+                    otr <= tr;
+                    back_link <= tr;
+                    tr <= ir[`TASK_MEM_ABIT+8:8];
+                    tsk_pres <= 7'h20;
+                    sdt_ra <= cs;
+                    store_what <= `STW_TR158;
+                    next_state(TSK1);
+`ifdef TASK_BL
+                    retstate <= ssm ? SSM1 : IFETCH;
+`else
+                    retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                    //retstate <= ssm ? SSM1 : IFETCH;
+                end
+            end
+        `TSK_ACC:
+            begin
+                if (tr != acc[`TASK_MEM_ABIT:0]) begin
+                    set_task_regs(24'd1);
+                    otr <= tr;
+                    back_link <= tr;
+                    tr <= acc[`TASK_MEM_ABIT:0];
+                    tsk_pres <= 7'h20;
+                    sdt_ra <= cs;
+                    store_what <= `STW_TR158;
+                    next_state(TSK1);
+`ifdef TASK_BL
+                    retstate <= ssm ? SSM1 : IFETCH;
+`else
+                    retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                end
+            end
+        `FORK_IMM:
+            begin
+                inc_pc(24'd3);
+                if (tr != ir[`TASK_MEM_ABIT+8:8]) begin
+                    set_task_regs(24'd3);
+                    sdt_ra <= cs;
+                    otr <= tr;
+                    back_link <= tr;
+                    tr <= ir[`TASK_MEM_ABIT+8:8];
+`ifdef TASK_BL
+                    next_state(ssm ? SSM1 : IFETCH);
+`else
+                    set_sp();
+                    seg <= ss_base;
+                    lmt <= ss_limit;
+                    mem_wr <= ss_wr;
+                    store_what <= `STW_TR158;
+                    if (!tj_prefix)
+                        next_state(STORE1);
+`endif
+                end
+            end
+        `FORK_ACC:
+            begin
+                if (tr != acc[`TASK_MEM_ABIT:0]) begin
+                    set_task_regs(24'd1);
+                    otr <= tr;
+                    sdt_ra <= cs;
+                    back_link <= tr;
+                    tr <= acc[`TASK_MEM_ABIT:0];
+`ifdef TASK_BL
+                    next_state(ssm ? SSM1 : IFETCH);                    
+`else
+                    set_sp();
+                    seg <= ss_base;
+                    lmt <= ss_limit;
+                    mem_wr <= ss_wr;
+                    store_what <= `STW_TR158;
+                    if (!tj_prefix)
+                        next_state(STORE1);
+`endif
+                end
+            end
+		`RTT:
+            begin
+                set_task_regs(24'd1);
+                tsk_pres <= 7'd0;
+`ifdef TASK_BL
+                tr <= back_link;
+                retstate <= IFETCH;
+                next_state(TSK1);
+`else
+                sp_i <= fn_add_to_sp(32'd2);
+                inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                load_what <= `LDW_TR70S;
+                state <= LOAD_MAC1;
+`endif
+            end
+        `LDT_XABS:
+            begin
+                inc_pc(24'd5);
+                cnt <= 4'd0;
+                radr <= ir[39:8];
+                next_state(LDT1);
+            end
+        `LDT_XABSX:
+            begin
+                inc_pc(24'd5);
+                cnt <= 4'd0;
+                radr <= ir[39:8] + (x << 5);
+                next_state(LDT1);
+            end
+        `JCF:
+            begin
+                inc_pc(24'd9);
+                if (tr != ir[`TASK_MEM_ABIT+48:48]) begin
+                    pc <= ir[31:8];
+                    cs <= ir[47:32];
+                    sdt_ra <= ir[47:32];
+                    back_link <= tr;
+                    set_task_regs(24'd9);
+                    otr <= tr;
+                    tr <= ir[`TASK_MEM_ABIT+48:48];
+                    maxcnt <= ir[68:64];
+                    if (ir[71]) begin
+                        tsk_pres[3:0] <= 4'hF;
+                        tsk_pres[4] <= TRUE;
+                        tsk_pres[5] <= TRUE;
+                        tsk_pres[6] <= TRUE;
+                    end
+                    else begin
+                        tsk_pres[3:0] <= 4'h0;
+                        tsk_pres[4] <= TRUE;
+                        tsk_pres[5] <= TRUE;
+                        tsk_pres[6] <= TRUE;
+                    end
+                    if (ir[68:64] > 5'd0) begin
+                        cnt <= 8'h00;
+                        load_what <= `CPY_BUF;
+                        store_what <= `STW_CPY_BUF;
+                        inc_sp();
+                        seg <= ss_base;
+                        lmt <= ss_limit;
+                        mem_wr <= ss_wr;
+                        next_state(LOAD_MAC1);
+                        retstate <= STORE1;
+                    end
+                    else begin 
+                        state <= TSK1;
+`ifdef TASK_BL
+                        retstate <= ssm ? SSM1 : IFETCH;
+`else                        
+                        store_what <= `STW_TR158;
+                        retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                    end
+                end
+            end
+        `JCL:
+            begin
+                inc_pc(24'd7);
+                if (tr != ir[`TASK_MEM_ABIT+32:32]) begin
+                    pc <= ir[31:8];
+                    back_link <= tr;
+                    set_task_regs(24'd7);
+                    otr <= tr;
+                    tr <= ir[`TASK_MEM_ABIT+32:32];
+                    maxcnt <= ir[52:48];
+                    if (ir[55]) begin
+                        tsk_pres[3:0] <= 4'hF;
+                        tsk_pres[4] <= TRUE;
+                        tsk_pres[5] <= TRUE;
+                        tsk_pres[6] <= FALSE;
+                    end
+                    else begin
+                        tsk_pres[3:0] <= 4'h0;
+                        tsk_pres[4] <= TRUE;
+                        tsk_pres[5] <= TRUE;
+                        tsk_pres[6] <= FALSE;
+                    end
+                    if (ir[52:48] > 5'd0) begin
+                        cnt <= 8'h00;
+                        load_what <= `CPY_BUF;
+                        store_what <= `STW_CPY_BUF;
+                        inc_sp();
+                        seg <= ss_base;
+                        lmt <= ss_limit;
+                        mem_wr <= ss_wr;
+                        next_state(LOAD_MAC1);
+                        retstate <= STORE1;
+                    end
+                    else begin 
+                        state <= TSK1;
+`ifdef TASK_BL
+                        retstate <= ssm ? SSM1 : IFETCH;
+`else                        
+                        store_what <= `STW_TR158;
+                        retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                    end
+                end
+            end
+        `JCR:
+            begin
+                inc_pc(24'd5);
+                if (tr != {8'h00,ir[31:24]}) begin
+                    pc <= {8'h00,ir[23:8]};
+                    back_link <= tr;
+                    set_task_regs(24'd5);
+                    otr <= tr;
+                    tr <= {8'h00,ir[31:24]};
+                    tsk_pres[3:0] <= 4'hF;
+                    tsk_pres[4] <= TRUE;
+                    tsk_pres[5] <= TRUE;
+                    tsk_pres[6] <= FALSE;
+                    state <= TSK1;
+`ifdef TASK_BL
+                    retstate <= ssm ? SSM1 : IFETCH;
+`else
+                    store_what <= `STW_TR158;
+                    retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                end
+            end
+        `JCI:
+            begin
+                if (tr != {8'h00,acc[31:24]}) begin
+                    pc <= acc[23:0];
+                    back_link <= tr;
+                    set_task_regs(24'd1);
+                    otr <= tr;
+                    tr <= {8'h00,acc[31:24]};
+                    tsk_pres[3:0] <= 4'hF;
+                    tsk_pres[4] <= TRUE;
+                    tsk_pres[5] <= TRUE;
+                    tsk_pres[6] <= FALSE;
+                    state <= TSK1;
+`ifdef TASK_BL
+                    retstate <= ssm ? SSM1 : IFETCH;
+`else
+                    store_what <= `STW_TR158;
+                    retstate <= tj_prefix ? IFETCH : STORE1;
+`endif
+                end
+            end
+		`RTC:
+            begin
+                inc_pc(24'd2);
+                set_task_regs(24'd2);
+                tsk_pres <= 7'hF;
+                sp_i <= fn_add_to_sp(ir[15:8]);
+`ifdef TASK_BL
+                tr <= back_link;
+                next_state(TSK1);
+                retstate <= ssm ? SSM1 : IFETCH;
+`else
+                inc_sp();
+                seg <= ss_base;
+                lmt <= ss_limit;
+                mem_wr <= ss_wr;
+                load_what <= `LDW_TR70S;
+                state <= LOAD_MAC1;
+`endif
+            end
+`endif
+        `FILL:
+            begin
+                mvndst_bank <= ir[15:8];
+                wadr <= mvndst_address;
+                store_what <= `STW_X70;
+                npc <= PC24 ? pc + 24'd2 : {pc[23:16],pc[15:0]+16'd2};
+                pc <= opc;      // override increment above
+                next_state(STORE1);
+            end
+`endif
+		`MVN,`MVP:
+            begin
+                mvndst_bank <= ir[15:8];
+                mvnsrc_bank <= ir[23:16];
+                radr <= mvnsrc_address;
+                load_what <= `BYTE_72;
+                npc <= PC24 ? pc + 24'd3 : {pc[23:16],pc[15:0]+16'd3};
+                pc <= opc;       // override increment above
+                state <= LOAD_MAC1;
+            end
+`ifdef SUPPORT_NEW_INSN
+        `CACHE:
+            begin
+                inc_pc(24'd2);
+                case(ir[15:8])
+                8'h00:  inv_icache <= TRUE; // invalidate entire instruction cache
+                8'h01:  begin
+                        ado1 <= {acc[31:4],4'h0};
+                        inv_iline <= TRUE;
+                        end
+                8'h02:  begin       // LICL
+                        rwo <= TRUE;
+                        vpa <= TRUE;
+                        vda <= TRUE;
+                        ado <= {acc[31:4],4'h0};
+                        wr_icache <= TRUE; 
+                        cnt <= 4'h0;
+                        // Going to the ICACHE2 state will ensure that loading
+                        // the cache line didn't dump the cache line that is
+                        // required by the PC.
+                        next_state(ICACHE2);
+                        end
+                default:    ;
+                endcase
+            end
+`endif
+        default:
+			begin
+				moveto_ifetch();
+			end
+		endcase
+	end
+`ifdef SUPPORT_TASK
+TSK1:
+    begin
+`ifdef SUPPORT_SEG
+        if (!tsk_pres[6]) begin sdt_ra <= cs_o; cs <= cs_o; end
+`endif
+        if (!tsk_pres[4]) pc <= pc_o;
+        if (!tsk_pres[3]) acc <= acc_o;
+        if (!tsk_pres[2]) x <= x_o;
+        if (!tsk_pres[1]) y <= y_o;
+        sp <= sp_o[31:0];
+        if (!tsk_pres[0]) cf <= sr_o[0];
+        if (!tsk_pres[0]) zf <= sr_o[1];
+        // Force further interrupts to be masked automatically when the task is
+        // invoked as an interrupt handler. Otherwise the task will be invoked
+        // continuously.
+        if (sr_o[2]|hwi)
+            im <= 1'b1;
+        else
+            imcd <= 3'b110;
+        df <= sr_o[3];
+        if (|srx_o[1:0]) begin
+            x_bit <= sr_o[4];
+            m_bit <= sr_o[5];
+        end
+        // The following load of the break flag is different than the '02
+        // which never loads the flag.
+        else if (POPBF)
+            bf <= sr_o[4];
+        if (!tsk_pres[0]) vf <= sr_o[6];
+        if (!tsk_pres[0]) nf <= sr_o[7];
+        m816 <= srx_o[0];
+        m832 <= srx_o[1];
+        mib <= srx_o[2];
+        ssm <= srx_o[4];
+        dbr <= dbr_o;
+        dpr <= dpr_o;
+        if (!tsk_pres[5]) back_link <= bl_o;
+        next_state(TSK2);
+    end
+TSK2:
+    begin
+        ds <= ds_o;
+        ss <= ss_o;
+        sdt_ra <= ds_o[11:0];
+        if (!tsk_pres[6]) begin
+            cs_base <= base_o;
+            cs_limit <= fn_limit(size_o);
+            cs_wr <= acr_o[3];
+        end
+        // Fault if the code segment isn't executable
+        if (!acr_o[4] & !tsk_pres[6])
+            seg_fault(SEGF_EXEC);
+        else
+            next_state(TSK3);
+    end
+TSK3:
+    begin
+        sdt_ra <= ss_o[11:0];
+        ds_base <= base_o;
+        ds_limit <= fn_limit(size_o);
+        ds_wr <= acr_o[3];
+        next_state(TSK4);
+    end
+TSK4:
+    begin
+        ss_base <= base_o;
+        ss_limit <= fn_limit(size_o);
+        ss_wr <= acr_o[3];
+        // Fault if the stack segment isn't writable
+        if (acr_o[3] != TRUE)
+            seg_fault(SEGF_WRITE);
+        else begin
+            if (!srx_o[2]) begin
+                if (retstate==STORE1) begin
+                    set_sp();
+                    seg <= base_o;
+                    lmt <= fn_limit(size_o);
+                    mem_wr <= acr_o[3];
+                end
+                next_state(retstate);
+            end
+            else
+                moveto_ifetch();
+        end
+    end
+JMF1:
+    begin
+        cs_base <= base_o;
+        cs_limit <= fn_limit(size_o);
+        cs_wr <= acr_o[3];
+        // Fault if the code segment isn't executable
+        if (!acr_o[4])
+            seg_fault(SEGF_EXEC);
+        else
+            moveto_ifetch();
+    end
+TASS1:
+    begin
+        ss_base <= base_o;
+        ss_limit <= fn_limit(size_o);
+        ss_wr <= acr_o[3];
+        // Fault if the stack segment isn't writable
+        if (acr_o[3] != TRUE)
+            seg_fault(SEGF_WRITE);
+        else
+            moveto_ifetch();
+    end
+PLDS1:
+    begin
+        sdt_ra <= res32[11:0];
+        next_state(PLDS2);
+    end
+PLDS2:
+    begin
+        ds_base <= base_o;
+        ds_limit <= fn_limit(size_o);
+        ds_wr <= acr_o[3];
+        moveto_ifetch();
+    end
+LDT1:
+    begin
+        cnt <= cnt + 4'd1;
+        s32 <= TRUE;
+        if (cnt < 4'd8) begin
+            data_read(radr,cnt==4'd0);
+            if (seg_fault_val == 4'd0) begin
+                load_what <= `LOAD_70;
+                next_state(LOAD_MAC2);
+                retstate <= LDT1;
+            end
+        end
+        case(cnt)
+        4'd1:   begin cs_i <= b32[15:0]; ds_i <= b32[31:16]; end
+        4'd2:   begin ss_i <= b32[15:0]; pc_i[15:0] <= b32[31:16]; end
+        4'd3:   begin pc_i[23:16] <= b32[7:0]; acc_i[23:0] <= b32[31:8]; end
+        4'd4:   begin acc_i[31:24] <= b32[7:0]; x_i[23:0] <= b32[31:8]; end
+        4'd5:   begin x_i[31:24] <= b32[7:0]; y_i[23:0] <= b32[31:8]; end
+        4'd6:   begin y_i[31:24] <= b32[7:0]; sp_i[23:0] <= b32[31:8]; end
+        4'd7:   begin sp_i[31:24] <= b32[7:0]; sr_i <= b32[15:8]; srx_i <= b32[23:16]; dbr_i <= b32[31:24]; end
+        4'd8:   begin dpr_i <= b32[15:0];
+                tskm_we <= TRUE;
+                tskm_wr <= TRUE;
+                tskm_wa <= x32[`TASK_MEM_ABIT:0];
+                moveto_ifetch();
+                end
+        endcase 
+    end
+INF1:
+    begin
+        if (x[15:4]==12'hFFF) begin
+            case(x[3:0])
+            4'h0:   res32 <= corenum;
+            4'hC:   res32 <= base_o;
+            4'hD:   res32 <= {acr_o,size_o};
+            4'hF:   res32 <= seg_fault_val;
+            default:    ;
+            endcase
+        end
+        else begin
+            case(x[3:0])
+            4'h0:   res32 <= cs_o;
+            4'h1:   res32 <= ds_o;
+            4'h2:   res32 <= ss_o;
+            4'h3:   res32 <= pc_o;
+            4'h4:   res32 <= acc_o;
+            4'h5:   res32 <= x_o;
+            4'h6:   res32 <= y_o;
+            4'h7:   res32 <= sp_o;
+            4'h8:   res32 <= {srx_o,sr_o};
+            4'h9:   res32 <= dbr_o;
+            4'hA:   res32 <= dpr_o;
+            4'hB:   res32 <= bl_o;
+            default:    ;
+            endcase
+        end
+        tr <= otr;
+        moveto_ifetch();
+    end
+`endif
+LOAD_MAC1:
+`ifdef SUPPORT_DCACHE
+    if (unCachedData)
+`endif
+    begin
+        if (load_what==`CPY_BUF && maxcnt > 1)
+            mlb <= 1'b1;
+        if (isRMW)
+            mlb <= 1'b1;
+        if (isBrk)
+            vpb <= `TRUE;
+        data_read(radr,0);
+        if (seg_fault_val==0)
+            state <= LOAD_MAC2;
+    end
+`ifdef SUPPORT_DCACHE
+    else if (dhit)
+        load_tsk(rdat,rdat8,rdat16);
+    else begin
+        retstate <= LOAD_MAC1;
+        state <= DCACHE1;
+    end
+`endif
+LOAD_MAC2:
+    if (rdy) begin
+        data_nack();
+        begin
+            case(load_what)
+            `CPY_BUF:
+                begin
+                    cnt <= cnt + 8'd1;
+                    cpybuf[cnt] <= db;
+                    if (cnt < maxcnt - 8'd1) begin
+                        inc_sp();
+                        next_state(LOAD_MAC1);
+                    end
+                    else begin
+                        mlb <= 1'b0;
+                        cnt <= cnt;
+                        next_state(TSK1);
+                    end
+                end
+            `BYTE_72:
+                        begin
+                            wdat[7:0] <= db;
+                            radr <= mvnsrc_address;
+                            wadr <= mvndst_address;
+                            store_what <= `STW_DEF70;
+                            if (m832)
+                                acc <= acc_dec;
+                            else
+                                acc[15:0] <= acc_dec[15:0];
+                            if (ir9==`MVN) begin
+                                if (xb32) begin
+                                    x <= x_inc;
+                                    y <= y_inc;
+                                end
+                                else if (xb16) begin
+                                    x <= {16'h0000,x_inc[15:0]};
+                                    y <= {16'h0000,y_inc[15:0]};
+                                end
+                                else begin
+                                    x <= {24'h0000,x_inc[7:0]};
+                                    y <= {24'h0000,y_inc[7:0]};
+                                end
+                            end
+                            else begin
+                                if (xb32) begin
+                                    x <= x_dec;
+                                    y <= y_dec;
+                                end
+                                else if (xb16) begin
+                                    x <= {16'h0000,x_dec[15:0]};
+                                    y <= {16'h0000,y_dec[15:0]};
+                                end
+                                else begin
+                                    x <= {24'h0000,x_dec[7:0]};
+                                    y <= {24'h0000,y_dec[7:0]};
+                                end
+                            end
+                            next_state(STORE1);
+                        end
+            `LOAD_70:
+                        begin
+                            radr <= inc_adr(radr);
+                            if (lds) begin
+                                b32 <= {{24{db[7]}},db};
+                                res32 <= {{24{db[7]}},db};
+                            end
+                            else begin
+                                b32 <= {24'd0,db};
+                                res32 <= {24'd0,db};
+                            end
+                            if (s16|s32) begin
+                                load_what <= `LOAD_158;
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(inc_adr(radr),0);
+                                    if (seg_fault_val==0)
+                                        state <= LOAD_MAC2;
+                                end
+                            end
+                            else
+                                state <= retstate;
+                        end
+            `LOAD_158:
+                        begin
+                            radr <= inc_adr(radr);
+                            if (lds) begin
+                                b32[31:8] <= {{16{db[7]}},db};
+                                res32[31:8] <= {{16{db[7]}},db};
+                            end
+                            else begin
+                                b32[31:8] <= {24'd0,db};
+                                res32[31:8] <= {24'd0,db};
+                            end
+                            if (s32) begin
+                                load_what <= `LOAD_2316;
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(inc_adr(radr),0);
+                                    if (seg_fault_val==0)
+                                        state <= LOAD_MAC2;
+                                end
+                            end
+                            else
+                                state <= retstate;
+                        end
+            `LOAD_2316:
+                        begin
+                            b32[23:16] <= db;
+                            res32[23:16] <= db;
+                            load_what <= `LOAD_3124;
+                            radr <= inc_adr(radr);
+                            if (DEAD_CYCLE) begin
+                                data_nack();
+                                next_state(LOAD_MAC1);
+                            end
+                            else begin
+                                data_read(inc_adr(radr),0);
+                                if (seg_fault_val==0)
+                                    state <= LOAD_MAC2;
+                            end
+                        end
+            `LOAD_3124:
+                        begin
+                            radr <= inc_adr(radr);
+                            b32[31:24] <= db;
+                            res32[31:24] <= db;
+                            state <= retstate;
+                        end
+            `WORD_71S:
+                        begin
+                            res32[7:0] <= db;
+                            if (s16|s32) begin
+                                load_what <= `WORD_159S;
+                                inc_sp();
+                                if (DEAD_CYCLE)
+                                    next_state(LOAD_MAC1);
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        next_state(LOAD_MAC2);
+                                end
+                            end
+                            else
+                                next_state(retstate);
+                        end
+            `WORD_159S:
+                        begin
+                            res32[15:8] <= db;
+                            if (s32) begin
+                                load_what <= `WORD_2317S;
+                                inc_sp();
+                                if (DEAD_CYCLE)
+                                    next_state(LOAD_MAC1);
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        next_state(LOAD_MAC2);
+                                end
+                            end
+                            else
+                                next_state(retstate);
+                        end
+            `WORD_2317S:
+                        begin
+                            res32[23:16] <= db;
+                            load_what <= `WORD_3125S;
+                            inc_sp();
+                            if (DEAD_CYCLE)
+                                next_state(LOAD_MAC1);
+                            else begin
+                                data_read(fn_add_to_sp(32'd1),0);
+                                if (seg_fault_val==0)
+                                    next_state(LOAD_MAC2);
+                            end
+                        end
+            `WORD_3125S:
+                        begin
+                            res32[31:24] <= db;
+                            state <= retstate;
+                        end
+            `SR_70:        begin
+                            cf <= db[0];
+                            zf <= db[1];
+                            if (db[2])
+                                im <= 1'b1;
+                            else
+                                imcd <= 3'b110;
+                            df <= db[3];
+                            if (m816|m832) begin
+                                x_bit <= db[4];
+                                m_bit <= db[5];
+//                                if (db[4]) begin
+//                                    x[31:8] <= 24'd0;
+//                                    y[31:8] <= 24'd0;
+//                                end
+                            end
+                            // The following load of the break flag is different than the '02
+                            // which never loads the flag.
+                            else if (POPBF)
+                                bf <= db[4];
+                            vf <= db[6];
+                            nf <= db[7];
+                            if (isRTI) begin
+                                load_what <= `PC_70;
+                                inc_sp();
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        state <= LOAD_MAC2;
+                                end
+                            end        
+                            else begin    // PLP
+                                if (m832) begin
+                                    load_what <= `SR_158;
+                                    inc_sp();
+                                    if (DEAD_CYCLE) begin
+                                        data_nack();
+                                        next_state(LOAD_MAC1);
+                                    end
+                                    else begin
+                                        data_read(fn_add_to_sp(32'd1),0);
+                                        if (seg_fault_val==0)
+                                            state <= LOAD_MAC2;
+                                    end
+                                end
+                                else
+                                    moveto_ifetch();
+                            end
+                        end
+             `SR_158:
+                        begin
+                            m816 <= db[0];
+                            m832 <= db[1];
+                            mib <= db[2];
+                            ssm <= db[4];
+                            moveto_ifetch();
+                        end
+`ifdef SUPPORT_TASK
+             // Vector to the task only if it's not the one currently running. 
+             `LDW_TR70: begin
+                            b32 <= db;
+                            radr <= inc_adr(radr);
+                            load_what <= `LDW_TR158;
+                            if (DEAD_CYCLE) begin
+                                data_nack();
+                                next_state(LOAD_MAC1);
+                            end
+                            else begin
+                                data_read(inc_adr(radr),0);
+                                if (seg_fault_val==0)
+                                    next_state(LOAD_MAC2);
+                            end
+                        end
+             `LDW_TR158: begin
+                           radr <= inc_adr(radr);
+                           vpb <= FALSE;
+                           if ({db,b32[7:0]} != tr) begin
+                               set_task_regs(hwi ? 24'd0 : 24'd2);
+                               tr <= {db,b32[7:0]};
+                               back_link <= tr;
+                               tsk_pres <= 7'h20;
+                               state <= TSK1;
+`ifdef TASK_BL
+                               retstate <= IFETCH;
+`else                               
+                               store_what <= `STW_TR158;
+                               retstate <= STORE1;
+`endif
+                           end
+                           else begin
+                               next_state(IFETCH);
+                           end
+                        end
+`ifndef TASK_BL
+             `LDW_TR70S:
+                        begin
+                           tr[7:0] <= db;
+                           load_what <= `LDW_TR158S;
+                           inc_sp();
+                           if (DEAD_CYCLE) begin
+                               data_nack();
+                               next_state(LOAD_MAC1);
+                           end
+                           else begin
+                               data_read(fn_add_to_sp(32'd1),0);
+                                if (seg_fault_val==0)
+                                   state <= LOAD_MAC2;
+                           end
+                        end
+             `LDW_TR158S:
+                       begin
+                          tr[`TASK_MEM_ABIT:8] <= db;
+                          next_state(TSK1);
+                          retstate <= ssm ? SSM1 : IFETCH;
+                       end
+`endif
+`endif
+             `PC_70:        begin
+                            pc[7:0] <= db;
+                            load_what <= `PC_158;
+                            if (isRTI|isRTS|isRTL|isRTF) begin
+                                inc_sp();
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        state <= LOAD_MAC2;
+                                end
+                            end
+                            else begin    // JMP (abs)
+                                radr <= inc_adr(radr);
+                                state <= LOAD_MAC1;
+                            end
+                        end
+            `PC_158:    begin
+                            pc[15:8] <= db;
+                            if ((isRTI&(m816|m832))|isRTL|isRTF) begin
+                                load_what <= `PC_2316;
+                                inc_sp();
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        state <= LOAD_MAC2;
+                                end
+                            end
+                            else if (isRTS) begin   // rts instruction
+                                sdt_ra <= cs;
+                                next_state(RTS1);
+                            end
+                            else if (isJLInd) begin   // jmp (abs)
+                                load_what <= `PC_2316;
+                                seg <= ds_base;
+                                lmt <= ds_limit;
+                                mem_wr <= ds_wr;
+                                radr <= inc_adr(radr);
+                                state <= LOAD_MAC1;
+                            end
+                            else
+                            begin
+                                vpb <= `FALSE;
+                                next_state(IFETCH);
+                            end
+                        end
+            `PC_2316:    begin
+                            pc[23:16] <= db;
+                            if (isRTF|(isRTI&m832)) begin
+                                load_what <= `CS_70;
+                                inc_sp();
+                                if (DEAD_CYCLE) begin
+                                    data_nack();
+                                    next_state(LOAD_MAC1);
+                                end
+                                else begin
+                                    data_read(fn_add_to_sp(32'd1),0);
+                                    if (seg_fault_val==0)
+                                        next_state(LOAD_MAC2);
+                                end
+                            end
+                            else if (isRTL) begin
+                                load_what <= `NOTHING;
+                                sdt_ra <= cs;
+                                next_state(RTS1);
+                            end
+                            else begin
+                                load_what <= `NOTHING;
+                                next_state(IFETCH);
+                            end
+                        end
+`ifdef SUPPORT_SEG
+              `CS_70:   begin
+                              load_what <= `CS_158;
+                              inc_sp();
+                              cs[7:0] <= db;
+                              if (DEAD_CYCLE) begin
+                                  data_nack();
+                                  next_state(LOAD_MAC1);
+                              end
+                              else begin
+                                  data_read(fn_add_to_sp(32'd1),0);
+                                  if (seg_fault_val==0)
+                                      next_state(LOAD_MAC2);
+                              end
+                        end
+              `CS_158:   begin
+                            cs[15:8] <= db;
+                            sdt_ra <= {db,cs[7:0]};
+                            if (isRTF)
+                                next_state(RTS1);
+                            else
+                                next_state(JMF1);
+                        end
+`endif
+        //    `PC_3124:    begin
+        //                    pc[31:24] <= db;
+        //                    load_what <= `NOTHING;
+        //                    next_state(BYTE_IFETCH);
+        //                end
+            `IA_70:
+                    begin
+                        radr <= radr + 32'd1;
+                        if (DEAD_CYCLE) begin
+                            data_nack();
+                            next_state(LOAD_MAC1);
+                        end
+                        else begin
+                            data_read(radr + 32'd1,0);
+                            if (seg_fault_val==0)
+                                state <= LOAD_MAC2;
+                        end
+                        ia[7:0] <= db;
+                        load_what <= `IA_158;
+                    end
+            `IA_158:
+                    begin
+                        ia[15:8] <= db;
+                        ia[23:16] <= dbr;
+                        ia[31:24] <= 8'h00;
+                        if (isIY24|isI24|isIY32|isI32) begin
+                            radr <= radr + 32'd1;
+                            if (DEAD_CYCLE) begin
+                                data_nack();
+                                next_state(LOAD_MAC1);
+                            end
+                            else begin
+                                data_read(radr + 32'd1,0);
+                                if (seg_fault_val==0)
+                                    state <= LOAD_MAC2;
+                            end
+                            load_what <= `IA_2316;
+                        end
+                        else begin
+                            seg <= ds_base;
+                            lmt <= ds_limit;
+                            mem_wr <= ds_wr;
+                            state <= isIY ? BYTE_IY5 : BYTE_IX5;
+                        end
+                    end
+            `IA_2316:
+                    begin
+                        ia[23:16] <= db;
+                        ia[31:24] <= 8'h00;
+                        if (isI32|isIY32) begin
+                            load_what <= `IA_3124;
+                            radr <= radr + 32'd1;
+                            if (DEAD_CYCLE) begin
+                                data_nack();
+                                next_state(LOAD_MAC1);
+                            end
+                            else begin
+                                data_read(radr + 32'd1,0);
+                                if (seg_fault_val==0)
+                                    next_state(LOAD_MAC2);
+                            end
+                        end
+                        else begin
+                            seg <= ds_base;
+                            lmt <= ds_limit;
+                            mem_wr <= ds_wr;
+                            state <= isIY24 ? BYTE_IY5 : BYTE_IX5;
+                        end
+                    end
+            `IA_3124:
+                    begin
+                        ia[31:24] <= db;
+                        seg <= ds_base;
+                        lmt <= ds_limit;
+                        mem_wr <= ds_wr;
+                        state <= isIY32 ? BYTE_IY5 : BYTE_IX5;
+                    end
+            endcase
+        end
+        //endtask
+//        load_tsk(db,b16);
+    end
+`ifdef SUPPORT_BERR
+    else if (err_i) begin
+        mlb <= 1'b0;
+        data_nack();
+        derr_address <= ado;
+        intno <= 9'd508;
+        state <= BUS_ERROR;
+    end
+`endif
+RTS1:
+    begin
+        if (ir9==`RTL_IMM || ir9==`RTS_IMM || ir9==`RTF)
+            sp <= fn_add_to_sp(ir[15:8]);
+        inc_pc(24'd1);
+        cs_base <= base_o;
+        cs_limit <= fn_limit(size_o);
+        moveto_ifetch();
+    end
+BYTE_IX5:
+    begin
+        isI24 <= `FALSE;
+        isI32 <= `FALSE;
+        bank_wrap <= FALSE;
+        page_wrap <= FALSE;
+        seg <= ds_base;
+        lmt <= ds_limit;
+        mem_wr <= ds_wr;
+        radr <= ia;
+        load_what <= `LOAD_70;
+        state <= LOAD_MAC1;
+        if (!sop) begin
+            if (m32) s32 <= TRUE;
+            else if (m16) s16 <= TRUE;
+        end
+        if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I || ir[7:0]==`STA_IL) begin
+            wadr <= ia;
+            store_what <= `STW_ACC70;
+            state <= STORE1;
+        end
+        else if (ir[7:0]==`PEI) begin
+            set_sp();
+            seg <= ss_base;
+            lmt <= ss_limit;
+            store_what <= isI32 ? `STW_IA3124 : `STW_IA158;
+            state <= STORE1;
+        end
+    end
+BYTE_IY5:
+    begin
+        isIY <= `FALSE;
+        isIY24 <= `FALSE;
+        isIY32 <= `FALSE;
+        bank_wrap <= FALSE;
+        page_wrap <= FALSE;
+        seg <= ds_base;
+        lmt <= ds_limit;
+        mem_wr <= ds_wr;
+        radr <= iapy8;
+        wadr <= iapy8;
+        if (!sop) begin
+            if (m32) s32 <= TRUE;
+            else if (m16) s16 <= TRUE;
+        end
+        store_what <= `STW_ACC70;
+        load_what <= `LOAD_70;
+        $display("IY addr: %h", iapy8);
+        if (ir[7:0]==`STA_IY || ir[7:0]==`STA_IYL || ir[7:0]==`STA_DSPIY)
+            state <= STORE1;
+        else
+            state <= LOAD_MAC1;
+    end
+
+STORE1:
+	begin
+		case(store_what)
+`ifdef SUPPORT_SEG
+		`STW_CS158:     begin data_write(wadr,cs[15:8],0); mlb <= TRUE; end
+		`STW_CS70:      data_write(wadr,cs[7:0],0);
+        `STW_DS70:      begin data_write(wadr,ds[7:0],0); mlb <= 1'b1; end
+        `STW_DS158:     data_write(wadr,ds[15:8],0);
+`endif
+		`STW_PC2316:	begin data_write(wadr,pc[23:16],0); mlb <= 1'b1; end
+		`STW_PC158:		data_write(wadr,pc[15:8],0);
+		`STW_PC70:		data_write(wadr,pc[7:0],0);
+		`STW_SR70:		data_write(wadr,sr8,0);
+		`STW_SR158:		begin data_write(wadr,srx,1); mlb <= TRUE; end
+		`STW_DEF70:		begin data_write(wadr,wdat,0); mlb <= s16|s32; end
+		`STW_DEF158:    data_write(wadr,wdat[15:8],0);
+		`STW_DEF2316:   data_write(wadr,wdat[23:16],0);
+		`STW_DEF3124:   data_write(wadr,wdat[31:24],0);
+		`STW_ACC70:		begin data_write(wadr,acc,0); mlb <= s16|s32; end
+		`STW_ACC158:	data_write(wadr,acc[15:8],0);
+		`STW_ACC2316:	data_write(wadr,acc[23:16],0);
+		`STW_ACC3124:	data_write(wadr,acc[31:24],0);
+		`STW_X70:		begin data_write(wadr,x,0); mlb <= s16|s32; end
+		`STW_X158:		data_write(wadr,x[15:8],0);
+		`STW_X2316:		data_write(wadr,x[23:16],0);
+		`STW_X3124:		data_write(wadr,x[31:24],0);
+		`STW_Y70:		begin data_write(wadr,y,0); mlb <= s16|s32; end
+		`STW_Y158:		data_write(wadr,y[15:8],0);
+		`STW_Y2316:		data_write(wadr,y[23:16],0);
+		`STW_Y3124:		data_write(wadr,y[31:24],0);
+		`STW_Z70:		begin data_write(wadr,8'h00,0); mlb <= s16|s32; end
+		`STW_Z158:		data_write(wadr,8'h00,0);
+		`STW_Z2316:		data_write(wadr,8'h00,0);
+		`STW_Z3124:		data_write(wadr,8'h00,0);
+		`STW_DBR:       data_write(wadr,dbr,0);
+		`STW_DPR158:	begin data_write(wadr,dpr[15:8],0); mlb<= 1'b1; end
+		`STW_DPR70:		begin data_write(wadr,dpr[7:0],0); mlb <= 1'b1; end
+		`STW_TMP3124:	begin data_write(wadr,tmp32[31:24],0); mlb <= 1'b1; end
+		`STW_TMP2316:	begin data_write(wadr,tmp32[23:16],0); mlb <= 1'b1; end
+		`STW_TMP158:	begin data_write(wadr,tmp32[15:8],0); mlb <= 1'b1; end
+		`STW_TMP70:		data_write(wadr,tmp32[7:0],0);
+		`STW_IA3124:	begin data_write(wadr,ia[31:24],0); mlb <= 1'b1; end
+		`STW_IA2316:	data_write(wadr,ia[23:16],0);
+		`STW_IA158:		begin data_write(wadr,ia[15:8],0); mlb <= 1'b1; end
+		`STW_IA70:		data_write(wadr,ia,0);
+`ifdef SUPPORT_TASK
+        `STW_TR158:     begin data_write(wadr,otr[`TASK_MEM_ABIT:8],1); mlb <= 1'b1; end
+        `STW_TR70:      data_write(wadr,otr[7:0],0);
+		`STW_CPY_BUF:   begin data_write(wadr,cpybuf[cnt],0); mlb <= maxcnt > 8'd1; end
+`endif
+		default:	data_write(wadr,wdat,0);
+		endcase
+`ifdef SUPPORT_DCACHE
+		radr <= wadr;		// Do a cache read to test the hit
+`endif
+        if (seg_fault_val==0)
+    		state <= STORE2;
+	end
+	
+// Terminal state for stores. Update the data cache if there was a cache hit.
+// Clear any previously set lock status
+STORE2:
+	if (rdy) begin
+//		wdat <= dat_o;
+		mlb <= 1'b0;
+		data_nack();
+		if (!em && (isMove|isSts)) begin
+			state <= MVN816;
+			retstate <= MVN816;
+		end
+		else begin
+			if (em) begin
+				if (isMove) begin
+					state <= MVN816;
+					retstate <= MVN816;
+				end
+				else begin
+					moveto_ifetch();
+					retstate <= IFETCH;
+				end
+			end
+			else begin
+				moveto_ifetch();
+				retstate <= IFETCH;
+			end
+		end
+		case(store_what)
+		`STW_CPY_BUF:
+		    begin
+		        if (cnt > 0) begin
+		            mlb <= TRUE;
+		            cnt <= cnt - 8'd1;
+                    set_sp();
+                    if (DEAD_CYCLE) begin
+                        data_nack();
+                        next_state(STORE1);
+                    end
+                    else begin
+                        data_write(fn_get_sp(sp),cpybuf[cnt-8'd1],0);
+                        if (seg_fault_val==0)
+                            state <= STORE2;
+                    end
+		        end
+		        else begin
+`ifdef TASK_BL
+                    moveto_ifetch();
+`else
+		            if (tj_prefix)
+		               moveto_ifetch();
+		            else begin
+    		            store_what <= `STW_TR158;
+    		            set_sp();
+                        if (DEAD_CYCLE)
+                            next_state(STORE1);
+                        else begin
+                            data_write(fn_get_sp(sp),otr[`TASK_MEM_ABIT:8],0);
+                            if (seg_fault_val==0)
+                                next_state(STORE2);
+    		            end
+		            end
+`endif
+		        end
+		    end
+		`STW_DEF70:
+			begin
+				wadr <= inc_adr(wadr);
+				if (s16|s32) begin
+				    mlb <= TRUE;
+                    store_what <= `STW_DEF158;
+                    if (DEAD_CYCLE)
+                        next_state(STORE1);
+                    else begin
+		                data_write(inc_adr(wadr),wdat[15:8],0);
+                        if (seg_fault_val==0)
+                            next_state(STORE2);
+                    end
+                end
+			end
+		`STW_DEF158:
+			if (s32) begin
+			    mlb <= TRUE;
+				wadr <= inc_adr(wadr);
+				if (DEAD_CYCLE)
+				    next_state(STORE1);
+				else begin
+                    data_write(inc_adr(wadr),wdat[23:16],0);
+                    if (seg_fault_val==0)
+                        next_state(STORE2);
+                end
+				store_what <= `STW_DEF2316;
+			end
+		`STW_DEF2316:
+            begin
+			    mlb <= TRUE;
+				wadr <= inc_adr(wadr);
+				if (DEAD_CYCLE) begin
+                    data_nack();
+				    next_state(STORE1);
+				end
+				else begin
+	                data_write(inc_adr(wadr),wdat[31:24],0);
+                    if (seg_fault_val==0)
+                        next_state(STORE2);
+	            end
+                store_what <= `STW_DEF3124;
+            end
+        `STW_ACC70:
+            if (s16|s32) begin
+				wadr <= inc_adr(wadr);
+			    mlb <= TRUE;
+                store_what <= `STW_ACC158;
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+		            data_write(inc_adr(wadr),acc[15:8],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+            end
+        `STW_ACC158:
+            if (s32) begin
+                wadr <= inc_adr(wadr);
+			    mlb <= TRUE;
+                store_what <= `STW_ACC2316;
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+		            data_write(inc_adr(wadr),acc[23:16],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+            end
+        `STW_ACC2316:
+            begin
+                wadr <= inc_adr(wadr);
+			    mlb <= TRUE;
+                store_what <= `STW_ACC3124;
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+		            data_write(inc_adr(wadr),acc[31:24],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+            end
+		`STW_X70:
+		    begin
+    	        do_fill_inc(MVN816); 
+                if (s16|s32) begin
+                    mlb <= 1'b1;
+                    wadr <= inc_adr(wadr);
+                    if (DEAD_CYCLE) begin
+                        data_nack();
+                        next_state(STORE1);
+                    end
+                    else begin
+                        data_write(inc_adr(wadr),x[15:8],0);
+                        if (seg_fault_val==0)
+                            next_state(STORE2);
+                    end
+                    store_what <= `STW_X158;
+    			end
+			end
+		`STW_X158:
+		    begin
+                do_fill_inc(MVN816);
+                if (s32) begin
+                    mlb <= 1'b1;
+                    wadr <= inc_adr(wadr);
+                    if (DEAD_CYCLE) begin
+                        data_nack();
+                        next_state(STORE1);
+                    end
+                    else begin
+                        data_write(inc_adr(wadr),x[23:16],0);
+                        if (seg_fault_val==0)
+                            state <= STORE2;
+                    end
+                    store_what <= `STW_X2316;
+                end
+            end          
+            
+		`STW_X2316:
+            begin
+                do_fill_inc(MVN816);
+                mlb <= 1'b1;
+                wadr <= inc_adr(wadr);
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+		            data_write(inc_adr(wadr),x[31:24],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_X3124;
+            end
+        `STW_X3124:
+             do_fill_inc(MVN816);
+        
+		`STW_Y70:
+			if (s16|s32) begin
+				mlb <= 1'b1;
+				wadr <= inc_adr(wadr);
+				if (DEAD_CYCLE) begin
+                    data_nack();
+				    next_state(STORE1);
+				end
+				else begin
+                    data_write(inc_adr(wadr),y[15:8],0);
+                    if (seg_fault_val==0)
+    		  	   	   state <= STORE2;
+    		    end
+				store_what <= `STW_Y158;
+			end
+		`STW_Y158:
+            if (s32) begin
+                mlb <= 1'b1;
+                wadr <= inc_adr(wadr);
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(inc_adr(wadr),y[23:16],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_Y2316;
+            end
+		`STW_Y2316:
+            begin
+                mlb <= 1'b1;
+                wadr <= inc_adr(wadr);
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(inc_adr(wadr),y[31:24],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_Y3124;
+            end
+		`STW_Z70:
+			if (s16|s32) begin
+				mlb <= 1'b1;
+				wadr <= inc_adr(wadr);
+				if (DEAD_CYCLE) begin
+                    data_nack();
+				    next_state(STORE1);
+				end
+				else begin
+                    data_write(inc_adr(wadr),8'h00,0);
+                    if (seg_fault_val==0)
+			     	    state <= STORE2;
+				end
+				store_what <= `STW_Z158;
+			end
+		`STW_Z158:
+            if (s32) begin
+                mlb <= 1'b1;
+                wadr <= inc_adr(wadr);
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(inc_adr(wadr),8'h00,0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_Z2316;
+            end
+		`STW_Z2316:
+            begin
+                mlb <= 1'b1;
+                wadr <= inc_adr(wadr);
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(inc_adr(wadr),8'h00,0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_Z3124;
+            end
+		`STW_DPR70:
+			begin
+				mlb <= 1'b1;
+				wadr <= inc_adr(wadr);
+				store_what <= `STW_DPR158;
+				state <= STORE1;
+			end
+`ifdef SUPPORT_TASK
+`ifndef TASK_BL
+		`STW_TR158:
+            begin
+                mlb <= `TRUE;
+                set_sp();
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(fn_get_sp(sp),otr[7:0],0);
+                    if (seg_fault_val==0)
+                        next_state(STORE2);
+                end
+                store_what <= `STW_TR70;
+            end
+        `STW_TR70:
+            begin
+                moveto_ifetch();
+            end
+`endif
+`endif
+`ifdef SUPPORT_SEG
+		`STW_DS70:
+		    begin
+				mlb <= 1'b1;
+				wadr <= inc_adr(wadr);
+				if (DEAD_CYCLE) begin
+                    data_nack();
+				    next_state(STORE1);
+				end
+				else begin
+				    data_write(inc_adr(wadr),ds[15:8],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_DS158;
+		    end
+        `STW_CS158:
+            begin
+			    mlb <= TRUE;
+                set_sp();
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(fn_get_sp(sp),cs[7:0],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_CS70;
+            end
+        `STW_CS70:
+            if (ir9 != `PHCS) begin
+			    mlb <= TRUE;
+                set_sp();
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(fn_get_sp(sp),pc[23:16],0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+                store_what <= `STW_PC2316;
+            end
+`endif
+		`STW_TMP158:
+			begin
+				set_sp();
+				store_what <= `STW_TMP70;
+				state <= STORE1;
+			end
+		`STW_IA3124:
+            begin
+                set_sp();
+                store_what <= `STW_IA2316;
+                state <= STORE1;
+            end
+		`STW_IA2316:
+            begin
+                set_sp();
+                store_what <= `STW_IA158;
+                state <= STORE1;
+            end
+		`STW_IA158:
+			begin
+				set_sp();
+				store_what <= `STW_IA70;
+				state <= STORE1;
+			end
+        `STW_PC2316:
+			begin
+				if (ir9 != `PHK) begin
+    			    mlb <= TRUE;
+					set_sp();
+					if (DEAD_CYCLE) begin
+                        data_nack();
+		 			    next_state(STORE1);
+					end
+					else begin
+                        data_write(fn_get_sp(sp),pc[15:8],0);
+                        if (seg_fault_val==0)
+                            state <= STORE2;
+    			    end
+					store_what <= `STW_PC158;
+				end
+			end
+		`STW_PC158:
+			begin
+			    mlb <= TRUE;
+				set_sp();
+				if (DEAD_CYCLE) begin
+                    data_nack();
+				    next_state(STORE1);
+				end
+				else begin
+                    data_write(fn_get_sp(sp),pc[7:0],0);
+                    if (seg_fault_val==0)
+    		      		state <= STORE2;
+    		    end
+				store_what <= `STW_PC70;
+			end
+		`STW_PC70:
+			begin
+				case(ir9)
+				`BRK,`BRK2,`COP:
+						begin
+        			    mlb <= TRUE;
+						set_sp();
+						if (DEAD_CYCLE) begin
+                            data_nack();
+						    next_state(STORE1);
+						end
+						else begin
+                            data_write(fn_get_sp(sp),sr8,0);
+                            if (seg_fault_val==0)
+    				    		state <= STORE2;
+    				    end
+					    store_what <= `STW_SR70;
+						end
+				`JSR:
+				    	begin
+					    pc[15:0] <= ir[23:8];
+						end
+				`JSL:
+				    	begin
+                        pc[23:0] <= ir[31:8];
+						end
+			     `BSR:   pc[15:0] <= pc[15:0] + ir[23:8] + 16'd1;
+			     `BSL:   pc <= pc + ir[31:8] + 24'd1;
+`ifdef SUPPORT_SEG
+			    `JSF,`JCF:
+			            begin
+    		            pc <= ir[31:8];
+                        cs <= ir[47:32];
+                        sdt_ra <= ir[47:32];
+                        next_state(JMF1);
+		                end
+`endif
+				`JSR_INDX:
+						begin
+						state <= LOAD_MAC1;
+						load_what <= `PC_70;
+						seg <= ds_base;
+                        lmt <= ds_limit;
+                        mem_wr <= ds_wr;
+						radr <= absx_address;
+						bank_wrap <= FALSE;
+						page_wrap <= FALSE;
+						end
+				`JSL_XINDX:
+                        begin
+                        state <= LOAD_MAC1;
+                        load_what <= `PC_70;
+                        seg <= ds_base;
+                        lmt <= ds_limit;
+                        mem_wr <= ds_wr;
+                        radr <= xalx_address;
+						bank_wrap <= FALSE;
+                        page_wrap <= FALSE;
+                        end
+				endcase
+			end
+		`STW_SR158:
+		    begin
+		        store_what <= `STW_SR70;
+				set_sp();
+                if (DEAD_CYCLE) begin
+                    data_nack();
+                    next_state(STORE1);
+                end
+                else begin
+                    data_write(fn_get_sp(sp),sr8,0);
+                    if (seg_fault_val==0)
+                        state <= STORE2;
+                end
+		    end
+        `STW_SR70:
+			begin
+				if (ir[7:0]==`BRK) begin
+					load_what <= `PC_70;
+					seg <= 32'd0;
+                    lmt <= 32'hFFFF;
+                    mem_wr <= FALSE;
+					state <= LOAD_MAC1;
+					pc[23:16] <= 8'h00;//abs8[23:16];
+					radr <= vect;
+					vpb <= TRUE;
+//					data_read(vect);
+					im <= hwi;
+					df <= 1'b0;
+					bank_wrap <= FALSE;
+                    page_wrap <= FALSE;
+				end
+				else if (ir[7:0]==`COP) begin
+					load_what <= `PC_70;
+					seg <= 32'd0;
+					lmt <= 32'hFFFF;
+					mem_wr <= FALSE;
+					state <= LOAD_MAC1;
+					pc[23:16] <= 8'h00;//abs8[23:16];
+					radr <= vect;
+					vpb <= TRUE;
+//					data_read(vect);
+					im <= 1'b1;
+					bank_wrap <= FALSE;
+                    page_wrap <= FALSE;
+				end
+			end
+		default:
+			if (isJsrIndx) begin
+				load_what <= `PC_310;
+				state <= LOAD_MAC1;
+				seg <= ds_base;
+                lmt <= ds_limit;
+                mem_wr <= ds_wr;
+				radr <= ir[31:8] + x;
+				bank_wrap <= FALSE;
+                page_wrap <= FALSE;
+			end
+			else if (isJsrInd) begin
+				load_what <= `PC_310;
+				state <= LOAD_MAC1;
+				seg <= ds_base;
+                lmt <= ds_limit;
+                mem_wr <= ds_wr;
+				radr <= ir[31:8];
+				bank_wrap <= FALSE;
+                page_wrap <= FALSE;
+			end
+		endcase
+`ifdef SUPPORT_DCACHE
+		if (!dhit && write_allocate) begin
+			state <= DCACHE1;
+		end
+`endif
+	end
+`ifdef SUPPORT_BERR
+	else if (err_i) begin
+		mlb <= 1'b0;
+		data_nack();
+		derr_address <= ado[23:0];
+		intno <= 9'd508;
+		state <= BUS_ERROR;
+	end
+`endif
+
+CALC:
+	begin
+    	moveto_ifetch();
+        store_what <= `STW_DEF70;
+        // The following calculations are the same regardless of the size.
+        case(ir9)
+    	`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_XABS,`ADC_XABSX,`ADC_XABSY,
+        `ADC_IYL,`ADC_XIYL,`ADC_I,`ADC_IL,`ADC_XIL,`ADC_AL,`ADC_ALX,`ADC_DSP,`ADC_DSPIY,`ADC_XDSPIY:
+              begin res32 <= acc + b32 + {31'b0,cf}; a32 <= acc; end
+        `SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_XABS,`SBC_XABSX,`SBC_XABSY,
+        `SBC_IYL,`SBC_XIYL,`SBC_I,`SBC_IL,`SBC_XIL,`SBC_AL,`SBC_ALX,`SBC_DSP,`SBC_DSPIY,`SBC_XDSPIY:
+              begin res32 <= acc - b32 - {31'b0,~cf}; a32 <= acc; end
+        `CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_XABS,`CMP_XABSX,`CMP_XABSY,
+        `CMP_IYL,`CMP_XIYL,`CMP_I,`CMP_IL,`CMP_XIL,`CMP_AL,`CMP_ALX,`CMP_DSP,`CMP_DSPIY,`CMP_XDSPIY:
+              begin res32 <= acc - b32; a32 <= acc; end
+        `CPX_IMM,`CPX_ZP,`CPX_ABS,`CPX_XABS:    begin res32 <= x - b32; a32 <= x; end
+        `CPY_IMM,`CPY_ZP,`CPY_ABS,`CPY_XABS:    begin res32 <= y - b32; a32 <= y; end
+        `AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_XABS,`AND_XABSX,`AND_XABSY,
+        `AND_IYL,`AND_XIYL,`AND_I,`AND_IL,`AND_XIL,`AND_AL,`AND_ALX,`AND_DSP,`AND_DSPIY,`AND_XDSPIY:
+              begin res32 <= acc & b32; end
+        `ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_XABS,`ORA_XABSX,`ORA_XABSY,
+        `ORA_IYL,`ORA_XIYL,`ORA_I,`ORA_IL,`ORA_XIL,`ORA_AL,`ORA_ALX,`ORA_DSP,`ORA_DSPIY,`ORA_XDSPIY:
+              begin res32 <= acc | b32; end
+        `EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_XABS,`EOR_XABSX,`EOR_XABSY,
+        `EOR_IYL,`EOR_XIYL,`EOR_I,`EOR_IL,`EOR_XIL,`EOR_AL,`EOR_ALX,`EOR_DSP,`EOR_DSPIY,`EOR_XDSPIY:
+              begin res32 <= acc ^ b32; end
+        `LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_XABS,`LDA_XABSX,`LDA_XABSY,
+        `LDA_IYL,`LDA_XIYL,`LDA_I,`LDA_IL,`LDA_XIL,`LDA_AL,`LDA_ALX,`LDA_DSP,`LDA_DSPIY,`LDA_XDSPIY:
+              begin res32 <= b32; end
+        `BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX,`BIT_XABS,`BIT_XABSX:    begin res32 <= acc & b32; end
+        `LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`LDX_XABS,`LDX_XABSY:    begin res32 <= b32; end
+        `LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`LDY_XABS,`LDY_XABSX:    begin res32 <= b32; end
+        `TRB_ZP,`TRB_ABS,`TRB_XABS:    begin res32 <= acc & b32; wdat <= ~acc & b32; state <= STORE1; data_nack(); end
+        `TSB_ZP,`TSB_ABS,`TSB_XABS:    begin res32 <= acc & b32; wdat <= acc | b32; state <= STORE1; data_nack(); end
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX,`INC_XABS,`INC_XABSX:    begin res32 <= b32 + 32'd1; wdat <= b32+32'd1; state <= STORE1; data_nack(); end
+        `DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX,`DEC_XABS,`DEC_XABSX:    begin res32 <= b32 - 32'd1; wdat <= b32-32'd1; state <= STORE1; data_nack(); end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX,`ASL_XABS,`ASL_XABSX:    begin res32 <= {b32,1'b0}; wdat <= {b32[30:0],1'b0}; state <= STORE1; data_nack(); end
+        `ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX,`ROL_XABS,`ROL_XABSX:    begin res32 <= {b32,cf}; wdat <= {b32[30:0],cf}; state <= STORE1; data_nack(); end
+		`INC_IMM:   begin res32 <= b32 + {{24{ir[23]}},ir[23:16]}; wdat <= {{24{ir[23]}},ir[23:16]}; state <= STORE1; data_nack(); end
+        default: begin
+			// The following calculations depend on the operand size.
+			if ((sop && mxb16) || (!sop && s16)) begin
+				case(ir9)
+				`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX,`LSR_XABS,`LSR_XABSX:    begin res32 <= {b32[0],17'b0,b32[15:1]}; wdat <= {17'b0,b32[15:1]}; state <= STORE1; data_nack(); end
+				`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX,`ROR_XABS,`ROR_XABSX:    begin res32 <= {b32[0],16'b0,cf,b32[15:1]}; wdat <= {16'h0,cf,b32[15:1]}; state <= STORE1; data_nack(); end
+				default: res32 <= 32'hDEADDEAD;
+				endcase
+			end
+			else if ((sop && mxb32) || (!sop && s32)) begin
+				case(ir9)
+				`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX,`LSR_XABS,`LSR_XABSX:    begin res32 <= {b32[0],1'b0,b32[31:1]}; wdat <= {1'b0,b32[31:1]}; state <= STORE1; data_nack(); end
+				`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX,`ROR_XABS,`ROR_XABSX:    begin res32 <= {b32[0],cf,b32[31:1]}; wdat <= {cf,b32[31:1]}; state <= STORE1; data_nack(); end
+				default: res32 <= 32'hDEADDEAD;
+				endcase
+			end
+			else begin
+				case(ir9)
+				`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX,`LSR_XABS,`LSR_XABSX:    begin res32 <= {b32[0],25'b0,b8[7:1]}; wdat <= {25'b0,b8[7:1]}; state <= STORE1; data_nack(); end
+				`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX,`ROR_XABS,`ROR_XABSX:    begin res32 <= {b32[0],24'b0,cf,b8[7:1]}; wdat <= {24'b0,cf,b8[7:1]}; state <= STORE1; data_nack(); end
+				default: res32 <= 32'hDEADDEAD;
+				endcase
+			end
+		end
+		endcase
+	end
+
+MVN816:
+	begin
+		moveto_ifetch();
+		if (m832) begin
+            if (&acc) begin
+                pc <= npc;
+            end
+		end
+		else begin
+            if (&acc[15:0]) begin
+                pc <= npc;
+                dbr <= mvndst_bank;
+            end
+		end
+	end
+SSM1:
+    begin
+        set_task_regs(24'd0);
+        otr <= tr;
+        back_link <= tr; 
+        tr <= 16'd3;        // single step task
+        tsk_pres <= 7'h2C;
+        acc <= tr;
+        x <= pc;
+`ifndef TASK_BL
+        seg <= ss_base;
+        lmt <= ss_limit;
+        mem_wr <= ss_wr;
+        store_what <= `STW_TR158;
+        retstate <= STORE1; // Do not switch on SSM here
+`else
+        retstate <= IFETCH; 
+`endif
+        next_state(TSK1);
+    end
+
+ICACHE1:
+    begin
+        rwo <= TRUE;
+        inv_icache <= FALSE;
+        inv_iline <= FALSE;
+        if (!hit0) begin
+            prc_hit0 <= TRUE;
+            vpa <= TRUE;
+            vda <= TRUE;
+            ado <= {cspc[31:4],4'h0};
+            wr_icache <= TRUE; 
+            cnt <= 8'h0;
+            next_state(ICACHE2);
+        end
+        else if (!hit1) begin
+            prc_hit1 <= TRUE;
+            vpa <= TRUE;
+            vda <= TRUE;
+            ado <= {cspc[31:4]+28'd1,4'h0};
+            wr_icache <= TRUE; 
+            cnt <= 8'h0;
+            next_state(ICACHE2);
+        end
+        else
+            next_state(IFETCH);
+    end
+ICACHE2:
+    if (rdy) begin
+        ado1 <= ado;
+        vda <= FALSE;
+        if (DEAD_CYCLE) begin
+            vpa <= FALSE;
+            ado <= 32'd0;
+            next_state(ICACHE3);
+        end
+        else
+            ado <= {ado[31:4],cnt[3:0]+4'd1};
+        if (cnt[3:0] == 4'hE)
+            wr_itag <= TRUE;
+        if (cnt[3:0] == 4'hF) begin
+            vpa <= FALSE;
+            ado <= 32'd0;
+            if ((hit1|prc_hit1)&hit0) begin
+                next_state(IFETCH);
+            end
+            else
+                next_state(ICACHE1);
+            wr_icache <= FALSE;
+        end
+        cnt <= cnt + 4'd1;
+    end
+ICACHE3:
+    begin
+        vpa <= TRUE;
+        ado <= {ado1[31:4],cnt[3:0]};
+        next_state(ICACHE2);
+    end
+ 
+endcase
+end
+
+task data_read;
+input [31:0] adr;
+input first;
+begin
+    if (adr > lmt)
+        seg_fault(SEGF_BOUND);
+    else begin
+        vpa <= `FALSE;
+        vda <= `TRUE;
+        rwo <= `TRUE;
+        ado <= seg + adr;
+	end
+end
+endtask
+
+task data_write;
+input [31:0] adr;
+input [7:0] dat;
+input first;
+begin
+    if (adr > lmt)
+        seg_fault(SEGF_BOUND);
+    else if (mem_wr) begin
+        vpa <= `FALSE;
+        vda <= `TRUE;
+        rwo <= `FALSE;
+        ado <= seg + adr;
+        dbo <= dat;
+	end
+	else
+	    seg_fault(SEGF_WRITE);
+end
+endtask
+
+task data_nack;
+begin
+	vpa <= `FALSE;
+	vda <= `FALSE;
+	rwo <= `TRUE;
+//	ado <= 32'h000000;
+//	dbo <= 8'h00;
+end
+endtask
+
+task set_task_regs;
+input [23:0] amt;
+begin
+    tskm_we <= TRUE;
+    tskm_wr <= TRUE;
+    tskm_wa <= tr;
+`ifdef SUPPORT_SEG
+    cs_i <= cs;
+    ds_i <= ds;
+    ss_i <= ss;
+`else
+    cs_i <= 16'd0;
+    ds_i <= 16'd0;
+    ss_i <= 16'd0;
+`endif
+    if (PC24)
+        pc_i <= pc + amt;
+    else
+        pc_i <= {pc[23:16],pc[15:0] + amt[15:0]};
+    acc_i <= acc;
+    x_i <= x;
+    y_i <= y;
+    sp_i <= sp;
+    sr_i <= sr8;
+    srx_i <= {3'b0,ssm,1'b0,mib,m832,m816};
+    dbr_i <= dbr;
+    dpr_i <= dpr;
+    bl_i <= back_link;
+end
+endtask
+
+task do_fill_inc;
+input [5:0] ns;
+begin
+    if (ir9==`FILL) begin
+        if (m832)
+            acc <= acc_dec;
+        else
+            acc[15:0] <= acc_dec[15:0];
+        if (xb32)
+            y <= y_inc;
+        else if (xb16)
+            y <= {16'h0000,y_inc[15:0]};
+        else
+            y <= {24'h0000,y_inc[7:0]};
+        next_state(ns);
+    end
+end
+endtask
+
+`include "FT832misc_task.v"
+
+task next_state;
+input [5:0] nxt;
+begin
+	state <= nxt;
+end
+endtask
+
+task inc_pc;
+input [23:0] amt;
+begin
+if (PC24)
+    pc <= pc + amt;
+else
+    pc[15:0] <= pc[15:0] + amt[15:0];
+end
+endtask
+
+task seg_fault;
+input [7:0] fault_num;
+begin
+    ir[7:0] <= `BRK;
+    hwi <= `TRUE;
+    if (m832)
+        vect <= `IRQ_VECT_832;
+    else if (m816)
+        vect <= `IRQ_VECT_816;
+    else
+        vect <= `BYTE_IRQ_VECT;
+    seg <= 32'd0;
+    next_state(DECODE);
+    seg_fault_val = fault_num;
+end
+endtask
+
+function [127:0] fnStateName;
+input [5:0] state;
+case(state)
+RESET1:	fnStateName = "RESET1     ";
+IFETCH:	fnStateName = "IFETCH     ";
+STORE1:	fnStateName = "STORE1     ";
+STORE2:	fnStateName = "STORE2     ";
+RTS1:	fnStateName = "RTS1       ";
+IY3:	fnStateName = "IY3        ";
+BYTE_IX5:	fnStateName = "BYTE_IX5   ";
+BYTE_IY5:	fnStateName = "BYTE_IY5   ";
+DECODE:	fnStateName = "DECODE    ";
+CALC:	fnStateName = "CALC      ";
+BUS_ERROR:	fnStateName = "BUS_ERROR  ";
+LOAD_MAC1:	fnStateName = "LOAD_MAC1  ";
+LOAD_MAC2:	fnStateName = "LOAD_MAC2  ";
+LOAD_MAC3:	fnStateName = "LOAD_MAC3  ";
+LOAD_DCACHE:	fnStateName = "LOAD_DCACHE";
+LOAD_ICACHE:	fnStateName = "LOAD_ICACHE";
+LOAD_IBUF1:		fnStateName = "LOAD_IBUF1 ";
+LOAD_IBUF2:		fnStateName = "LOAD_IBUF2 ";
+LOAD_IBUF3:		fnStateName = "LOAD_IBUF3 ";
+ICACHE1:		fnStateName = "ICACHE1    ";
+ICACHE2:		fnStateName = "ICACHE2    ";
+ICACHE3:		fnStateName = "ICACHE3    ";
+IBUF1:			fnStateName = "IBUF1      ";
+DCACHE1:		fnStateName = "DCACHE1    ";
+MVN816:			fnStateName = "MVN816     ";
+TSK1:           fnStateName = "TSK1       ";
+LDT1:           fnStateName = "LDT1       ";
+INF1:           fnStateName = "INF1       ";
+SSM1:           fnStateName = "SSM1       ";
+default:		fnStateName = "UNKNOWN    ";
+endcase
+endfunction
+
+endmodule
+
+
+// ============================================================================
+// Cache Memories
+// ============================================================================
+module ft832_icachemem(wclk, wce, wr, wa, i, rclk, rce, pc, insn);
+input wclk;
+input wce;
+input wr;
+input [7:0] i;
+input rclk;
+input rce;
+output [127:0] insn;
+reg [127:0] insn;
+
+`ifdef ICACHE_4K
+input [11:0] wa;
+input [11:0] pc;
+reg [127:0] mem [0:255];
+reg [11:0] rpc,rpcp16;
+wire [127:0] insn0 = mem[rpc[11:4]];
+wire [127:0] insn1 = mem[rpcp16[11:4]];
+`elsif ICACHE_16K
+input [13:0] wa;
+input [13:0] pc;
+reg [127:0] mem [0:1023];
+reg [13:0] rpc,rpcp16;
+wire [127:0] insn0 = mem[rpc[13:4]];
+wire [127:0] insn1 = mem[rpcp16[13:4]];
+`endif
+
+genvar g;
+generate
+begin : wstrobes
+for (g = 0; g < 16; g = g + 1)
+always @(posedge wclk)
+`ifdef ICACHE_4K
+	if (wce & wr && wa[3:0]==g) mem[wa[11:4]][g*8+7:g*8] <= i;
+`elsif ICACHE_16K
+	if (wce & wr && wa[3:0]==g) mem[wa[13:4]][g*8+7:g*8] <= i;
+`endif
+end
+endgenerate
+
+always @(posedge rclk)
+	if (rce) rpc <= pc;
+always @(posedge rclk)
+	if (rce) rpcp16 <= pc + 16'd16;
+always @(insn0 or insn1 or rpc)
+case(rpc[3:0])
+4'h0:	insn <= insn0;
+4'h1:	insn <= {insn1[7:0],insn0[127:8]};
+4'h2:	insn <= {insn1[15:0],insn0[127:16]};
+4'h3:	insn <= {insn1[23:0],insn0[127:24]};
+4'h4:	insn <= {insn1[31:0],insn0[127:32]};
+4'h5:	insn <= {insn1[39:0],insn0[127:40]};
+4'h6:	insn <= {insn1[47:0],insn0[127:48]};
+4'h7:	insn <= {insn1[55:0],insn0[127:56]};
+4'h8:	insn <= {insn1[63:0],insn0[127:64]};
+4'h9:	insn <= {insn1[71:0],insn0[127:72]};
+4'hA:	insn <= {insn1[79:0],insn0[127:80]};
+4'hB:	insn <= {insn1[87:0],insn0[127:88]};
+4'hC:	insn <= {insn1[95:0],insn0[127:96]};
+4'hD:	insn <= {insn1[103:0],insn0[127:104]};
+4'hE:	insn <= {insn1[111:0],insn0[127:112]};
+4'hF:	insn <= {insn1[119:0],insn0[127:120]};
+endcase
+
+endmodule
+
+module ft832_itagmem(wclk, wce, wr, wa, invalidate, invalidate_line, rclk, rce, pc, hit0, hit1);
+input wclk;
+input wce;
+input wr;
+input [31:0] wa;
+input invalidate;
+input invalidate_line;
+input rclk;
+input rce;
+input [31:0] pc;
+output hit0;
+output hit1;
+
+`ifdef ICACHE_4K
+wire [20:0] tag0,tag1;
+reg [31:12] mem [0:255];
+reg [0:255] tvalid;
+`elsif ICACHE_16K
+wire [18:0] tag0,tag1;
+reg [31:14] mem [0:1023];
+reg [0:1023] tvalid;
+`endif
+reg [31:0] rpc,rpcp16;
+
+always @(posedge rclk)
+	if (rce) rpc <= pc;
+always @(posedge rclk)
+	if (rce) rpcp16 <= pc + 32'd16;
+
+`ifdef ICACHE_4K
+always @(posedge wclk)
+	if (wce & wr) mem[wa[11:4]] <= wa[31:12];
+always @(posedge wclk)
+        if (invalidate) tvalid <= 256'd0;
+        else if (invalidate_line) tvalid[wa[11:4]] <= 1'b0;
+        else if (wce & wr) tvalid[wa[11:4]] <= 1'b1;
+assign tag0 = {mem[rpc[11:4]],tvalid[rpc[11:4]]};
+assign tag1 = {mem[rpcp16[11:4]],tvalid[rpcp16[11:4]]};
+
+assign hit0 = tag0 == {rpc[31:12],1'b1};
+assign hit1 = tag1 == {rpcp16[31:12],1'b1};
+
+`elsif ICACHE_16K
+always @(posedge wclk)
+	if (wce & wr) mem[wa[13:4]] <= wa[31:14];
+always @(posedge wclk)
+        if (invalidate) tvalid <= 1024'd0;
+        else if (invalidate_line) tvalid[wa[13:4]] <= 1'b0;
+        else if (wce & wr) tvalid[wa[13:4]] <= 1'b1;
+assign tag0 = {mem[rpc[13:4]],tvalid[rpc[13:4]]};
+assign tag1 = {mem[rpcp16[13:4]],tvalid[rpcp16[13:4]]};
+
+assign hit0 = tag0 == {rpc[31:14],1'b1};
+assign hit1 = tag1 == {rpcp16[31:14],1'b1};
+`endif
+
+endmodule
+
+module task_mem(wclk, wce, wr, wa,
+    cs_i, ds_i, ss_i, pc_i, acc_i, x_i, y_i, sp_i, sr_i, srx_i, db_i, dpr_i, bl_i,
+    rclk, rce, ra,
+    cs_o, ds_o, ss_o, pc_o, acc_o, x_o, y_o, sp_o, sr_o, srx_o, db_o, dpr_o, bl_o
+);
+input wclk;
+input wce;
+input wr;
+input [`TASK_MEM_ABIT:0] wa;
+input [15:0] cs_i;
+input [15:0] ds_i;
+input [15:0] ss_i;
+input [23:0] pc_i;
+input [31:0] acc_i;
+input [31:0] x_i;
+input [31:0] y_i;
+input [31:0] sp_i;
+input [7:0] sr_i;
+input [7:0] srx_i;
+input [7:0] db_i;
+input [15:0] dpr_i;
+input [`TASK_MEM_ABIT:0] bl_i;
+input rclk;
+input rce;
+input [`TASK_MEM_ABIT:0] ra;
+output [15:0] cs_o;
+output [15:0] ds_o;
+output [15:0] ss_o;
+output [23:0] pc_o;
+output [31:0] acc_o;
+output [31:0] x_o;
+output [31:0] y_o;
+output [31:0] sp_o;
+output [7:0] sr_o;
+output [7:0] srx_o;
+output [7:0] db_o;
+output [15:0] dpr_o;
+output [`TASK_MEM_ABIT:0] bl_o;
+reg [`TASK_MEM_ABIT+240:0] mem [`TASK_MEM-1:0];
+always @(posedge wclk)
+    if (wce & wr)
+        mem[wa] <= {bl_i,cs_i,ds_i,ss_i,pc_i,acc_i,x_i,y_i,sp_i,sr_i,srx_i,db_i,dpr_i};
+wire [`TASK_MEM_ABIT+240:0] memo;
+reg [`TASK_MEM_ABIT:0] rra;
+always @(posedge rclk)
+    rra <= ra;
+assign memo = mem[rra];
+assign dpr_o = memo[15:0];
+assign db_o = memo[23:16];
+assign srx_o = memo[31:24];
+assign sr_o = memo[39:32];
+assign sp_o = memo[71:40];
+assign y_o = memo[103:72];
+assign x_o = memo[135:104];
+assign acc_o = memo[167:136];
+assign pc_o = memo[191:168];
+assign ss_o = memo[207:192];
+assign ds_o = memo[223:208];
+assign cs_o = memo[239:224];
+assign bl_o = memo[`TASK_MEM_ABIT+240:240];
+
+endmodule
+
+module SegDescTbl(wclk, wce, wr, wa, acr_i, size_i, base_i, rclk, rce, ra, acr_o, size_o, base_o);
+input wclk;
+input wce;
+input wr;
+input [11:0] wa; 
+input [7:0] acr_i;
+input [3:0] size_i;
+input [31:0] base_i;
+input rclk;
+input rce;
+input [11:0] ra;
+output [7:0] acr_o;
+output [3:0] size_o;
+output [31:0] base_o;
+
+reg [43:0] mem [4095:0];
+reg [11:0] rra;
+always @(posedge wclk)
+    if (wce & wr) mem[wa] <= {acr_i,size_i,base_i};
+always @(posedge rclk)
+    rra <= ra;
+assign acr_o = mem[rra][43:36];
+assign size_o = mem[rra][35:32];
+assign base_o = mem[rra][31:0];
+
+endmodule
Index: ultimate_cart/veronica/FT832misc_task.v
===================================================================
--- ultimate_cart/veronica/FT832misc_task.v	(nonexistent)
+++ ultimate_cart/veronica/FT832misc_task.v	(revision 438)
@@ -0,0 +1,187 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2015  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+function [31:0] fn_get_sp;
+input [31:0] sp;
+begin
+    if (m832)
+        fn_get_sp = {4'd0,sp};
+    else if (m816)
+        fn_get_sp = {stack_bank,sp[15:0]};
+    else
+        fn_get_sp = {stack_page,sp[7:0]};
+end
+endfunction
+
+function [31:0] fn_add_to_sp;
+input [31:0] amt;
+begin
+    if (m832)
+        fn_add_to_sp = sp + amt;
+    else if (m816)
+        fn_add_to_sp = {stack_bank,sp[15:0] + amt[15:0]};
+    else
+        fn_add_to_sp = {stack_page,sp[7:0] + amt[7:0]};
+end
+endfunction
+
+function [31:0] fn_limit;
+input [3:0] size;
+begin
+    case(size)
+    4'd0:   fn_limit = 32'd0;
+    4'd1:   fn_limit = 32'd255;
+    4'd2:   fn_limit = 32'd1023;
+    4'd3:   fn_limit = 32'd4095;
+    4'd4:   fn_limit = 32'd16383;
+    4'd5:   fn_limit = 32'd65535;
+    4'd6:   fn_limit = 32'd262143;
+    4'd7:   fn_limit = 32'd1048575;
+    4'd8:   fn_limit = 32'd4194303;
+    4'd9:   fn_limit = 32'd16777215;
+    4'd10:  fn_limit = 32'd67108863;
+    4'd11:  fn_limit = 32'd268435454;
+    4'd12:  fn_limit = 32'd1073741823;
+    4'd13:  fn_limit = 32'd4294967295;   // one less
+    default:    fn_limit = 32'd4095;
+    endcase 
+end
+endfunction
+
+task set_sp;
+begin
+    radr <= fn_get_sp(sp);
+    wadr <= fn_get_sp(sp);
+    sp <= fn_add_to_sp(32'hFFFFFFFF);
+	if (m816)
+        bank_wrap <= TRUE;
+	else if (!m832)
+        page_wrap <= TRUE;
+end
+endtask
+
+task inc_sp;
+begin
+    radr <= fn_add_to_sp(32'd1);
+    sp <= fn_add_to_sp(32'd1);
+    if (m816)
+        bank_wrap <= TRUE;
+    else if (!m832)
+        page_wrap <= TRUE;
+end
+endtask
+
+function [31:0] fn_sp_inc;
+input [31:0] sp_inc;
+begin
+    fn_sp_inc = fn_add_to_sp(32'd1);
+end
+endfunction
+
+task tsk_push;
+input [5:0] SW8;
+input szFlg;
+input szFlg2;
+begin
+    if (m832) begin
+		if (szFlg2) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFD);
+		    wadr <= fn_add_to_sp(32'hFFFFFFFD);
+			sp <= fn_add_to_sp(32'hFFFFFFFC);
+			store_what <= SW8;
+			s32 <= TRUE;
+		end
+		else if (szFlg) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFF);
+            wadr <= fn_add_to_sp(32'hFFFFFFFF);
+            sp <= fn_add_to_sp(32'hFFFFFFFE);
+			s16 <= TRUE;
+			store_what <= SW8;
+		end
+		else begin
+			radr <= sp;
+			wadr <= sp;
+			store_what <= SW8;
+			sp <= fn_add_to_sp(32'hFFFFFFFF);
+		end
+    end
+	else if (m816) begin
+		if (szFlg2) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFD);
+            wadr <= fn_add_to_sp(32'hFFFFFFFD);
+            sp <= fn_add_to_sp(32'hFFFFFFFC);
+            store_what <= SW8;
+            s32 <= TRUE;
+        end
+		else if (szFlg) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFF);
+            wadr <= fn_add_to_sp(32'hFFFFFFFF);
+            sp <= fn_add_to_sp(32'hFFFFFFFE);
+			s16 <= TRUE;
+			store_what <= SW8;
+		end
+		else begin
+			radr <= {stack_bank,sp[15:0]};
+			wadr <= {stack_bank,sp[15:0]};
+			store_what <= SW8;
+			sp <= fn_add_to_sp(32'hFFFFFFFF);;
+		end
+        bank_wrap <= TRUE;
+	end
+	else begin
+	    // We could be pushing the CS or DS from
+	    // emulation mode.
+		if (szFlg2) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFD);
+            wadr <= fn_add_to_sp(32'hFFFFFFFD);
+            sp <= fn_add_to_sp(32'hFFFFFFFC);
+            store_what <= SW8;
+            s32 <= TRUE;
+        end
+		else if (szFlg) begin
+		    radr <= fn_add_to_sp(32'hFFFFFFFF);
+            wadr <= fn_add_to_sp(32'hFFFFFFFF);
+            sp <= fn_add_to_sp(32'hFFFFFFFE);
+            s16 <= TRUE;
+            store_what <= SW8;
+        end
+        else begin
+            radr <= {stack_page,sp[7:0]};
+            wadr <= {stack_page,sp[7:0]};
+            store_what <= SW8;
+            sp <= fn_add_to_sp(32'hFFFFFFFF);
+        end
+        page_wrap <= TRUE;
+	end
+	data_nack();
+	seg <= ss_base;
+	lmt <= ss_limit;
+	state <= STORE1;
+end
+endtask
+
+task moveto_ifetch;
+begin
+	next_state(ssm ? SSM1 : IFETCH);
+end
+endtask
+
Index: ultimate_cart/veronica/FT832mpu.v
===================================================================
--- ultimate_cart/veronica/FT832mpu.v	(nonexistent)
+++ ultimate_cart/veronica/FT832mpu.v	(revision 438)
@@ -0,0 +1,330 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2015  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// FT832mpu.v
+//  - 16 bit CPU
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+`define TRUE 	1'b1
+`define FALSE	1'b0
+
+module FT832mpu(rst, clk, clko, phi11, phi12, phi81, phi82, rdy, e, mx, nmi, irq, abort, be, vpa, vda, mlb, vpb,
+    rw, ad, db, cs0, cs1, cs2, cs3, cs4, cs5, cs6, ct0, ct1, ct2);
+parameter pIOAddress = 32'h0000B000;
+parameter pZPAddress = 32'h00000010;
+input rst;
+input clk;
+output clko;
+output phi11;
+output phi12;
+output phi81;
+output phi82;
+input rdy;
+output e;
+output mx;
+input nmi;
+input irq;
+input abort;
+input be;
+output vpa;
+output vda;
+output mlb;
+output vpb;
+output tri rw;
+output tri [31:0] ad;
+inout tri [7:0] db;
+output cs0;
+output cs1;
+output cs2;
+output cs3;
+output cs4;
+output cs5;
+output cs6;
+input ct0;
+input ct1;
+input ct2;
+
+wire ivda;
+wire [4:0] cycle;
+reg [15:0] dec_cs0;
+reg [15:0] dec_cs1;
+reg [15:0] dec_cs2;
+reg [15:0] dec_cs3;
+reg [8:0] dec_cs4;
+reg [8:0] dec_cs5;
+reg [7:0] mh1, mh8, mh32;
+reg isRegEnabled;
+reg cntIrq0,cntIrqEn0;
+reg cntIrq1,cntIrqEn1;
+reg cntIrq2,cntIrqEn2;
+reg cntUp0,cntUp1,cntUp2;
+reg [23:0] cntLimit0;
+reg [23:0] realCnt0;
+reg autoCnt0,cntTrig0;
+reg [23:0] cntLimit1;
+reg [23:0] realCnt1;
+reg autoCnt1,cntTrig1;
+reg [23:0] cntLimit2;
+reg [23:0] realCnt2;
+reg autoCnt2,cntTrig2;
+reg [1:0] cntSrc0,cntSrc1,cntSrc2;
+reg [7:0] zp_shadow [15:0];
+
+reg phi1d;
+always @(posedge clko)
+	phi1d <= phi11;
+
+wire match_cs0 = ad[31:8]==dec_cs0;
+wire match_cs1 = ad[31:8]==dec_cs1;
+wire match_cs2 = ad[31:8]==dec_cs2;
+wire match_cs3 = ad[31:8]==dec_cs3;
+wire match_cs4 = ad[31:15]==dec_cs4;
+wire match_cs5 = ad[31:15]==dec_cs5;
+
+wire dec_match1 = (match_cs0 & mh1[0]) |
+				  (match_cs1 & mh1[1]) |
+				  (match_cs2 & mh1[2]) |
+				  (match_cs3 & mh1[3]) |
+				  (match_cs4 & mh1[4]) |
+				  (match_cs5 & mh1[5])
+				  ;
+wire dec_match8 = (match_cs0 & mh8[0]) |
+				  (match_cs1 & mh8[1]) |
+				  (match_cs2 & mh8[2]) |
+				  (match_cs3 & mh8[3]) |
+				  (match_cs4 & mh8[4]) |
+				  (match_cs5 & mh8[5])
+				  ;
+wire dec_match32 = (match_cs0 & mh32[0]) |
+				  (match_cs1 & mh32[1]) |
+				  (match_cs2 & mh32[2]) |
+				  (match_cs3 & mh32[3]) |
+				  (match_cs4 & mh32[4]) |
+				  (match_cs5 & mh32[5])
+				  ;
+
+
+wire iirq = !((cntIrqEn0 & cntIrq0) || 
+			(cntIrqEn1 & cntIrq1) || 
+			(cntIrqEn2 & cntIrq2)) &&
+			irq
+			;
+
+reg [7:0] shadow_ram [31:0];
+
+always @(posedge clko)
+if (~rst) begin
+	isRegEnabled <= `TRUE;
+	dec_cs0 <= 16'h00D0;
+	dec_cs1 <= 16'h00D1;
+	dec_cs2 <= 16'h00D2;
+	dec_cs3 <= 16'h00D3;
+	dec_cs4 <= 9'h001;
+	dec_cs5 <= 9'h002;
+	mh1 <= 8'h0F;
+	mh8 <= 8'h30;
+	mh32 <= 8'h00;
+	cntIrqEn0 <= 1'b0;
+	cntIrqEn1 <= 1'b0;
+	cntIrqEn2 <= 1'b0;
+	cntIrq0 <= 1'b0;
+	cntIrq1 <= 1'b0;
+	cntIrq2 <= 1'b0;
+	cntSrc0 <= 2'b00;
+	cntSrc1 <= 2'b00;
+	cntSrc2 <= 2'b00;
+	cntTrig0 <= 1'b0;
+	cntTrig1 <= 1'b0;
+	cntTrig2 <= 1'b0;
+	cntUp0 <= 1'b1;
+	cntUp1 <= 1'b1;
+	cntUp2 <= 1'b1;
+end
+else begin
+	cntTrig0 <= 1'b0;
+	cntTrig1 <= 1'b0;
+	cntTrig2 <= 1'b0;
+	if (cntSrc0==2'b01 || cntTrig0 || (cntSrc0==2'b10 && ct0))
+		realCnt0 <= cntUp0 ? realCnt0 + 24'd1 : realCnt0 - 24'd1;
+	if (cntSrc1==2'b01 || cntTrig1 || (cntSrc1==2'b10 && ct1))
+		realCnt1 <= cntUp1 ? realCnt1 + 24'd1 : realCnt1 - 24'd1;
+	if (cntSrc2==2'b01 || cntTrig2 || (cntSrc2==2'b10 && ct2))
+		realCnt2 <= cntUp2 ? realCnt2 + 24'd1 : realCnt2 - 24'd1;
+	if (((cntUp0 && realCnt0==cntLimit0) || (!cntUp0 && realCnt0==24'd0)) && cntIrqEn0)
+		cntIrq0 <= 1'b1;
+	if (((cntUp0 && realCnt0==cntLimit0) || (!cntUp0 && realCnt0==24'd0)))
+		realCnt0 <= cntUp0 ? 24'd0 : cntLimit0;
+	if (((cntUp1 && realCnt1==cntLimit1) || (!cntUp1 && realCnt1==24'd0)) && cntIrqEn1)
+		cntIrq1 <= 1'b1;
+	if (((cntUp1 && realCnt1==cntLimit1) || (!cntUp1 && realCnt1==24'd0)))
+		realCnt1 <= cntUp1 ? 24'd0 : cntLimit1;
+	if (((cntUp2 && realCnt2==cntLimit2) || (!cntUp2 && realCnt2==24'd0)) && cntIrqEn2)
+		cntIrq2 <= 1'b1;
+	if (((cntUp2 && realCnt2==cntLimit2) || (!cntUp2 && realCnt2==24'd0)))
+		realCnt2 <= cntUp2 ? 24'd0 : cntLimit2;
+	if (ivda && ad[31:8]==pIOAddress[31:8] && isRegEnabled && ~rw) begin
+		shadow_ram[ad[4:0]] <= db;
+		case(ad[4:0])
+		5'h00:	dec_cs0[7:0] <= db;
+		5'h01:	dec_cs0[15:8] <= db;
+		5'h02:	dec_cs1[7:0] <= db;
+		5'h03:	dec_cs1[15:8] <= db;
+		5'h04:	dec_cs2[7:0] <= db;
+		5'h05:	dec_cs2[15:8] <= db;
+		5'h06:	dec_cs3[7:0] <= db;
+		5'h07:	dec_cs3[15:8] <= db;
+		5'h08:	dec_cs4[7:0] <= db;
+		5'h09:	dec_cs4[8] <= db[0];
+		5'h0A:	dec_cs5[7:0] <= db;
+		5'h0B:	dec_cs5[8] <= db[0];
+		5'h0C:	mh1 <= db;
+		5'h0D:	mh8 <= db;
+		5'h0E:	mh32 <= db;
+		5'h0F:	if (db==8'hE0)
+					isRegEnabled <= `FALSE;
+		5'h10:	cntLimit0[7:0] <= db;
+		5'h11:	cntLimit0[15:8] <= db;
+		5'h12:	cntLimit0[23:16] <= db;
+		5'h13:	begin
+				cntIrqEn0 <= db[0];
+				cntIrq0 <= 1'b0;
+				cntSrc0 <= db[3:2];
+				cntUp0 <= db[4];
+				end
+		5'h14:	cntLimit1[7:0] <= db;
+		5'h15:	cntLimit1[15:8] <= db;
+		5'h16:	cntLimit1[23:16] <= db;
+		5'h17:	begin
+				cntIrqEn1 <= db[0];
+				cntIrq1 <= 1'b0;
+				cntSrc1 <= db[3:2];
+				cntUp1 <= db[4];
+				end
+		5'h18:	cntLimit2[7:0] <= db;
+		5'h19:	cntLimit2[15:8] <= db;
+		5'h1A:	cntLimit2[23:16] <= db;
+		5'h1B:	begin
+				cntIrqEn2 <= db[0];
+				cntIrq2 <= 1'b0;
+				cntSrc2 <= db[3:2];
+				cntUp2 <= db[4];
+				end
+		5'h1C:	cntTrig0 <= 1'b1;
+		5'h1D:	cntTrig1 <= 1'b1;
+		5'h1E:	cntTrig2 <= 1'b1;
+		endcase
+	end
+	if (ivda && ad[31:4]==pZPAddress[31:4] && ~rw) begin
+		zp_shadow[ad[3:0]] <= db;
+		case(ad[3:0])
+		4'h0:	realCnt0[7:0] <= db;
+		4'h1:	realCnt0[15:8] <= db;
+		4'h2:	realCnt0[23:16] <= db;
+		4'h4:	realCnt1[7:0] <= db;
+		4'h5:	realCnt1[15:8] <= db;
+		4'h6:	realCnt1[23:16] <= db;
+		4'h8:	realCnt2[7:0] <= db;
+		4'h9:	realCnt2[15:8] <= db;
+		4'hA:	realCnt2[23:16] <= db;
+		endcase
+	end
+end
+
+reg [7:0] dbo1;
+always @(ad or realCnt0 or realCnt1 or realCnt2)
+case(ad[3:0])
+4'h0:	dbo1 <= realCnt0[7:0];
+4'h1:	dbo1 <= realCnt0[15:8];
+4'h2:	dbo1 <= realCnt0[23:16];
+4'h4:	dbo1 <= realCnt1[7:0];
+4'h5:	dbo1 <= realCnt1[15:8];
+4'h6:	dbo1 <= realCnt1[23:16];
+4'h8:	dbo1 <= realCnt2[7:0];
+4'h9:	dbo1 <= realCnt2[15:8];
+4'hA:	dbo1 <= realCnt2[23:16];
+default:	dbo1 <= zp_shadow[ad[3:0]];
+endcase
+
+wire cs_mpu = (ivda && ad[31:4]==pZPAddress[31:4]) || (ivda && ad[31:8]==pIOAddress[31:8]);
+assign db = (ivda && ad[31:4]==pZPAddress[31:4] && rw) ? dbo1 : {8{1'bz}};
+assign db =	(ivda && ad[31:8]==pIOAddress[31:8] && rw) ? (
+	ad[4:0]==5'h1F ? {cntIrq2,cntIrq1,cntIrq0} :
+	shadow_ram[ad[4:0]] ) :
+	{8{1'bz}};
+assign vda = !cs_mpu & ivda;
+
+reg trig1;
+reg trig8;
+always @(posedge clko)
+begin
+	if (cycle==5'd0 & dec_match1 & (vpa | vda))
+		trig1 <= `TRUE;
+	if (cycle==5'd30 && rdy)
+		trig1 <= `FALSE;
+	if ((cycle==5'd0 || cycle==5'd8 || cycle==5'd16 || cycle==5'd24) & dec_match8 & (vpa | vda))
+		trig8 <= `TRUE;
+	if ((cycle==5'd6 || cycle==5'd14 || cycle==5'd22 || cycle==5'd30) && rdy)
+		trig8 <= `FALSE;
+end
+
+assign cs0 = !((trig1 & match_cs0 & mh1[0]) | (trig8 & match_cs0 & mh8[0]) | (match_cs0 & mh32[0]));
+assign cs1 = !((trig1 & match_cs1 & mh1[1]) | (trig8 & match_cs1 & mh8[1]) | (match_cs1 & mh32[1]));
+assign cs2 = !((trig1 & match_cs2 & mh1[2]) | (trig8 & match_cs2 & mh8[2]) | (match_cs2 & mh32[2]));
+assign cs3 = !((trig1 & match_cs3 & mh1[3]) | (trig8 & match_cs3 & mh8[3]) | (match_cs3 & mh32[3]));
+assign cs4 = !((trig1 & match_cs4 & mh1[4]) | (trig8 & match_cs4 & mh8[4]) | (match_cs4 & mh32[4]));
+assign cs5 = !((trig1 & match_cs5 & mh1[5]) | (trig8 & match_cs5 & mh8[5]) | (match_cs5 & mh32[5]));
+assign cs6 = !(!(match_cs0 | match_cs1 | match_cs2 | match_cs3 | match_cs4 | match_cs5) & (vda | vpa));
+
+wire rdy832 = (vda|vpa) ? (
+			  dec_match1 ? trig1 && (cycle==5'd30) && rdy :
+			  dec_match8 ? trig8 && (cycle==5'd30 || cycle==5'd22 || cycle==5'd14 || cycle==5'd6) && rdy :
+				rdy) : 1'b1;
+
+FT832 u1
+(
+	.rst(rst),
+	.clk(clk),
+	.clko(clko),
+	.nmi(nmi),
+	.irq(iirq),
+	.abort(abort),
+	.e(e),
+	.mx(mx),
+	.cyc(cycle),
+	.phi11(phi11),
+	.phi12(phi12),
+	.phi81(phi81),
+	.phi82(phi82),
+	.mlb(mlb),
+	.vpb(vpb),
+	.rdy(rdy832),
+	.be(be),
+	.vpa(vpa),
+	.vda(ivda),
+	.rw(rw),
+	.ad(ad),
+	.db(db),
+	.err_i(1'b0),
+	.rty_i(1'b0)
+);
+
+endmodule
Index: ultimate_cart/veronica/PRNG.v
===================================================================
--- ultimate_cart/veronica/PRNG.v	(nonexistent)
+++ ultimate_cart/veronica/PRNG.v	(revision 438)
@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// PRNG.v
+//  - Random number generator
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+//-----------------------------------------------------------------------------
+// Uses George Marsaglia's multiply method.
+//-----------------------------------------------------------------------------
+
+module PRNG(rst, clk, vda, rw, ad, db, rdy);
+parameter pIOAddress = 24'hFEA100;
+input rst;
+input clk;
+input vda;
+input rw;
+input [23:0] ad;
+inout tri [7:0] db;
+output rdy;
+
+reg [31:0] m_z;
+reg [31:0] m_w;
+reg [31:0] next_m_z;
+reg [31:0] next_m_w;
+
+always @(m_z or m_w)
+begin
+	next_m_z <= (18'd36969 * m_z[15:0]) + m_z[31:16];
+	next_m_w <= (18'd18000 * m_w[15:0]) + m_w[31:16];
+end
+
+wire [31:0] rand = {m_z[15:0],16'd0} + m_w;
+
+reg rdy1,rdy2;
+reg [7:0] dbo;
+wire cs_rand = vda && (ad[23:4]==pIOAddress[23:4]);
+assign db = cs_rand & rw ? dbo : {8{1'bz}};
+assign rdy = !cs_rand ? 1'b1 : ~rw ? 1'b1 : rdy2;
+
+always @(posedge clk)
+if (rst) begin
+	rdy1 <= 1'b0;
+	rdy2 <= 1'b0;
+end
+else begin
+	rdy1 <= cs_rand;
+	rdy2 <= rdy1 & cs_rand;
+end
+
+always @(posedge clk)
+if (rst) begin
+	m_z <= 32'h99999999;
+	m_w <= 32'h88888888;
+	dbo <= 8'h00;
+end
+else begin
+	if (vda & cs_rand & ~rw)
+		case(ad[3:0])
+		4'd0:	m_z[7:0] <= db;
+		4'd1:	m_z[15:8] <= db;
+		4'd2:	m_z[23:16] <= db;
+		4'd3:	m_z[31:24] <= db;
+		4'd4:	m_w[7:0] <= db;
+		4'd5:	m_w[15:8] <= db;
+		4'd6:	m_w[23:16] <= db;
+		4'd7:	m_w[31:24] <= db;
+		4'd14:	begin
+				m_z <= next_m_z;
+				m_w <= next_m_w;
+				end
+		endcase
+	case(ad[3:0])
+	4'd8:	dbo <= rand[7:0];
+	4'd9:	dbo <= rand[15:8];
+	4'd10:	dbo <= rand[23:16];
+	4'd11:	dbo <= rand[31:24];
+	default:	dbo <= rand[7:0];
+	endcase
+end
+
+endmodule
Index: ultimate_cart/veronica/atari_address_decoder.vhd
===================================================================
--- ultimate_cart/veronica/atari_address_decoder.vhd	(nonexistent)
+++ ultimate_cart/veronica/atari_address_decoder.vhd	(revision 438)
@@ -0,0 +1,34 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY atari_address_decoder IS
+	PORT (
+				s4 : in std_logic;
+				s5 : in std_logic;
+				ctl : in std_logic;
+				addr_in: in std_logic_vector(12 downto 0);
+				bus_request: in std_logic;
+				
+				bank_half_select : in std_logic;
+				bank_select : in std_logic;
+				
+				config_select : out std_logic;
+				sram_select : out std_logic;
+				sram_address : out std_logic_vector(16 downto 0)
+			);
+END atari_address_decoder;
+
+ARCHITECTURE vhdl OF atari_address_decoder IS
+begin
+
+	sram_address(16) <= '1';
+	sram_address(15 downto 14) <= bank_select&bank_half_select;
+	sram_address(13) <= not(s4) and s5;
+	sram_address(12 downto 0) <= addr_in;
+	
+	sram_select <= bus_request and (s4 or s5);
+	config_select <= bus_request and ctl and or_reduce(addr_in(7 downto 6)&not(addr_in(5 downto 0)));
+	
+end vhdl;

Property changes on: ultimate_cart/veronica/atari_address_decoder.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/bus_task.v
===================================================================
--- ultimate_cart/veronica/bus_task.v	(nonexistent)
+++ ultimate_cart/veronica/bus_task.v	(revision 438)
@@ -0,0 +1,73 @@
+// ============================================================================
+// bus_task.v
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+task opcode_read;
+begin
+	vpa <= `TRUE;
+	vda <= `TRUE;
+	rwo <= `TRUE;
+	ado <= pc;
+end
+endtask
+
+task insn_read;
+input [23:0] adr;
+begin
+	vpa <= `TRUE;
+	vda <= `FALSE;
+	rwo <= `TRUE;
+	ado <= adr;
+end
+endtask
+
+task data_read;
+input [23:0] adr;
+begin
+	vpa <= `FALSE;
+	vda <= `TRUE;
+	rwo <= `TRUE;
+	ado <= adr;
+end
+endtask
+
+task data_write;
+input [7:0] dat;
+begin
+	vpa <= `FALSE;
+	vda <= `TRUE;
+	rwo <= `FALSE;
+	ado <= wadr;
+	dbo <= dat;
+end
+endtask
+
+task data_nack;
+begin
+	vpa <= `FALSE;
+	vda <= `FALSE;
+	rwo <= `TRUE;
+	ado <= 24'h000000;
+	dbo <= 8'h00;
+end
+endtask
+
Index: ultimate_cart/veronica/byte_calc.v
===================================================================
--- ultimate_cart/veronica/byte_calc.v	(nonexistent)
+++ ultimate_cart/veronica/byte_calc.v	(revision 438)
@@ -0,0 +1,50 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//          
+// Datapath calculations - eight/sixteen bit mode                                                                
+// ============================================================================
+//
+BYTE_CALC:
+	begin
+		moveto_ifetch();
+		store_what <= `STW_DEF8;
+		case(ir[7:0])
+		`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_IYL,`ADC_I,`ADC_IL,`ADC_AL,`ADC_ALX,`ADC_DSP,`ADC_DSPIY:	begin res8 <= acc8 + b8 + {7'b0,cf}; end
+		`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_IYL,`SBC_I,`SBC_IL,`SBC_AL,`SBC_ALX,`SBC_DSP,`SBC_DSPIY:	begin res8 <= acc8 - b8 - {7'b0,~cf}; end
+		`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_IYL,`CMP_I,`CMP_IL,`CMP_AL,`CMP_ALX,`CMP_DSP,`CMP_DSPIY:	begin res8 <= acc8 - b8; end
+		`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_IYL,`AND_I,`AND_IL,`AND_AL,`AND_ALX,`AND_DSP,`AND_DSPIY:	begin res8 <= acc8 & b8; end
+		`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_IYL,`ORA_I,`ORA_IL,`ORA_AL,`ORA_ALX,`ORA_DSP,`ORA_DSPIY:	begin res8 <= acc8 | b8; end
+		`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_IYL,`EOR_I,`EOR_IL,`EOR_AL,`EOR_ALX,`EOR_DSP,`EOR_DSPIY:	begin res8 <= acc8 ^ b8; end
+		`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_IYL,`LDA_I,`LDA_IL,`LDA_AL,`LDA_ALX,`LDA_DSP,`LDA_DSPIY: 	begin res8 <= b8; end
+		`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:	begin res8 <= acc8 & b8; end
+		`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:	begin res8 <= b8; end
+		`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:	begin res8 <= b8; end
+		`CPX_IMM,`CPX_ZP,`CPX_ABS:	begin res8 <= x8 - b8; end
+		`CPY_IMM,`CPY_ZP,`CPY_ABS:	begin res8 <= y8 - b8; end
+		`TRB_ZP,`TRB_ABS:	begin res8 <= ~acc8 & b8; wdat <= ~acc8 & b8; state <= STORE1; data_nack(); end
+		`TSB_ZP,`TSB_ABS:	begin res8 <= acc8 | b8; wdat <= acc8 | b8; state <= STORE1; data_nack(); end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX:	begin res8 <= {b8,1'b0}; wdat <= {b8[6:0],1'b0}; state <= STORE1; data_nack(); end
+		`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX:	begin res8 <= {b8,cf}; wdat <= {b8[6:0],cf}; state <= STORE1; data_nack(); end
+		`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX:	begin res8 <= {b8[0],1'b0,b8[7:1]}; wdat <= {1'b0,b8[7:1]}; state <= STORE1; data_nack(); end
+		`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX:	begin res8 <= {b8[0],cf,b8[7:1]}; wdat <= {cf,b8[7:1]}; state <= STORE1; data_nack(); end
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX:	begin res8 <= b8 + 8'd1; wdat <= {b8+8'd1}; state <= STORE1; data_nack(); end
+		`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX:	begin res8 <= b8 - 8'd1; wdat <= {b8-8'd1}; state <= STORE1; data_nack(); end
+		endcase
+	end
Index: ultimate_cart/veronica/config_regs_6502.vhd
===================================================================
--- ultimate_cart/veronica/config_regs_6502.vhd	(nonexistent)
+++ ultimate_cart/veronica/config_regs_6502.vhd	(revision 438)
@@ -0,0 +1,91 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY config_regs_6502 IS
+	PORT (
+				CLK: in std_logic;
+				RESET_N: in std_logic;
+				
+				SEM_OUT: out std_logic;
+				BANKA_ENABLE: out std_logic;
+				BANK8_ENABLE: out std_logic;
+				BANK_HALF_SELECT: out std_logic;
+				BANK_SELECT: out std_logic;
+				ENABLE_65816: out std_logic;
+
+				
+				DATA_IN: in std_logic_vector(7 downto 0);
+				DATA_OUT: out std_logic_vector(7 downto 0);
+				RW_N: in std_logic
+			);
+END config_regs_6502;
+
+ARCHITECTURE vhdl OF config_regs_6502 IS
+
+	signal sem_next : std_logic;
+	signal sem_reg : std_logic;
+
+	signal banka_enable_next : std_logic;
+	signal banka_enable_reg  : std_logic;
+	
+	signal bank8_enable_next : std_logic;
+	signal bank8_enable_reg  : std_logic;	
+	
+	signal bank_half_next : std_logic;
+	signal bank_half_reg : std_logic;
+
+	signal bank_select_next : std_logic;
+	signal bank_select_reg : std_logic;
+
+	signal enable_65816_next : std_logic;
+	signal enable_65816_reg : std_logic;
+	
+begin
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			sem_reg <= '1';
+			banka_enable_reg <= '0';
+			bank8_enable_reg <= '0';
+			bank_half_reg <= '1';
+			bank_select_reg <= '0';
+			enable_65816_reg <= '0';
+		elsif (clk'event and clk='1') then
+			sem_reg <= sem_next;
+			banka_enable_reg <= banka_enable_next;
+			bank8_enable_reg <= bank8_enable_next;
+			bank_half_reg <= bank_half_next;
+			bank_select_reg <= bank_select_next;
+			enable_65816_reg <= enable_65816_next;
+		end if;
+	end process;
+	
+	process(data_in,rw_n,sem_reg,banka_enable_reg,bank8_enable_reg,bank_half_reg,bank_select_reg,enable_65816_reg)
+	begin
+		sem_next <= sem_reg;
+		banka_enable_next <= banka_enable_reg;
+		bank8_enable_next <= bank8_enable_reg;
+		bank_half_next <= bank_half_reg;
+		bank_select_next <= bank_select_reg;
+		enable_65816_next <= enable_65816_reg;
+		
+		if (rw_n='0') then
+			sem_next <= data_in(7);
+			banka_enable_next <= data_in(5);
+			bank8_enable_next <= data_in(4);
+			bank_half_next <= data_in(3);
+			bank_select_next <= data_in(1);
+			enable_65816_next <= data_in(0);
+		end if;
+	end process;
+	
+	data_out <= sem_reg&'1'&banka_enable_reg&bank8_enable_reg&bank_half_reg&'1'&bank_select_reg&enable_65816_reg;
+	sem_out <= sem_reg;
+	banka_enable <= banka_enable_reg;
+	bank8_enable <= bank8_enable_reg;
+	bank_half_select<=bank_half_reg;
+	bank_select<=bank_select_reg;
+	enable_65816<=enable_65816_reg;
+	
+end vhdl;

Property changes on: ultimate_cart/veronica/config_regs_6502.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/config_regs_veronica.vhd
===================================================================
--- ultimate_cart/veronica/config_regs_veronica.vhd	(nonexistent)
+++ ultimate_cart/veronica/config_regs_veronica.vhd	(revision 438)
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY config_regs_veronica IS
+	PORT (
+				CLK: in std_logic;
+				RESET_N: in std_logic;
+				
+				SEM_IN: in std_logic;
+				WINDOW_ADDRESS: out std_logic;
+				BANK_HALF_SELECT: out std_logic;
+				
+				DATA_IN: in std_logic_vector(7 downto 0);
+				DATA_OUT: out std_logic_vector(7 downto 0);
+				RW_N: in std_logic
+			);
+END config_regs_veronica;
+
+
+ARCHITECTURE vhdl OF config_regs_veronica IS
+	signal window_address_next : std_logic;
+	signal window_address_reg  : std_logic;
+	
+	signal bank_half_next : std_logic;
+	signal bank_half_reg : std_logic;
+	
+begin
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			window_address_reg <= '0';
+			bank_half_reg <= '1';
+		elsif (clk'event and clk='1') then
+			window_address_reg <= window_address_next;
+			bank_half_reg <= bank_half_next;
+		end if;
+	end process;
+	
+	process(rw_n,window_address_reg,bank_half_reg,data_in)
+	begin
+		window_address_next <= window_address_reg;
+		bank_half_next <= bank_half_reg;
+		
+		if (rw_n='0') then
+			window_address_next <= data_in(6);
+			bank_half_next <= data_in(5);
+		end if;
+	end process;
+	
+	data_out <= not(sem_in)&window_address_reg&bank_half_reg&"11111";
+	window_address <= window_address_reg;
+	bank_half_select <= bank_half_reg;
+
+end vhdl;

Property changes on: ultimate_cart/veronica/config_regs_veronica.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/half_calc.v
===================================================================
--- ultimate_cart/veronica/half_calc.v	(nonexistent)
+++ ultimate_cart/veronica/half_calc.v	(revision 438)
@@ -0,0 +1,50 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@finitron.ca
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//          
+// Datapath calculations - sixteen bit mode                                                                
+// ============================================================================
+//
+HALF_CALC:
+	begin
+		moveto_ifetch();
+		store_what <= `STW_DEF70;
+		case(ir[7:0])
+		`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_IYL,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_AL,`ADC_ALX,`ADC_I,`ADC_IL,`ADC_DSP,`ADC_DSPIY:	begin res16 <= acc16 + b16 + {15'd0,cf}; end
+		`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_IYL,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_AL,`SBC_ALX,`SBC_I,`SBC_IL,`SBC_DSP,`SBC_DSPIY:	begin res16 <= acc16 - b16 - {15'd0,~cf}; end
+		`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_IYL,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_AL,`CMP_ALX,`CMP_I,`CMP_IL,`CMP_DSP,`CMP_DSPIY:	begin res16 <= acc16 - b16; end
+		`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_IYL,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_AL,`AND_ALX,`AND_I,`AND_IL,`AND_DSP,`AND_DSPIY:	begin res16 <= acc16 & b16; end
+		`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_IYL,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_AL,`ORA_ALX,`ORA_I,`ORA_IL,`ORA_DSP,`ORA_DSPIY:	begin res16 <= acc16 | b16; end
+		`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_IYL,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_AL,`EOR_ALX,`EOR_I,`EOR_IL,`EOR_DSP,`EOR_DSPIY:	begin res16 <= acc16 ^ b16; end
+		`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_IYL,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_AL,`LDA_ALX,`LDA_I,`LDA_IL,`LDA_DSP,`LDA_DSPIY:	begin res16 <= b16; end
+		`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:	begin res16 <= acc16 & b16; end
+		`TRB_ZP,`TRB_ABS:	begin res16 <= ~acc16 & b16; wdat <= ~acc16 & b16; state <= STORE1; data_nack(); end
+		`TSB_ZP,`TSB_ABS:	begin res16 <= acc16 | b16; wdat <= acc16 | b16; state <= STORE1; data_nack(); end
+		`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY:	begin res16 <= b16; end
+		`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX:	begin res16 <= b16; end
+		`CPX_IMM,`CPX_ZP,`CPX_ABS:	begin res16 <= x16 - b16; end
+		`CPY_IMM,`CPY_ZP,`CPY_ABS:	begin res16 <= y16 - b16; end
+		`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX:	begin res16 <= {b16,1'b0}; wdat <= {b16[14:0],1'b0}; state <= STORE1; data_nack(); end
+		`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX:	begin res16 <= {b16,cf}; wdat <= {b16[14:0],cf}; state <= STORE1; data_nack(); end
+		`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX:	begin res16 <= {b16[0],1'b0,b16[15:1]}; wdat <= {1'b0,b16[15:1]}; state <= STORE1; data_nack(); end
+		`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX:	begin res16 <= {b16[0],cf,b16[15:1]}; wdat <= {cf,b16[15:1]}; state <= STORE1; data_nack(); end
+		`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX:	begin res16 <= {b24,b16} + 24'd1; wdat <= {{b24,b16}+24'd1}; state <= STORE1; data_nack(); end
+		`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX:	begin res16 <= {b24,b16} - 24'd1; wdat <= {{b24,b16}-24'd1}; state <= STORE1; data_nack(); end
+		endcase
+	end
Index: ultimate_cart/veronica/load_mac.v
===================================================================
--- ultimate_cart/veronica/load_mac.v	(nonexistent)
+++ ultimate_cart/veronica/load_mac.v	(revision 438)
@@ -0,0 +1,95 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+LOAD_MAC1:
+`ifdef SUPPORT_DCACHE
+	if (unCachedData)
+`endif
+	begin
+		if (isRMW)
+			mlb <= 1'b1;
+		if (isBrk)
+			vpb <= `TRUE;
+		data_read(radr);
+		state <= LOAD_MAC2;
+	end
+`ifdef SUPPORT_DCACHE
+	else if (dhit)
+		load_tsk(rdat,rdat8,rdat16);
+	else begin
+		retstate <= LOAD_MAC1;
+		state <= DCACHE1;
+	end
+`endif
+LOAD_MAC2:
+	if (rdy) begin
+		data_nack();
+		//TODO FIXME TODO load_tsk(db);
+	end
+`ifdef SUPPORT_BERR
+	else if (err_i) begin
+		mlb <= 1'b0;
+		data_nack();
+		derr_address <= ado;
+		intno <= 9'd508;
+		state <= BUS_ERROR;
+	end
+`endif
+RTS1:
+	begin
+		vpa <= `TRUE;
+		vda <= `TRUE;
+		pc <= pc + 24'd1;
+		ado <= pc + 24'd1;
+		next_state(IFETCH1);
+	end
+BYTE_IX5:
+	begin
+		isI24 <= `FALSE;
+		radr <= ia;
+		load_what <= m16 ? `HALF_70 : `BYTE_70;
+		state <= LOAD_MAC1;
+		if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I || ir[7:0]==`STA_IL) begin
+			wadr <= ia;
+			store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+			state <= STORE1;
+		end
+		else if (ir[7:0]==`PEI) begin
+			set_sp();
+			store_what <= `STW_IA158;
+			state <= STORE1;
+		end
+	end
+BYTE_IY5:
+	begin
+		isIY <= `FALSE;
+		isIY24 <= `FALSE;
+		radr <= iapy8;
+		wadr <= iapy8;
+		store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
+		load_what <= m16 ? `HALF_70 : `BYTE_70;
+		$display("IY addr: %h", iapy8);
+		if (ir[7:0]==`STA_IY || ir[7:0]==`STA_IYL || ir[7:0]==`STA_DSPIY)
+			state <= STORE1;
+		else
+			state <= LOAD_MAC1;
+	end
Index: ultimate_cart/veronica/load_tsk.v
===================================================================
--- ultimate_cart/veronica/load_tsk.v	(nonexistent)
+++ ultimate_cart/veronica/load_tsk.v	(revision 438)
@@ -0,0 +1,205 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+//task load_tsk;
+//input [7:0] db;
+begin
+	case(load_what)
+	`BYTE_70:
+			begin
+				b8 <= db;
+				state <= BYTE_CALC;
+			end
+	`BYTE_71:
+			begin
+				moveto_ifetch();
+				res8 <= db;
+			end
+	`HALF_70:
+				begin
+					b16[7:0] <= db;
+					load_what <= `HALF_158;
+					radr <= radr+24'd1;
+					state <= LOAD_MAC1;
+				end
+	`HALF_158:
+				begin
+					b16[15:8] <= db;
+					if (isTribyte) begin
+						radr <= radr+24'd1;
+						load_what <= `TRIP_2316;
+						next_state(LOAD_MAC1);
+					end
+					else
+						state <= HALF_CALC;
+				end
+	`TRIP_2316:	begin
+					b24 <= db;
+					next_state(HALF_CALC);
+				end
+	`HALF_71:
+				begin
+					res16[7:0] <= db;
+					load_what <= `HALF_159;
+					radr <= radr+32'd1;
+					next_state(LOAD_MAC1);
+				end
+	`HALF_159:
+				begin
+					res16[15:8] <= db;
+					moveto_ifetch();
+				end
+	`HALF_71S:
+				begin
+					res16[7:0] <= db;
+					load_what <= `HALF_159S;
+					inc_sp();
+					next_state(LOAD_MAC1);
+				end
+	`HALF_159S:
+				begin
+					res16[15:8] <= db;
+					moveto_ifetch();
+				end
+	`BYTE_72:
+				begin
+					wdat[7:0] <= db;
+					radr <= mvndst_address;
+					wadr <= mvndst_address;
+					store_what <= `STW_DEF8;
+					acc[15:0] <= acc_dec[15:0];
+					if (ir9==`MVN) begin
+						x[15:0] <= x_inc[15:0];
+						y[15:0] <= y_inc[15:0];
+					end
+					else begin
+						x[15:0] <= x_dec[15:0];
+						y[15:0] <= y_dec[15:0];
+					end
+					next_state(STORE1);
+				end
+	`SR_70:		begin
+					cf <= db[0];
+					zf <= db[1];
+					if (db[2])
+						im <= 1'b1;
+					else
+						imcd <= 3'b110;
+					df <= db[3];
+					if (m816) begin
+						x_bit <= db[4];
+						m_bit <= db[5];
+						if (db[4]) begin
+							x[15:8] <= 8'd0;
+							y[15:8] <= 8'd0;
+						end
+						//if (db[5]) acc[31:8] <= 24'd0;
+					end
+					// The following load of the break flag is different than the '02
+					// which never loads the flag.
+					else
+						bf <= db[4];
+					vf <= db[6];
+					nf <= db[7];
+					if (isRTI) begin
+						load_what <= `PC_70;
+						inc_sp();
+						state <= LOAD_MAC1;
+					end		
+					else begin	// PLP
+						moveto_ifetch();
+					end
+				end
+	`PC_70:		begin
+					pc[7:0] <= db;
+					load_what <= `PC_158;
+					if (isRTI|isRTS|isRTL) begin
+						inc_sp();
+					end
+					else begin	// JMP (abs)
+						radr <= radr + 24'd1;
+					end
+					state <= LOAD_MAC1;
+				end
+	`PC_158:	begin
+					pc[15:8] <= db;
+					if ((isRTI&m816)|isRTL) begin
+						load_what <= `PC_2316;
+						inc_sp();
+						state <= LOAD_MAC1;
+					end
+					else if (isRTS)	// rts instruction
+						next_state(RTS1);
+					else			// jmp (abs)
+					begin
+						vpb <= `FALSE;
+						next_state(IFETCH0);
+					end
+				end
+	`PC_2316:	begin
+					pc[23:16] <= db;
+					if (isRTL) begin
+						load_what <= `NOTHING;
+						next_state(RTS1);
+					end
+					else begin
+						load_what <= `NOTHING;
+						next_state(IFETCH0);
+//						load_what <= `PC_3124;
+//						if (isRTI) begin
+//							inc_sp();
+//						end
+//						state <= LOAD_MAC1;	
+					end
+				end
+//	`PC_3124:	begin
+//					pc[31:24] <= db;
+//					load_what <= `NOTHING;
+//					next_state(BYTE_IFETCH);
+//				end
+	`IA_70:
+			begin
+				radr <= radr + 24'd1;
+				ia[7:0] <= db;
+				load_what <= `IA_158;
+				state <= LOAD_MAC1;
+			end
+	`IA_158:
+			begin
+				ia[15:8] <= db;
+				ia[23:16] <= dbr;
+				if (isIY24|isI24) begin
+					radr <= radr + 24'd1;
+					load_what <= `IA_2316;
+					state <= LOAD_MAC1;
+				end
+				else
+					state <= isIY ? BYTE_IY5 : BYTE_IX5;
+			end
+	`IA_2316:
+			begin
+				ia[23:16] <= db;
+				state <= isIY24 ? BYTE_IY5 : BYTE_IX5;
+			end
+	endcase
+end
+//endtask
Index: ultimate_cart/veronica/misc_task.v
===================================================================
--- ultimate_cart/veronica/misc_task.v	(nonexistent)
+++ ultimate_cart/veronica/misc_task.v	(revision 438)
@@ -0,0 +1,90 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                                          
+// ============================================================================
+//
+task set_sp;
+begin
+	if (m816) begin
+		radr <= {8'h00,sp[15:0]};
+		wadr <= {8'h00,sp[15:0]};
+		sp <= sp_dec;
+	end
+	else begin
+		radr <= {16'h0001,sp[7:0]};
+		wadr <= {16'h0001,sp[7:0]};
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+end
+endtask
+
+task inc_sp;
+begin
+	if (m816) begin
+		radr <= {8'h00,sp_inc[15:0]};
+		sp <= sp_inc;
+	end
+	else begin
+		radr <= {16'h0001,sp_inc[7:0]};
+		sp <= {8'h1,sp_inc[7:0]};
+	end
+end
+endtask
+
+task tsk_push;
+input [5:0] SW8;
+input [5:0] SW16;
+input szFlg;
+begin
+	if (m816) begin
+		if (szFlg) begin
+			radr <= {8'h00,sp_dec[15:0]};
+			wadr <= {8'h00,sp_dec[15:0]};
+			store_what <= SW16;
+			sp <= sp_dec2;
+		end
+		else begin
+			radr <= {8'h00,sp[15:0]};
+			wadr <= {8'h00,sp[15:0]};
+			store_what <= SW8;
+			sp <= sp_dec;
+		end
+	end
+	else begin
+		radr <= {16'h01,sp[7:0]};
+		wadr <= {16'h01,sp[7:0]};
+		store_what <= SW8;
+		sp[7:0] <= sp[7:0] - 8'd1;
+		sp[15:8] <= 8'h1;
+	end
+	state <= STORE1;
+end
+endtask
+
+task moveto_ifetch;
+begin
+	vpa <= `TRUE;
+	vda <= `TRUE;
+	ado <= pc;
+	next_state(IFETCH1);
+end
+endtask
+
Index: ultimate_cart/veronica/output_mux.vhd
===================================================================
--- ultimate_cart/veronica/output_mux.vhd	(nonexistent)
+++ ultimate_cart/veronica/output_mux.vhd	(revision 438)
@@ -0,0 +1,26 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY output_mux IS
+	PORT (
+				config_select : in std_logic;
+				sram_select : in std_logic;
+				
+				config_data : in std_logic_vector(7 downto 0);
+				sram_data : in std_logic_vector(7 downto 0);
+				
+				read_data : out std_logic_vector(7 downto 0)
+			);
+END output_mux;
+
+ARCHITECTURE vhdl OF output_mux IS
+begin
+	process(config_select,sram_select,config_data,sram_data)
+	begin
+		read_data <= sram_data;
+		if (config_select='1') then
+			read_data <= config_data;
+		end if;
+	end process;
+end vhdl;

Property changes on: ultimate_cart/veronica/output_mux.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/pll_veronica.qip
===================================================================
--- ultimate_cart/veronica/pll_veronica.qip	(nonexistent)
+++ ultimate_cart/veronica/pll_veronica.qip	(revision 438)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "15.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_veronica.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_veronica.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_veronica.ppf"]

Property changes on: ultimate_cart/veronica/pll_veronica.qip
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/pll_veronica.vhd
===================================================================
--- ultimate_cart/veronica/pll_veronica.vhd	(nonexistent)
+++ ultimate_cart/veronica/pll_veronica.vhd	(revision 438)
@@ -0,0 +1,393 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_veronica.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus Prime License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_veronica IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_veronica;
+
+
+ARCHITECTURE SYN OF pll_veronica IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire2_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2_bv(0 DOWNTO 0) <= "0";
+	sub_wire2    <= To_stdlogicvector(sub_wire2_bv);
+	sub_wire0    <= inclk0;
+	sub_wire1    <= sub_wire2(0 DOWNTO 0) & sub_wire0;
+	sub_wire5    <= sub_wire3(1);
+	sub_wire4    <= sub_wire3(0);
+	c0    <= sub_wire4;
+	c1    <= sub_wire5;
+	locked    <= sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 20,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 7,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 20,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 49,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 25000,
+		intended_device_family => "MAX 10",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_veronica",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire1,
+		clk => sub_wire3,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "98.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "40.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "98.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_veronica.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "49"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "25000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_veronica_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

Property changes on: ultimate_cart/veronica/pll_veronica.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/slave_timing_6502.vhd
===================================================================
--- ultimate_cart/veronica/slave_timing_6502.vhd	(nonexistent)
+++ ultimate_cart/veronica/slave_timing_6502.vhd	(revision 438)
@@ -0,0 +1,109 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY slave_timing_6502 IS
+	PORT (
+				CLK: in std_logic;
+				RESET_N: in std_logic;
+				
+				PHI2 : in std_logic; -- async to our clk:-(
+				bus_addr : in std_logic_vector(12 downto 0);
+				bus_data : in std_logic_vector(7 downto 0);
+				bus_ctl : in std_logic;
+				bus_rw : in std_logic;
+				bus_s4 : in std_logic;
+				bus_s5 : in std_logic;
+	
+				bus_data_out : out std_logic_vector(7 downto 0);
+				bus_drive : out std_logic;
+
+				ADDR_IN: out std_logic_vector(12 downto 0);
+				DATA_IN: out std_logic_vector(7 downto 0);
+				DATA_OUT: in std_logic_vector(7 downto 0);
+				RW_N: out std_logic;
+				BUS_REQUEST: out std_logic;
+				S4 : out std_logic;
+				s5 : out std_logic;
+				ctl : out std_logic
+			);
+END slave_timing_6502;
+
+ARCHITECTURE vhdl OF slave_timing_6502 IS
+
+	signal PHI2_sync : std_logic;
+	signal bus_addr_sync : std_logic_vector(12 downto 0);
+	signal bus_data_sync : std_logic_vector(7 downto 0);
+	signal bus_ctl_sync : std_logic;
+	signal bus_rw_sync : std_logic;
+	signal bus_s4_sync : std_logic;
+	signal bus_s5_sync : std_logic;
+	signal bus_misc_sync : std_logic_vector(3 downto 0);
+	
+	signal phi_edge_prev_next : std_logic;
+	signal phi_edge_prev_reg: std_logic;	
+
+	signal drive_bus_shift_next : std_logic_vector(3 downto 0);	
+	signal drive_bus_shift_reg : std_logic_vector(3 downto 0);
+	
+	signal bus_data_out_next : std_logic_vector(7 downto 0);	
+	signal bus_data_out_reg : std_logic_vector(7 downto 0);
+	
+begin
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			phi_edge_prev_reg <= '1';
+			drive_bus_shift_reg <= (others=>'0');
+			bus_data_out_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			phi_edge_prev_reg <= phi_edge_prev_next;
+			drive_bus_shift_reg <= drive_bus_shift_next;
+			bus_data_out_reg <= bus_data_out_next;
+		end if;
+	end process;
+	
+	synchronizer_phi : entity work.synchronizer
+				 port map (clk=>clk, raw=>PHI2, sync=>PHI2_SYNC);
+	synchronizer_addr : entity work.synchronizer_vector
+				generic map(BITS=>13)
+				port map (clk=>clk, raw=>bus_addr, sync=>bus_addr_sync);
+	synchronizer_data : entity work.synchronizer_vector
+				generic map(BITS=>8)
+				port map (clk=>clk, raw=>bus_data, sync=>bus_data_sync);				
+	synchronizer_ctl : entity work.synchronizer_vector
+				generic map(BITS=>4)
+				port map (clk=>clk, raw=>bus_ctl&bus_rw&bus_s4&bus_s5, sync=>bus_misc_sync);
+	
+	bus_ctl_sync<=bus_misc_sync(3);
+	bus_rw_sync<=bus_misc_sync(2);
+	bus_s4_sync<=bus_misc_sync(1);
+	bus_s5_sync<=bus_misc_sync(0);
+
+	phi_edge_prev_next <= phi2_sync;
+	
+	addr_in <= bus_addr_sync;
+	data_in <= bus_data_sync;
+	rw_n <= bus_rw_sync;	
+	s4 <= bus_s4_sync;
+	s5 <= bus_s5_sync;
+	ctl <= bus_ctl_sync;
+
+	process(data_out, phi2_sync, phi_edge_prev_reg, drive_bus_shift_reg, bus_data_out_reg, bus_rw_sync)
+	begin
+		bus_request <= '0';
+		drive_bus_shift_next <= drive_bus_shift_reg(2 downto 0)&'0';
+		bus_data_out_next <= bus_data_out_reg;
+		if (phi2_sync = '1' and phi_edge_prev_reg='0') then -- rising edge (delayed 3 cycles - we have 7 to do our output...)
+			bus_request <= '1';
+			drive_bus_shift_next(0) <= not(bus_rw_sync); -- driven for 4 cycles
+			bus_data_out_next <= data_out;
+		end if;
+		bus_drive <= or_reduce(drive_bus_shift_reg(3 downto 0));
+		
+	end process;
+	
+	bus_data_out <= bus_data_out_reg;
+				 
+end vhdl;

Property changes on: ultimate_cart/veronica/slave_timing_6502.vhd
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/store.v
===================================================================
--- ultimate_cart/veronica/store.v	(nonexistent)
+++ ultimate_cart/veronica/store.v	(revision 438)
@@ -0,0 +1,274 @@
+// ============================================================================
+//        __
+//   \\__/ o\    (C) 2013, 2014  Robert Finch, Stratford
+//    \  __ /    All rights reserved.
+//     \/_//     robfinch<remove>@opencores.org
+//       ||
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU Lesser General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or     
+// (at your option) any later version.                                      
+//                                                                          
+// This source file is distributed in the hope that it will be useful,      
+// but WITHOUT ANY WARRANTY; without even the implied warranty of           
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
+// GNU General Public License for more details.                             
+//                                                                          
+// You should have received a copy of the GNU General Public License        
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
+//                                                            
+// Memory store states
+// The store states work for 8, 16 or 32 bit mode              
+// ============================================================================
+//
+// Stores always write through to memory, then optionally update the cache if
+// there was a write hit.
+STORE1:
+	begin
+		case(store_what)
+		`STW_ACC8:	data_write(acc[7:0]);
+		`STW_X8:	data_write(x[7:0]);
+		`STW_Y8:	data_write(y[7:0]);
+		`STW_Z8:	data_write(8'h00);
+		
+		`STW_PC2316:	data_write(pc[23:16]);
+		`STW_PC158:		data_write(pc[15:8]);
+		`STW_PC70:		data_write(pc[7:0]);
+		`STW_SR70:		data_write(sr8);
+		`STW_DEF8:		data_write(wdat);
+		`STW_DEF70:		begin data_write(wdat); mlb <= 1'b1; end
+		`STW_DEF158:	data_write(wdat[15:8]);
+		`STW_DEF2316:	data_write(wdat[23:16]);
+		`STW_ACC70:		begin data_write(acc); mlb <= 1'b1; end
+		`STW_ACC158:	data_write(acc[15:8]);
+		`STW_X70:		begin data_write(x); mlb <= 1'b1; end
+		`STW_X158:		data_write(x[15:8]);
+		`STW_Y70:		begin data_write(y); mlb <= 1'b1; end
+		`STW_Y158:		data_write(y[15:8]);
+		`STW_Z70:		begin data_write(8'h00); mlb <= 1'b1; end
+		`STW_Z158:		data_write(8'h00);
+		`STW_DBR:		data_write(dbr);
+		`STW_DPR158:	begin data_write(dpr[15:8]); mlb<= 1'b1; end
+		`STW_DPR70:		data_write(dpr);
+		`STW_TMP158:	begin data_write(tmp16[15:8]); mlb <= 1'b1; end
+		`STW_TMP70:		data_write(tmp16);
+		`STW_IA158:		begin data_write(ia[15:8]); mlb <= 1'b1; end
+		`STW_IA70:		data_write(ia);
+		default:	data_write(wdat);
+		endcase
+`ifdef SUPPORT_DCACHE
+		radr <= wadr;		// Do a cache read to test the hit
+`endif
+		state <= STORE2;
+	end
+	
+// Terminal state for stores. Update the data cache if there was a cache hit.
+// Clear any previously set lock status
+STORE2:
+	if (rdy) begin
+//		wdat <= dat_o;
+		mlb <= 1'b0;
+		data_nack();
+		if (!em && (isMove|isSts)) begin
+			state <= MVN3;
+			retstate <= MVN3;
+		end
+		else begin
+			if (em) begin
+				if (isMove) begin
+					state <= MVN816;
+					retstate <= MVN816;
+				end
+				else begin
+					moveto_ifetch();
+					retstate <= IFETCH1;
+				end
+			end
+			else begin
+				moveto_ifetch();
+				retstate <= IFETCH1;
+			end
+		end
+		case(store_what)
+		`STW_DEF70:
+			begin
+				wadr <= wadr + 24'd1;
+				store_what <= `STW_DEF158;
+				retstate <= STORE1;
+				if ((b16[15:8]!=wdat[15:8]) || !STORE_SKIPPING || isTribyte) begin
+					mlb <= 1'b1;
+					vpa <= `FALSE;	// override moveto_ifetch() setting.
+					vda <= `FALSE;
+					state <= STORE1;
+				end
+			end
+		`STW_DEF158:
+			if (isTribyte) begin
+				mlb <= 1'b1;
+				wadr <= wadr + 24'd1;
+				vpa <= `FALSE;	// override moveto_ifetch() setting.
+				vda <= `FALSE;
+				store_what <= `STW_DEF2316;
+				state <= STORE1;
+			end
+		`STW_ACC70:
+			begin
+				mlb <= 1'b1;
+				wadr <= wadr + 24'd1;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_ACC158;
+				state <= STORE1;
+			end
+		`STW_X70:
+			begin
+				mlb <= 1'b1;
+				wadr <= wadr + 24'd1;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_X158;
+				state <= STORE1;
+			end
+		`STW_Y70:
+			begin
+				mlb <= 1'b1;
+				wadr <= wadr + 24'd1;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_Y158;
+				state <= STORE1;
+			end
+		`STW_Z70:
+			begin
+				mlb <= 1'b1;
+				wadr <= wadr + 24'd1;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_Z158;
+				state <= STORE1;
+			end
+		`STW_DPR158:
+			begin
+				set_sp();
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_DPR70;
+				state <= STORE1;
+			end
+		`STW_TMP158:
+			begin
+				set_sp();
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_TMP70;
+				state <= STORE1;
+			end
+		`STW_IA158:
+			begin
+				set_sp();
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_IA70;
+				state <= STORE1;
+			end
+		`STW_PC2316:
+			begin
+				if (ir9 != `PHK) begin
+					set_sp();
+					vpa <= `FALSE;
+					vda <= `FALSE;
+					store_what <= `STW_PC158;
+					state <= STORE1;
+				end
+			end
+		`STW_PC158:
+			begin
+				set_sp();
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				store_what <= `STW_PC70;
+				state <= STORE1;
+			end
+		`STW_PC70:
+			begin
+				case({1'b0,ir[7:0]})
+				`BRK,`COP:
+						begin
+						set_sp();
+						vpa <= `FALSE;
+						vda <= `FALSE;
+						store_what <= `STW_SR70;
+						state <= STORE1;
+						end
+				`JSR: 	begin
+						pc[15:0] <= ir[23:8];
+						ado <= {pc[23:16],ir[23:8]};
+						end
+				`JSL: 	begin
+						pc[23:0] <= ir[31:8];
+						ado <= ir[31:8];
+						end
+				`JSR_INDX:
+						begin
+						vpa <= `FALSE;
+						vda <= `FALSE;
+						state <= LOAD_MAC1;
+						load_what <= `PC_70;
+						radr <= absx_address;
+						end
+				endcase
+			end
+		`STW_SR70:
+			begin
+				if (ir[7:0]==`BRK) begin
+					load_what <= `PC_70;
+					state <= LOAD_MAC1;
+					vpa <= `FALSE;
+					vda <= `FALSE;
+					pc[23:16] <= 8'h00;//abs8[23:16];
+					radr <= vect;
+					im <= hwi;
+					df <= 1'b0;
+				end
+				else if (ir[7:0]==`COP) begin
+					load_what <= `PC_70;
+					vpa <= `FALSE;
+					vda <= `FALSE;
+					state <= LOAD_MAC1;
+					pc[23:16] <= 8'h00;//abs8[23:16];
+					radr <= vect;
+					im <= 1'b1;
+				end
+			end
+		default:
+			if (isJsrIndx) begin
+				load_what <= `PC_310;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				state <= LOAD_MAC1;
+				radr <= ir[31:8] + x;
+			end
+			else if (isJsrInd) begin
+				load_what <= `PC_310;
+				vpa <= `FALSE;
+				vda <= `FALSE;
+				state <= LOAD_MAC1;
+				radr <= ir[31:8];
+			end
+		endcase
+`ifdef SUPPORT_DCACHE
+		if (!dhit && write_allocate) begin
+			state <= DCACHE1;
+		end
+`endif
+	end
+`ifdef SUPPORT_BERR
+	else if (err_i) begin
+		mlb <= 1'b0;
+		data_nack();
+		derr_address <= ado[23:0];
+		intno <= 9'd508;
+		state <= BUS_ERROR;
+	end
+`endif
Index: ultimate_cart/veronica/veronica.qpf
===================================================================
--- ultimate_cart/veronica/veronica.qpf	(nonexistent)
+++ ultimate_cart/veronica/veronica.qpf	(revision 438)
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 08:06:31  April 05, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.1"
+DATE = "08:06:31  April 05, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "veronica"

Property changes on: ultimate_cart/veronica/veronica.qpf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/veronica.qsf.bak
===================================================================
--- ultimate_cart/veronica/veronica.qsf.bak	(nonexistent)
+++ ultimate_cart/veronica/veronica.qsf.bak	(revision 438)
@@ -0,0 +1,66 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+# Date created = 08:06:31  April 05, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		veronica_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M08SAE144C8G
+set_global_assignment -name TOP_LEVEL_ENTITY veronica
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:06:31  APRIL 05, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name VERILOG_FILE BCDMath.v
+set_global_assignment -name VHDL_FILE veronica.vhd
+set_global_assignment -name VERILOG_FILE FT816.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name QIP_FILE pll_veronica.qip
\ No newline at end of file

Property changes on: ultimate_cart/veronica/veronica.qsf.bak
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ultimate_cart/veronica/veronica.vhd
===================================================================
--- ultimate_cart/veronica/veronica.vhd	(nonexistent)
+++ ultimate_cart/veronica/veronica.vhd	(revision 438)
@@ -0,0 +1,342 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY veronica IS
+	PORT (
+				CLK: in std_logic;
+				LED: out std_logic_vector(0 downto 0);
+				
+				CART_ADDR: in std_logic_vector(12 downto 0);
+				CART_DATA: inout std_logic_vector(7 downto 0);
+				CART_RD5: out std_logic;
+				CART_RD4: out std_logic;
+				CART_S5: in std_logic;
+				CART_S4: in std_logic;
+				CART_PHI2: in std_logic;
+				CART_CTL: in std_logic;
+				CART_RW: in std_logic;
+				
+				SD_CARD_cs: out std_logic;
+				SD_CARD_sclk: out std_logic;
+				SD_CARD_mosi: out std_logic;
+				SD_CARD_miso: in std_logic;
+				
+				EXT_SRAM_ADDR: out std_logic_vector(19 downto 0);
+				EXT_SRAM_DATA: inout std_logic_vector(7 downto 0);
+				EXT_SRAM_CE: out std_logic;
+				EXT_SRAM_OE: out std_logic;
+				EXT_SRAM_WE: out std_logic
+			);
+END veronica;
+
+ARCHITECTURE vhdl OF veronica IS
+
+component FT816 is
+port(
+	rst : in std_logic;
+	clk : in std_logic;
+
+	-- Various clock outputs - perhaps useful for memory layer?
+	clko : out std_logic;
+	cyc : out std_logic_vector(4 downto 0);
+	phi11 : out std_logic;
+	phi12 : out std_logic;
+	phi81 : out std_logic;
+	phi82 : out std_logic;
+
+	nmi : in std_logic; -- active low
+	irq : in std_logic; -- active low
+
+	rdy : in std_logic;   -- good old rdy!
+
+	-- Some unknown inputs
+	abort : in std_logic; -- another interrupt (active low)
+	be : in std_logic;    -- bus enable (active high)
+	err_i : in std_logic; -- set to 1 in example
+	rty_i : in std_logic; -- set to 1 in example
+
+	-- Some unknown outputs
+	vpa : out std_logic; -- valid program address
+	vda : out std_logic; -- valid data address (both high for op code??)
+	mlb : out std_logic; -- memory busy
+	vpb : out std_logic; -- ?
+	e : out std_logic;   -- !m816 (emulation pin)
+	mx : out std_logic;  -- status bits? m_bit when clk high, x_bit when clk low
+
+	-- data and address bus
+	ad : out std_logic_vector(23 downto 0);
+	rw : out std_logic;
+	db : in std_logic_vector(7 downto 0);
+	dw : out std_logic_Vector(7 downto 0)
+	);
+end component;
+
+	signal clk_adj : std_logic;
+	signal clk_adj7x : std_logic;
+	signal reset_n : std_logic;
+	
+	signal veronica_reset : std_logic;
+
+	-- 65816 bus
+	signal veronica_address : std_logic_vector(23 downto 0);
+	signal veronica_read_data : std_logic_vector(7 downto 0);
+	signal veronica_write_data : std_logic_vector(7 downto 0);
+	signal veronica_w_n : std_logic;
+	signal veronica_config_w_n : std_logic;
+	
+	-- 6502 bus
+	signal atari_bus_request : std_logic;	
+	signal atari_address : std_logic_vector(12 downto 0);
+	signal atari_data_bus : std_logic_vector(7 downto 0);
+	signal atari_read_data : std_logic_vector(7 downto 0);
+	signal atari_write_data : std_logic_vector(7 downto 0);
+	signal atari_w_n : std_logic;
+	signal atari_config_w_n : std_logic;
+	signal atari_s4 : std_logic;
+	signal atari_s5 : std_logic;
+	signal atari_ctl : std_logic;
+	
+	-- address decode
+	signal veronica_config_select : std_logic;	
+	signal veronica_sram_select : std_logic;
+	signal veronica_sram_address: std_logic_vector(16 downto 0);	
+	signal atari_config_select : std_logic;
+	signal atari_sram_select : std_logic;	
+	signal atari_sram_address: std_logic_vector(16 downto 0);
+
+	-- veronica config
+	signal veronica_window_address : std_logic;
+	signal veronica_bank_half_select : std_logic;	
+	signal veronica_config_data : std_logic_vector(7 downto 0);
+	
+	-- atari config
+	signal atari_banka_enable : std_logic;
+	signal atari_bank8_enable : std_logic;
+	signal atari_bank_half_select : std_logic;
+	signal atari_config_data : std_logic_vector(7 downto 0);
+
+	-- common config
+	signal common_sem : std_logic;	
+	signal common_bank_select : std_logic;
+	
+	-- cart driving
+	signal cart_bus_data_out : std_logic_vector(7 downto 0);
+	signal cart_bus_drive : std_logic;
+	
+	-- sram driving
+	signal sram_write_data : std_logic_vector(7 downto 0);
+	signal sram_drive_data : std_logic;
+	signal sram_read_data : std_logic_vector(7 downto 0);
+	
+begin
+	
+
+	pll1:work.pll_veronica
+	PORT map
+	(
+		inclk0 => clk,
+		c0 => clk_adj,     -- 14MHz (>70ns/cycle)
+		c1 => clk_adj7x,   -- 70MHz
+		locked => reset_n 
+	);
+	
+
+	cpu_65816_rob:FT816
+		port map (
+			rst => reset_n and veronica_reset,
+			clk => clk_adj,
+			nmi => '1',
+			irq => '1',
+			rdy => not(atari_bus_request), -- 6502 priority for sram access!
+			abort => '1',
+			be => '1',
+			err_i => '1',
+			rty_i => '1',
+			ad => veronica_address,
+			rw => veronica_w_n,
+			dw => veronica_write_data,
+			db => veronica_read_data
+		);
+		
+	SD_CARD_cs <= 'Z';
+	SD_CARD_sclk <= 'Z';
+	LED(0) <= '1';
+
+	veronica_config_w_n <= veronica_w_n or not(veronica_config_select);
+	
+	glue1: entity work.config_regs_veronica
+	port map
+	(
+		clk => clk_adj,
+		reset_n => reset_n,
+		
+		sem_in => common_sem,
+		window_address => veronica_window_address,
+		bank_half_select => veronica_bank_half_select,
+		
+		data_in => veronica_write_data,
+		data_out => veronica_config_data,
+		rw_n => veronica_config_w_n
+	);
+	
+	
+	atari_config_w_n <= atari_w_n or not(atari_config_select);
+	
+	glue2: entity work.config_regs_6502
+	port map
+	(
+		clk => clk_adj,
+		reset_n => reset_n,	
+	
+		sem_out => common_sem,
+		banka_enable => atari_banka_enable,
+		bank8_enable => atari_bank8_enable,
+		bank_half_select => atari_bank_half_select,
+		bank_select => common_bank_select,
+		enable_65816 => veronica_reset,
+		
+		data_in => atari_write_data,
+		data_out => atari_config_data,
+		rw_n => atari_config_w_n		
+	);	
+	
+	glue3: entity work.slave_timing_6502
+	port map
+	(
+		clk => clk_adj,
+		reset_n => reset_n,
+		phi2 => CART_PHI2,
+		bus_addr => CART_ADDR,
+		bus_data => CART_DATA,
+		bus_ctl => CART_CTL,
+		bus_rw => CART_RW,
+		bus_s4 => CART_S4,
+		bus_s5 => CART_S5,
+		
+		bus_data_out => cart_bus_data_out,
+		bus_drive => cart_bus_drive,
+		
+		s4 => atari_s4,
+		s5 => atari_s5,
+		ctl => atari_ctl,
+		addr_in => atari_address,
+		data_in => atari_write_data,
+		data_out => atari_read_data,
+		rw_n => atari_w_n,
+		bus_request => atari_bus_request
+	);
+	CART_DATA <= cart_bus_data_out when cart_bus_drive='1' else (others=>'Z');
+
+	glue4: entity work.atari_address_decoder
+	port map
+	(	
+		s4 => atari_s4,
+		s5 => atari_s5,
+		ctl => atari_ctl,
+		addr_in => atari_address,
+		bus_request => atari_bus_request,
+		
+		bank_half_select => atari_bank_half_select,
+		bank_select => common_bank_select,
+		
+		config_select => atari_config_select,
+		sram_select => atari_sram_select,
+		sram_address => atari_sram_address
+	);
+	
+	glue5: entity work.veronica_address_decoder
+	port map
+	(
+			addr_in => veronica_address(15 downto 0),
+			
+			window_address => veronica_window_address,
+			bank_half_select => veronica_bank_half_select,
+			bank_select => common_bank_select,	
+			
+			config_select => veronica_config_select,
+			sram_select => veronica_sram_select,
+			sram_address => veronica_sram_address
+	);
+
+	glue6: entity work.sram_mux
+	port map
+	(
+		clk => clk_adj,
+		clk7x => clk_adj7x,
+		reset_n => reset_n,
+		
+		sram_addr => EXT_SRAM_ADDR,
+		sram_data_out => sram_write_data,
+		sram_drive_data => sram_drive_data,
+		sram_we_n => EXT_SRAM_WE,
+
+		atari_bus_request => atari_bus_request,
+		atari_sram_select => atari_sram_select,
+		atari_address => atari_sram_address,
+		atari_w_n => atari_w_n,
+		atari_write_data => atari_write_data,
+		
+		veronica_address => veronica_sram_address,
+		veronica_sram_select => veronica_sram_select,
+		veronica_w_n => veronica_w_n,
+		veronica_write_data => veronica_write_data
+	);
+	
+	EXT_SRAM_DATA <= sram_write_data when sram_drive_data='1' else (others=>'Z');
+	EXT_SRAM_OE <= '0';
+	sram_read_data <= EXT_SRAM_DATA;
+	
+	glue7: entity work.output_mux
+	port map
+	(
+		config_select => atari_config_select,
+		sram_select => atari_sram_select,
+		
+		config_data => atari_config_data,
+		sram_data => sram_read_data,
+		
+		read_data => atari_read_data	
+	);
+	
+	glue8: entity work.output_mux
+	port map
+	(
+		config_select => veronica_config_select,
+		sram_select => veronica_sram_select,
+		
+		config_data => veronica_config_data,
+		sram_data => sram_read_data,
+		
+		read_data => veronica_read_data
+	);
+	
+	EXT_SRAM_CE <= '0';
+	
+	cart_rd4 <= '1' when atari_bank8_enable='1' else 'Z';
+	cart_rd5 <= '1' when atari_banka_enable='1' else 'Z';
+	
+	sd_card_mosi <= 'Z';
+
+-- DONE:Instantiate 65816 (review 2 changes needed - one in particular deleted something, still needed?)
+
+-- SRAM adaptor for 6502 and 65816 (55ns SRAM)
+
+-- veronica reg
+-- 64KB - 65816
+-- 32KB - bank1 (either 6502 or 65816)
+-- 32KB - bank2 (either 6502 or 65816)
+
+-- 65816 memory map:
+-- 0x0000-0xffff - first 64k (-below...)
+-- 0x0200-0x020f - control reg
+--	7-semaphore
+--      6-window at 0xc0000-0xffff(0) or 0x4000-7fff
+--      5-0=half A,1=half B
+--      4-0 res (read as 1)
+-- 6502 memory map:
+-- in cart space...
+
+-- How to mux ram access? 1/8 6502 and 7/8 65816?
+
+end vhdl;
