Index: mcc216/atari800core.qsf
===================================================================
--- mcc216/atari800core.qsf	(revision 44)
+++ mcc216/atari800core.qsf	(revision 45)
@@ -296,6 +296,7 @@
 set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
 set_global_assignment -name SDC_FILE atari800core.sdc
 set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
 set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
 
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: mcc216/atari800core_mcc.vhd
===================================================================
--- mcc216/atari800core_mcc.vhd	(revision 44)
+++ mcc216/atari800core_mcc.vhd	(revision 45)
@@ -281,9 +281,6 @@
 	SIGNAL CONSOL_SELECT : std_logic;
 	SIGNAL CONSOL_OPTION : std_logic;
 
-	-- 6502 throttling
-	SIGNAL THROTTLE_COUNT_6502 : std_logic_vector(5 downto 0);
-
 	-- scandoubler
 	signal scandouble_clk : std_logic;
 
@@ -305,6 +302,37 @@
 	signal svideo_y : std_logic_vector(7 downto 0);
 	signal svideo_c : std_logic_vector(5 downto 0);
 
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
 BEGIN 
 
 dac_left : hq_dac
@@ -374,8 +402,6 @@
 JOY1_IN_N <= JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3);
 JOY2_IN_N <= JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3);
 
--- THROTTLE
-THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(1,6));
 
 --atari800xl : entity work.atari800core_helloworld
 --	GENERIC MAP
@@ -462,9 +488,9 @@
 		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
 		KEYBOARD_SCAN => KEYBOARD_SCAN,
 
-		SIO_COMMAND => open,
-		SIO_RXD => '1',
-		SIO_TXD => open,
+		SIO_COMMAND => zpu_sio_command,
+		SIO_RXD => zpu_sio_txd,
+		SIO_TXD => zpu_sio_rxd,
 
 		CONSOL_OPTION => CONSOL_OPTION,
 		CONSOL_SELECT => CONSOL_SELECT,
@@ -482,20 +508,21 @@
 		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
 		SDRAM_REFRESH => SDRAM_REFRESH,
 
-		DMA_FETCH => '0',
-		DMA_READ_ENABLE => '0',
-		DMA_32BIT_WRITE_ENABLE => '0',
-		DMA_16BIT_WRITE_ENABLE => '0',
-		DMA_8BIT_WRITE_ENABLE => '0',
-		DMA_ADDR => (others=>'1'),
-		DMA_WRITE_DATA => (others=>'1'),
-		MEMORY_READY_DMA => open,
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
 
-   		RAM_SELECT => (others=>'0'),
+   		RAM_SELECT => ram_select,
     		ROM_SELECT => "000001",
 		PAL => PAL,
-		HALT => '0',
-		THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
+		HALT => pause_atari,
+		THROTTLE_COUNT_6502 => speed_6502
 	);
 
 	process(clk_sdram,sdram_reset_ctrl_n_reg)
@@ -546,12 +573,15 @@
 		end if;
 	end process;
 
-	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg)
+	process(seq_reg, seq_next, sdram_rdy, sdram_reset_n_reg, reset_atari)
 	begin
 		sdram_reset_n_next <= sdram_reset_n_reg;
 		if (sdram_rdy = '1' and seq_next(8)='1' and seq_reg(8)='0') then
 			sdram_reset_n_next <= '1';
 		end if;
+		if (reset_atari = '1') then
+			sdram_reset_n_next <= '0';
+		end if;
 	end process;
 
 	-- Adapt SDRAM
@@ -581,7 +611,7 @@
 				if (SDRAM_WIDTH_8BIT_ACCESS = '1') then
 					ram_di_next <= (others=>'0');
 				else
-					ram_di_next <= SDRAM_DI(15 downto 0);
+					ram_di_next <= SDRAM_DI(31 downto 16);
 					ram_bena_next <= "11";
 				end if;
 			end if;
@@ -706,9 +736,9 @@
 	end generate;
 
 	gen_scandouble_on: if scandouble=1 generate
-		process(scandouble_clk,reset_n)
+		process(scandouble_clk,sdram_reset_n_reg)
 		begin
-			if (reset_n='0') then
+			if (sdram_reset_n_reg='0') then
 				half_scandouble_enable_reg <= '0';
 			elsif (scandouble_clk'event and scandouble_clk='1') then
 				half_scandouble_enable_reg <= half_scandouble_enable_next;
@@ -721,7 +751,7 @@
 		PORT MAP
 		( 
 			CLK => SCANDOUBLE_CLK,
-		        RESET_N => RESET_N and sdram_rdy,
+		        RESET_N => sdram_reset_n_reg,
 			
 			VGA => '1',
 			COMPOSITE_ON_HSYNC => '0', -- TODO
@@ -777,4 +807,76 @@
 
 end generate;
 
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1 -- TODO
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_rdy,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_dat0,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_dat3,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"00000000",
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>16) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
 END vhdl;
Index: mcc216/build.sh
===================================================================
--- mcc216/build.sh	(revision 44)
+++ mcc216/build.sh	(revision 45)
@@ -73,10 +73,11 @@
 	`cp atari800core_mcc.vhd $dir`;
 	`cp *pll*.* $dir`;
 	`cp sdram_ctrl_3_ports.v $dir`;
+	`cp zpu_rom.vhdl $dir`;
 	`cp atari800core.sdc $dir`;
 
 	chdir $dir;
-	`../makeqsf ../atari800core.qsf ../svideo ../../common/a8core ../../common/components`;
+	`../makeqsf ../atari800core.qsf ../svideo ../../common/a8core ../../common/components ../../common/zpu`;
 
 	foreach my $key (sort keys %{$variants{$variant}})
 	{
Index: mcc216/simulate_full.sh
===================================================================
--- mcc216/simulate_full.sh	(revision 44)
+++ mcc216/simulate_full.sh	(revision 45)
@@ -32,7 +32,10 @@
 	cp `find ../../common/a8core/ -iname "*.vhdl"` .
 	cp `find ../../common/components/ -iname "*.vhd"` .
 	cp `find ../../common/components/ -iname "*.vhdl"` .
+	cp `find ../../common/zpu/ -iname "*.vhd"` .
+	cp `find ../../common/zpu/ -iname "*.vhdl"` .
 	cp ../atari800core_mcc.vhd .
+	cp ../zpu_rom.vhdl .
 	cp ../sdram_ctrl_3_ports.v .
 	cp ../*pll*.vhd* .
 	cp ../svideo/* .
Index: mcc216/zpu_rom.vhdl
===================================================================
--- mcc216/zpu_rom.vhdl	(nonexistent)
+++ mcc216/zpu_rom.vhdl	(revision 45)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80db",
+X"9c738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80e0",
+X"ac0c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580d6",
+X"e72d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580d4fb",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"8d9f0480",
+X"3d0d80e1",
+X"c4087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80e1",
+X"c4087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80e1c408",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80e1c408",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"e1c40870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"e1c40870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80e1c408",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80e1c408",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80e1c4",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80e1c4",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80e1b4",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d848080",
+X"53805288",
+X"800a51ff",
+X"b33f8180",
+X"80538052",
+X"82800a51",
+X"c63f843d",
+X"0d04803d",
+X"0d8151fd",
+X"dc3f7280",
+X"2e8338d2",
+X"3f8051fd",
+X"d03f8051",
+X"fd9d3f82",
+X"3d0d04fd",
+X"3d0d7552",
+X"805480ff",
+X"72258838",
+X"810bff80",
+X"135354ff",
+X"bf125170",
+X"99268638",
+X"e012529e",
+X"39ff9f12",
+X"51997127",
+X"9538d012",
+X"e0137054",
+X"54518971",
+X"2788388f",
+X"73278338",
+X"80527380",
+X"2e853881",
+X"80125271",
+X"81ff0683",
+X"e0800c85",
+X"3d0d0480",
+X"3d0d823d",
+X"0d04ff3d",
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+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
