Index: ultimate_cart/veronica/cpu65816.wcfg
===================================================================
--- ultimate_cart/veronica/cpu65816.wcfg	(revision 452)
+++ ultimate_cart/veronica/cpu65816.wcfg	(revision 453)
@@ -18,7 +18,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="40" />
+   <WVObjectSize size="49" />
    <wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/rst" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">rst</obj_property>
       <obj_property name="ObjectShortName">rst</obj_property>
@@ -27,6 +27,10 @@
       <obj_property name="ElementShortName">clk</obj_property>
       <obj_property name="ObjectShortName">clk</obj_property>
    </wvobject>
+   <wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">state[5:0]</obj_property>
+      <obj_property name="ObjectShortName">state[5:0]</obj_property>
+   </wvobject>
    <wvobject fp_name="divider60" type="divider">
       <obj_property name="label">Input</obj_property>
       <obj_property name="DisplayName">label</obj_property>
@@ -109,6 +113,16 @@
       <obj_property name="ObjectShortName">ad[23:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
+   <wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/ado" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ado[23:0]</obj_property>
+      <obj_property name="ObjectShortName">ado[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/sp" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sp[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sp[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
    <wvobject fp_name="/veronica_tb/thebigone/cpu_65816_rob/dw" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">dw[7:0]</obj_property>
       <obj_property name="ObjectShortName">dw[7:0]</obj_property>
@@ -180,10 +194,12 @@
    <wvobject fp_name="/veronica_tb/thebigone/glue6/sram_addr" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">sram_addr[19:0]</obj_property>
       <obj_property name="ObjectShortName">sram_addr[19:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
    <wvobject fp_name="/veronica_tb/thebigone/glue6/sram_data_out" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">sram_data_out[7:0]</obj_property>
       <obj_property name="ObjectShortName">sram_data_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
    <wvobject fp_name="/veronica_tb/thebigone/glue6/sram_drive_data" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">sram_drive_data</obj_property>
@@ -193,4 +209,30 @@
       <obj_property name="ElementShortName">sram_we_n</obj_property>
       <obj_property name="ObjectShortName">sram_we_n</obj_property>
    </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/nwe" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">nwe</obj_property>
+      <obj_property name="ObjectShortName">nwe</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/nce" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">nce</obj_property>
+      <obj_property name="ObjectShortName">nce</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/noe" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">noe</obj_property>
+      <obj_property name="ObjectShortName">noe</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">a[16:0]</obj_property>
+      <obj_property name="ObjectShortName">a[16:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/d" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">d[7:0]</obj_property>
+      <obj_property name="ObjectShortName">d[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/veronica_tb/sram_model/read_active" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">read_active</obj_property>
+      <obj_property name="ObjectShortName">read_active</obj_property>
+   </wvobject>
 </wave_config>
Index: ultimate_cart/veronica/tb_veronica/sram.vhd
===================================================================
--- ultimate_cart/veronica/tb_veronica/sram.vhd	(revision 452)
+++ ultimate_cart/veronica/tb_veronica/sram.vhd	(revision 453)
@@ -419,7 +419,7 @@
                undef_adr_vec;
 
   read_active <=    (     (nOE = '0') AND (nOE'DELAYED(tLZOE_min) = '0') AND nOE'STABLE(tLZOE_min) 
-                      AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '0'))
+                      AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '1'))
                       AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tLZCE_min) AND CE2'STABLE(tLZCE_min))
                  OR (read_active AND (nOE'DELAYED(tHZOE_max) = '0') 
                                  AND (nWE'DELAYED(tHZWE_max) = '1')
Index: ultimate_cart/veronica/tb_veronica/veronica_tb.vhd
===================================================================
--- ultimate_cart/veronica/tb_veronica/veronica_tb.vhd	(revision 452)
+++ ultimate_cart/veronica/tb_veronica/veronica_tb.vhd	(revision 453)
@@ -274,86 +274,65 @@
 	CART_S5 <= bus_s5_n when bus_control_oe='1' else 'Z';
 	CART_CTL <= bus_cctl_n when bus_control_oe='1' else 'Z';
 
---	sram_model : entity work.sram
---	generic map
---	(
---		clear_on_power_up: boolean := FALSE;    -- if TRUE, RAM is initialized with zeroes at start of simulation
---		                                        -- Clearing of RAM is carried out before download takes place
---		
---		download_on_power_up: boolean := TRUE;  -- if TRUE, RAM is downloaded at start of simulation 
---		  
---		trace_ram_load: boolean := TRUE;        -- Echoes the data downloaded to the RAM on the screen
---		                                        -- (included for debugging purposes)
---		
---		
---		enable_nWE_only_control: boolean := TRUE;  -- Read-/write access controlled by nWE only
---		                                           -- nOE may be kept active all the time
---		
---		
---		
---		-- Configuring RAM size
---		
---		size:      INTEGER :=  8;  -- number of memory words
---		adr_width: INTEGER :=  3;  -- number of address bits
---		width:     INTEGER :=  8;  -- number of bits per memory word
---		
---		
---		-- READ-cycle timing parameters
---		
---		tAA_max:    TIME := 20 NS; -- Address Access Time
---		tOHA_min:   TIME :=  3 NS; -- Output Hold Time
---		tACE_max:   TIME := 20 NS; -- nCE/CE2 Access Time
---		tDOE_max:   TIME :=  8 NS; -- nOE Access Time
---		tLZOE_min:  TIME :=  0 NS; -- nOE to Low-Z Output
---		tHZOE_max:  TIME :=  8 NS; --  OE to High-Z Output
---		tLZCE_min:  TIME :=  3 NS; -- nCE/CE2 to Low-Z Output
---		tHZCE_max:  TIME := 10 NS; --  CE/nCE2 to High Z Output
---		
---		
---		-- WRITE-cycle timing parameters
---		
---		tWC_min:    TIME := 20 NS; -- Write Cycle Time
---		tSCE_min:   TIME := 18 NS; -- nCE/CE2 to Write End
---		tAW_min:    TIME := 15 NS; -- tAW Address Set-up Time to Write End
---		tHA_min:    TIME :=  0 NS; -- tHA Address Hold from Write End
---		tSA_min:    TIME :=  0 NS; -- Address Set-up Time
---		tPWE_min:   TIME := 13 NS; -- nWE Pulse Width
---		tSD_min:    TIME := 10 NS; -- Data Set-up to Write End
---		tHD_min:    TIME :=  0 NS; -- Data Hold from Write End
---		tHZWE_max:  TIME := 10 NS; -- nWE Low to High-Z Output
---		tLZWE_min:  TIME :=  0 NS  -- nWE High to Low-Z Output
---	);
---	port map
---	(
---		nCE: IN std_logic := '1';  -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
---		nOE: IN std_logic := '1';  -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
---		nWE: IN std_logic := '1';  -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
---		
---		A:   IN std_logic_vector(adr_width-1 downto 0); -- address bus of the SRAM device
---		D:   INOUT std_logic_vector(width-1 downto 0);  -- bidirectional data bus to/from the SRAM device
---		
---		CE2: IN std_logic := '1';  -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
---		
---		
---		download: IN boolean := FALSE;    -- A FALSE-to-TRUE transition on this signal downloads the data
---		                                  -- in file specified by download_filename to the RAM
---		
---		download_filename: IN string := "sram_load.dat";  -- name of the download source file
---		                                                  --            Passing the filename via a port of type
---		                                                  -- ********** string may cause a problem with some
---		                                                  -- WATCH OUT! simulators. The string signal assigned
---		                                                  -- ********** to the port at least should have the
---		                                                  --            same length as the default value.
---		
---		dump: IN boolean := FALSE;       -- A FALSE-to-TRUE transition on this signal dumps
---		                                 -- the current content of the memory to the file
---		                                 -- specified by dump_filename.
---		dump_start: IN natural := 0;     -- Written to the dump-file are the memory words from memory address 
---		dump_end: IN natural := size-1;  -- dump_start to address dump_end (default: all addresses)
---		
---		dump_filename: IN string := "sram_dump.dat"  -- name of the dump destination file
---                                                 -- (See note at port  download_filename)
---	);
+	sram_model : entity work.sram
+	generic map
+	(
+		clear_on_power_up => TRUE,
+		                                        -- Clearing of RAM is carried out before download takes place
+		download_on_power_up => FALSE,  -- if TRUE, RAM is downloaded at start of simulation 
+		  
+		trace_ram_load => TRUE,        -- Echoes the data downloaded to the RAM on the screen
+		                                        -- (included for debugging purposes)
+		
+		enable_nWE_only_control => TRUE,  -- Read-/write access controlled by nWE only
+		                                           -- nOE may be kept active all the time
+		
+		-- Configuring RAM size
+		
+		size => 131072,  -- number of memory words
+		adr_width => 17,  -- number of address bits
+		width => 8,  -- number of bits per memory word
+		
+		
+		-- READ-cycle timing parameters
+		
+		tAA_max  => 55 NS, -- Address Access Time
+		tOHA_min =>  3 NS, -- Output Hold Time
+		tACE_max => 55 NS, -- nCE/CE2 Access Time
+		tDOE_max => 30 NS, -- nOE Access Time
+		tLZOE_min=>  5 NS, -- nOE to Low-Z Output
+		tHZOE_max=> 20 NS, --  OE to High-Z Output
+		tLZCE_min=> 10  NS, -- nCE/CE2 to Low-Z Output
+		tHZCE_max=> 20 NS, --  CE/nCE2 to High Z Output
+		
+		
+		-- WRITE-cycle timing parameters
+		
+		tWC_min => 55 NS, -- Write Cycle Time
+		tSCE_min=> 50 NS, -- nCE/CE2 to Write End
+		tAW_min => 50 NS, -- tAW Address Set-up Time to Write End
+		tHA_min =>  0 NS, -- tHA Address Hold from Write End
+		tSA_min =>  0 NS, -- Address Set-up Time
+		tPWE_min=> 45 NS, -- nWE Pulse Width
+		tSD_min => 25 NS, -- Data Set-up to Write End
+		tHD_min =>  0 NS, -- Data Hold from Write End
+		tHZWE_max=> 20 NS, -- nWE Low to High-Z Output
+		tLZWE_min=>  0 NS  -- nWE High to Low-Z Output
+	)
+	--signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
+	--signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
+	--signal EXT_SRAM_CE: std_logic;
+	--signal EXT_SRAM_OE: std_logic;
+	--signal EXT_SRAM_WE: std_logic;
+	port map
+	(
+		nCE => EXT_SRAM_CE,
+		nOE => EXT_SRAM_OE,
+		nWE => EXT_SRAM_WE,
+		
+		A => EXT_SRAM_ADDR(16 downto 0),
+		D => EXT_SRAM_DATA
+	);
 
 end rtl;
 
