Index: common/antic.cmd
===================================================================
--- common/antic.cmd	(nonexistent)
+++ common/antic.cmd	(revision 61)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: common/antic.wcfg
===================================================================
--- common/antic.wcfg	(nonexistent)
+++ common/antic.wcfg	(revision 61)
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="antic.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="antic_tb" />
+            <top_module name="attributes" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="34" />
+   <wave_markers>
+      <marker time="517213670600" label="" />
+   </wave_markers>
+   <wvobject fp_name="/antic_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cpu_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cpu_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cpu_data_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cpu_wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_wr_en</obj_property>
+      <obj_property name="ObjectShortName">cpu_wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/memory_ready_antic" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready_antic</obj_property>
+      <obj_property name="ObjectShortName">memory_ready_antic</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/memory_ready_cpu" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_ready_cpu</obj_property>
+      <obj_property name="ObjectShortName">memory_ready_cpu</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/memory_data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">memory_data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">memory_data_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic_enable_179" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">antic_enable_179</obj_property>
+      <obj_property name="ObjectShortName">antic_enable_179</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/enable_179_memwait" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_179_memwait</obj_property>
+      <obj_property name="ObjectShortName">enable_179_memwait</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cpu_shared_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpu_shared_enable</obj_property>
+      <obj_property name="ObjectShortName">cpu_shared_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/an" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">an[2:0]</obj_property>
+      <obj_property name="ObjectShortName">an[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cc_out_orig" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cc_out_orig</obj_property>
+      <obj_property name="ObjectShortName">cc_out_orig</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cc_out_used" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cc_out_used</obj_property>
+      <obj_property name="ObjectShortName">cc_out_used</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/cc_out_used_doubled" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cc_out_used_doubled</obj_property>
+      <obj_property name="ObjectShortName">cc_out_used_doubled</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">fetch</obj_property>
+      <obj_property name="ObjectShortName">fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/fetch_address" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fetch_address[15:0]</obj_property>
+      <obj_property name="ObjectShortName">fetch_address[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/refresh" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">refresh</obj_property>
+      <obj_property name="ObjectShortName">refresh</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/hcount_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hcount_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">hcount_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/vcount_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">vcount_out[8:0]</obj_property>
+      <obj_property name="ObjectShortName">vcount_out[8:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_clock_character_name" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_clock_character_name</obj_property>
+      <obj_property name="ObjectShortName">dma_clock_character_name</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_clock_character_inc" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_clock_character_inc</obj_property>
+      <obj_property name="ObjectShortName">dma_clock_character_inc</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_clock_bitmap_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_clock_bitmap_data</obj_property>
+      <obj_property name="ObjectShortName">dma_clock_bitmap_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_clock_character_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_clock_character_data</obj_property>
+      <obj_property name="ObjectShortName">dma_clock_character_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/character_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">character_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">character_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/displayed_character_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">displayed_character_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">displayed_character_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/character_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">character_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">character_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/display_shift_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">display_shift_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">display_shift_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/instruction_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">instruction_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">instruction_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/line_buffer_address_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">line_buffer_address_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">line_buffer_address_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/line_buffer_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">line_buffer_write</obj_property>
+      <obj_property name="ObjectShortName">line_buffer_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/enable_shift" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_shift</obj_property>
+      <obj_property name="ObjectShortName">enable_shift</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/playfield_load" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">playfield_load</obj_property>
+      <obj_property name="ObjectShortName">playfield_load</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/delay_display_shift_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">delay_display_shift_reg[24:0]</obj_property>
+      <obj_property name="ObjectShortName">delay_display_shift_reg[24:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: common/romgen/createall
===================================================================
--- common/romgen/createall	(revision 60)
+++ common/romgen/createall	(revision 61)
@@ -1,7 +1,9 @@
-cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.bin .
-cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.dis .
+#cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.bin .
+#cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.dis .
 ./create_rom.pl 1 ATARIXL.ROM os16 > os16.vhdl
 ./create_rom.pl 1 ATARIBAS.ROM basic > basic.vhdl
-./create_rom.pl 4 HelloTinyROM.bin zpu_rom 12 > zpu_rom.vhdl
-cp *.vhdl ../source/
-cp *.vhdl ../sim/
+./create_rom.pl 4 JustStartAtari.bin zpu_rom 12 > zpu_rom.vhdl
+#./create_rom.pl 4 HelloTinyROM.bin zpu_rom 12 > zpu_rom.vhdl
+#cp *.vhdl ../source/
+#cp *.vhdl ../sim/
+cp zpu_rom.vhdl ../../mcc216/
Index: common/romgen/zpu_rom.vhdl
===================================================================
--- common/romgen/zpu_rom.vhdl	(revision 60)
+++ common/romgen/zpu_rom.vhdl	(revision 61)
@@ -20,7 +20,7 @@
         signal ROM:rom_type:=
 (
 	X"0b0b0b89",
-X"ab040b0b",
+X"ad040b0b",
 X"0b0b0b0b",
 X"0b0b0b0b",
 X"0b0b0b0b",
@@ -180,8 +180,8 @@
 X"00000000",
 X"00000000",
 X"71fc0608",
-X"0b0b0b92",
-X"b8738306",
+X"0b0b80f7",
+X"d0738306",
 X"10100508",
 X"060b0b0b",
 X"88a20400",
@@ -188,7 +188,7 @@
 X"00000000",
 X"00000000",
 X"0b0b0b88",
-X"fe040000",
+X"ff040000",
 X"00000000",
 X"00000000",
 X"00000000",
@@ -227,15 +227,15 @@
 X"00000000",
 X"00000000",
 X"00000000",
-X"810b92c8",
-X"0c510400",
+X"810b80fb",
+X"880c5104",
 X"00000000",
 X"00000000",
 X"00000000",
 X"00000000",
 X"00000000",
-X"00718105",
-X"52040000",
+X"00007181",
+X"05520400",
 X"00000000",
 X"00000000",
 X"00000000",
@@ -250,9 +250,9 @@
 X"00000000",
 X"00000000",
 X"00000000",
-X"00028405",
-X"72101005",
-X"52040000",
+X"00000284",
+X"05721010",
+X"05520400",
 X"00000000",
 X"00000000",
 X"00000000",
@@ -266,15 +266,15 @@
 X"00000000",
 X"00000000",
 X"00000000",
-X"00717105",
-X"ff057153",
-X"51020d04",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
 X"00000000",
 X"00000000",
 X"00000000",
 X"00000000",
 X"00000000",
-X"00000000",
 X"10101010",
 X"10101010",
 X"10101010",
@@ -300,191 +300,3399 @@
 X"83e08008",
 X"83e08408",
 X"83e08808",
-X"75758f82",
+X"757580f2",
+X"802d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580f094",
 X"2d505083",
 X"e0800856",
 X"83e0880c",
 X"83e0840c",
 X"83e0800c",
-X"510483e0",
-X"800883e0",
-X"840883e0",
-X"88087575",
-X"8d962d50",
-X"5083e080",
-X"085683e0",
-X"880c83e0",
-X"840c83e0",
-X"800c5104",
-X"00008004",
-X"89a80489",
-X"a80b8cd8",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"96a10480",
+X"3d0d80fc",
+X"a8087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80fc",
+X"a8087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80fca808",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80fca808",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"fca80870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"fca80870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80fca808",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80fca808",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80fca8",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80fca8",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"fcb80870",
+X"0870842c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fcb80870",
+X"0870852c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fcb80870",
+X"0870862c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"fcb80870",
+X"0870872c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80fc98",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d848080",
+X"53805288",
+X"800a51ff",
+X"b33f8180",
+X"80538052",
+X"82800a51",
+X"c63f843d",
+X"0d04803d",
+X"0d8151fc",
+X"fc3f7280",
+X"2e8338d2",
+X"3f8051fc",
+X"f03f8051",
+X"fcbd3f82",
+X"3d0d04fd",
+X"3d0d7552",
+X"805480ff",
+X"72258838",
+X"810bff80",
+X"135354ff",
+X"bf125170",
+X"99268638",
+X"e012529e",
+X"39ff9f12",
+X"51997127",
+X"9538d012",
+X"e0137054",
+X"54518971",
+X"2788388f",
+X"73278338",
+X"80527380",
+X"2e853881",
+X"80125271",
+X"81ff0683",
+X"e0800c85",
+X"3d0d0480",
+X"3d0d86b8",
+X"c0518071",
+X"70810553",
+X"347086c0",
+X"c02e0981",
+X"06f03882",
+X"3d0d04fe",
+X"3d0d0297",
+X"053351ff",
+X"863f83e0",
+X"800881ff",
+X"0683e09c",
+X"08545280",
+X"73249b38",
+X"83e0b408",
+X"137283e0",
+X"b8080753",
+X"53717334",
+X"83e09c08",
+X"810583e0",
+X"9c0c843d",
+X"0d04fa3d",
+X"0d82800a",
+X"1b83e0b0",
+X"08537952",
+X"55bc9b3f",
+X"83e08008",
+X"973883e0",
+X"80085788",
+X"3dfc0554",
+X"79537452",
+X"83e0b008",
+X"51b5f73f",
+X"883d0d04",
+X"803d0dfb",
+X"cc3f83e0",
+X"80088726",
+X"80cd3883",
+X"e0800884",
+X"2980f7e0",
+X"05517008",
+X"040b0b80",
+X"f8c851b7",
+X"390b0b80",
+X"f8cc51af",
+X"390b0b80",
+X"f8d451a7",
+X"390b0b80",
+X"f8e0519f",
+X"390b0b80",
+X"f8ec5197",
+X"390b0b80",
+X"f8f8518f",
+X"390b0b80",
+X"f9845187",
+X"390b0b80",
+X"f9885170",
+X"83e0800c",
+X"823d0d04",
+X"ee3d0d80",
+X"43804280",
+X"4180705a",
+X"5bfe843f",
+X"800b83e0",
+X"9c0c800b",
+X"83e0b80c",
+X"0b0b80f9",
+X"8c51b180",
+X"3f81800b",
+X"83e0b80c",
+X"0b0b80f9",
+X"9051b0f0",
+X"3f80d00b",
+X"83e09c0c",
+X"7830707a",
+X"07802570",
+X"872b83e0",
+X"b80c5155",
+X"f9ee3f83",
+X"e0800852",
+X"0b0b80f9",
+X"9851b0c8",
+X"3f80f80b",
+X"83e09c0c",
+X"78813270",
+X"30707207",
+X"80257087",
+X"2b83e0b8",
+X"0c515656",
+X"fea23f83",
+X"e0800852",
+X"0b0b80f9",
+X"a451b09c",
+X"3f81a00b",
+X"83e09c0c",
+X"78823270",
+X"30707207",
+X"80257087",
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Index: common/simulate_antic.sh
===================================================================
--- common/simulate_antic.sh	(nonexistent)
+++ common/simulate_antic.sh	(revision 61)
@@ -0,0 +1,65 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=antic
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_antic/* .
+
+        # copy source files
+	cp `find ../a8core/ -iname "*.vhd"` .
+	cp `find ../a8core/ -iname "*.vhdl"` .
+	cp `find ../components/ -iname "*.vhd"` .
+	cp `find ../components/ -iname "*.vhdl"` .
+
+        # set up project definition file
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat > $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: common/simulate_antic.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/tb_antic/antic_tb.vhd
===================================================================
--- common/tb_antic/antic_tb.vhd	(nonexistent)
+++ common/tb_antic/antic_tb.vhd	(revision 61)
@@ -0,0 +1,233 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity antic_tb is
+end;
+
+architecture rtl of antic_tb is
+
+  constant CLK_A_PERIOD : time := 1 us / (1.79*32);
+
+  signal reset_n : std_logic;
+	signal clk_a : std_logic;
+
+	signal cpu_addr : std_logic_vector(15 downto 0);
+	signal cpu_data_in : std_logic_vector(7 downto 0);
+	signal cpu_wr_en : std_logic;
+	signal memory_ready_antic : std_logic;
+	signal memory_ready_cpu : std_logic;
+	signal memory_data_in : std_logic_vector(7 downto 0);
+	signal antic_enable_179 : std_logic;
+	signal enable_179_memwait : std_logic;
+	signal cpu_shared_enable : std_logic;
+	signal an : std_logic_vector(2 downto 0);
+	signal cc_out_orig : std_logic;
+	signal cc_out_used : std_logic;
+	signal cc_out_used_doubled : std_logic;
+	signal fetch : std_logic;
+	signal fetch_address : std_logic_vector(15 downto 0);
+	signal refresh : std_logic;
+	signal hcount : std_logic_vector(7 downto 0);
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk_a <= '1';
+	wait for CLK_A_PERIOD/2;
+	clk_a <= '0';
+	wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+--	signal cpu_addr : std_logic_vector(15 downto 0);
+--	signal cpu_data_in : std_logic_vector(7 downto 0);
+--	signal cpu_wr_en : std_logic;
+--	signal memory_ready_antic : std_logic;
+--	memory_ready_antic <= '0';
+--	signal memory_ready_cpu : std_logic;
+	memory_ready_cpu <= cpu_shared_enable and not(fetch) and not(refresh);
+--	signal memory_data_in : std_logic_vector(7 downto 0);
+--	memory_data_in <= (others=>'0');
+--	signal an : std_logic_vector(2 downto 0);
+--	signal cc_out_orig : std_logic;
+--	signal cc_out_used : std_logic;
+--	signal cc_out_used_doubled : std_logic;
+--	signal fetch : std_logic;
+--	signal fetch_address : std_logic_vector(!5 downto 0);
+
+	process_setup_antic : process
+	begin
+	cpu_wr_en <= '0';
+
+	wait for 1100ns;
+
+	cpu_wr_en <= '1';
+	cpu_addr<= x"d402";
+	cpu_data_in <= x"00";
+	wait for clk_a_period;
+
+	cpu_addr<= x"d403";
+	cpu_data_in <= x"06";
+	wait for clk_a_period;
+
+	cpu_addr <= x"d400";
+	cpu_data_in <= x"22";
+	wait for clk_a_period;
+
+	cpu_wr_en <= '0';
+	wait for 100000000us;
+
+	end process;
+
+	process_antic_dl_data : process
+		variable fetch_pos : integer;
+		type MEM is array(0 to 1000) of std_logic_vector(7 downto 0); 
+		variable fetch_data : MEM;
+	begin
+--		fetch_data(0) := x"42";
+--		fetch_data(1) := x"11";
+--		fetch_data(2) := x"22";
+--		fetch_data(3) := x"33";
+--		fetch_data(4) := x"44";
+--		fetch_data(5) := x"55";
+--		fetch_data(6) := x"00";
+--		fetch_data(7) := x"07";
+--		fetch_data(8) := x"92"; -- char1
+--		fetch_data(9) := x"34"; -- char2
+--		fetch_data(10) := x"ff"; -- char1 data
+--		fetch_data(11) := x"d6"; -- char3
+--		fetch_data(12) := x"00"; -- char2 data
+--		fetch_data(13) := x"78"; -- char4
+--		fetch_data(14) := x"ff"; -- char3 data
+--		fetch_data(15):= x"12"; -- char5
+--		fetch_data(16):= x"00"; -- char4 data
+--		fetch_data(17):= x"12"; -- char6
+--		fetch_data(18):= x"a5"; -- char5 data
+--		fetch_data(19):= x"12"; -- char7
+--		fetch_data(20):= x"a5"; -- char6 data
+--		fetch_data(21):= x"12"; -- char8
+
+--		fetch_data(0) := x"42";
+--		fetch_data(1) := x"00";
+--		fetch_data(2) := x"07";
+--		fetch_data(3) := x"92"; -- char1
+--		fetch_data(4) := x"34"; -- char2
+--		fetch_data(5) := x"ff"; -- char1 data
+--		fetch_data(6) := x"d6"; -- char3
+--		fetch_data(7) := x"00"; -- char2 data
+--		fetch_data(8) := x"78"; -- char4
+--		fetch_data(9) := x"ff"; -- char3 data
+--		fetch_data(10):= x"12"; -- char5
+--		fetch_data(11):= x"00"; -- char4 data
+--		fetch_data(12):= x"12"; -- char6
+--		fetch_data(13):= x"a5"; -- char5 data
+--		fetch_data(14):= x"12"; -- char7
+--		fetch_data(15):= x"a5"; -- char6 data
+--		fetch_data(16):= x"12"; -- char8
+
+		fetch_data(0) := x"48";
+		fetch_data(1) := x"00";
+		fetch_data(2) := x"07";
+		fetch_data(3) := x"ff"; -- char1
+		fetch_data(4) := x"55"; -- char2
+		fetch_data(5) := x"ff"; -- char1 data
+		fetch_data(6) := x"ff"; -- char3
+		fetch_data(7) := x"ff"; -- char2 data
+		fetch_data(8) := x"ff"; -- char4
+		fetch_data(9) := x"ff"; -- char3 data
+		fetch_data(10):= x"ff"; -- char5
+		fetch_data(11):= x"ff"; -- char4 data
+		fetch_data(12):= x"ff"; -- char6
+		fetch_data(13):= x"ff"; -- char5 data
+		fetch_data(14):= x"ff"; -- char7
+		fetch_data(15):= x"ff"; -- char6 data
+		fetch_data(16):= x"ff"; -- char8
+
+		fetch_pos := 0;
+
+		memory_ready_antic <= '0';
+		memory_data_in <= (others=>'0');
+		loop
+			wait until fetch='1';
+			--wait for fetch_delay(fetch_pos);
+			--wait for clk_a_period*9;
+			wait for clk_a_period*3;
+			memory_data_in <= fetch_data(fetch_pos);
+			memory_ready_antic <= '1';
+			wait until fetch = '0';
+			memory_ready_antic <= '0';
+			memory_data_in <= (others=>'0');
+
+			fetch_pos := fetch_pos +1;
+		end loop;
+	end process;
+	
+	enables : entity work.shared_enable
+	GENERIC MAP(cycle_length => 16)
+	PORT MAP(CLK => CLK_a,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 ANTIC_REFRESH => refresh,
+		 PAUSE_6502 => '0',
+		 THROTTLE_COUNT_6502 => "000001",
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE);
+
+	antic1: entity work.antic
+	generic map
+	(
+		cycle_length => 16
+	)
+	port map 
+	( 
+		CLK => clk_a,
+		ADDR => cpu_addr(3 downto 0),
+		CPU_DATA_IN => cpu_data_in, -- for writes
+		WR_EN => cpu_wr_en,
+		
+		RESET_N => reset_n,
+		
+		MEMORY_READY_ANTIC => memory_ready_antic,
+		MEMORY_READY_CPU => memory_ready_cpu,
+		MEMORY_DATA_IN => memory_data_in, -- for fetches
+		ANTIC_ENABLE_179 => antic_enable_179,
+		
+		PAL => '1',
+		
+		lightpen => '0',
+		
+		-- CPU interface
+		DATA_OUT => open,
+		NMI_N_OUT => open,
+		ANTIC_READY => open,
+		
+		-- GTIA interface
+		AN => an,
+		COLOUR_CLOCK_ORIGINAL_OUT => cc_out_orig,
+		COLOUR_CLOCK_OUT => cc_out_used,
+		HIGHRES_COLOUR_CLOCK_OUT => cc_out_used_doubled,
+		
+		-- DMA fetch
+		dma_fetch_out => fetch,
+		dma_address_out => fetch_address,
+		
+		-- refresh
+		refresh_out =>refresh,
+		
+		-- for debugging
+		dma_clock_out => open,
+		hcount_out => hcount,
+		vcount_out => open
+	);
+
+end rtl;
+
