Index: common/a8core/synchronizer.vhdl
===================================================================
--- common/a8core/synchronizer.vhdl	(revision 6)
+++ common/a8core/synchronizer.vhdl	(nonexistent)
@@ -1,39 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY synchronizer IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	RAW : IN STD_LOGIC;
-	SYNC : OUT STD_LOGIC
-);
-END synchronizer;
-
-ARCHITECTURE vhdl OF synchronizer IS
-	signal ff_next : std_logic_vector(2 downto 0);
-	signal ff_reg : std_logic_vector(2 downto 0);
-begin
-	-- register
-	process(clk)
-	begin
-		if (clk'event and clk='1') then						
-			ff_reg <= ff_next;	
-		end if;
-	end process;
-	
-	ff_next <= RAW&ff_reg(2 downto 1);
-	
-	SYNC <= ff_reg(0);
-
-end vhdl;
-
-
Index: common/a8core/generic_ram_infer.vhdl
===================================================================
--- common/a8core/generic_ram_infer.vhdl	(revision 6)
+++ common/a8core/generic_ram_infer.vhdl	(nonexistent)
@@ -1,45 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-use ieee.numeric_std.all;
-
-ENTITY generic_ram_infer IS
-	generic
-	(
-		ADDRESS_WIDTH : natural := 9;
-		SPACE : natural := 512;
-		DATA_WIDTH : natural := 8
-	);
-   PORT
-   (
-      clock: IN   std_logic;
-      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
-      address:  IN   std_logic_vector(address_width-1 downto 0);
-      we:    IN   std_logic;
-      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
-   );
-END generic_ram_infer;
-
-ARCHITECTURE rtl OF generic_ram_infer IS
-   TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
-   SIGNAL ram_block : mem;
-BEGIN
-   PROCESS (clock)
-   BEGIN
-      IF (clock'event AND clock = '1') THEN
-         q<= (others=>'1');
-         IF (to_integer(to_01(unsigned(address))) < space) THEN
-           IF (we = '1') THEN
-              ram_block(to_integer(to_01(unsigned(address)))) <= data;
-           END IF;
-           q <= ram_block(to_integer(to_01(unsigned(address))));
-         END IF;
-      END IF;
-   END PROCESS;
-END rtl;
Index: common/a8core/complete_address_decoder.vhdl
===================================================================
--- common/a8core/complete_address_decoder.vhdl	(revision 6)
+++ common/a8core/complete_address_decoder.vhdl	(nonexistent)
@@ -1,52 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-	
-ENTITY complete_address_decoder IS
-generic (width : natural := 1);
-PORT 
-( 
-	addr_in : in std_logic_vector(width-1 downto 0);	
-	
-	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
-);
-END complete_address_decoder;
-
---ARCHITECTURE vhdl OF complete_address_decoder IS
---BEGIN
---	comp_gen:
---	for i in 0 to ((2**width)-1) generate
---		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
---	end generate;
---end vhdl;
-
-architecture tree of complete_address_decoder is
-	constant STAGE : natural:=width;
-	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
-	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
-	signal a: std_logic_vector(width-1 downto 0) ;
-begin
-	a<=addr_in;
-	process(a,p)
-	begin
-		p(stage,0) <= '1';
-		
-		for s in stage downto 1 loop
-			for r in 0 to (2**(stage-s)-1) loop
-				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
-				p(s-1,2*r+1) <= a(s-1) and p(s,r);
-			end loop;
-		end loop;
-		
-		for i in  0 to (2**stage-1) loop
-			addr_decoded(i) <= p(0,i);
-		end loop;
-	end process;
-end tree;
\ No newline at end of file
Index: common/a8core/delay_line.vhdl
===================================================================
--- common/a8core/delay_line.vhdl	(revision 6)
+++ common/a8core/delay_line.vhdl	(nonexistent)
@@ -1,57 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY delay_line IS
-generic(COUNT : natural := 1);
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	SYNC_RESET : IN STD_LOGIC;
-	DATA_IN : IN STD_LOGIC;
-	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
-	RESET_N : IN STD_LOGIC;
-	
-	DATA_OUT : OUT STD_LOGIC
-);
-END delay_line;
-
-ARCHITECTURE vhdl OF delay_line IS
-	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
-	signal shift_next : std_logic_vector(COUNT-1 downto 0);
-BEGIN
-	-- register
-	process(clk,reset_n)
-	begin
-		if (reset_N = '0') then
-			shift_reg <= (others=>'0');
-		elsif (clk'event and clk='1') then
-			shift_reg <= shift_next;
-		end if;
-	end process;
-
-	-- shift on enable
-	process(shift_reg,enable,data_in,sync_reset)
-	begin
-		shift_next <= shift_reg;
-				
-		if (enable = '1') then
-			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
-		end if;		
-		
-		if (sync_reset = '1') then
-			shift_next <= (others=>'0');
-		end if;		
-	end process;
-	
-	-- output
-	data_out <= shift_reg(0) and enable;
-		
-END vhdl;
Index: common/a8core/syncreset_enable_divider.vhd
===================================================================
--- common/a8core/syncreset_enable_divider.vhd	(revision 6)
+++ common/a8core/syncreset_enable_divider.vhd	(nonexistent)
@@ -1,81 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY syncreset_enable_divider IS
-generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	SYNCRESET : in std_logic;
-	RESET_N : IN STD_LOGIC;
-	ENABLE_IN : IN STD_LOGIC;
-	
-	ENABLE_OUT : OUT STD_LOGIC
-);
-END syncreset_enable_divider;
-
-ARCHITECTURE vhdl OF syncreset_enable_divider IS
-	function log2c(n : integer) return integer is
-		variable m,p : integer;
-	begin
-		m := 0;
-		p := 1;
-		while p<n loop
-			m:=m+1;
-			p:=p*2;
-		end loop;
-		return m;
-	end log2c;
-
-	constant WIDTH : natural := log2c(COUNT);
-	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
-	signal count_next : std_logic_vector(WIDTH-1 downto 0);
-	
-	signal enabled_out_next : std_logic;
-	signal enabled_out_reg : std_logic;
-BEGIN
-	-- register
-	process(clk,reset_n)
-	begin
-		if (reset_n = '0') then
-			count_reg <= (others=>'0');
-			enabled_out_reg <= '0';
-		elsif (clk'event and clk='1') then
-			count_reg <= count_next;
-			enabled_out_reg <= enabled_out_next;
-		end if;
-	end process;
-
-	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
-	process(count_reg,enable_in,enabled_out_reg,syncreset)
-	begin
-		count_next <= count_reg;
-		enabled_out_next <= enabled_out_reg;
-		
-		if (enable_in = '1') then
-			count_next <= std_logic_vector(unsigned(count_reg) + 1);
-			enabled_out_next <= '0';
-		
-			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
-				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
-				enabled_out_next <= '1';
-			end if;
-		end if;
-		
-		if (syncreset='1') then
-			count_next <= std_logic_vector(to_unsigned(resetcount,width));
-		end if;
-	end process;
-	
-	-- output
-	enable_out <= enabled_out_reg and enable_in;
-		
-END vhdl;
Index: common/a8core/countdown_timer.vhdl
===================================================================
--- common/a8core/countdown_timer.vhdl	(revision 6)
+++ common/a8core/countdown_timer.vhdl	(nonexistent)
@@ -1,102 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY pokey_countdown_timer IS
-generic(UNDERFLOW_DELAY : natural := 3);
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	ENABLE : IN STD_LOGIC;
-	ENABLE_UNDERFLOW : IN STD_LOGIC;
-	RESET_N : IN STD_LOGIC;
-	
-	WR_EN : IN STD_LOGIC;
-	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
-
-	DATA_OUT : OUT STD_LOGIC
-);
-END pokey_countdown_timer;
-
-ARCHITECTURE vhdl OF pokey_countdown_timer IS
-	component delay_line IS
-	generic(COUNT : natural := 1);
-	PORT 
-	( 
-		CLK : IN STD_LOGIC;
-		SYNC_RESET : IN STD_LOGIC;
-		DATA_IN : IN STD_LOGIC;
-		
-		ENABLE : IN STD_LOGIC;
-		RESET_N : IN STD_LOGIC;
-		
-		DATA_OUT : OUT STD_LOGIC
-	);
-	END component;
-	
-	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
-	begin
-		if L then
-			return('1');
-		else
-			return('0');
-		end if;
-	end function To_Std_Logic;
-	
-	signal count_reg : std_logic_vector(7 downto 0);
-	signal count_next: std_logic_vector(7 downto 0);
-	
-	signal underflow : std_logic;
-	
-	signal count_command : std_logic_vector(1 downto 0);	
-	signal underflow_command: std_logic_vector(1 downto 0);	
-BEGIN
-	-- Instantiate delay (provides output)
-	underflow0_delay : delay_line
-		generic map (COUNT=>UNDERFLOW_DELAY)
-		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
-
-	-- register
-	process(clk,reset_n)
-	begin
-		if (reset_N = '0') then
-			count_reg <= (others=>'0');
-		elsif (clk'event and clk='1') then
-			count_reg <= count_next;
-		end if;
-	end process;
-
-	-- count down on enable
-	process(count_reg,enable,wr_en,count_command,data_in)
-	begin	
-		count_command <= enable&wr_en;
-		case count_command is
-			when "10" =>
-				count_next <= std_logic_vector(unsigned(count_reg) -1);
-			when "01"|"11" =>
-				count_next <= data_in;
-			when others =>
-				count_next <= count_reg;
-		end case;
-	end process;
-		
-	-- underflow
-	process(count_reg,enable,underflow_command)
-	begin
-		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
-		case underflow_command is
-			when "11" =>
-				underflow <= '1';
-			when others =>
-				underflow <= '0';
-		end case;
-	end process;
-		
-END vhdl;
Index: common/zpu/zpu_rom.vhdl
===================================================================
--- common/zpu/zpu_rom.vhdl	(revision 6)
+++ common/zpu/zpu_rom.vhdl	(nonexistent)
@@ -1,4130 +0,0 @@
-
---
---ROMsUsingBlockRAMResources.
---VHDLcodeforaROMwithregisteredoutput(template2)
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity zpu_rom is
-port(
-        clock:in std_logic;
-        address:in std_logic_vector(11 downto 0);
-        q:out std_logic_vector(31 downto 0)
-);
-end zpu_rom;
-
-architecture syn of zpu_rom is
-        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
-        signal ROM:rom_type:=
-(
-	X"0b0b0b89",
-X"ab040b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"0b0b0b0b",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"71fd0608",
-X"72830609",
-X"81058205",
-X"832b2a83",
-X"ffff0652",
-X"04000000",
-X"00000000",
-X"00000000",
-X"71fd0608",
-X"83ffff73",
-X"83060981",
-X"05820583",
-X"2b2b0906",
-X"7383ffff",
-X"0b0b0b0b",
-X"83a70400",
-X"72098105",
-X"72057373",
-X"09060906",
-X"73097306",
-X"070a8106",
-X"53510400",
-X"00000000",
-X"00000000",
-X"72722473",
-X"732e0753",
-X"51040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"71737109",
-X"71068106",
-X"30720a10",
-X"0a720a10",
-X"0a31050a",
-X"81065151",
-X"53510400",
-X"00000000",
-X"72722673",
-X"732e0753",
-X"51040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"0b0b0b88",
-X"bc040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"720a722b",
-X"0a535104",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72729f06",
-X"0981050b",
-X"0b0b889f",
-X"05040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72722aff",
-X"739f062a",
-X"0974090a",
-X"8106ff05",
-X"06075351",
-X"04000000",
-X"00000000",
-X"00000000",
-X"71715351",
-X"020d0406",
-X"73830609",
-X"81058205",
-X"832b0b2b",
-X"0772fc06",
-X"0c515104",
-X"00000000",
-X"72098105",
-X"72050970",
-X"81050906",
-X"0a810653",
-X"51040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72098105",
-X"72050970",
-X"81050906",
-X"0a098106",
-X"53510400",
-X"00000000",
-X"00000000",
-X"00000000",
-X"71098105",
-X"52040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72720981",
-X"05055351",
-X"04000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72097206",
-X"73730906",
-X"07535104",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"71fc0608",
-X"72830609",
-X"81058305",
-X"1010102a",
-X"81ff0652",
-X"04000000",
-X"00000000",
-X"00000000",
-X"71fc0608",
-X"0b0b0b92",
-X"b8738306",
-X"10100508",
-X"060b0b0b",
-X"88a20400",
-X"00000000",
-X"00000000",
-X"0b0b0b88",
-X"fe040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"0b0b0b88",
-X"d8040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"72097081",
-X"0509060a",
-X"8106ff05",
-X"70547106",
-X"73097274",
-X"05ff0506",
-X"07515151",
-X"04000000",
-X"72097081",
-X"0509060a",
-X"098106ff",
-X"05705471",
-X"06730972",
-X"7405ff05",
-X"06075151",
-X"51040000",
-X"05ff0504",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"810b92c8",
-X"0c510400",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00718105",
-X"52040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00028405",
-X"72101005",
-X"52040000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00717105",
-X"ff057153",
-X"51020d04",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"10101010",
-X"10101010",
-X"10101010",
-X"10101010",
-X"10101010",
-X"10101010",
-X"10101010",
-X"10101053",
-X"51047381",
-X"ff067383",
-X"06098105",
-X"83051010",
-X"102b0772",
-X"fc060c51",
-X"51043c04",
-X"72728072",
-X"8106ff05",
-X"09720605",
-X"71105272",
-X"0a100a53",
-X"72ed3851",
-X"51535104",
-X"83e08008",
-X"83e08408",
-X"83e08808",
-X"75758f82",
-X"2d505083",
-X"e0800856",
-X"83e0880c",
-X"83e0840c",
-X"83e0800c",
-X"510483e0",
-X"800883e0",
-X"840883e0",
-X"88087575",
-X"8d962d50",
-X"5083e080",
-X"085683e0",
-X"880c83e0",
-X"840c83e0",
-X"800c5104",
-X"00008004",
-X"89a80489",
-X"a80b8cd8",
-X"0483e08c",
-X"080283e0",
-X"8c0cfe3d",
-X"0d83e08c",
-X"08880508",
-X"7070832b",
-X"70733170",
-X"822b7083",
-X"e08c08fc",
-X"050c92d4",
-X"0883e08c",
-X"08fc0508",
-X"710c5151",
-X"51515252",
-X"843d0d83",
-X"e08c0c04",
-X"83e08c08",
-X"0283e08c",
-X"0cff3d0d",
-X"800b83e0",
-X"8c08fc05",
-X"0c92e408",
-X"51ff87c3",
-X"e1f0710c",
-X"92e00851",
-X"80710c88",
-X"800a0b83",
-X"e08c08fc",
-X"050c83e0",
-X"8c08fc05",
-X"08818480",
-X"802e9e38",
-X"83e08c08",
-X"fc050851",
-X"80713483",
-X"e08c08fc",
-X"05088105",
-X"83e08c08",
-X"fc050cd6",
-X"3992e408",
-X"5185aad5",
-X"aad5710c",
-X"92e00851",
-X"85aad5aa",
-X"d5710c82",
-X"800a0b83",
-X"e08c08fc",
-X"050c83e0",
-X"8c08fc05",
-X"08848480",
-X"802e9e38",
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-
-);
-        signal rdata:std_logic_vector(31 downto 0);
-begin
-        rdata<=ROM(conv_integer(address));
-
-        process(clock)
-        begin
-                if(clock'event and clock='1')then
-                	q<=rdata;
-                end if;
-        end process;
-end syn;
Index: common/a8core/atari800core.vhd
===================================================================
--- common/a8core/atari800core.vhd	(revision 6)
+++ common/a8core/atari800core.vhd	(revision 7)
@@ -215,10 +215,7 @@
 -- TODO - review/explain what all these are for
 SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
 SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
-SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
 SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
 
 -- POKEY
 SIGNAL	POKEY_IRQ :  STD_LOGIC;
@@ -286,12 +283,9 @@
 		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
 		 PAUSE_6502 => HALT,
 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
-		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
 		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
 		 oldcpu_enable => ENABLE_179_MEMWAIT,
-		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
-		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
-		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE);
 
 
 CPU_6502_RESET <= NOT(RESET_N); -- TODO, allow external reset
Index: common/a8core/pokey_countdown_timer.vhdl
===================================================================
--- common/a8core/pokey_countdown_timer.vhdl	(nonexistent)
+++ common/a8core/pokey_countdown_timer.vhdl	(revision 7)
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_countdown_timer IS
+generic(UNDERFLOW_DELAY : natural := 3);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	ENABLE_UNDERFLOW : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	WR_EN : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+	DATA_OUT : OUT STD_LOGIC
+);
+END pokey_countdown_timer;
+
+ARCHITECTURE vhdl OF pokey_countdown_timer IS
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal count_reg : std_logic_vector(7 downto 0);
+	signal count_next: std_logic_vector(7 downto 0);
+	
+	signal underflow : std_logic;
+	
+	signal count_command : std_logic_vector(1 downto 0);	
+	signal underflow_command: std_logic_vector(1 downto 0);	
+BEGIN
+	-- Instantiate delay (provides output)
+	underflow0_delay : delay_line
+		generic map (COUNT=>UNDERFLOW_DELAY)
+		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+		end if;
+	end process;
+
+	-- count down on enable
+	process(count_reg,enable,wr_en,count_command,data_in)
+	begin	
+		count_command <= enable&wr_en;
+		case count_command is
+			when "10" =>
+				count_next <= std_logic_vector(unsigned(count_reg) -1);
+			when "01"|"11" =>
+				count_next <= data_in;
+			when others =>
+				count_next <= count_reg;
+		end case;
+	end process;
+		
+	-- underflow
+	process(count_reg,enable,underflow_command)
+	begin
+		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
+		case underflow_command is
+			when "11" =>
+				underflow <= '1';
+			when others =>
+				underflow <= '0';
+		end case;
+	end process;
+		
+END vhdl;
Index: common/a8core/shared_enable.vhdl
===================================================================
--- common/a8core/shared_enable.vhdl	(revision 6)
+++ common/a8core/shared_enable.vhdl	(revision 7)
@@ -9,6 +9,8 @@
 USE ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+-- TODO - review this whole scheme
+-- Massively overcomplex and turbo doesn't even work with it right now!
 ENTITY shared_enable IS
 GENERIC
 (
@@ -23,14 +25,10 @@
 	PAUSE_6502 : in std_logic;
 	THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
 
-	POKEY_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same
 	ANTIC_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same - 1 cycle early
 	oldcpu_enable : OUT STD_LOGIC;     -- always about 1.79MHz to keep sound the same - expanded to next ready
-	CPU_ENABLE_OUT : OUT STD_LOGIC;    -- for compatibility run at 1.79MHz, for speed run as fast as we can
+	CPU_ENABLE_OUT : OUT STD_LOGIC    -- for compatibility run at 1.79MHz, for speed run as fast as we can
 	
-	SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC; -- double antic's rate - due to high-res mode
-	SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC -- four times antic's rate - due to high-res mode
-	
 	-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by 31 cycles vs CPU_ENABLE (when in 1.79MHz mode)
 	-- XXX watch out on clock speed change from 56MHz!
 );
@@ -65,7 +63,6 @@
 	
 	signal enable_179 : std_logic;
 	signal enable_179_early : std_logic;
-	signal enable_179_late : std_logic;
 	signal cpu_enable : std_logic;
 	
 	signal cpu_extra_enable_next : std_logic;
@@ -85,13 +82,6 @@
 	signal memory_ready : std_logic;
 begin
 	-- instantiate some clock calcs
-	-- TODO - scandouble clocks assume 58MHz...
-	SCANDOUBLER_ENABLE_HIGH <= '1';
-		
-	sl_enable_colour_clock_div : enable_divider
-		generic map (COUNT=>2)
-		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
-
 	enable_179_clock_div : enable_divider
 		generic map (COUNT=>cycle_length)
 		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
@@ -128,10 +118,6 @@
 		generic map (COUNT=>cycle_length-1)
 		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
 
-	delay_line_phase2 : delay_line
-		generic map (COUNT=>cycle_length/2)
-		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
-	
 	-- registers
 	process(clk,reset_n)
 	begin
@@ -157,7 +143,6 @@
 	enable_179_expanded <= oldcpu_extra_enable_reg or enable_179;
 	
 	-- output
-	POKEY_ENABLE_179 <= enable_179_late; -- aka enable_179_late!  TODO!!!
 	oldcpu_enable <= enable_179_expanded;
 	ANTIC_ENABLE_179 <= enable_179_early;
 	
Index: common/components/complete_address_decoder.vhdl
===================================================================
--- common/components/complete_address_decoder.vhdl	(nonexistent)
+++ common/components/complete_address_decoder.vhdl	(revision 7)
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);	
+	
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END complete_address_decoder;
+
+--ARCHITECTURE vhdl OF complete_address_decoder IS
+--BEGIN
+--	comp_gen:
+--	for i in 0 to ((2**width)-1) generate
+--		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
+--	end generate;
+--end vhdl;
+
+architecture tree of complete_address_decoder is
+	constant STAGE : natural:=width;
+	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
+	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
+	signal a: std_logic_vector(width-1 downto 0) ;
+begin
+	a<=addr_in;
+	process(a,p)
+	begin
+		p(stage,0) <= '1';
+		
+		for s in stage downto 1 loop
+			for r in 0 to (2**(stage-s)-1) loop
+				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
+				p(s-1,2*r+1) <= a(s-1) and p(s,r);
+			end loop;
+		end loop;
+		
+		for i in  0 to (2**stage-1) loop
+			addr_decoded(i) <= p(0,i);
+		end loop;
+	end process;
+end tree;
\ No newline at end of file
Index: common/components/delay_line.vhdl
===================================================================
--- common/components/delay_line.vhdl	(nonexistent)
+++ common/components/delay_line.vhdl	(revision 7)
@@ -0,0 +1,57 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY delay_line IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC
+);
+END delay_line;
+
+ARCHITECTURE vhdl OF delay_line IS
+	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
+	signal shift_next : std_logic_vector(COUNT-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>'0');
+		end if;		
+	end process;
+	
+	-- output
+	data_out <= shift_reg(0) and enable;
+		
+END vhdl;
Index: common/components/generic_ram_infer.vhdl
===================================================================
--- common/components/generic_ram_infer.vhdl	(nonexistent)
+++ common/components/generic_ram_infer.vhdl	(revision 7)
@@ -0,0 +1,45 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+ENTITY generic_ram_infer IS
+	generic
+	(
+		ADDRESS_WIDTH : natural := 9;
+		SPACE : natural := 512;
+		DATA_WIDTH : natural := 8
+	);
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END generic_ram_infer;
+
+ARCHITECTURE rtl OF generic_ram_infer IS
+   TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         q<= (others=>'1');
+         IF (to_integer(to_01(unsigned(address))) < space) THEN
+           IF (we = '1') THEN
+              ram_block(to_integer(to_01(unsigned(address)))) <= data;
+           END IF;
+           q <= ram_block(to_integer(to_01(unsigned(address))));
+         END IF;
+      END IF;
+   END PROCESS;
+END rtl;
Index: common/components/synchronizer.vhdl
===================================================================
--- common/components/synchronizer.vhdl	(nonexistent)
+++ common/components/synchronizer.vhdl	(revision 7)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END synchronizer;
+
+ARCHITECTURE vhdl OF synchronizer IS
+	signal ff_next : std_logic_vector(2 downto 0);
+	signal ff_reg : std_logic_vector(2 downto 0);
+begin
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then						
+			ff_reg <= ff_next;	
+		end if;
+	end process;
+	
+	ff_next <= RAW&ff_reg(2 downto 1);
+	
+	SYNC <= ff_reg(0);
+
+end vhdl;
+
+
Index: common/components/syncreset_enable_divider.vhd
===================================================================
--- common/components/syncreset_enable_divider.vhd	(nonexistent)
+++ common/components/syncreset_enable_divider.vhd	(revision 7)
@@ -0,0 +1,81 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY syncreset_enable_divider IS
+generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNCRESET : in std_logic;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END syncreset_enable_divider;
+
+ARCHITECTURE vhdl OF syncreset_enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg,syncreset)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+		
+		if (syncreset='1') then
+			count_next <= std_logic_vector(to_unsigned(resetcount,width));
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: common/zpu/simulate_zpu.sh
===================================================================
--- common/zpu/simulate_zpu.sh	(nonexistent)
+++ common/zpu/simulate_zpu.sh	(revision 7)
@@ -0,0 +1,77 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=zpucore
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb/* .
+
+        # copy source files
+	cp `find ../ -iname "*.vhd"` .
+	cp `find ../ -iname "*.vhdl"` .
+	cp "../../components/generic_ram_infer.vhdl" .
+	cp "../../components/spi_master.vhd" .
+	cp "../../components/complete_address_decoder.vhdl" .
+	cp "../../components/delay_line.vhdl" .
+	cp "../../components/syncreset_enable_divider.vhd" .
+	cp "../../components/synchronizer.vhdl" .
+
+	cp "../../a8core/pokey.vhdl" .
+	cp "../../a8core/pokey_keyboard_scanner.vhdl" .
+	cp "../../a8core/pokey_countdown_timer.vhdl" .
+	cp "../../a8core/pokey_noise_filter.vhdl" .
+	cp "../../a8core/poly_4.vhdl" .
+	cp "../../a8core/poly_5.vhdl" .
+	cp "../../a8core/poly_17_9.vhdl" .
+
+        # set up project definition file
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat > $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: common/zpu/simulate_zpu.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/zpu/tb/zpucore_tb.vhd
===================================================================
--- common/zpu/tb/zpucore_tb.vhd	(nonexistent)
+++ common/zpu/tb/zpucore_tb.vhd	(revision 7)
@@ -0,0 +1,91 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity zpucore_tb is
+end;
+
+architecture rtl of zpucore_tb is
+
+  constant CLK_A_PERIOD : time := 1 us / (1.79*32);
+
+  signal CLK_A : std_logic;
+
+  signal reset_n : std_logic;
+
+	signal ZPU_FETCH : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE : std_logic;
+	signal ZPU_READ_ENABLE : std_logic;
+	signal ZPU_MEMORY_DATA : std_logic_vector(31 downto 0);
+	signal ZPU_MEMORY_READY : std_logic;
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk_a <= '1';
+	wait for CLK_A_PERIOD/2;
+	clk_a <= '0';
+	wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+zpu1 : entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 42
+	)
+	PORT MAP
+	(
+		CLK => CLK_A,
+		RESET_N => RESET_N,
+
+		-- TODO - wire up a simple ram...
+		ZPU_FETCH => ZPU_FETCH,
+		ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		ZPU_MEMORY_DATA => ZPU_MEMORY_DATA,
+		ZPU_MEMORY_READY => ZPU_MEMORY_READY,
+
+		-- TODO - wire up a simple rom
+		ZPU_ADDR_ROM => ZPU_ADDR_ROM,
+		ZPU_ROM_DATA => ZPU_ROM_DATA, 
+
+		ZPU_SD_DAT0 => '1',
+		ZPU_SD_CLK => open,
+		ZPU_SD_CMD => open,
+		ZPU_SD_DAT3 => open,
+
+		-- SIO
+		ZPU_POKEY_ENABLE => '1',
+		ZPU_SIO_TXD => open,
+		ZPU_SIO_RXD => '1',
+		ZPU_SIO_COMMAND => '1',
+
+		-- external control
+		ZPU_IN1 => x"11345678",
+		ZPU_IN2 => x"22345678",
+		ZPU_IN3 => x"33345678",
+		ZPU_IN4 => x"44345678",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => open,
+		ZPU_OUT2 => open,
+		ZPU_OUT3 => open,
+		ZPU_OUT4 => open
+	);
+
+end rtl;
+
Index: common/zpu/zpu_config_regs.vhdl
===================================================================
--- common/zpu/zpu_config_regs.vhdl	(revision 6)
+++ common/zpu/zpu_config_regs.vhdl	(revision 7)
@@ -10,23 +10,32 @@
 use ieee.numeric_std.all;
 
 ENTITY zpu_config_regs IS
+GENERIC
+(
+	platform : integer := 1 -- So ROM can detect which type of system...
+);
 PORT 
 ( 
 	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
 	
-	ENABLE_179 : in std_logic;
+	POKEY_ENABLE : in std_logic;
 	
 	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
 	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 	WR_EN : IN STD_LOGIC;
 	
-	-- SWITCHES
-	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
-	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	-- GENERIC INPUT REGS (need to synchronize upstream...)
+	IN1 : in std_logic_vector(31 downto 0); 
+	IN2 : in std_logic_vector(31 downto 0); 
+	IN3 : in std_logic_vector(31 downto 0); 
+	IN4 : in std_logic_vector(31 downto 0); 
 	
-	-- LEDS
-	LEDG : out std_logic_vector(7 downto 0);
-	LEDR : out std_logic_vector(9 downto 0);
+	-- GENERIC OUTPUT REGS
+	OUT1 : out  std_logic_vector(31 downto 0); 
+	OUT2 : out  std_logic_vector(31 downto 0); 
+	OUT3 : out  std_logic_vector(31 downto 0); 
+	OUT4 : out  std_logic_vector(31 downto 0); 
 	
 	-- SDCARD
 	SDCARD_CLK : out std_logic;
@@ -36,102 +45,16 @@
 	
 	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
 	SIO_DATA_IN  : out std_logic;
-	SIO_COMMAND_OUT : in std_logic;
+	SIO_COMMAND : in std_logic;
 	SIO_DATA_OUT : in std_logic;
 	
 	-- CPU interface
 	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-	PAUSE_ZPU : out std_logic;
-	
-	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
-	PAL : OUT STD_LOGIC;
-	USE_SDRAM : OUT STD_LOGIC;
-	RAM_SELECT : OUT STD_LOGIC_VECTOR(2 downto 0);
-	VGA : OUT STD_LOGIC;
-	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
-	GPIO_ENABLE : OUT STD_LOGIC;
-	ROM_SELECT : out stD_logic_vector(1 downto 0);
-	
-	-- sector buffer
-	sector : out std_logic_vector(31 downto 0);
-	sector_request : out std_logic;
-	sector_ready : in std_logic;
-
-	-- system reset/halt
-	PLL_LOCKED : IN STD_LOGIC; -- pll locked
-	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
-	
-	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
-	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
-	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
-	
-	PAUSE_6502 : out std_logic;
-	
-	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
-	
-	ZPU_HEX : out std_logic_vector(15 downto 0)
-
---	-- synchronize async inputs
---	locked_synchronizer : synchronizer
---		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
-	
+	PAUSE_ZPU : out std_logic
 );
 END zpu_config_regs;
 
 ARCHITECTURE vhdl OF zpu_config_regs IS
-	COMPONENT complete_address_decoder IS
-	generic (width : natural := 4);
-	PORT 
-	( 
-		addr_in : in std_logic_vector(width-1 downto 0);			
-		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
-	);
-	END component;
-	
-	component pokey IS
-	PORT 
-	( 
-		CLK : IN STD_LOGIC;
-		--ENABLE_179 :in std_logic;
-		CPU_MEMORY_READY :in std_logic;
-		ANTIC_MEMORY_READY :in std_logic;
-		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		WR_EN : IN STD_LOGIC;
-		
-		RESET_N : IN STD_LOGIC;
-		
-		-- keyboard interface
-		keyboard_scan : out std_logic_vector(5 downto 0);
-		keyboard_response : in std_logic_vector(1 downto 0);
-		
-		-- pots - go high as capacitor charges
-		POT_IN : in std_logic_vector(7 downto 0);
-		
-		-- sio interface
-		SIO_IN1 : IN std_logic;
-		SIO_IN2 : IN std_logic;
-		SIO_IN3 : IN std_logic;
-		
-		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		
-		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		
-		IRQ_N_OUT : OUT std_logic;
-		
-		SIO_OUT1 : OUT std_logic;
-		SIO_OUT2 : OUT std_logic;
-		SIO_OUT3 : OUT std_logic;
-		
-		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
-		
-		POT_RESET : out std_logic
-	);
-	END component;	
-	
 	function vectorize(s: std_logic) return std_logic_vector is
 	variable v: std_logic_vector(0 downto 0);
 	begin
@@ -141,35 +64,15 @@
 	
 	signal addr_decoded : std_logic_vector(15 downto 0);	
 	
-	signal config_6502_next : std_logic_vector(7 downto 0);
-	signal config_6502_reg : std_logic_vector(7 downto 0);
-	signal ram_select_next : std_logic_vector(2 downto 0);
-	signal ram_select_reg : std_logic_vector(2 downto 0);
-	signal rom_select_next : std_logic_vector(1 downto 0);
-	signal rom_select_reg : std_logic_vector(1 downto 0);
-	signal gpio_enable_next : std_logic;
-	signal gpio_enable_reg : std_logic;
+	signal out1_next : std_logic_vector(31 downto 0);
+	signal out1_reg : std_logic_vector(31 downto 0);
+	signal out2_next : std_logic_vector(31 downto 0);
+	signal out2_reg : std_logic_vector(31 downto 0);
+	signal out3_next : std_logic_vector(31 downto 0);
+	signal out3_reg : std_logic_vector(31 downto 0);
+	signal out4_next : std_logic_vector(31 downto 0);
+	signal out4_reg : std_logic_vector(31 downto 0);
 	
-	signal pause_next : std_logic_vector(31 downto 0);
-	signal pause_reg : std_logic_vector(31 downto 0);
-	signal paused_next : std_logic;
-	signal paused_reg : std_logic;
-	
-	signal ledg_next : std_logic_vector(7 downto 0);
-	signal ledg_reg : std_logic_vector(7 downto 0);
-
-	signal ledr_next : std_logic_vector(9 downto 0);
-	signal ledr_reg : std_logic_vector(9 downto 0);
-	
-	signal reset_n_next : std_logic;
-	signal reset_n_reg : std_logic;
-	
-	signal reset_6502_cpu_next : std_logic;
-	signal reset_6502_cpu_reg : std_logic;
-	
-	signal reset_zpu_next : std_logic;
-	signal reset_zpu_reg : std_logic;	
-	
 	signal spi_miso : std_logic;
 	signal spi_mosi : std_logic;
 	signal spi_busy : std_logic;	
@@ -182,76 +85,50 @@
 	
 	signal spi_addr_next : std_logic;
 	signal spi_addr_reg : std_logic;
+	signal spi_addr_reg_integer : integer;
 	signal spi_speed_next : std_logic_vector(7 downto 0);
 	signal spi_speed_reg : std_logic_vector(7 downto 0);
+	signal spi_speed_reg_integer : integer;
 
-	signal zpu_hex_next : std_logic_vector(15 downto 0);
-	signal zpu_hex_reg : std_logic_vector(15 downto 0);
-	
 	signal pokey_data_out : std_logic_vector(7 downto 0);
 	
-	signal sector_next : std_logic_vector(31 downto 0);
-	signal sector_reg : std_logic_vector(31 downto 0);
-	signal sector_request_next : std_logic;
-	signal sector_request_reg : std_logic; -- cleared when ready asserted
+	signal wr_en_pokey : std_logic;
 
-	signal spi_addr_reg_integer : integer;
-	signal spi_speed_reg_integer : integer;
-	signal wr_en_pokey : std_logic;
-	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
 begin
 	-- register
-	process(clk,pll_locked)
+	process(clk,reset_n)
 	begin
-		if (clk'event and clk='1') then	
-			if (pll_locked = '0') then
-				config_6502_reg <= "1"&"0"&"001111"; -- reset_6502, halt_6502, run_every 16 cycles
-				rom_select_reg <= "01";
-				ram_select_reg <= "010";
-				gpio_enable_reg <= '0';
-				pause_reg <= (others=>'0');
-				paused_reg <= '0';
-				ledg_reg <= (others=>'0');
-				ledr_reg <= (others=>'0');
-				
-				spi_addr_reg <= '1';
-				spi_speed_reg <= X"80";
-				
-				zpu_hex_reg <= X"b007";
-				
-				reset_n_reg <= '0';			
-				reset_zpu_reg <= '1';
-				reset_6502_cpu_reg <= '1';											
-				
-				sector_reg <= (others=>'0');
-				sector_request_reg <= '0';
-			else
-				config_6502_reg <= config_6502_next;
-				rom_select_reg <= rom_select_next;
-				ram_select_reg <= ram_select_next;
-				gpio_enable_reg <= gpio_enable_next;			
-				pause_reg <= pause_next;
-				paused_reg <= paused_next;
-				ledg_reg <= ledg_next;
-				ledr_reg <= ledr_next;
-				
-				spi_addr_reg <= spi_addr_next;
-				spi_speed_reg <= spi_speed_next;
-	
-				zpu_hex_reg <= zpu_hex_next;
-	
-				reset_n_reg <= reset_n_next;			
-				reset_zpu_reg <= reset_zpu_next;
-				reset_6502_cpu_reg <= reset_6502_cpu_next;							
-				
-				sector_reg <= sector_next;
-				sector_request_reg <= sector_request_next;				
-			end if;
+		if (reset_n='0') then
+			out1_reg <= (others=>'0');
+			out2_reg <= (others=>'0');
+			out3_reg <= (others=>'0');
+			out4_reg <= (others=>'0');
+			
+			spi_addr_reg <= '1';
+			spi_speed_reg <= X"80";
+
+			pause_reg <= (others=>'0');
+			paused_reg <= '0';
+		elsif (clk'event and clk='1') then	
+			out1_reg <= out1_next;
+			out2_reg <= out2_next;
+			out3_reg <= out3_next;
+			out4_reg <= out4_next;
+			
+			spi_addr_reg <= spi_addr_next;
+			spi_speed_reg <= spi_speed_next;
+
+			pause_reg <= pause_next;
+			paused_reg <= paused_next;
 		end if;
 	end process;
 
 	-- decode address
-	decode_addr1 : complete_address_decoder
+	decode_addr1 : entity work.complete_address_decoder
 		generic map(width=>4)
 		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
 
@@ -267,9 +144,9 @@
 	
 	-- uart - another Pokey! Running at atari frequency.
 	wr_en_pokey <= addr(4) and wr_en;
-	uart1 : pokey
-		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>wr_en_pokey, 
-		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+	pokey1 : entity work.pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>pokey_enable,ANTIC_MEMORY_READY=>pokey_enable,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>wr_en_pokey, 
+		reset_n=>reset_n,keyboard_response=>"11",pot_in=>X"00",
 		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
 		data_out=>pokey_data_out, 
 		sio_out1=>sio_data_in);
@@ -276,80 +153,33 @@
 
 	-- hardware regs for ZPU
 	--
-	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
-	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
-	-- these need storing somewhere...
-	-- TODO - volume output from here
-	-- TODO - hex digits register
-	-- TODO - if we take over antic we need to point antic to alternative RAM!
-	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
-	-- TODO - reset pokey and pia interrupts too?
-	--
-	-- virtual joystick button -> keyboard (windows key?)
-	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
-	--
-	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
-	--
-	-- STEP 1 -> joystick -> keyboard (DONE)
-	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
-	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
-	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
-	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
-	--
-	-- CONFIG_ATARI: 
-	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
-	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
-	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
-	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
-	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
-	-- SWITCH (DONE)
-	--		R: 0-9 - switches
-	-- KEY (DONE)
-	--    R: 0-3 - keys
-	-- LEDG (DONE) 
-	--    R/W: 0-9
-	-- LEDR (DONE) 
-	--    R/W: 0-9
+	-- 0-3: GENERIC INPUT (RO)
+	-- 4-7: GENERIC OUTPUT (R/W)
+	--  8: PAUSE
+	--   9: SPI_DATA
 	-- SPI_DATA (DONE) 
 	--		W - write data (starts transmission)
 	--		R - read data (wait for complete first)
+	--  10: SPI_STATE
 	-- SPI_STATE/SPI_CTRL (DONE) 
 	--    R: 0=busy
 	--    W: 0=select_n, speed
+	--  11: SIO
 	-- SIO
 	--    R: 0=CMD
+	--  12: TYPE
 	-- FPGA board (DONE) 
 	--    R(32 bits) 0=DE1
-	-- HEX digits
-	--    W(16 bits)
-	-- SECTOR
-	--   W(32 bits) - write here initiates a request_reset_zpu
-	--   R: 0=request_active
-	
-	-- TODO, ROM select, RAM select etc etc
-	-- TODO firmware with OSD!
+	--  16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
 				
 	-- Writes to registers
-	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
+	process(cpu_data_in,wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, pause_reg)
 	begin
-		config_6502_next <= config_6502_reg;
-		rom_select_next <= rom_select_reg;
-		ram_select_next <= ram_select_reg;
-		gpio_enable_next <= gpio_enable_reg;
-		pause_next <= pause_reg;
-		ledg_next <= ledg_reg;
-		ledr_next <= ledr_reg;
-		
 		spi_speed_next <= spi_speed_reg;
 		spi_addr_next <= spi_addr_reg;
 		spi_tx_data <= (others=>'0');
 		spi_enable <= '0';
 		
-		zpu_hex_next <= zpu_hex_reg;
-		
-		sector_next <= sector_reg;
-		sector_request_next <= sector_request_reg and not(sector_ready);
-		
 		paused_next <= '0';
 		if (not(pause_reg = X"00000000")) then
 			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
@@ -357,33 +187,34 @@
 		end if;
 	
 		if (wr_en = '1' and addr(4) = '0') then
-			if(addr_decoded(0) = '1') then
-				config_6502_next <= cpu_data_in(7 downto 0);
-				ram_select_next <= cpu_DATA_IN(10 downto 8);
-				rom_select_next <= cpu_DATA_IN(13 downto 12);
-				gpio_enable_next <= cpu_DATA_IN(16);
-			end if;	
-			
-			if(addr_decoded(1) = '1') then
-				pause_next <= cpu_data_in;
-				paused_next <= '1';
-			end if;				
-
 			if(addr_decoded(4) = '1') then
-				ledg_next <= cpu_data_in(7 downto 0);
+				out1_next <= cpu_data_in;
 			end if;	
 			
 			if(addr_decoded(5) = '1') then
-				ledr_next <= cpu_data_in(9 downto 0);
+				out2_next <= cpu_data_in;
 			end if;	
 
 			if(addr_decoded(6) = '1') then
+				out3_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				out4_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(8) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;	
+
+			if(addr_decoded(9) = '1') then
 				-- TODO, check overrun?
 				spi_tx_data <= cpu_data_in(7 downto 0);
 				spi_enable <= '1';
 			end if;	
 
-			if(addr_decoded(7) = '1') then
+			if(addr_decoded(10) = '1') then
 				spi_addr_next <= cpu_data_in(0);
 				if (cpu_data_in(1) = '1') then
 					spi_speed_next <= X"80"; -- slow, for init
@@ -391,125 +222,80 @@
 					spi_speed_next <= X"04"; -- turbo!
 				end if;
 			end if;	
-
-			if(addr_decoded(10) = '1') then
-				zpu_hex_next <= cpu_data_in(15 downto 0);
-			end if;	
 			
-			if(addr_decoded(11) = '1') then
-				sector_next <= cpu_data_in;
-				sector_request_next <= '1';
-			end if;
-			
 		end if;
 	end process;
 	
 	-- Read from registers
-	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
+	process(addr,addr_decoded, in1, in2, in3, in4, out1_reg, out2_reg, out3_reg, out4_reg, SIO_COMMAND, spi_rx_data, spi_busy, pokey_data_out)
 	begin
 		data_out <= (others=>'0');
 
 		if (addr(4) = '0') then
 			if (addr_decoded(0) = '1') then
-				data_out(7 downto 0) <= config_6502_reg;
-				data_out(10 downto 8) <= ram_select_reg;
-				data_out(13 downto 12) <= rom_select_reg;
-				data_out(16) <= gpio_enable_reg;
+				data_out <= in1;
 			end if;
 			
+			if (addr_decoded(1) = '1') then
+				data_out <= in2;
+			end if;		
+			
 			if (addr_decoded(2) = '1') then
-				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+				data_out <= in3;
 			end if;		
 			
 			if (addr_decoded(3) = '1') then
-				data_out(3 downto 0) <= key;
-			end if;		
-			
+				data_out <= in4;
+			end if;
+
 			if (addr_decoded(4) = '1') then
-				data_out(7 downto 0) <= ledg_reg;
+				data_out <= out1_reg;
 			end if;
-
+			
 			if (addr_decoded(5) = '1') then
-				data_out(9 downto 0) <= ledr_reg;
+				data_out <= out2_reg;
+			end if;		
+			
+			if (addr_decoded(6) = '1') then
+				data_out <= out3_reg;
+			end if;		
+			
+			if (addr_decoded(7) = '1') then
+				data_out <= out4_reg;
 			end if;
 
-			if (addr_decoded(6) = '1') then
+			if (addr_decoded(9) = '1') then
 				data_out(7 downto 0) <= spi_rx_data;
 			end if;
 
-			if (addr_decoded(7) = '1') then
+			if (addr_decoded(10) = '1') then
 				data_out(0) <= spi_busy;
 			end if;		
 
-			if(addr_decoded(8) = '1') then
-				data_out(0) <= sio_command_OUT;
+			if(addr_decoded(11) = '1') then
+				data_out(0) <= SIO_COMMAND;
 			end if;	
 			
-			if (addr_decoded(9) = '1') then
-				--data_out <= X"00000000"; -- DE1!
-				--data_out <= X"00000001"; -- DE2!
-				--data_out <= X"00000002"; -- SOCKIT!
-				--data_out <= X"00000003"; -- REPLAY!
-				data_out <= X"00000004"; -- MMC!		
+			if (addr_decoded(12) = '1') then
+				data_out <= std_logic_vector(to_unsigned(platform,32));
 			end if;
-			
-			if (addr_decoded(10) = '1') then
-				data_out(15 downto 0) <= zpu_hex_reg;
-			end if;			
-			
-			if (addr_decoded(11) = '1') then
-				data_out(0) <= sector_request_reg;
-			end if;			
-			
 		else
 			data_out(7 downto 0) <= pokey_data_out;
 		end if;
 	end process;	
 	
-	process(request_reset_zpu, config_6502_next, config_6502_reg)
-	begin
-		reset_n_next <= '1';
-		reset_zpu_next <= '0';
-		reset_6502_cpu_next <= config_6502_reg(7);
-		
-		if (request_reset_zpu = '1') then
-			reset_n_next <= '0';
-			reset_zpu_next <= '1';
-			reset_6502_cpu_next <= '1';
-		end if;
-	end process;
-	
 	-- outputs
 	PAUSE_ZPU <= paused_reg;
-	LEDG <= ledg_reg;
-	LEDR <= ledr_reg;
+
+	out1 <= out1_reg;
+	out2 <= out2_reg;
+	out3 <= out3_reg;
+	out4 <= out4_reg;
 	
 	SDCARD_CLK <= spi_clk_out;
 	SDCARD_CMD <= spi_mosi;
 	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
 	SDCARD_DAT3 <= spi_chip_select(0);
-	
-	PAL <= '1'; -- TODO
-	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
-	--USE_SDRAM <= '0'; -- should not be all or nothing. can mix for higher ram settings...
-	RAM_SELECT <= ram_select_reg;
-	VGA <= '1';
-	COMPOSITE_ON_HSYNC <= '0';
-	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
-	ROM_SELECT <= "01";--rom_select_reg;
-	
-	reset_n <= reset_n_reg; -- system reset or pll not locked
-	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
-	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
-	
-	pause_6502 <= config_6502_reg(6); -- zpu software controlled
-	
-	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
-	
-	zpu_hex <= zpu_hex_reg;
-	
-	sector <= sector_reg;
-	sector_request <= sector_request_reg;
 end vhdl;
 
 
Index: common/zpu/zpu_glue.vhdl
===================================================================
--- common/zpu/zpu_glue.vhdl	(revision 6)
+++ common/zpu/zpu_glue.vhdl	(revision 7)
@@ -24,12 +24,11 @@
 	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
 	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
 	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
-	ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
 	
 	ZPU_DO : out std_logic_vector(31 downto 0);
 	
-	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(15 downto 0); -- direct from zpu, for short paths
 	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
 	
 	-- request
@@ -130,11 +129,6 @@
 	constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";	
 	constant result_config     : std_logic_vector(4 downto 0) := "01011";	
 	constant result_external_special : std_logic_vector(4 downto 0) := "01100";
-	constant result_sec        : std_logic_vector(4 downto 0) := "01101";
-	constant result_sec_8bit_0 : std_logic_vector(4 downto 0) := "01110";
-	constant result_sec_8bit_1 : std_logic_vector(4 downto 0) := "01111";
-	constant result_sec_8bit_2 : std_logic_vector(4 downto 0) := "10000";
-	constant result_sec_8bit_3 : std_logic_vector(4 downto 0) := "10001";
 	
 	signal request_type : std_logic_vector(4 downto 0);
 	
@@ -251,41 +245,21 @@
 				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
 				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
 			when "01010" =>
-				-- TODO - addr(14) should just feed 1 bit in result reg!
-				if (zpu_addr_unsigned(14) = '1') then
-					if (zpu_8bit_read_enable_temp='1') then
-						case (zpu_addr_unsigned(1 downto 0)) is
-						when "00" =>
-							result_next <= result_sec_8bit_0;										
-						when "01" =>
-							result_next <= result_sec_8bit_1;
-						when "10" =>
-							result_next <= result_sec_8bit_2;										
-						when "11" =>
-							result_next <= result_sec_8bit_3;
-						when others =>
-							--nop
-						end case;
-					else
-						result_next <= result_sec;
-					end if;					
+				if (zpu_8bit_read_enable_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_rom_8bit_3;										
+					when "01" =>
+						result_next <= result_rom_8bit_2;
+					when "10" =>
+						result_next <= result_rom_8bit_1;										
+					when "11" =>
+						result_next <= result_rom_8bit_0;
+					when others =>
+						--nop
+					end case;
 				else
-					if (zpu_8bit_read_enable_temp='1') then
-						case (zpu_addr_unsigned(1 downto 0)) is
-						when "00" =>
-							result_next <= result_rom_8bit_3;										
-						when "01" =>
-							result_next <= result_rom_8bit_2;
-						when "10" =>
-							result_next <= result_rom_8bit_1;										
-						when "11" =>
-							result_next <= result_rom_8bit_0;
-						when others =>
-							--nop
-						end case;
-					else
-						result_next <= result_rom;
-					end if;
+					result_next <= result_rom;
 				end if;
 				ZPU_MEM_BUSY <= '1';
 				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
@@ -328,7 +302,7 @@
 	end process;
 
 	zpu_di_next <= zpu_di;
-	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di, zpu_sector_di)
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
 	begin
 		zpu_di_use <= (others=>'0');
 		case result_reg is 
@@ -356,16 +330,6 @@
 				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
 			when result_ram_8bit_3 =>
 				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
-			when result_sec =>
-				zpu_di_use <= zpu_sector_DI;
-			when result_sec_8bit_0 =>
-				zpu_di_use(7 downto 0) <= zpu_sector_DI(7 downto 0);
-			when result_sec_8bit_1 =>
-				zpu_di_use(7 downto 0) <= zpu_sector_DI(15 downto 8);
-			when result_sec_8bit_2 =>
-				zpu_di_use(7 downto 0) <= zpu_sector_DI(23 downto 16);
-			when result_sec_8bit_3 =>
-				zpu_di_use(7 downto 0) <= zpu_sector_DI(31 downto 24);								
 			when result_config =>
 				zpu_di_use <= zpu_config_di;
 			when others =>
@@ -384,7 +348,7 @@
 	
 	zpu_di_unsigned <= unsigned(zpu_di_use);
 	zpu_do <= zpu_do_next;
-	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next(15 downto 0);
 	ZPU_ADDR_FETCH <= zpu_addr_reg;
 		
 	zpu_read_enable <= zpu_read_reg;
Index: common/zpu/zpucore.cmd
===================================================================
--- common/zpu/zpucore.cmd	(nonexistent)
+++ common/zpu/zpucore.cmd	(revision 7)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: common/zpu/zpucore.vhd
===================================================================
--- common/zpu/zpucore.vhd	(nonexistent)
+++ common/zpu/zpucore.vhd	(revision 7)
@@ -0,0 +1,212 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY zpucore IS 
+	GENERIC
+	(
+		platform : integer := 1 -- So ROM can detect which type of system...
+	);
+	PORT
+	(
+		-- standard...
+		CLK : in std_logic;
+		RESET_N : in std_logic;
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0);
+		ZPU_DATA_OUT : out std_logic_vector(31 downto 0);
+		ZPU_FETCH : out std_logic;
+		ZPU_32BIT_WRITE_ENABLE : out std_logic;
+		ZPU_16BIT_WRITE_ENABLE : out std_logic;
+		ZPU_8BIT_WRITE_ENABLE : out std_logic;
+		ZPU_READ_ENABLE : out std_logic;
+		ZPU_MEMORY_READY : in std_logic;
+		ZPU_MEMORY_DATA : in std_logic_vector(31 downto 0);
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM : out std_logic_vector(15 downto 0);
+		ZPU_ROM_DATA : in std_logic_vector(31 downto 0);
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 :  IN  STD_LOGIC;
+		ZPU_SD_CLK :  OUT  STD_LOGIC;
+		ZPU_SD_CMD :  OUT  STD_LOGIC;
+		ZPU_SD_DAT3 :  OUT  STD_LOGIC;
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE : in std_logic; -- if run at 1.79MHz we can use standard dividers...
+		ZPU_SIO_TXD : out std_logic;
+		ZPU_SIO_RXD : in std_logic;
+		ZPU_SIO_COMMAND : in std_logic;
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 : in std_logic_vector(31 downto 0);
+		ZPU_IN2 : in std_logic_vector(31 downto 0);
+		ZPU_IN3 : in std_logic_vector(31 downto 0);
+		ZPU_IN4 : in std_logic_vector(31 downto 0);
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 : out std_logic_vector(31 downto 0);
+		ZPU_OUT2 : out std_logic_vector(31 downto 0);
+		ZPU_OUT3 : out std_logic_vector(31 downto 0);
+		ZPU_OUT4 : out std_logic_vector(31 downto 0)
+	);
+END zpucore;
+
+ARCHITECTURE vhdl OF zpucore IS 
+	signal ZPU_PAUSE : std_logic;
+	signal ZPU_RESET : std_logic;
+
+	signal ZPU_DO : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM_RAM : std_logic_vector(15 downto 0);
+
+	signal ZPU_RAM_DATA : std_logic_vector(31 downto 0);
+	signal ZPU_STACK_WRITE : std_logic_vector(3 downto 0);
+
+	signal ZPU_CONFIG_DO : std_logic_vector(31 downto 0);
+	signal ZPU_CONFIG_WRITE_ENABLE : std_logic;
+BEGIN 
+
+ZPU_RESET <= not(reset_n);
+zpu_and_glue : entity work.zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => ZPU_MEMORY_READY,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => ZPU_MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+config_regs : entity work.zpu_config_regs
+GENERIC MAP (
+	platform => platform
+)
+PORT MAP (
+	CLK => CLK,
+	RESET_N => RESET_N,
+	
+	POKEY_ENABLE => ZPU_POKEY_ENABLE,
+	
+	ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+	CPU_DATA_IN => ZPU_DO,
+	WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+	
+	IN1 => ZPU_IN1,
+	IN2 => ZPU_IN2,
+	IN3 => ZPU_IN3,
+	IN4 => ZPU_IN4,
+	
+	OUT1 => ZPU_OUT1,
+	OUT2 => ZPU_OUT2,
+	OUT3 => ZPU_OUT3,
+	OUT4 => ZPU_OUT4,
+	
+	SDCARD_DAT => ZPU_SD_DAT0,
+	SDCARD_CLK => ZPU_SD_CLK,
+	SDCARD_CMD => ZPU_SD_CMD,
+	SDCARD_DAT3 => ZPU_SD_DAT3,
+	
+	SIO_DATA_IN => ZPU_SIO_TXD,
+	SIO_DATA_OUT => ZPU_SIO_RXD,
+	SIO_COMMAND => ZPU_SIO_COMMAND,
+	
+	DATA_OUT => ZPU_CONFIG_DO,
+	PAUSE_ZPU => ZPU_PAUSE
+	);
+
+ram_31_24 : entity work.generic_ram_infer
+	GENERIC MAP
+	(
+		ADDRESS_WIDTH => 10,
+		SPACE => 1024,
+		DATA_WIDTH => 8
+	)
+	PORT MAP
+	(
+		we => ZPU_STACK_WRITE(3),
+		clock => CLK,
+		address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		data => ZPU_DO(31 DOWNTO 24),
+		q => ZPU_RAM_DATA(31 DOWNTO 24)
+	);
+
+ram23_16 : entity work.generic_ram_infer
+	GENERIC MAP
+	(
+		ADDRESS_WIDTH => 10,
+		SPACE => 1024,
+		DATA_WIDTH => 8
+	)
+	PORT MAP
+	(
+		we => ZPU_STACK_WRITE(2),
+		clock => CLK,
+		address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		data => ZPU_DO(23 DOWNTO 16),
+		q => ZPU_RAM_DATA(23 DOWNTO 16)
+	);
+
+ram_15_8 : entity work.generic_ram_infer
+	GENERIC MAP
+	(
+		ADDRESS_WIDTH => 10,
+		SPACE => 1024,
+		DATA_WIDTH => 8
+	)
+	PORT MAP
+	(
+		we => ZPU_STACK_WRITE(1),
+		clock => CLK,
+		address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		data => ZPU_DO(15 DOWNTO 8),
+		q => ZPU_RAM_DATA(15 DOWNTO 8)
+	);
+
+ram_7_0 : entity work.generic_ram_infer
+	GENERIC MAP
+	(
+		ADDRESS_WIDTH => 10,
+		SPACE => 1024,
+		DATA_WIDTH => 8
+	)
+	PORT MAP
+	(
+		we => ZPU_STACK_WRITE(0),
+		clock => CLK,
+		address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		data => ZPU_DO(7 DOWNTO 0),
+		q => ZPU_RAM_DATA(7 DOWNTO 0)
+	);
+
+	-- OUTPUT
+	ZPU_ADDR_ROM <= ZPU_ADDR_ROM_RAM;
+	ZPU_DATA_OUT <= ZPU_DO;
+
+end vhdl;
Index: common/zpu/zpucore.wcfg
===================================================================
--- common/zpu/zpucore.wcfg	(nonexistent)
+++ common/zpu/zpucore.wcfg	(revision 7)
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="zpucore.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="attributes" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_misc" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+            <top_module name="zpucore_tb" />
+            <top_module name="zpupkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="12" />
+   <wvobject fp_name="/zpucore_tb/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_fetch" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_fetch</obj_property>
+      <obj_property name="ObjectShortName">zpu_fetch</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_32bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_32bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_32bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_16bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_16bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_16bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_8bit_write_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_8bit_write_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_8bit_write_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_read_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_read_enable</obj_property>
+      <obj_property name="ObjectShortName">zpu_read_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_memory_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_memory_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_memory_ready</obj_property>
+      <obj_property name="ObjectShortName">zpu_memory_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_addr_rom" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_addr_rom[15:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_addr_rom[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/zpu_rom_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">zpu_rom_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">zpu_rom_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/zpucore_tb/clk_a_period" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a_period</obj_property>
+      <obj_property name="ObjectShortName">clk_a_period</obj_property>
+   </wvobject>
+</wave_config>
