Index: mist/atari800core.qsf
===================================================================
--- mist/atari800core.qsf	(revision 69)
+++ mist/atari800core.qsf	(revision 70)
@@ -309,6 +309,7 @@
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 set_global_assignment -name VHDL_FILE data_io.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
 set_global_assignment -name SDC_FILE atari800core.sdc
 set_global_assignment -name QIP_FILE mist_sector_buffer.qip
 set_global_assignment -name VHDL_FILE atari800core_mist.vhd
Index: mist/atari800core_mist.vhd
===================================================================
--- mist/atari800core_mist.vhd	(revision 69)
+++ mist/atari800core_mist.vhd	(revision 70)
@@ -1,5 +1,4 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
+--------------------------------------------------------------------------- -- (c) 2013 mark watson
 -- I am happy for anyone to use this for non-commercial use.
 -- If my vhdl files are used commercially or otherwise sold,
 -- please contact me for explicit permission at scrameta (gmail).
@@ -74,14 +73,14 @@
 	   CORE_TYPE : in std_logic_vector(7 downto 0);
 		JOY0 : out std_logic_vector(5 downto 0);
 		JOY1 : out std_logic_vector(5 downto 0);
-		KEYBOARD : out std_logic_vector(127 downto 0);
 		BUTTONS : out std_logic_vector(1 downto 0);
-		SWITCHES : out std_logic_vector(1 downto 0)
+		SWITCHES : out std_logic_vector(1 downto 0);
+		CLK : in std_logic;
+		PS2_CLK : out std_logic;
+		PS2_DATA : out std_logic
 	  );
 end component;
 
-
-
   signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
   signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
 
@@ -93,16 +92,12 @@
   signal CLK : std_logic;
   signal CLK_SDRAM : std_logic;
 
-  signal keyboard : std_logic_vector(127 downto 0);
-  signal atari_keyboard : std_logic_vector(63 downto 0);
-  
-  SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
-  SIGNAL	BREAK_PRESSED :  STD_LOGIC;
-  SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
-
+  SIGNAL PS2_CLK : std_logic;
+  SIGNAL PS2_DAT : std_logic;
   SIGNAL	CONSOL_OPTION :  STD_LOGIC;
   SIGNAL	CONSOL_SELECT :  STD_LOGIC;
   SIGNAL	CONSOL_START :  STD_LOGIC;
+  SIGNAL FKEYS : std_logic_vector(11 downto 0);
 
   signal capslock_pressed : std_logic;
   signal capsheld_next : std_logic;
@@ -112,8 +107,10 @@
   signal mist_sector_ready_sync : std_logic;
   signal mist_sector_request : std_logic;
   signal mist_sector_request_sync : std_logic;
-  signal mist_sector : std_logic_vector(31 downto 0);
-  signal mist_sector_sync : std_logic_vector(31 downto 0);
+  signal mist_sector_write : std_logic;
+  signal mist_sector_write_sync : std_logic;
+  signal mist_sector : std_logic_vector(23 downto 0);
+  signal mist_sector_sync : std_logic_vector(23 downto 0);
   
   		
   signal mist_addr : std_logic_vector(8 downto 0);
@@ -135,8 +132,6 @@
   SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
 
-  SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-
   SIGNAL PAL : std_logic;
 
   signal SDRAM_REQUEST : std_logic;
@@ -152,10 +147,48 @@
 
   signal SDRAM_REFRESH : std_logic;
   
-  signal SYSTEM_RESET_REQUEST: std_logic;
-  
   signal SDRAM_RESET_N : std_logic;
 
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
+	-- mist sector
+	signal ZPU_ROM_DATA_MUX :  std_logic_vector(31 downto 0);
+	signal ZPU_SECTOR_DATA :  std_logic_vector(31 downto 0);
+	signal ZPU_ROM_DO :  std_logic_vector(31 downto 0);
+	signal ZPU_ROM_WREN :  std_logic;
+
+	-- ps2
+	signal SLOW_PS2_CLK : std_logic; -- around 16KHz
+
 BEGIN 
 pal <= '1'; -- TODO, two builds, with appropriate pll settings
 
@@ -173,7 +206,9 @@
 		SPI_MOSI => spi_di,
 		
 		-- Sector access request
-		request => mist_sector_request_sync,
+		read_request => mist_sector_request_sync,
+		write_request => mist_sector_write_sync,
+		--request => mist_sector_request_sync,
 		sector => mist_sector_sync(23 downto 0),
 		ready => mist_sector_ready,
 		
@@ -191,6 +226,9 @@
 	select_sync2 : entity work.synchronizer
 	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
 
+	select_sync3 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_write, sync=>mist_sector_write_sync);
+
 	sector_sync0 : entity work.synchronizer
 	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
 
@@ -270,15 +308,15 @@
 	PORT map
 	(
 		address_a		=> mist_addr,
-		address_b		=> "0000000", -- TODO - need to expose a 2nd dma channel of some kind, so we don't have to halt 6502 to access sector buffer! ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
+		address_b		=> zpu_addr_rom(8 downto 2),
 		clock_a		=> spi_sck,
 		clock_b		=> clk,
 		data_a		=> mist_do,
-		data_b		=> X"00000000", -- TODO zpu_do,
+		data_b		=> dma_write_data(7 downto 0)&dma_write_data(15 downto 8)&dma_write_data(23 downto 16)&dma_write_data(31 downto 24),
 		wren_a		=> mist_wren,
-		wren_b		=> '0',
+		wren_b		=> zpu_rom_wren, 
 		q_a		=> mist_di,
-		q_b		=> open -- TODO zpu_sector_data
+		q_b		=> zpu_sector_data
 	);
 	
 my_user_io : user_io
@@ -290,135 +328,35 @@
 	   CORE_TYPE => x"A4",
 		JOY0 => joy1,
 		JOY1 => joy2,
-		KEYBOARD => keyboard,
 		BUTTONS => mist_buttons,
-		SWITCHES => mist_switches
+		SWITCHES => mist_switches,
+		CLK => SLOW_PS2_CLK,
+		PS2_CLK => ps2_clk,
+		PS2_DATA => ps2_dat
 	  );
 	  
 	 joy1_n <= not(joy1(4 downto 0));
 	 joy2_n <= not(joy2(4 downto 0));
-	 
-	process(clk,reset_n)
-	begin
-		if (reset_n='0') then
-			capsheld_reg <= '0';
-		elsif (clk'event and clk='1') then
-			capsheld_reg <= capsheld_next;
-		end if;
-	end process;
 
--- TODO, this doesn't work yet
-	process(keyboard,capsheld_reg)
-	begin
-		capsheld_next <= capsheld_reg;
-		capslock_pressed <= '0';
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari800
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2_clk,
+		PS2_DAT => ps2_dat,
 		
-		if ((keyboard(58) xor capsheld_reg)='1') then
-			capsheld_next <= keyboard(58);
-			
-			-- assert something for 10 frames
-			capslock_pressed <= '1';
-		end if;
-	end process;
-	
--- TODO, this is mapping from ST keycode, make mist firmware send PS2 keycodes or USB keycodes if possible
-atari_keyboard(63) <= keyboard(30);
-atari_keyboard(62) <= keyboard(31);
-atari_keyboard(61) <= keyboard(34);
-atari_keyboard(60) <= '0';
-atari_keyboard(58) <= keyboard(32);
-atari_keyboard(57) <= keyboard(35);
-atari_keyboard(56) <= keyboard(33);
-atari_keyboard(55) <= keyboard(13);
-atari_keyboard(54) <= keyboard(12);
-atari_keyboard(53) <= keyboard(9);
-atari_keyboard(52) <= keyboard(14);
-atari_keyboard(51) <= keyboard(8);
-atari_keyboard(50) <= keyboard(11);
-atari_keyboard(48) <= keyboard(10);
-atari_keyboard(47) <= keyboard(16);
-atari_keyboard(46) <= keyboard(17);
-atari_keyboard(45) <= keyboard(20);
-atari_keyboard(44) <= keyboard(15);
-atari_keyboard(43) <= keyboard(21);
-atari_keyboard(42) <= keyboard(18);
-atari_keyboard(40) <= keyboard(19);
-atari_keyboard(39) <= keyboard(56);
-atari_keyboard(38) <= keyboard(53);
-atari_keyboard(37) <= keyboard(50);
-atari_keyboard(35) <= keyboard(49);
-atari_keyboard(34) <= keyboard(52);
-atari_keyboard(33) <= keyboard(57);
-atari_keyboard(32) <= keyboard(51);
-atari_keyboard(31) <= keyboard(2);
-atari_keyboard(30) <= keyboard(3);
-atari_keyboard(29) <= keyboard(6);
-atari_keyboard(28) <= keyboard(1);
-atari_keyboard(27) <= keyboard(7);
-atari_keyboard(26) <= keyboard(4);
-atari_keyboard(24) <= keyboard(5);
-atari_keyboard(23) <= keyboard(44);
-atari_keyboard(22) <= keyboard(45);
-atari_keyboard(21) <= keyboard(48);
-atari_keyboard(18) <= keyboard(46);
-atari_keyboard(17) <= keyboard(59);
-atari_keyboard(16) <= keyboard(47);
-atari_keyboard(15) <= keyboard(27);
-atari_keyboard(14) <= keyboard(26);
-atari_keyboard(13) <= keyboard(23);
-atari_keyboard(12) <= keyboard(28);
-atari_keyboard(11) <= keyboard(22);
-atari_keyboard(10) <= keyboard(25);
-atari_keyboard(8) <= keyboard(24);
-atari_keyboard(7) <= keyboard(41);
-atari_keyboard(6) <= keyboard(40);
-atari_keyboard(5) <= keyboard(37);
-atari_keyboard(2) <= keyboard(39);
-atari_keyboard(1) <= keyboard(36);
-atari_keyboard(0) <= keyboard(38);
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
 
-	  
-shift_pressed <= keyboard(54) or keyboard(42);
-control_pressed <= keyboard(29);
-break_pressed <= keyboard(96); -- TODO - not on st keyboard
-
-consol_start <= keyboard(60); --F2
-consol_select <= keyboard(61); --F3
-consol_option <= keyboard(62); -- F4
+		CONSOL_START => CONSOL_START,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_OPTION => CONSOL_OPTION,
 		
---f5 <= keyboard(63);
---f6 <= keyboard(64);
---f7 <= keyboard(65);
---f8 <= keyboard(66);
---f9 <= keyboard(67);
---f10 <= keyboard(68);
-
---HOT KEYS! Connect to ZPU when present...
---virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
-SYSTEM_RESET_REQUEST <= keyboard(63);
-
--- TODO this should be common, same for PS2 after mapping...
-process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
-	begin	
-		keyboard_response <= (others=>'1');		
-		
-		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
-			keyboard_response(0) <= '0';
-		end if;
-		
-		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-		
-		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-
-		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-end process;		 
-		  
+		FKEYS => FKEYS
+	);
+	 
 dac_left : hq_dac
 port map
 (
@@ -439,27 +377,21 @@
   dac_out => audio_r
 );
 
--- TODO - mist joystick mapping!
---GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
---fire is bit 4...
-
 mist_pll : entity work.pll
 PORT MAP(inclk0 => CLOCK_27(0),
 		 c0 => CLK_SDRAM,
 		 c1 => CLK,
 		 c2 => SDRAM_CLK,
+		 c3 => SLOW_PS2_CLK,
 		 locked => PLL_LOCKED);
 
 reset_n <= PLL_LOCKED;
 
--- THROTTLE
-THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(1,6));
-
 atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
 	GENERIC MAP
 	(
 		cycle_length => 32,
-		internal_rom => 1,
+		internal_rom => 0,
 		internal_ram => 0,
 		video_bits => 6
 	)
@@ -466,7 +398,7 @@
 	PORT MAP
 	(
 		CLK => CLK,
-		RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
+		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
 
 		VIDEO_VS => VGA_VS_RAW,
 		VIDEO_HS => VGA_HS_RAW,
@@ -477,15 +409,15 @@
 		AUDIO_L => AUDIO_L_PCM,
 		AUDIO_R => AUDIO_R_PCM,
 
-		JOY1_n => JOY1_n,
-		JOY2_n => JOY2_n,
+		JOY1_n => JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3),
+		JOY2_n => JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3),
 
 		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
 		KEYBOARD_SCAN => KEYBOARD_SCAN,
 
-		SIO_COMMAND => open,
-		SIO_RXD => '1',
-		SIO_TXD => open,
+		SIO_COMMAND => zpu_sio_command,
+		SIO_RXD => zpu_sio_txd,
+		SIO_TXD => zpu_sio_rxd,
 
 		CONSOL_OPTION => CONSOL_OPTION,
 		CONSOL_SELECT => CONSOL_SELECT,
@@ -501,21 +433,23 @@
 		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
 		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
 		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_REFRESH => SDRAM_REFRESH,
 
-		DMA_FETCH => '0',
-		DMA_READ_ENABLE => '0',
-		DMA_32BIT_WRITE_ENABLE => '0',
-		DMA_16BIT_WRITE_ENABLE => '0',
-		DMA_8BIT_WRITE_ENABLE => '0',
-		DMA_ADDR => (others=>'1'),
-		DMA_WRITE_DATA => (others=>'1'),
-		MEMORY_READY_DMA => open,
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
 
-   		RAM_SELECT => (others=>'0'),
-    		ROM_SELECT => "000001",
+   		RAM_SELECT => ram_select,
+    		ROM_SELECT => rom_select,
 		PAL => PAL,
-		HALT => '0',
-		THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
+		HALT => pause_atari,
+		THROTTLE_COUNT_6502 => speed_6502
 	);
 
 sdram_adaptor : entity work.sdram_statemachine
@@ -526,7 +460,7 @@
 			)
 PORT MAP(CLK_SYSTEM => CLK,
 		 CLK_SDRAM => CLK_SDRAM,
-		 RESET_N =>  RESET_N and not(SYSTEM_RESET_REQUEST),
+		 RESET_N =>  RESET_N,
 		 READ_EN => SDRAM_READ_ENABLE,
 		 WRITE_EN => SDRAM_WRITE_ENABLE,
 		 REQUEST => SDRAM_REQUEST,
@@ -553,7 +487,7 @@
 		 );
 		 
 SDRAM_A(12) <= '0';
-SDRAM_REFRESH <= '0'; -- TODO
+--SDRAM_REFRESH <= '0'; -- TODO
 
 -- Until SDRAM enabled... TODO
 --SDRAM_nCS <= '1';
@@ -565,4 +499,91 @@
 VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
 VGA_VS <= not(VGA_VS_RAW);
 
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_reset_n,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data_mux,
+	
+		ZPU_ROM_WREN => zpu_rom_wren, -- special for mist...
+
+		-- spi master
+		-- not used for mist...
+		ZPU_SD_DAT0 => '0',
+		ZPU_SD_CLK => open,
+		ZPU_SD_CMD => open,
+		ZPU_SD_DAT3 => open,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"00000"&FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"000000"&"0000000"&mist_sector_ready_sync,
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	mist_sector <= zpu_out4(23 downto 0);
+	mist_sector_request <= zpu_out4(24);
+	mist_sector_write <= zpu_out4(25);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+process(zpu_addr_rom, zpu_rom_data, zpu_sector_data)
+begin
+	zpu_rom_data_mux <= zpu_rom_data;
+	if (zpu_addr_rom(15 downto 14) = "01") then
+		zpu_rom_data_mux <= zpu_sector_data(7 downto 0)&zpu_sector_data(15 downto 8)&zpu_sector_data(23 downto 16)&zpu_sector_data(31 downto 24);
+	end if;
+end process;
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>32) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
 END vhdl;
Index: mist/build.sh
===================================================================
--- mist/build.sh	(revision 69)
+++ mist/build.sh	(revision 70)
@@ -6,13 +6,16 @@
 cp data_io.vhdl build
 cp user_io.v build
 cp mist_sector_buffer.* build
+cp zpu_rom.vhdl build
 mkdir build/common
 mkdir build/common/a8core
 mkdir build/common/components
+mkdir build/common/zpu
 cp ../common/a8core/* ./build/common/a8core
 cp ../common/components/* ./build/common/components
+cp ../common/zpu/* ./build/common/zpu
 
 cd build
-../makeqsf ../atari800core.qsf ./common/a8core ./common/components
+../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu
 
 quartus_sh --flow compile atari800core
Index: mist/data_io.cmd
===================================================================
--- mist/data_io.cmd	(nonexistent)
+++ mist/data_io.cmd	(revision 70)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mist/data_io.vhdl
===================================================================
--- mist/data_io.vhdl	(revision 69)
+++ mist/data_io.vhdl	(revision 70)
@@ -16,8 +16,9 @@
 	   SPI_MISO: out std_logic;
 	   SPI_MOSI : in std_logic;
 		
-		-- Sector access request
-		request : in std_logic;
+		-- Sector access read_request
+		read_request : in std_logic;
+		write_request : in std_logic;
 		sector : in std_logic_vector(23 downto 0);
 		ready : out std_logic;
 		
@@ -40,6 +41,9 @@
 	
 	signal cnt_next : std_logic_vector(15 downto 0);
 	signal cnt_reg : std_logic_vector(15 downto 0);
+
+	signal data_in_next : std_logic_vector(7 downto 0);
+	signal data_in_reg : std_logic_vector(7 downto 0);
 
 	signal data_out_next : std_logic_vector(7 downto 0);
 	signal data_out_reg : std_logic_vector(7 downto 0);
@@ -59,18 +63,29 @@
 	signal sector_next : std_logic_vector(23 downto 0);
 	signal sector_reg : std_logic_vector(23 downto 0);
 	
-	signal request_next : std_logic;
-	signal request_reg : std_logic;
+	signal read_request_next : std_logic;
+	signal read_request_reg : std_logic;
 	
+	signal write_request_next : std_logic;
+	signal write_request_reg : std_logic;
+
+	signal clk2 : std_logic;
 begin	 
-	process(clk,reset_n)
+	clk2 <= clk or spi_ss_io;
+
+	process(clk2,reset_n,spi_ss_io)
 	begin
-		if (reset_n = '0') then
+		if (spi_ss_io = '1') then
+			cnt_reg <= (others=>'0');
+			cmd_reg <= (others=>'0');
+			wren_reg <= '0';
+		elsif (reset_n = '0') then
 			cnt_reg <= (others=>'0');
 			cmd_reg <= (others=>'0');
 			sbuf_reg <= (others=>'0');
 			
 			addr_reg <= (others => '0');
+			data_in_reg <= (others => '0');
 			data_out_reg <= (others => '0');
 			wren_reg <= '0';			
 			
@@ -78,14 +93,16 @@
 			
 			transmit_reg <= (others=>'0');
 			
-			request_reg <= '0';
+			read_request_reg <= '0';
+			write_request_reg <= '0';
 			sector_reg <=(others=>'0');
-		elsif (clk'event and clk='1') then
+		elsif (clk2'event and clk2='1') then
 			cnt_reg <= cnt_next;
 			cmd_reg <= cmd_next;
 			sbuf_reg <= sbuf_next;			
 			
 			addr_reg <= addr_next;
+			data_in_reg <= data_in_next;
 			data_out_reg <= data_out_next;
 			wren_reg <= wren_next;
 			
@@ -93,7 +110,8 @@
 		
 			transmit_reg <= transmit_next;
 
-			request_reg <= request_next;
+			read_request_reg <= read_request_next;
+			write_request_reg <= write_request_next;
 			sector_reg <= sector_next;			
 		end if;
 	end process;	
@@ -107,13 +125,15 @@
 
 --	select_sync : synchronizer
 --	PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
+
+	data_in_next <= data_in;
 
-	process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, request_reg, ready_reg,request,sector)
+	process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, write_request_reg, read_request_reg, ready_reg,read_request,write_request,sector,data_in_reg)
 	begin
 		cnt_next <= cnt_reg;
 		sbuf_next <= sbuf_reg;
 		cmd_next <= cmd_reg;
-		ready_next <= ready_reg and request; -- stay ready until request cleared (received by other end)
+		ready_next <= ready_reg and (read_request or write_request); -- stay ready until read_request cleared (received by other end)
 		
 		transmit_next <= transmit_reg;
 		
@@ -122,7 +142,8 @@
 		addr_next <= addr_reg;
 		
 		sector_next <= sector_reg;
-		request_next <= request_reg;		
+		read_request_next <= read_request_reg;		
+		write_request_next <= write_request_reg;		
 		
 --- It polls get_status 10 times a second
 --- it uses SPI_SS2 for this
@@ -146,23 +167,22 @@
 		
 		sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
 		sbuf_next(0) <= SPI_MOSI;
+
+		if (cnt_reg = X"0000") then
+			addr_next <= (others=>'0');
+		end if;
 			
 		if (cnt_reg = X"0007") then
 			cmd_next(7 downto 1) <= sbuf_reg;
 			cmd_next(0) <= SPI_MOSI;
-			addr_next <= (others=>'1');
 			
 			sector_next <= sector;
-			request_next <= request;		
+			read_request_next <= read_request;		
+			write_request_next <= write_request;		
 		end if;
 			
 		--end if;
 		
-		if (spi_ss_io = '1') then
-			cnt_next <= (others=>'0');
-			cmd_next <= (others=>'0');
-		end if;	
-		
 		case cmd_reg is
 		when X"50" => --get status
 			case cnt_reg is 
@@ -173,21 +193,33 @@
 			when X"0018" =>
 				transmit_next <= sector_reg(7 downto 0);				
 			when X"0020" =>
-				transmit_next <= "1010010"&request_reg; --read request
+				transmit_next <= "101001"&write_request_reg&read_request_reg; --read read_request
 			when others =>
 				-- nothing
 			end case;
 		when X"51" => --sector read from sd, write it...
+			if (cnt_reg = X"0008") then
+				addr_next <= (others=>'1');
+			end if;
 			if (cnt_reg(2 downto 0) = "111") then
 				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
 				data_out_next(7 downto 1) <= sbuf_reg;
 				data_out_next(0) <= SPI_MOSI;
-				wren_next <= request;
+				wren_next <= read_request;
 				
 				if (cnt_reg(12) = '1')then
 					ready_next <= '1';
 				end if;
 			end if;
+		when X"52" => -- read from write, write to sd
+			if (cnt_reg(2 downto 0) = "000") then
+				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
+				transmit_next <= data_in_reg;
+				
+				if (cnt_reg(12) = '1')then
+					ready_next <= '1';
+				end if;
+			end if;
 		when others =>
 			-- nop
 		end case;
@@ -194,9 +226,9 @@
 	end process;
 
 	-- outputs
-	addr <= addr_reg;
-	data_out <= data_out_reg;
-	wr_en <= wren_reg;
+	addr <= addr_next;
+	data_out <= data_out_next;
+	wr_en <= wren_next;
 	
 	ready <= ready_reg;
 
Index: mist/data_io.wcfg
===================================================================
--- mist/data_io.wcfg	(nonexistent)
+++ mist/data_io.wcfg	(revision 70)
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="data_io.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="data_io_tb" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="19" />
+   <wvobject fp_name="/data_io_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">request</obj_property>
+      <obj_property name="ObjectShortName">request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write</obj_property>
+      <obj_property name="ObjectShortName">write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_miso</obj_property>
+      <obj_property name="ObjectShortName">spi_miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_mosi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_mosi</obj_property>
+      <obj_property name="ObjectShortName">spi_mosi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_clk</obj_property>
+      <obj_property name="ObjectShortName">spi_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_tx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_tx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_tx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_busy</obj_property>
+      <obj_property name="ObjectShortName">spi_busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_enable</obj_property>
+      <obj_property name="ObjectShortName">spi_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/cmd_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cmd_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cmd_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/cnt_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cnt_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">cnt_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/sbuf_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sbuf_reg[6:0]</obj_property>
+      <obj_property name="ObjectShortName">sbuf_reg[6:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[8:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[8:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_ss_io" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_ss_io[1:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_ss_io[1:0]</obj_property>
+   </wvobject>
+</wave_config>
Index: mist/pll.bsf
===================================================================
--- mist/pll.bsf	(revision 69)
+++ mist/pll.bsf	(revision 70)
@@ -1,100 +1,112 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2012 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.2"))
-(symbol
-	(rect 0 0 256 184)
-	(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 25 180)(font "Arial" ))
-	(port
-		(pt 0 64)
-		(input)
-		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 40 64))
-	)
-	(port
-		(pt 256 64)
-		(output)
-		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
-	)
-	(port
-		(pt 256 80)
-		(output)
-		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
-	)
-	(port
-		(pt 256 96)
-		(output)
-		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
-	)
-	(port
-		(pt 256 112)
-		(output)
-		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
-		(text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
-	)
-	(drawing
-		(text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
-		(text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
-		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
-		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
-		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
-		(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
-		(text "DC (%)" (rect 134 93 298 197)(font "Arial" ))
-		(text "c0" (rect 54 107 116 225)(font "Arial" ))
-		(text "69/16" (rect 72 107 165 225)(font "Arial" ))
-		(text "0.00" (rect 105 107 226 225)(font "Arial" ))
-		(text "50.00" (rect 138 107 297 225)(font "Arial" ))
-		(text "c1" (rect 54 121 115 253)(font "Arial" ))
-		(text "69/32" (rect 72 121 165 253)(font "Arial" ))
-		(text "0.00" (rect 105 121 226 253)(font "Arial" ))
-		(text "50.00" (rect 138 121 297 253)(font "Arial" ))
-		(text "c2" (rect 54 135 116 281)(font "Arial" ))
-		(text "69/16" (rect 72 135 165 281)(font "Arial" ))
-		(text "-100.60" (rect 99 135 227 281)(font "Arial" ))
-		(text "50.00" (rect 138 135 297 281)(font "Arial" ))
-		(line (pt 0 0)(pt 257 0))
-		(line (pt 257 0)(pt 257 185))
-		(line (pt 0 185)(pt 257 185))
-		(line (pt 0 0)(pt 0 185))
-		(line (pt 48 91)(pt 166 91))
-		(line (pt 48 104)(pt 166 104))
-		(line (pt 48 118)(pt 166 118))
-		(line (pt 48 132)(pt 166 132))
-		(line (pt 48 146)(pt 166 146))
-		(line (pt 48 91)(pt 48 146))
-		(line (pt 69 91)(pt 69 146)(line_width 3))
-		(line (pt 96 91)(pt 96 146)(line_width 3))
-		(line (pt 131 91)(pt 131 146)(line_width 3))
-		(line (pt 165 91)(pt 165 146))
-		(line (pt 40 48)(pt 207 48))
-		(line (pt 207 48)(pt 207 167))
-		(line (pt 40 167)(pt 207 167))
-		(line (pt 40 48)(pt 40 167))
-		(line (pt 255 64)(pt 207 64))
-		(line (pt 255 80)(pt 207 80))
-		(line (pt 255 96)(pt 207 96))
-		(line (pt 255 112)(pt 207 112))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 224 168)
+	(text "pll" (rect 106 0 120 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 157 22 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 22 9)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 55 21 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 224 64)
+		(output)
+		(text "c0" (rect 0 0 9 9)(font "Arial" (font_size 8)))
+		(text "c0" (rect 212 55 218 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 224 80)
+		(output)
+		(text "c1" (rect 0 0 9 9)(font "Arial" (font_size 8)))
+		(text "c1" (rect 212 71 218 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 224 96)
+		(output)
+		(text "c2" (rect 0 0 9 9)(font "Arial" (font_size 8)))
+		(text "c2" (rect 212 87 219 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 224 112)
+		(output)
+		(text "c3" (rect 0 0 9 9)(font "Arial" (font_size 8)))
+		(text "c3" (rect 212 103 218 111)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 224 128)
+		(output)
+		(text "locked" (rect 0 0 24 9)(font "Arial" (font_size 8)))
+		(text "locked" (rect 199 119 219 127)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 181 161 394 328)(font "Arial" ))
+		(text "inclk0 frequency: 27.000 MHz" (rect 50 71 191 148)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 79 175 164)(font "Arial" ))
+		(text "Clk " (rect 51 92 112 190)(font "Arial" ))
+		(text "Ratio" (rect 74 92 163 190)(font "Arial" ))
+		(text "Ph (dg)" (rect 102 92 226 190)(font "Arial" ))
+		(text "DC (%)" (rect 129 92 279 190)(font "Arial" ))
+		(text "c0" (rect 53 101 112 208)(font "Arial" ))
+		(text "69/16" (rect 73 101 162 208)(font "Arial" ))
+		(text "0.00" (rect 106 101 224 208)(font "Arial" ))
+		(text "50.00" (rect 131 101 278 208)(font "Arial" ))
+		(text "c1" (rect 53 110 112 226)(font "Arial" ))
+		(text "69/32" (rect 73 110 163 226)(font "Arial" ))
+		(text "0.00" (rect 106 110 224 226)(font "Arial" ))
+		(text "50.00" (rect 131 110 278 226)(font "Arial" ))
+		(text "c2" (rect 53 119 113 244)(font "Arial" ))
+		(text "69/16" (rect 73 119 162 244)(font "Arial" ))
+		(text "-100.60" (rect 101 119 224 244)(font "Arial" ))
+		(text "50.00" (rect 131 119 278 244)(font "Arial" ))
+		(text "c3" (rect 53 128 112 262)(font "Arial" ))
+		(text "23/32768" (rect 67 128 162 262)(font "Arial" ))
+		(text "0.00" (rect 106 128 224 262)(font "Arial" ))
+		(text "50.00" (rect 131 128 278 262)(font "Arial" ))
+		(line (pt 0 0)(pt 225 0))
+		(line (pt 225 0)(pt 225 170))
+		(line (pt 0 170)(pt 225 170))
+		(line (pt 0 0)(pt 0 170))
+		(line (pt 48 90)(pt 152 90))
+		(line (pt 48 98)(pt 152 98))
+		(line (pt 48 107)(pt 152 107))
+		(line (pt 48 116)(pt 152 116))
+		(line (pt 48 125)(pt 152 125))
+		(line (pt 48 134)(pt 152 134))
+		(line (pt 48 90)(pt 48 134))
+		(line (pt 64 90)(pt 64 134)(line_width 3))
+		(line (pt 98 90)(pt 98 134)(line_width 3))
+		(line (pt 126 90)(pt 126 134)(line_width 3))
+		(line (pt 151 90)(pt 151 134))
+		(line (pt 40 48)(pt 183 48))
+		(line (pt 183 48)(pt 183 152))
+		(line (pt 40 152)(pt 183 152))
+		(line (pt 40 48)(pt 40 152))
+		(line (pt 223 64)(pt 183 64))
+		(line (pt 223 80)(pt 183 80))
+		(line (pt 223 96)(pt 183 96))
+		(line (pt 223 112)(pt 183 112))
+		(line (pt 223 128)(pt 183 128))
+	)
+)
Index: mist/pll.cmp
===================================================================
--- mist/pll.cmp	(revision 69)
+++ mist/pll.cmp	(revision 70)
@@ -1,25 +1,26 @@
---Copyright (C) 1991-2012 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component pll
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mist/pll.ppf
===================================================================
--- mist/pll.ppf	(revision 69)
+++ mist/pll.ppf	(revision 70)
@@ -1,12 +1,13 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mist/pll.qip
===================================================================
--- mist/pll.qip	(revision 69)
+++ mist/pll.qip	(revision 70)
@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "12.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: mist/pll.vhd
===================================================================
--- mist/pll.vhd	(revision 69)
+++ mist/pll.vhd	(revision 70)
@@ -1,424 +1,456 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2012 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC 
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	locked    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 16,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 69,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 32,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 69,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 16,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 69,
-		clk2_phase_shift => "-2400",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "OFF",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0,
-		locked => sub_wire2
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	locked    <= sub_wire3;
+	c0    <= sub_wire4;
+	c2    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 16,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 69,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 32,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 69,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 16,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 69,
+		clk2_phase_shift => "-2400",
+		clk3_divide_by => 32768,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 23,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "32768"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.018951"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "32768"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mist/simulate_data_io.sh
===================================================================
--- mist/simulate_data_io.sh	(nonexistent)
+++ mist/simulate_data_io.sh	(revision 70)
@@ -0,0 +1,65 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=data_io
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_data/* .
+
+        # copy source files
+	cp ../data_io.vhdl .
+	cp ../../common/components/spi_master.vhd .
+	cp ../../common/components/generic_ram_infer.vhdl .
+
+        # set up project definition file
+	ls *.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat >> $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: mist/simulate_data_io.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mist/tb_data/data_io_tb.vhd
===================================================================
--- mist/tb_data/data_io_tb.vhd	(nonexistent)
+++ mist/tb_data/data_io_tb.vhd	(revision 70)
@@ -0,0 +1,319 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity data_io_tb is
+end;
+
+architecture rtl of data_io_tb is
+
+  constant CLK_A_PERIOD : time := 1 us / (1.79*32);
+
+  signal CLK_A : std_logic;
+
+  signal reset_n : std_logic;
+
+  signal spi_clk : std_logic;
+  signal spi_ss_io : std_logic_vector(1 downto 0);
+  signal spi_miso : std_logic;
+  signal spi_mosi : std_logic;
+
+  signal request : std_logic;
+  signal write : std_logic;
+  signal ready : std_logic;
+  signal sector : std_logic_vector(23 downto 0);
+
+  signal addr : std_logic_vector(8 downto 0);
+  signal data_out : std_logic_vector(7 downto 0);
+  signal data_in : std_logic_vector(7 downto 0);
+  signal wr_en : std_logic;
+
+  signal spi_enable : std_logic;
+  signal spi_tx_data : std_logic_vector(7 downto 0);
+  signal spi_rx_data : std_logic_vector(7 downto 0);
+  signal spi_busy : std_logic;
+
+  signal spi_addr : integer;
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk_a <= '1';
+	wait for CLK_A_PERIOD/2;
+	clk_a <= '0';
+	wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+
+	spi_master1 : entity work.spi_master
+		generic map(slaves=>2,d_width=>8)
+		port map (clock=>clk_a,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>4,addr=>spi_addr,
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk,ss_n=>spi_ss_io,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+
+	spi_fake : process
+ 	variable type_conv : std_logic_vector(8 downto 0);
+	begin
+	spi_enable <= '0';
+	spi_addr <= 0;
+	wait for 1500us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"51";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		type_conv := std_logic_vector(to_unsigned(i,9));
+		spi_tx_data <= type_conv(7 downto 0);
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	-- NEXT
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"51";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		type_conv := std_logic_vector(to_unsigned(511-i,9));
+		spi_tx_data <= type_conv(7 downto 0);
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	-- NEXT - WRITE...
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"52";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		spi_tx_data <= x"FF";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	wait for 100ms;
+	
+	end process;
+
+	spi_request : process
+	begin
+	sector <= (others=>'0');
+	request <= '0';
+	write <= '0';
+	wait for 1500us;
+
+	sector <= x"123456";
+	request <= '1';
+	wait until ready = '1';
+	request <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+
+	sector <= x"654321";
+	request <= '1';
+	wait until ready = '1';
+	request <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+	sector <= x"111111";
+	write <= '1';
+	wait until ready = '1';
+	write <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+	wait for 100ms;
+	end process;
+
+	ram : entity work.generic_ram_infer
+	generic map
+	(
+		ADDRESS_WIDTH => 9,
+		SPACE => 512,
+		DATA_WIDTH => 8
+	)
+   PORT map
+   (
+      clock => spi_clk,
+      data => data_out,
+      address => addr,
+      we => wr_en,
+      q => data_in
+   );
+
+	data_io : entity work.data_io
+	PORT MAP
+	(
+		CLK => spi_clk,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK => spi_clk,
+	   SPI_SS_IO => spi_ss_io(0),
+	   SPI_MISO => spi_miso,
+	   SPI_MOSI => spi_mosi,
+		
+		-- Sector access request
+		read_request => request,
+		write_request => write,
+		sector => sector,
+		ready => ready,
+		
+		-- DMA to RAM
+		ADDR => addr,
+		DATA_OUT => data_out,
+		DATA_IN => data_in,
+		WR_EN => wr_en
+	 );
+
+end rtl;
+
Index: mist/user_io.v
===================================================================
--- mist/user_io.v	(revision 69)
+++ mist/user_io.v	(revision 70)
@@ -1,91 +1,153 @@
-module user_io(
-	   input      SPI_CLK,
-	   input      SPI_SS_IO,
-	   output     reg SPI_MISO,
-	   input      SPI_MOSI,
-	   input [7:0] CORE_TYPE,
-		output [5:0] JOY0,
-		output [5:0] JOY1,
-		output [127:0] KEYBOARD,		
-		output [1:0] BUTTONS,
-		output [1:0] SWITCHES
-	   );
-
-   reg [6:0]         sbuf;
-   reg [7:0]         cmd;
-   reg [7:0] 	      cnt;
-   reg [5:0]         joystick0;
-   reg [5:0]         joystick1;
-	reg [119:0]       keyboard;
-	reg [127:0]       keyboard_out;	
-   reg [3:0] 	      but_sw;
-
-	assign JOY0 = joystick0;
-	assign JOY1 = joystick1;
-	assign KEYBOARD = keyboard_out;
-	assign BUTTONS = but_sw[1:0];
-	assign SWITCHES = but_sw[3:2];
-   
-   always@(negedge SPI_CLK) begin
-		if(SPI_SS_IO == 1) begin
-		   SPI_MISO <= 1'bZ;
-		end else begin
-	      if(cnt < 8) begin
-			  SPI_MISO <= CORE_TYPE[7-cnt];
-			end else begin
-		     SPI_MISO <= 1'bZ;
-			end
-	   end
-	end
-		
-   always@(posedge SPI_CLK) begin
-		if(SPI_SS_IO == 1) begin
-        cnt <= 0;
-		end else begin
-			sbuf[6:1] <= sbuf[5:0];
-			sbuf[0] <= SPI_MOSI;
-
-			cnt <= cnt + 1;
-
-	      if(cnt == 7) begin
-			   cmd[7:1] <= sbuf; 
-				cmd[0] <= SPI_MOSI;
-		   end	
-
-	      if(cnt == 15) begin
-			   if(cmd == 1) begin
-					 but_sw[3:1] <= sbuf[2:0]; 
-					 but_sw[0] <= SPI_MOSI; 
-				end
-			   if(cmd == 2) begin
-					 joystick0[5:1] <= sbuf[4:0]; 
-					 joystick0[0] <= SPI_MOSI; 
-				end
-			   if(cmd == 3) begin
-					 joystick1[5:1] <= sbuf[4:0]; 
-					 joystick1[0] <= SPI_MOSI; 
-				end			
-			end	
+// MiST user_io
+
+module user_io(
+	input      		SPI_CLK,
+	input      		SPI_SS_IO,
+	output     		reg SPI_MISO,
+	input      		SPI_MOSI,
+	
+	input [7:0] 	CORE_TYPE,
+	
+	output [5:0] 	JOY0,
+	output [5:0] 	JOY1,
+	output [1:0] 	BUTTONS,
+	output [1:0] 	SWITCHES,
+	
+	input 	  		clk,
+	output	 		ps2_clk,
+	output reg 		ps2_data
+);
+
+reg [6:0]         sbuf;
+reg [7:0]         cmd;
+reg [4:0] 	      cnt;
+reg [5:0]         joystick0;
+reg [5:0]         joystick1;
+reg [3:0] 	      but_sw;
+
+assign JOY0 = joystick0;
+assign JOY1 = joystick1;
+assign BUTTONS = but_sw[1:0];
+assign SWITCHES = but_sw[3:2];
+   
+// drive MISO only when transmitting core id
+always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+      if(cnt < 8) begin
+		  SPI_MISO <= CORE_TYPE[7-cnt];
+		end else begin
+	     SPI_MISO <= 1'bZ;
+		end
+   end
+end
+
+// 8 byte fifo to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_tx_state;
+reg [7:0] ps2_tx_byte;
+reg ps2_parity;
+
+assign ps2_clk = clk || (ps2_tx_state == 0);
+
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_r_inc;
+always@(posedge clk) begin
+	ps2_r_inc <= 1'b0;
+	
+	if(ps2_r_inc)
+		ps2_rptr <= ps2_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_wptr != ps2_rptr) begin
+			// load tx register from fifo
+			ps2_tx_byte <= ps2_fifo[ps2_rptr];
+			ps2_r_inc <= 1'b1;
 			
-			// 15,23,31,39,47,55,63,71
-			if (cnt[2:0]==7) begin
-			   if(cmd == 5) begin
-					if (!cnt[7]) begin
-					 keyboard[111:0] <= keyboard[119:8];
-					 keyboard[119:113] <= sbuf[6:0]; 
-					 keyboard[112] <= SPI_MOSI; 
-					end
-					if (cnt[7]) begin
-					 keyboard_out[119:0] <= keyboard[119:0];
-					 keyboard_out[127:121] <= sbuf[6:0]; 
-					 keyboard_out[120] <= SPI_MOSI; 					
-					end
-				end
+			// reset parity
+			ps2_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
+			ps2_data <= ps2_tx_byte[0];			  // data bits
+			ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
+			if(ps2_tx_byte[0]) 
+				ps2_parity <= !ps2_parity;
+		end
+
+		// transmission of parity
+		if(ps2_tx_state == 9)
+			ps2_data <= ps2_parity;
+			
+		// transmission of stop bit
+		if(ps2_tx_state == 10)
+			ps2_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_tx_state < 11)
+			ps2_tx_state <= ps2_tx_state + 4'd1;
+		else	
+			ps2_tx_state <= 4'd0;
+	
+	end
+end
+
+// SPI receiver
+//reg ps2_w_inc;
+always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
+//	ps2_w_inc <= 1'b0;
+//	if(ps2_w_inc)
+//		ps2_wptr <= ps2_wptr + 1;
+
+	if(SPI_SS_IO == 1) begin
+	   cnt <= 1'b0;
+	end else begin
+		sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+		// counter counts 0-7, 8-15, 8-15 ...
+		// 0-7 is command, 8-15 is payload
+		if(cnt != 15)  cnt <= cnt + 4'd1;
+		else				cnt <= 4'd8;
+
+		// finished reading command byte
+      if(cnt == 7)
+		   cmd <= { sbuf, SPI_MOSI};
+
+      if(cnt == 15) begin
+		   if(cmd == 1)
+				but_sw <= { sbuf[2:0], SPI_MOSI }; 
+
+			if(cmd == 2)
+				joystick0 <= { sbuf[4:0], SPI_MOSI };
+				 
+			if(cmd == 3)
+				joystick1 <= { sbuf[4:0], SPI_MOSI };
+				 
+		   if(cmd == 5) begin
+				// store incoming keyboard bytes in 
+				ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI }; 
+				ps2_wptr <= ps2_wptr + 1;
 			end
-		end
-   end		
-//   always@(posedge clk2) begin
-//      LED <= ~LED;
-//   end
-   
-endmodule
+				
+		end	
+	end
+end
+   
+endmodule
Index: mist/zpu_rom.vhdl
===================================================================
--- mist/zpu_rom.vhdl	(nonexistent)
+++ mist/zpu_rom.vhdl	(revision 70)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80f2",
+X"d4738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80f5",
+X"cc0c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580ed",
+X"842d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580eb98",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"97b30480",
+X"3d0d80f6",
+X"f0087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80f6",
+X"f0087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80f6f008",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80f6f008",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"f6f00870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"f6f00870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80f6f008",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80f6f008",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80f6f0",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80f6f0",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"f7800870",
+X"0870882c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"f7800870",
+X"0870892c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"f7800870",
+X"08708a2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"f7800870",
+X"08708b2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80f6e0",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d848080",
+X"53805288",
+X"800a51ff",
+X"b33f8180",
+X"80538052",
+X"82800a51",
+X"c63f843d",
+X"0d04803d",
+X"0d8151fc",
+X"ce3f7280",
+X"2e8338d2",
+X"3f8151fc",
+X"f03f8051",
+X"fceb3f80",
+X"51fcb83f",
+X"823d0d04",
+X"fd3d0d75",
+X"52805480",
+X"ff722588",
+X"38810bff",
+X"80135354",
+X"ffbf1251",
+X"70992686",
+X"38e01252",
+X"9e39ff9f",
+X"12519971",
+X"279538d0",
+X"12e01370",
+X"54545189",
+X"71278838",
+X"8f732783",
+X"38805273",
+X"802e8538",
+X"81801252",
+X"7181ff06",
+X"83e0800c",
+X"853d0d04",
+X"803d0d86",
+X"b8c05180",
+X"71708105",
+X"53347086",
+X"c0c02e09",
+X"8106f038",
+X"823d0d04",
+X"fe3d0d02",
+X"97053351",
+X"ff863f83",
+X"e0800881",
+X"ff0683e0",
+X"9c085452",
+X"8073249b",
+X"3883e0b8",
+X"08137283",
+X"e0bc0807",
+X"53537173",
+X"3483e09c",
+X"08810583",
+X"e09c0c84",
+X"3d0d04fa",
+X"3d0d8280",
+X"0a1b5580",
+X"57883dfc",
+X"05547953",
+X"74527851",
+X"b7ae3f88",
+X"3d0d04fe",
+X"3d0d83e0",
+X"b0085274",
+X"51bde83f",
+X"83e08008",
+X"8c387653",
+X"755283e0",
+X"b00851c7",
+X"3f843d0d",
+X"04fe3d0d",
+X"83e0b008",
+X"53755274",
+X"51b8af3f",
+X"83e08008",
+X"8d387753",
+X"765283e0",
+X"b00851ff",
+X"a23f843d",
+X"0d04fe3d",
+X"0d83e0b4",
+X"0851b7af",
+X"3f83e080",
+X"08818080",
+X"2e098106",
+X"883883c1",
+X"8080539b",
+X"3983e0b4",
+X"0851b793",
+X"3f83e080",
+X"0880d080",
+X"2e098106",
+X"933883c1",
+X"b0805383",
+X"e0800852",
+X"83e0b408",
+X"51fed83f",
+X"843d0d04",
+X"803d0dfa",
+X"cc3f83e0",
+X"80088726",
+X"80cd3883",
+X"e0800884",
+X"2980f2e4",
+X"05517008",
+X"040b0b80",
+X"f3cc51b7",
+X"390b0b80",
+X"f3d051af",
+X"390b0b80",
+X"f3d851a7",
+X"390b0b80",
+X"f3e4519f",
+X"390b0b80",
+X"f3f05197",
+X"390b0b80",
+X"f3fc518f",
+X"390b0b80",
+X"f4885187",
+X"390b0b80",
+X"f48c5170",
+X"83e0800c",
+X"823d0d04",
+X"ee3d0d80",
+X"43804280",
+X"4180705a",
+X"5bfd893f",
+X"800b83e0",
+X"9c0c800b",
+X"83e0bc0c",
+X"0b0b80f4",
+X"9051b19d",
+X"3f81800b",
+X"83e0bc0c",
+X"0b0b80f4",
+X"9451b18d",
+X"3f80d00b",
+X"83e09c0c",
+X"7830707a",
+X"07802570",
+X"872b83e0",
+X"bc0c5155",
+X"f8ee3f83",
+X"e0800852",
+X"0b0b80f4",
+X"9c51b0e5",
+X"3f80f80b",
+X"83e09c0c",
+X"78813270",
+X"30707207",
+X"80257087",
+X"2b83e0bc",
+X"0c515656",
+X"fea23f83",
+X"e0800852",
+X"0b0b80f4",
+X"a851b0b9",
+X"3f81a00b",
+X"83e09c0c",
+X"78823270",
+X"30707207",
+X"80257087",
+X"2b83e0bc",
+X"0c515683",
+X"e0b40852",
+X"56b1ff3f",
+X"83e08008",
+X"520b0b80",
+X"f4b051b0",
+X"883f81f0",
+X"0b83e09c",
+X"0c810b83",
+X"e0a05b58",
+X"83e09c08",
+X"82197a32",
+X"70307072",
+X"07802570",
+X"872b83e0",
+X"bc0c5157",
+X"8e3d7055",
+X"ff1b5457",
+X"5757a5e6",
+X"3f797084",
+X"055b0851",
+X"b1b43f74",
+X"5483e080",
+X"08537752",
+X"0b0b80f4",
+X"b851afb9",
+X"3fa81783",
+X"e09c0c81",
+X"18587785",
+X"2e098106",
+X"ffae3883",
+X"900b83e0",
+X"9c0c7887",
+X"32703070",
+X"72078025",
+X"70872b83",
+X"e0bc0c51",
+X"560b0b80",
+X"f4c85256",
+X"af833f83",
+X"e00b83e0",
+X"9c0c7888",
+X"32703070",
+X"72078025",
+X"70872b83",
+X"e0bc0c51",
+X"560b0b80",
+X"f4dc5256",
+X"aedf3f86",
+X"8da051f8",
+X"c73f8052",
+X"913d7052",
+X"558bd43f",
+X"83527451",
+X"8bcd3f61",
+X"19597880",
+X"25853880",
+X"59903988",
+X"79258538",
+X"88598739",
+X"78882682",
+X"ae387882",
+X"2b5580f3",
+X"84150804",
+X"f69a3f83",
+X"e0800861",
+X"57557581",
+X"2e098106",
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+X"00040074",
+X"00040068",
+X"00040060",
+X"0004005c",
+X"00040058",
+X"00040054",
+X"00040050",
+X"0004004c",
+X"00040048",
+X"00040044",
+X"00040040",
+X"00040034",
+X"00040030",
+X"0004002c",
+X"00040028",
+X"00040024",
+X"00040020",
+X"0004001c",
+X"00040018",
+X"00040014",
+X"00040010",
+X"0004000c",
+X"00040008",
+X"00040004",
+X"00040000",
+X"72025f07",
+X"f807a900",
+X"8d04038d",
+X"4402a907",
+X"8d0503a9",
+X"708d0a03",
+X"a9018d0b",
+X"03850960",
+X"7d8a4820",
+X"53e488d0",
+X"fa68aa8c",
+X"8e07ad7d",
+X"07ee8e07",
+X"60a9938d",
+X"e202a907",
+X"8de302a2",
+X"0220da07",
+X"954320da",
+X"07954435",
+X"43c9fff0",
+X"f0caca10",
+X"ec3006e6",
+X"45d002e6",
+X"4620da07",
+X"a2018144",
+X"b545d543",
+X"d0edca10",
+X"f720d207",
+X"4c9407a9",
+X"038d0fd2",
+X"6ce202ad",
+X"8e07cd7f",
+X"07d0abee",
+X"0a03d003",
+X"ee0b03ad",
+X"7d070d7e",
+X"07d08e20",
+X"d2076ce0",
+X"0220da07",
+X"8de00220",
+X"da078de1",
+X"022de002",
+X"c9fff0ed",
+X"a9008d8e",
+X"07f08200",
+X"2f617461",
+X"72693830",
+X"302f726f",
+X"6d000000",
+X"2f617461",
+X"72693830",
+X"302f7573",
+X"65720000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
