Index: eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl
===================================================================
--- eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl	(revision 982)
+++ eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl	(revision 983)
@@ -56,8 +56,10 @@
 	O_TMDS_L : OUT STD_LOGIC_VECTOR(7 downto 0);
 	
 	-- I2C params
-	scl : inout std_logic;
-	sda : inout std_logic
+    scl_in           : in std_logic;
+    sda_in           : in std_logic;
+	 scl_wen          : out std_logic;
+	 sda_wen          : out std_logic 
 );
 END scandoubler_hdmi;
 
@@ -213,6 +215,12 @@
 signal shift_b_next	: std_logic_vector(9 downto 0) := "0000000000";	
 signal shift_clk_next : std_logic_vector(9 downto 0) := "0000000000";
 	
+-- i2c
+signal multiscale_sda_wen : std_logic;
+signal crtc_sda_wen : std_logic;
+signal multiscale_scl_wen : std_logic;
+signal crtc_scl_wen : std_logic;
+	
 BEGIN
 
 --------------------------------------------------------
@@ -465,8 +473,10 @@
 		vsync => vsync_next,
 		blank => blank_next,
 				
-		sda => sda,
-		scl => scl		
+		scl_in => scl_in,
+		sda_in => sda_in,	
+		scl_wen => multiscale_scl_wen,
+		sda_wen => multiscale_sda_wen
 	);	
 
 -- Resynchronization logic
@@ -525,8 +535,10 @@
 		video_id_code => crtc_video_id_code,
 		scaler_select => crtc_scaler_select,
 
-		sda => sda,
-		scl => scl
+		scl_in => scl_in,
+		sda_in => sda_in,	
+		scl_wen => crtc_scl_wen,
+		sda_wen => crtc_sda_wen
 	);
 
 hdmiav_inst : entity work.hdmi
@@ -696,6 +708,10 @@
 O_TMDS_H <= shift_r_reg(0) & nshift_r_reg(0) & shift_g_reg(0) & nshift_g_reg(0) & shift_b_reg(0) & nshift_b_reg(0) & shift_clk_reg(0) & nshift_clk_reg(0);
 O_TMDS_L <= shift_r_reg(1) & nshift_r_reg(1) & shift_g_reg(1) & nshift_g_reg(1) & shift_b_reg(1) & nshift_b_reg(1) & shift_clk_reg(1) & nshift_clk_reg(1);
 
+-- I2C outputs
+sda_wen <= multiscale_sda_wen or crtc_sda_wen;
+scl_wen <= multiscale_scl_wen or crtc_scl_wen;
+
 end vhdl;
 
 
Index: eclaireXL_ITX/scaler/areascale.vhd
===================================================================
--- eclaireXL_ITX/scaler/areascale.vhd	(revision 982)
+++ eclaireXL_ITX/scaler/areascale.vhd	(revision 983)
@@ -49,8 +49,10 @@
     blank : out std_logic;
 	 
     -- to set up params
-    sda : inout std_logic;
-    scl : inout std_logic	 
+    scl_in           : in std_logic;
+    sda_in           : in std_logic;
+	 scl_wen          : out std_logic;
+	 sda_wen          : out std_logic
   );
 END areascale;
 
@@ -275,8 +277,10 @@
 		bits => 11
 	)
 	port map (
-		scl => scl,
-		sda => sda,
+		scl_in => scl_in,
+		sda_in => sda_in,		
+		scl_wen => scl_wen,
+		sda_wen => sda_wen,		
 		clk => clock,
 		rst => not(reset_n),
 		
Index: eclaireXL_ITX/scaler/crtc.vhdl
===================================================================
--- eclaireXL_ITX/scaler/crtc.vhdl	(revision 982)
+++ eclaireXL_ITX/scaler/crtc.vhdl	(revision 983)
@@ -37,8 +37,10 @@
 	scaler_select : out std_logic;
 
 	-- to set up params
-	sda : inout std_logic;
-	scl : inout std_logic
+    scl_in           : in std_logic;
+    sda_in           : in std_logic;
+	 scl_wen          : out std_logic;
+	 sda_wen          : out std_logic
 );
 END crtc;
 
@@ -186,8 +188,11 @@
 		bits => 12
 	)
 	port map (
-		scl => scl,
-		sda => sda,
+		scl_in => scl_in,
+		sda_in => sda_in,
+		scl_wen => scl_wen,
+		sda_wen => sda_wen,
+		
 		clk => clk_pixel,
 		rst => not(reset_n),
 		
Index: eclaireXL_ITX/scaler/multiscale.vhd
===================================================================
--- eclaireXL_ITX/scaler/multiscale.vhd	(revision 982)
+++ eclaireXL_ITX/scaler/multiscale.vhd	(revision 983)
@@ -49,8 +49,10 @@
     blank : out std_logic;
 	 
     -- to set up params
-    sda : inout std_logic;
-    scl : inout std_logic	 
+    scl_in           : in std_logic;
+    sda_in           : in std_logic;
+	 scl_wen          : out std_logic;
+	 sda_wen          : out std_logic 
   );
 END multiscale;
 
@@ -105,8 +107,10 @@
 		vsync => poly_vsync_next,
 		blank => poly_blank_next,
 				
-		sda => sda,
-		scl => scl		
+		scl_in => scl_in,
+		sda_in => sda_in,		
+		scl_wen => scl_wen,
+		sda_wen => sda_wen
 	);
 end generate gen_polyphasic_on;	
 	
@@ -136,8 +140,10 @@
 		vsync => area_vsync_next,
 		blank => area_blank_next,
 		
-		sda => sda,
-		scl => scl
+		scl_in => scl_in,
+		sda_in => sda_in,
+		scl_wen => scl_wen,
+		sda_wen => sda_wen
 	);
 end generate gen_area_on;	
 	
Index: eclaireXL_ITX/scaler/polyphasicscale.vhd
===================================================================
--- eclaireXL_ITX/scaler/polyphasicscale.vhd	(revision 982)
+++ eclaireXL_ITX/scaler/polyphasicscale.vhd	(revision 983)
@@ -42,8 +42,10 @@
     blank : out std_logic;
 	 
     -- to set up params
-    sda : inout std_logic;
-    scl : inout std_logic	 
+    scl_in           : in std_logic;
+    sda_in           : in std_logic;
+	 scl_wen          : out std_logic;
+	 sda_wen          : out std_logic
   );
 END polyphasicscale;
 
@@ -385,8 +387,10 @@
 		bits => 11
 	)
 	port map (
-		scl => scl,
-		sda => sda,
+		scl_in => scl_in,
+		sda_in => sda_in,
+		scl_wen => scl_wen,
+		sda_wen => sda_wen,		
 		clk => clock,
 		rst => not(reset_n),
 		
