Project

General

Profile

Pinouts » History » Revision 10

Revision 9 (foft, 04/15/2018 07:48 PM) → Revision 10/12 (foft, 04/15/2018 08:05 PM)

h1. Pinouts 

 h2. V1 

 h3. Use in core 

 *Cartridge/PBI interface* 
 1: CCTL_N 
 2: PHI2 
 3: RD5 
 4: RW_N 
 5: A10 
 6: A11 
 7: S5_N 
 8: D7 
 9: D6 
 10:D3 
 11:NC 
 12:NC 
 13:D0 
 14:A12 
 15:D1 
 16:A9 
 17:D2 
 18:A8 
 19:D5 
 20:A7 
 21:D4 
 22:A6 
 23:A0 
 24:A5 
 25:A1 
 26:A4 
 27:A2 
 28:A3 
 29:MIC_PBI (To ADC jumper) 
 30:MIC_PBI (To ADC jumper) 
 31:RD4 
 32:S4_N 
 33:EXTSEL_N 
 34:A13 
 35:A14 
 36:A15 
 37:MPD_N 
 38:REF_N 
 39:IRQ_N 
 40:RST_N 

 *SIO interface* 
 1: SIO CLOCK OUT 
 2: SIO COMMAND 
 3: SIO IN 
 4: SIO PROCEED 
 5: SIO IRQ 
 6: SIO CLOCK IN 
 7: SIO OUT 
 8: SIO MOTOR EN 
 9: SIO MIC (To ADC jumper) 
 10:SIO MOTOR EN 

 



 h3. By connection to FPGA 

 Useful information if building your own core. 
 In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. 

 *GPIO:* 
 1-10: Direct to FPGA 
 11: 5V 
 12: GND 
 13-28: Direct to FPGA 
 29: 3.3V 
 30: GND 
 31-40: Direct to FPGA 

 *Cartridge/PBI interface* 
 All level shifted to 3.3V. 
 Special pins: 
 31:10k pulldown 
 3: 10k pulldown 
 10/11: NC 
 29:To ADC jumper (PBI) 
 30:To ADC jumper (PBI) 
 33:4.7k pullup to 5V 
 37:4.7k pullup to 5V 
 38:4.7k pullup to 5V 
 39:4.7k pullup to 5V 

 *SIO interface* 
 1-7: 3.3V level shifted, 5V pull-up. 
 8,10: 5V transistor drive (for tape motor) 
 9: To ADC jumper (SIO) 

 h2. V2 

 h3. Use in core 

 *Interface 1:* 
 1-16: A0-A15 (1=A0,2=A1, etc) 
 17-24: D0-D7 (17=D0, 18=D1 etc) 
 25: PHI2 
 26: HALT (not implemented yet) 
 27: RST_N 
 28: IRQ_N 
 29: D1XX (not implemented yet) 
 30: CASINH_N 
 31: CCTL_N 
 32: REF_N 
 33: CAS_N 
 34: MPD_N 
 35: RAS_N 
 36: RW_N 
 37: RD4 
 38: S4_N 
 39: S5_N 
 40: RD5 

 *Interface 2:* 
 1: USBDM    (FTDI USB RS232) 
 2: USBRES (FTDI USB RS232) 
 3: USBDP    (FTDI USB RS232) 
 4: GND 
 5: 5V0 
 6: 5V0 
 7: J2 ANAL_B (Paddle in) 
 8: J2 ANAL_A 
 9: J1 ANAL_B 
 10:J1 ANAL_A 
 11:J2 FIRE 
 12:J2 UP 
 13:J2 DOWN 
 14:J2 LEFT 
 15:J2 RIGHT 
 16:J1 FIRE 
 17:J1 UP 
 18:J1 DOWN 
 19:J1 LEFT 
 20:J1 RIGHT 
 21:J4 FIRE 
 22:J4 UP 
 23:J4 DOWN 
 24:J4 LEFT 
 25:J4 RIGHT 
 26:J3 FIRE 
 27:J3 UP 
 28:J3 DOWN 
 29:J3 LEFT 
 30:J3 RIGHT 
 31:GND 
 32:SIO IRQ 
 33:SIO PROCEED 
 34:SIO MOTOR_EN 
 35:SIO COMMAND 
 36:SIO DATA OUT 
 37:SIO DATA IN 
 38:CLOCK OUT 
 39:CLOCK IN 
 40:EXTSEL_N 

 h3. By connection to FPGA 

 Useful information if building your own core. 
 In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. 

 *GPIO:* 
 1-17: direct to FPGA 
 18: SDA (i2c) - clock gen also on here (*V2 FIX only*) 
 19: SCL (i2c) - clock gen also on here (*V2 FIX only*) 
 20-22: GND 
 23-34: 3.3V 
 25-26: 5.0V 

 *Interface 1:* 
 All level shifted to 3.3V. 
 Special pins: 
 37:10k 37:RD4: 10k pulldown 
 40:10k 40:RD5: 10k pulldown 
 34:4.7k 34:MPD_N: 4.7k pullup to 5V 
 28:4.7k 28:IRQ_N: 4.7k pullup to 5V 
 32:2k 32:REF_N: 2k pullup to 5V (*V2 FIX 2k, V2 4.7k*) 

 *Interface 2:* 
 1-3: USB to FTDI  
 4: GND 
 5,6: 5V 
 7-10: Charge cap, FPGA compares with ref voltage (about 2V) 
 11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance in addition (330 ohm total to FPGA). (needed?) 
 31: GND 
 32-33: level shifted to 3.3V. 4.7k pullup to 5V 
 34: 5V transistor drive (for tape motor) 
 35-40: 35-49: level shifted to 3.3V. 4.7k pullup o 5V 
 40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V