Pinouts
h2. V1
h2. V2
h3. Use in core¶

By connection to FPGA
GPIO:
1-17: direct to FPGA
18: SDA (i2c) - clock gen also on here
19: SCL (i2c) - clock gen also on here
20-22: GND
23-34: 3.3V
25-26: 5.0V¶

Interface 1:
All level shifted to 3.3V.
Special pins:
37:RD4: 10k pulldown
40:RD5: 10k pulldown
34:MPD_N: 4.7k pullup to 5V
28:IRQ_N: 4.7k pullup to 5V
32:REF_N: 2k pullup to 5V

Interface 2:
1-3: USB to FTDI
4: GND
5,6: 5V
7-10: Charge cap, FPGA compares with ref voltage
11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?)
31: GND
32-33: level shifted to 3.3V. 4.7k pullup to 5V
34: 5V transistor drive (for tape motor)
35-49: level shifted to 3.3V. 4.7k pullup o 5V
40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V