Pinouts¶

V1¶

V2¶

Use in core¶

Interface 1:
1-16: A0-A15 (1=A0,2=A1, etc)
17-24: D0-D7 (17=D0, 18=D1 etc)
25: PHI2
26: HALT (not implemented yet)
27: RST_N
28: IRQ_N
29: D1XX (not implemented yet)
30: CASINH_N
31: CCTL_N
32: REF_N
33: CAS_N
34: MPD_N
35: RAS_N
36: RW_N
37: RD4
38: S4_N
39: S5_N
40: RD5

Interface 2:

By connection to FPGA¶

GPIO:
1-17: direct to FPGA
18: SDA (i2c) - clock gen also on here (V2 FIX only)
19: SCL (i2c) - clock gen also on here (V2 FIX only)
20-22: GND
23-34: 3.3V
25-26: 5.0V

Interface 1:
All level shifted to 3.3V.
Special pins:
37:RD4: 10k pulldown
40:RD5: 10k pulldown
34:MPD_N: 4.7k pullup to 5V
28:IRQ_N: 4.7k pullup to 5V
32:REF_N: 2k pullup to 5V

Interface 2:
1-3: USB to FTDI
4: GND
5,6: 5V
7-10: Charge cap, FPGA compares with ref voltage
11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?)
31: GND
32-33: level shifted to 3.3V. 4.7k pullup to 5V
34: 5V transistor drive (for tape motor)
35-49: level shifted to 3.3V. 4.7k pullup o 5V
40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V