Pinouts » History » Revision 8
Revision 7 (foft, 04/15/2018 07:35 PM) → Revision 8/12 (foft, 04/15/2018 07:38 PM)
h1. Pinouts h2. V1 h2. V2 h3. Use in core *Interface 1:* Interface 1: 1-16: A0-A15 (1=A0,2=A1, etc) 17-24: D0-D7 (17=D0, 18=D1 etc) 25: PHI2 26: HALT (not implemented yet) 27: RST_N 28: IRQ_N 29: D1XX (not implemented yet) 30: CASINH_N 31: CCTL_N 32: REF_N 33: CAS_N 34: MPD_N 35: RAS_N 36: RW_N 37: RD4 38: S4_N 39: S5_N 40: RD5 *Interface 2:* 1: USBDM (FTDI USB RS232) 2: USBRES (FTDI USB RS232) 3: USBDP (FTDI USB RS232) 4: GND 5: 5V0 6: 5V0 7: J2 ANAL_B (Paddle in) 8: J2 ANAL_A 9: J1 ANAL_B 10:J1 ANAL_A 11:J2 FIRE 12:J2 UP 13:J2 DOWN 14:J2 LEFT 15:J2 RIGHT 16:J1 FIRE 17:J1 UP 18:J1 DOWN 19:J1 LEFT 20:J1 RIGHT 21:J4 FIRE 22:J4 UP 23:J4 DOWN 24:J4 LEFT 25:J4 RIGHT 26:J3 FIRE 27:J3 UP 28:J3 DOWN 29:J3 LEFT 30:J3 RIGHT 31:GND 32:SIO IRQ 33:SIO PROCEED 34:SIO MOTOR_EN 35:SIO COMMAND 36:SIO DATA OUT 37:SIO DATA IN 38:CLOCK OUT 39:CLOCK IN 40:EXTSEL_N h3. By connection to FPGA Useful information if building your own core. In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. *GPIO:* 1-17: direct to FPGA 18: SDA (i2c) - clock gen also on here (*V2 FIX only*) 19: SCL (i2c) - clock gen also on here (*V2 FIX only*) 20-22: GND 23-34: 3.3V 25-26: 5.0V *Interface 1:* All level shifted to 3.3V. Special pins: 37:RD4: 10k pulldown 40:RD5: 10k pulldown 34:MPD_N: 4.7k pullup to 5V 28:IRQ_N: 4.7k pullup to 5V 32:REF_N: 2k pullup to 5V *Interface 2:* 1-3: USB to FTDI 4: GND 5,6: 5V 7-10: Charge cap, FPGA compares with ref voltage 11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?) 31: GND 32-33: level shifted to 3.3V. 4.7k pullup to 5V 34: 5V transistor drive (for tape motor) 35-49: level shifted to 3.3V. 4.7k pullup o 5V 40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V