EclaireXL

Tried a 1 cycle and a half cycle delay on the input to the xor. Neither are seeming quite right, but 1 cycle delay is closest...

Been checking on the scope. The one cycle delay looks correct.
Some jitter issues due to when I activate pokey. I was doing so on the memory access completion, but this really varies too much when accessing SDRAM and block RAM. So I've changed it to activate on the final cycle, as with antic.

Problem with stimer??

Aha, got it...

The issue was that the write to stimer was now exactly on the enable cycle. I modified the latch delay line to support this. Fundamentally though, this isn’t meant to happen, so perhaps an issue with the pbi implementation is causing the writes to be on an unexpected cycle??

Anyway v23 sounds nice for pdm, reliably.