Activity
From 03/22/2016 to 04/20/2016
04/19/2016
- 11:13 PM Revision 445 (repo2): Register bus_data before we write it
- 11:13 PM Revision 444 (repo2): Fixed c0 decode and made more explicit
04/18/2016
04/16/2016
- 04:31 PM Revision 442 (repo2): constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.
- 04:29 PM Revision 441 (repo2): register output data
- 04:28 PM Revision 440 (repo2): Missed commit
- 03:27 PM Revision 439 (repo2): Simulated/corrected sram back-back write timings
- 12:33 PM Revision 438 (repo2): First cut implementation of veronica clone for ultimate cart - does not work yet, but getting close. Project to try out Rob Finchs 65816 core.
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