Activity
From 06/04/2026 to 07/03/2026
06/29/2026
- 10:45 PM EclaireXL Revision 1558 (repo2): Add v4 xel build: CS1 forced high. Left external pin carries right internal audio instead.
06/20/2026
- 02:33 PM EclaireXL Revision 1557 (repo2): Forgot to commit a few files
06/19/2026
- 08:55 PM EclaireXL Revision 1555 (repo2): Refreshed v1
- 08:50 PM EclaireXL Revision 1554 (repo2): Allow recording 4 selected channels at once. Gate record behind a flag. Include board version in version string instead of useless leading 1
06/14/2026
- 11:07 PM EclaireXL Revision 1553 (repo2): Only instantiate DC blocker if needed
- 11:00 PM EclaireXL Revision 1552 (repo2): Added dc blocker to all builds
- 10:16 PM EclaireXL Revision 1551 (repo2): Move dc blocker to be per unsigned channel. Works better for recording and now everything is signed in priciple with no dc offset for the mixer.
- 10:15 PM EclaireXL Revision 1550 (repo2): Allow reading the record reg.
06/09/2026
- 10:19 PM EclaireXL Revision 1549 (repo2): Sid routing is using wrong bit
- 09:15 PM EclaireXL Revision 1548 (repo2): Recording channels were flipped
06/08/2026
- 10:50 PM EclaireXL Revision 1547 (repo2): Fix pm v1 and sidmax builds following sample changes
- 10:50 PM EclaireXL Revision 1546 (repo2): Fix the CPU writes to sample ram
- 09:12 PM EclaireXL Revision 1545 (repo2): Allow recording of a channel to the sample memory (for looping etc). Allow feeding a channel to the SID ext input, in order to use filters. This mutes the original channel so its not duplicated..
06/07/2026
- 09:31 AM EclaireXL Revision 1543 (repo2): Fix for right channel detection logic
06/06/2026
- 11:57 PM EclaireXL Revision 1542 (repo2): Correct a few sensitivity list issues
- 11:27 PM EclaireXL Revision 1541 (repo2): Fix unintentional latch
- 11:26 PM EclaireXL Revision 1540 (repo2): Fix channel 0 getting mixed in everywhere!