EclaireXL

04/28/2016

10:35 PM Revision 453 (repo2): Plugged in the sram model to check timings

markw

10:34 PM Revision 452 (repo2): Need to review further, but these changes seem to bring the 65816 core to life somewhat

markw

04/23/2016

03:28 PM Revision 451 (repo2): Added testbenches. Do not respond to bus cycles that do not target the cart

markw

04/22/2016

11:11 PM Revision 450 (repo2): sram model for tb

markw

10:28 PM Revision 449 (repo2): Moved memory timing bridge inside slave_timing, its an internal detail really

markw

04/21/2016

11:02 PM Revision 448 (repo2): Adjusted delays and verified in sim

markw

10:02 PM Revision 447 (repo2): Trivial but important fixes, thanks to quartus warnings

markw

09:55 PM Revision 446 (repo2): 70ns accuracy is not enough for reliable Atari bus sampling, use faster clock we are already using for sram

markw

04/19/2016

11:13 PM Revision 445 (repo2): Register bus_data before we write it

markw

11:13 PM Revision 444 (repo2): Fixed c0 decode and made more explicit

markw

04/18/2016

10:33 PM Revision 443 (repo2): Simulated and repaired 6502 bus and sram bus

markw

04/16/2016

04:31 PM Revision 442 (repo2): constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.

markw

04:29 PM Revision 441 (repo2): register output data

markw

04:28 PM Revision 440 (repo2): Missed commit

markw

03:27 PM Revision 439 (repo2): Simulated/corrected sram back-back write timings

markw

12:33 PM Revision 438 (repo2): First cut implementation of veronica clone for ultimate cart - does not work yet, but getting close. Project to try out Rob Finchs 65816 core.

markw