Activity

From 11/10/2019 to 12/09/2019

09:10 PM Feature #84: Add SID: Attaching some of the octave files from investigating this for reference + the wave files + other useful bits I found... foft
09:07 PM Feature #84: Add SID: Did some research over the weekend. Generating these isn't a terribly trivial problem!
I tried for some time to ge... foft

10:19 PM Feature #84: Add SID: It sounds good to me, but not sure what it is meant to sound like!! foft
10:19 PM Feature #84: Add SID: Also wondering if the clk frequency is important (not enable), I see some state table increment on every clock, which... foft
10:18 PM Feature #84: Add SID: Wondering about some kind of bit map of unpopulated locations (reducing locations) or a 2nd lookup layer (reducing bi... foft
10:04 PM Feature #84: Add SID: I loaded the tables in to octave to take a look.
Observations...
* Not a simple curve
* Lots of zeros, >80% in ... foft
10:02 PM Feature #84: Add SID: Actually the issue with fitting in v2 is block ram, not ALMs. Though its always good to save ALMs!
The sid tables ... foft
09:05 AM Core v37 released again!: EclaireXL/A4: SID frequency was too fast, made it closer to 1MHz (still approx, but better than 1.77MHz).
xxl kind... foft

10:12 PM Core v37 released: EclaireXL/MCC216/MCCTV:
* Fixed USB failure after 70 minutes.
* Fixed full speed usb init issue, this fixes my non-... foft
09:40 PM Revision 966 (repo2): Get sockit firmware building: markw
01:51 PM Revision 965 (repo2): Latest firmware with usb fix: markw
01:49 PM Revision 964 (repo2): version bump: markw
01:48 PM Revision 963 (repo2): experimental sid support, only fits in larger fpga: markw
01:47 PM Revision 962 (repo2): Path fix: markw
01:46 PM Revision 961 (repo2): Package a few additional files: markw
01:44 PM Revision 960 (repo2): Experimental sid support: markw

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