repo2/atari_chips/antic/antic_dma_clock.vhdl
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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| 568 | markw | ENTITY antic_dma_clock_del IS
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| 1 | markw | PORT
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(
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CLK : IN STD_LOGIC;
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RESET_n : IN STD_LOGIC;
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enable_dma : IN STD_LOGIC;
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playfield_start : in std_logic;
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playfield_end : in std_logic;
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vblank : in std_logic;
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slow_dma : in std_logic;
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medium_dma : in std_logic;
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fast_dma : in std_logic;
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dma_clock_out_0 : out std_logic;
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dma_clock_out_1 : out std_logic;
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dma_clock_out_2 : out std_logic;
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dma_clock_out_3 : out std_logic
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);
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| 568 | markw | END antic_dma_clock_del;
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| 1 | markw | ||
| 568 | markw | ARCHITECTURE vhdl OF antic_dma_clock_del IS
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| 1 | markw | signal dma_shiftreg_next : std_logic_vector(7 downto 0);
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signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
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signal tick : std_logic;
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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dma_shiftreg_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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dma_shiftreg_reg <= dma_shiftreg_next;
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end if;
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end process;
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-- next state
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tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
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process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
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begin
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dma_shiftreg_next <= dma_shiftreg_reg;
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if (enable_dma = '1') then
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dma_shiftreg_next <=
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| 568 | markw | not(('0' nor tick)
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or playfield_end or vblank)
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&
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not((playfield_start nor dma_shiftreg_reg(7))
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or vblank)
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&dma_shiftreg_reg(6 downto 1);
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| 1 | markw | end if;
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end process;
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-- output
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dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
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dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
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dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
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dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
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END vhdl;
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