repo2/atari_chips/pokeyv2/sigmadelta_1storder.vhd
| 1081 | markw | ---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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--
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-- Simple sigma delta based on https://aip.scitation.org/doi/pdf/10.1063/1.3526240
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY sigmadelta_1storder IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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AUDIN : IN UNSIGNED(15 downto 0);
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AUDOUT : OUT std_logic
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);
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END sigmadelta_1storder;
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ARCHITECTURE vhdl OF sigmadelta_1storder IS
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signal sigma_latch_next : unsigned(17 downto 0);
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signal sigma_latch_reg : unsigned(17 downto 0);
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signal out_next : std_logic;
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signal out_reg : std_logic;
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BEGIN
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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sigma_latch_reg <= (others=>'0');
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out_reg <= '0';
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elsif (clk'event and clk='1') then
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sigma_latch_reg <= sigma_latch_next;
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out_reg <= out_next;
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end if;
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end process;
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process(audin,sigma_latch_reg)
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variable deltab : unsigned(17 downto 0);
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variable delta_adder_tmp : unsigned(17 downto 0);
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variable sigma_adder_tmp : unsigned(17 downto 0);
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begin
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deltab:= (others=>'0');
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deltab(17) := sigma_latch_reg(17);
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deltab(16) := sigma_latch_reg(17); -- not a typo
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delta_adder_tmp := audin + deltab;
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sigma_adder_tmp := delta_adder_tmp + sigma_latch_reg;
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sigma_latch_next <= sigma_adder_tmp;
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out_next <= sigma_latch_reg(17);
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end process;
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audout <= out_reg;
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end vhdl;
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