repo2/atari_chips/pokeyv2/sigmadelta_2ndorder.vhd
| 1081 | markw | ---------------------------------------------------------------------------
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| 1132 | markw | -- (c) 2020 mark watson
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| 1081 | markw | -- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY sigmadelta_2ndorder IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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| 1087 | markw | ||
ENABLE : IN STD_LOGIC := '1';
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| 1081 | markw | ||
AUDIN : IN UNSIGNED(15 downto 0);
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AUDOUT : OUT std_logic
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);
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END sigmadelta_2ndorder;
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ARCHITECTURE vhdl OF sigmadelta_2ndorder IS
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| 1087 | markw | signal ttl1_next : signed(21 downto 1);
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signal ttl1_reg : signed(21 downto 1);
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| 1134 | markw | signal ttl2_next : signed(23 downto 1);
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signal ttl2_reg : signed(23 downto 1);
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| 1081 | markw | ||
signal out_next : std_logic;
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signal out_reg : std_logic;
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BEGIN
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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ttl1_reg <= (others=>'0');
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ttl2_reg <= (others=>'0');
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out_reg <= '0';
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elsif (clk'event and clk='1') then
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ttl1_reg <= ttl1_next;
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ttl2_reg <= ttl2_next;
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out_reg <= out_next;
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end if;
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end process;
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--a1= -2.00000;
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--a2= -10.00000;
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--b1= 2.00000;
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--c1= 2.00000;
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--c2= 1.00000;
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| 1132 | markw | ||
| 1089 | markw | process(audin,out_reg,ttl1_reg,ttl2_reg,enable)
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| 1132 | markw | variable audinadj : unsigned(16 downto 0);
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| 1087 | markw | variable fb : signed(21 downto 0);
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| 1090 | markw | variable ttl1_tmp : signed(21 downto 1);
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| 1081 | markw | begin
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| 1087 | markw | out_next <= out_reg;
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ttl1_next <= ttl1_reg;
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ttl2_next <= ttl2_reg;
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if (enable='1') then
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| 1132 | markw | audinadj := resize(audin,17) + to_unsigned(4096,17) - resize(audin(15 downto 3) ,17);
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| 1087 | markw | fb:=(others=>'0');
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| 1134 | markw | if (ttl2_reg(23 downto 16)>0) then
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| 1087 | markw | fb(16) := '1';
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else
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fb(16) := '0';
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end if;
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| 1132 | markw | ttl1_tmp := ttl1_reg + resize(signed("0"&audinadj),22-1) - (fb(21-1 downto 0));
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| 1090 | markw | ttl1_next <= ttl1_tmp;
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| 1087 | markw | ||
| 1134 | markw | ttl2_next <= ttl2_reg + resize(((ttl1_tmp(21-1 downto 1)&"0") - ((fb(21-1 downto 0))+(fb(21-3 downto 0)&"00"))),23);
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| 1087 | markw | ||
out_next <= fb(16);
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| 1081 | markw | end if;
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end process;
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audout <= out_reg;
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end vhdl;
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