repo2/common/a8core/internalromram.vhd
| 1 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY internalromram IS
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| 3 | markw | GENERIC
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(
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| 4 | markw | internal_rom : integer := 1;
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| 3 | markw | internal_ram : integer := 16384
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);
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| 1 | markw | PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
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| 803 | markw | ROM_WR_ENABLE : in std_logic;
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ROM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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| 1 | markw | ROM_REQUEST_COMPLETE : out STD_LOGIC;
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ROM_REQUEST : in std_logic;
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ROM_DATA : out std_logic_vector(7 downto 0);
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RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
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RAM_WR_ENABLE : in std_logic;
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RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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RAM_REQUEST_COMPLETE : out STD_LOGIC;
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RAM_REQUEST : in std_logic;
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RAM_DATA : out std_logic_vector(7 downto 0)
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);
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END internalromram;
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architecture vhdl of internalromram is
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signal rom_request_reg : std_logic;
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| 803 | markw | signal rom_request_next : std_logic;
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| 1 | markw | signal ram_request_reg : std_logic;
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| 803 | markw | signal ram_request_next : std_logic;
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| 1 | markw | ||
signal ROM16_DATA : std_logic_vector(7 downto 0);
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| 106 | markw | signal ROM8_DATA : std_logic_vector(7 downto 0);
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signal ROM2_DATA : std_logic_vector(7 downto 0);
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| 1 | markw | signal BASIC_DATA : std_logic_vector(7 downto 0);
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| 321 | markw | signal ramwe_temp : std_logic;
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| 803 | markw | ||
signal romwe_temp : std_logic;
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signal os_romwe_temp : std_logic;
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signal basic_romwe_temp : std_logic;
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| 1 | markw | begin
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process(clock,reset_n)
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begin
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if (reset_n ='0') then
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rom_request_reg <= '0';
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ram_request_reg <= '0';
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elsif (clock'event and clock='1') then
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| 803 | markw | rom_request_reg <= rom_request_next;
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ram_request_reg <= ram_request_next;
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| 1 | markw | end if;
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end process;
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| 178 | markw | gen_internal_5200 : if internal_rom=4 generate
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-- f000 to ffff (4k)
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rom4 : entity work.os_5200
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PORT MAP(clock => clock,
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address => rom_addr(10 downto 0),
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q => ROM_data
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);
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| 840 | markw | rom_request_next <= rom_request and not(ROM_WR_ENABLE);
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| 178 | markw | rom_request_complete <= rom_request_reg;
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end generate;
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| 106 | markw | gen_internal_os_b : if internal_rom=3 generate
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-- d800 to dfff (2k)
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rom2 : entity work.os2
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PORT MAP(clock => clock,
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address => rom_addr(10 downto 0),
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q => ROM2_data
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);
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-- e000 to ffff (8k)
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rom10 : entity work.os8
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PORT MAP(clock => clock,
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address => rom_addr(12 downto 0),
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q => ROM8_data
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);
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process(rom_addr)
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begin
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case rom_addr(13 downto 11) is
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when "011" =>
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ROM_DATA <= ROM2_data;
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when "100"|"101"|"110"|"111" =>
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ROM_DATA <= ROM8_data;
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when others=>
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ROM_DATA <= x"ff";
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end case;
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end process;
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rom_request_complete <= rom_request_reg;
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end generate;
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| 34 | markw | gen_internal_os_loop : if internal_rom=2 generate
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rom16a : entity work.os16_loop
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PORT MAP(clock => clock,
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address => rom_addr(13 downto 0),
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q => ROM16_data
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);
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ROM_DATA <= ROM16_DATA;
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rom_request_complete <= rom_request_reg;
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end generate;
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| 4 | markw | gen_internal_os : if internal_rom=1 generate
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| 34 | markw | rom16a : entity work.os16
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| 3 | markw | PORT MAP(clock => clock,
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address => rom_addr(13 downto 0),
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| 803 | markw | we => os_romwe_temp,
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data => rom_data_in(7 downto 0),
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| 3 | markw | q => ROM16_data
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);
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| 34 | markw | basic1 : entity work.basic
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| 3 | markw | PORT MAP(clock => clock,
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address => rom_addr(12 downto 0),
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| 803 | markw | we => basic_romwe_temp,
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data => rom_data_in(7 downto 0),
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| 3 | markw | q => BASIC_data
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);
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| 803 | markw | romwe_temp <= ROM_WR_ENABLE and rom_request;
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process(rom16_data,basic_data, rom_addr(15 downto 0),romwe_temp)
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| 1 | markw | begin
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| 803 | markw | os_romwe_temp <= romwe_temp;
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basic_romwe_temp <= '0';
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| 1 | markw | ROM_DATA <= ROM16_DATA;
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if (rom_addr(15)='1') then
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ROM_DATA <= BASIC_DATA;
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| 803 | markw | os_romwe_temp <= '0';
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basic_romwe_temp <= romwe_temp;
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| 1 | markw | end if;
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end process;
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| 3 | markw | ||
| 803 | markw | rom_request_next <= rom_request and not(ROM_WR_ENABLE);
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rom_request_complete <= romwe_temp or rom_request_reg;
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| 1 | markw | ||
| 3 | markw | end generate;
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| 273 | markw | ||
| 803 | markw | --gen_internal_os_nobasic : if internal_rom=5 generate
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-- rom16a : entity work.os16
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-- PORT MAP(clock => clock,
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-- address => rom_addr(13 downto 0),
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-- q => ROM16_data
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-- );
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--
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-- process(rom16_data,basic_data, rom_addr(15 downto 0))
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-- begin
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-- ROM_DATA <= ROM16_DATA;
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-- if (rom_addr(15)='1') then
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-- ROM_DATA <= x"FF";
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-- end if;
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-- end process;
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--
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-- rom_request_complete <= rom_request_reg;
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--
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--end generate;
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| 273 | markw | ||
| 4 | markw | gen_no_internal_os : if internal_rom=0 generate
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| 3 | markw | ROM16_data <= (others=>'0');
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| 4 | markw | rom_request_complete <= '0';
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| 3 | markw | end generate;
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| 1 | markw | ||
| 4 | markw | gen_internal_ram: if internal_ram>0 generate
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| 321 | markw | ramwe_temp <= RAM_WR_ENABLE and ram_request;
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| 34 | markw | ramint1 : entity work.generic_ram_infer
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| 1 | markw | generic map
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(
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| 3 | markw | ADDRESS_WIDTH => 19,
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SPACE => internal_ram,
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| 1 | markw | DATA_WIDTH =>8
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)
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PORT MAP(clock => clock,
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| 3 | markw | address => ram_addr,
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| 1 | markw | data => ram_data_in(7 downto 0),
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| 321 | markw | we => ramwe_temp,
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| 3 | markw | q => ram_data
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| 1 | markw | );
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| 803 | markw | ram_request_next <= ram_request and not(RAM_WR_ENABLE);
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ram_request_complete <= ramwe_temp or ram_request_reg;
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| 3 | markw | end generate;
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| 4 | markw | gen_no_internal_ram : if internal_ram=0 generate
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| 42 | markw | ram_request_complete <='1';
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| 3 | markw | ram_data <= (others=>'1');
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end generate;
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| 1 | markw | end vhdl;
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