repo2/common/a8core/internalromram_fast.vhd
| 516 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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------
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-- CLK 1100110011001100110011
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-- CLK2X 1010101010101010101010
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-- readValid 0011001100110011001100 (data is valid here)
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-- writeValid 0011001100110011001100 (only allow write to happen here!)
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--
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-- ts 000011110000111100001111
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-- tf 0000001111000011110000
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-- out 0000110011001100110011
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ENTITY internalromram_fast IS
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GENERIC
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(
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internal_rom : integer := 1;
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internal_ram : integer := 16384
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);
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PORT(
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clock2x : IN STD_LOGIC; --system clock2x 2x faster
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clock1x : IN STD_LOGIC; --system clock2x
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reset_n : IN STD_LOGIC; --asynchronous reset
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ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
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ROM_REQUEST_COMPLETE : out STD_LOGIC;
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ROM_REQUEST : in std_logic;
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ROM_DATA : out std_logic_vector(7 downto 0);
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RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
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RAM_WR_ENABLE : in std_logic;
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RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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RAM_REQUEST_COMPLETE : out STD_LOGIC;
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RAM_REQUEST : in std_logic;
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RAM_DATA : out std_logic_vector(7 downto 0)
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);
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END internalromram_fast;
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architecture vhdl of internalromram_fast is
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signal toggle_fast_next : std_logic;
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signal toggle_fast_reg : std_logic;
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signal toggle_slow_next : std_logic;
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signal toggle_slow_reg : std_logic;
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signal writePossible : std_logic;
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signal ROM16_DATA : std_logic_vector(7 downto 0);
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signal ROM8_DATA : std_logic_vector(7 downto 0);
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signal ROM2_DATA : std_logic_vector(7 downto 0);
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signal BASIC_DATA : std_logic_vector(7 downto 0);
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signal ramwe_temp : std_logic;
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begin
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process(clock2x,reset_n)
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begin
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if (reset_n ='0') then
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toggle_fast_reg <= '0';
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elsif (clock2x'event and clock2x='1') then
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toggle_fast_reg <= toggle_fast_next;
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end if;
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end process;
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toggle_fast_next <= toggle_slow_reg;
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process(clock1x,reset_n)
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begin
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if (reset_n ='0') then
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toggle_slow_reg <= '0';
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elsif (clock1x'event and clock1x='1') then
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toggle_slow_reg <= toggle_slow_next;
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end if;
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end process;
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toggle_slow_next <= not(toggle_slow_reg);
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writePossible <= toggle_fast_reg xnor toggle_slow_reg;
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gen_internal_5200 : if internal_rom=4 generate
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-- f000 to ffff (4k)
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rom4 : entity work.os_5200
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PORT MAP(clock => clock2x,
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address => rom_addr(10 downto 0),
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q => ROM_data
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);
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rom_request_complete <= rom_request;
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end generate;
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gen_internal_os_b : if internal_rom=3 generate
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-- d800 to dfff (2k)
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rom2 : entity work.os2
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PORT MAP(clock => clock2x,
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address => rom_addr(10 downto 0),
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q => ROM2_data
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);
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-- e000 to ffff (8k)
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rom10 : entity work.os8
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PORT MAP(clock => clock2x,
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address => rom_addr(12 downto 0),
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q => ROM8_data
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);
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process(rom_addr)
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begin
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case rom_addr(13 downto 11) is
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when "011" =>
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ROM_DATA <= ROM2_data;
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when "100"|"101"|"110"|"111" =>
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ROM_DATA <= ROM8_data;
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when others=>
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ROM_DATA <= x"ff";
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end case;
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end process;
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rom_request_complete <= rom_request;
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end generate;
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gen_internal_os_loop : if internal_rom=2 generate
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rom16a : entity work.os16_loop
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PORT MAP(clock => clock2x,
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address => rom_addr(13 downto 0),
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q => ROM16_data
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);
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ROM_DATA <= ROM16_DATA;
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rom_request_complete <= rom_request;
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end generate;
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gen_internal_os : if internal_rom=1 generate
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rom16a : entity work.os16
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PORT MAP(clock => clock2x,
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address => rom_addr(13 downto 0),
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q => ROM16_data
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);
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basic1 : entity work.basic
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PORT MAP(clock => clock2x,
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address => rom_addr(12 downto 0),
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q => BASIC_data
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);
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process(rom16_data,basic_data, rom_addr(15 downto 0))
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begin
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ROM_DATA <= ROM16_DATA;
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if (rom_addr(15)='1') then
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ROM_DATA <= BASIC_DATA;
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end if;
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end process;
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rom_request_complete <= rom_request;
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end generate;
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gen_internal_os_nobasic : if internal_rom=5 generate
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rom16a : entity work.os16
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PORT MAP(clock => clock2x,
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address => rom_addr(13 downto 0),
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q => ROM16_data
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);
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process(rom16_data,basic_data, rom_addr(15 downto 0))
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begin
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ROM_DATA <= ROM16_DATA;
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if (rom_addr(15)='1') then
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ROM_DATA <= x"FF";
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end if;
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end process;
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rom_request_complete <= rom_request;
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end generate;
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gen_no_internal_os : if internal_rom=0 generate
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ROM16_data <= (others=>'0');
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rom_request_complete <= '0';
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end generate;
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gen_internal_ram: if internal_ram>0 generate
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ramwe_temp <= writePossible and RAM_WR_ENABLE and ram_request;
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ramint1 : entity work.generic_ram_infer
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generic map
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(
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ADDRESS_WIDTH => 19,
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SPACE => internal_ram,
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DATA_WIDTH =>8
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)
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PORT MAP(clock => clock2x,
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address => ram_addr,
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data => ram_data_in(7 downto 0),
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we => ramwe_temp,
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q => ram_data
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);
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ram_request_complete <= ram_request;
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end generate;
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gen_no_internal_ram : if internal_ram=0 generate
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ram_request_complete <='1';
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ram_data <= (others=>'1');
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end generate;
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end vhdl;
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