repo2/common/a8core/internalromram_simple.vhd
| 507 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY internalromram_simple IS
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PORT(
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clock : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --asynchronous reset
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ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
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ROM_REQUEST_COMPLETE : out STD_LOGIC;
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ROM_REQUEST : in std_logic;
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OS_DATA : out std_logic_vector(7 downto 0);
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BASIC_DATA : out std_logic_vector(7 downto 0);
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RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
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RAM_WR_ENABLE : in std_logic;
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RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
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RAM_REQUEST_COMPLETE : out STD_LOGIC;
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RAM_REQUEST : in std_logic;
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RAM_DATA : out std_logic_vector(7 downto 0)
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);
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END internalromram_simple;
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architecture vhdl of internalromram_simple is
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signal rom_request_reg : std_logic;
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signal ram_request_reg : std_logic;
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signal ramwe_temp : std_logic;
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begin
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process(clock,reset_n)
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begin
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if (reset_n ='0') then
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rom_request_reg <= '0';
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ram_request_reg <= '0';
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elsif (clock'event and clock='1') then
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rom_request_reg <= rom_request;
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ram_request_reg <= ram_request;
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end if;
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end process;
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rom16a : entity work.os16
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PORT MAP(clock => clock,
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address => rom_addr(13 downto 0),
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q => OS_DATA
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);
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basic1 : entity work.basic
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PORT MAP(clock => clock,
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address => rom_addr(12 downto 0),
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q => BASIC_data
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);
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rom_request_complete <= rom_request_reg;
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ramwe_temp <= RAM_WR_ENABLE and ram_request;
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ramint1 : entity work.generic_ram_infer
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generic map
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(
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ADDRESS_WIDTH => 19,
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SPACE => 65536,
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DATA_WIDTH =>8
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)
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PORT MAP(clock => clock,
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reset_n => reset_n,
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address => ram_addr,
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data => ram_data_in(7 downto 0),
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we => ramwe_temp,
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q => ram_data
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);
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ram_request_complete <= ram_request_reg;
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end vhdl;
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