repo2/common/a8core/pokey_mixer.vhdl
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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| 111 | markw | use IEEE.STD_LOGIC_MISC.all;
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| 1 | markw | ||
ENTITY pokey_mixer IS
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PORT
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(
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| 321 | markw | CLK : IN STD_LOGIC;
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| 1 | markw | CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
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CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
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GTIA_SOUND : IN STD_LOGIC;
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| 803 | markw | SIO_AUDIO : IN STD_LOGIC_VECTOR(7 downto 0);
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| 1 | markw | ||
COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
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COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
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| 960 | markw | ||
SID_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
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| 1 | markw | ||
| 185 | markw | VOLUME_OUT_NEXT : OUT STD_LOGIC_vector(15 downto 0)
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| 1 | markw | );
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END pokey_mixer;
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ARCHITECTURE vhdl OF pokey_mixer IS
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| 321 | markw | signal volume_sum_next : std_logic_vector(9 downto 0);
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signal volume_sum_reg : std_logic_vector(9 downto 0);
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| 11 | markw | signal volume_next : std_logic_vector(15 downto 0);
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| 321 | markw | ||
signal y1 : signed(15 downto 0);
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signal y1_reg : signed(15 downto 0);
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signal y2 : signed(15 downto 0);
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signal ych : signed(15 downto 0);
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signal yadj_next : signed(31 downto 0);
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signal yadj_reg : signed(31 downto 0);
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signal b_in : signed(15 downto 0);
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| 1 | markw | BEGIN
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| 321 | markw | process(clk)
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begin
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if (clk'event and clk='1') then
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VOLUME_SUM_REG <= VOLUME_SUM_NEXT;
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YADJ_REG <= YADJ_NEXT;
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Y1_REG <= Y1;
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END IF;
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END PROCESS;
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| 1 | markw | -- next state
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| 960 | markw | process (channel_0,channel_1,channel_2,channel_3,covox_CHANNEL_0,covox_channel_1,sid_channel_0,gtia_sound,sio_audio)
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| 111 | markw | variable channel0_en_long : unsigned(10 downto 0);
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variable channel1_en_long : unsigned(10 downto 0);
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variable channel2_en_long : unsigned(10 downto 0);
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variable channel3_en_long : unsigned(10 downto 0);
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variable gtia_sound_long : unsigned(10 downto 0);
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| 803 | markw | variable sio_audio_long : unsigned(10 downto 0);
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| 111 | markw | variable covox_0_long : unsigned(10 downto 0);
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variable covox_1_long : unsigned(10 downto 0);
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| 960 | markw | variable sid_0_long : unsigned(10 downto 0);
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| 111 | markw | ||
variable volume_int_sum : unsigned(10 downto 0);
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| 1 | markw | begin
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| 111 | markw | channel0_en_long := (others=>'0');
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channel1_en_long := (others=>'0');
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channel2_en_long := (others=>'0');
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channel3_en_long := (others=>'0');
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gtia_sound_long := (others=>'0');
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| 803 | markw | sio_audio_long := (others=>'0');
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| 111 | markw | covox_0_long := (others=>'0');
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covox_1_long := (others=>'0');
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| 960 | markw | sid_0_long := (others=>'0');
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| 111 | markw | ||
| 185 | markw | channel0_en_long(7 downto 4) := unsigned(channel_0);
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channel1_en_long(7 downto 4) := unsigned(channel_1);
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channel2_en_long(7 downto 4) := unsigned(channel_2);
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channel3_en_long(7 downto 4) := unsigned(channel_3);
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| 111 | markw | gtia_sound_long(7 downto 4) := gtia_sound>ia_sound>ia_sound>ia_sound;
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| 803 | markw | sio_audio_long(7 downto 0) := unsigned(sio_audio);
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| 111 | markw | covox_0_long(7 downto 0) := unsigned(covox_channel_0);
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covox_1_long(7 downto 0) := unsigned(covox_channel_1);
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| 960 | markw | sid_0_long(7 downto 0) := unsigned(sid_channel_0);
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| 111 | markw | ||
| 960 | markw | volume_int_sum := ((channel0_en_long + channel1_en_long) + (channel2_en_long + channel3_en_long)) + ((gtia_sound_long + sio_audio_long) + (covox_0_long + covox_1_long) + (sid_0_long + sid_0_long));
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| 111 | markw | ||
| 321 | markw | volume_sum_next(9 downto 0) <= std_logic_vector(volume_int_sum(9 downto 0)) or volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10)&volume_int_sum(10);
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| 1 | markw | end process;
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| 321 | markw | process (volume_sum_reg, y1, y2, y1_reg, yadj_reg)
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type LOOKUP_TYPE is array (0 to 32) of signed(15 downto 0);
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variable lookup : LOOKUP_TYPE;
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| 1 | markw | begin
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| 321 | markw | -- replace with piecewise interp. Takes a mul unit but saves lookup space.
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lookup := (x"86E8" ,x"9E40" ,x"B3E3" ,x"C7E3" ,x"DA52" ,x"EB42" ,x"FAC5" ,x"08ED" ,x"15CB" ,x"2172" ,x"2BF4" ,x"3562" ,x"3DCE" ,x"454B" ,x"4BEA" ,x"51BD" ,x"56D6" ,x"5B47" ,x"5F22" ,x"6278" ,x"655C" ,x"67E0" ,x"6A15" ,x"6C0D" ,x"6DDB" ,x"6F90" ,x"713E" ,x"72F7" ,x"74CD" ,x"76D2" ,x"7918" ,x"7BB0" ,x"7EAD");
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y1 <= lookup(to_integer(unsigned(volume_sum_reg(9 downto 5))));
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y2 <= lookup(to_integer(unsigned(volume_sum_reg(9 downto 5)))+1);
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ych <= y2-y1;
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volume_next <= std_logic_vector(yadj_reg(20 downto 5) + y1_reg);
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--case volume_sum(9 downto 0) is
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--end case;
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| 11 | markw | end process;
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| 111 | markw | ||
| 321 | markw | B_in <= signed("00000000000"&volume_sum_reg(4 downto 0));
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linterp_mult : entity work.mult_infer
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PORT MAP( A => signed(ych),
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B => b_in,
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RESULT => yadj_next);
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| 1 | markw | -- output
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| 185 | markw | volume_out_next <= volume_next;
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| 1 | markw | ||
| 11 | markw | END vhdl;
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