repo2/eclaireXL_ITX/hardware/test/test_hdmi/pll2.cmp
| 479 | markw | component pll2 is
|
|
port (
|
|||
refclk : in std_logic := 'X'; -- clk
|
|||
rst : in std_logic := 'X'; -- reset
|
|||
outclk_0 : out std_logic; -- clk
|
|||
outclk_1 : out std_logic; -- clk
|
|||
locked : out std_logic -- export
|
|||
);
|
|||
end component pll2;
|