EclaireXL

component pll_acore is

port (

refclk : in std_logic := 'X'; -- clk

rst : in std_logic := 'X'; -- reset

outclk_0 : out std_logic; -- clk

outclk_1 : out std_logic; -- clk

outclk_2 : out std_logic; -- clk

outclk_3 : out std_logic; -- clk

locked : out std_logic; -- export

reconfig_to_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_to_pll

reconfig_from_pll : out std_logic_vector(63 downto 0) -- reconfig_from_pll

);

end component pll_acore;