repo2/papilioduo/pll/coregen.cgp
| 327 | markw | # Date: Wed Mar 18 19:59:48 2015
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET verilogsim = false
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SET vhdlsim = true
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SET workingdirectory = ./tmp/
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# CRC: 71981ec3
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