repo2/papilioduo/pll/coregen.log
| 327 | markw | Welcome to Xilinx CORE Generator.
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Help system initialized.
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The IP Catalog has been reloaded.
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Wrote CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Resolving generics for 'pll_5'...
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Applying external generics to 'pll_5'...
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Delivering associated files for 'pll_5'...
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WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL
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synthesis
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Delivering EJava files for 'pll_5'...
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Delivered 3 files into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5
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Delivered 1 file into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5
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Generating ASY schematic symbol...
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Loading device for application Rf_Device from file '6slx9.nph' in environment
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/home/markw/fpga/xilinx/14.7/ISE_DS/ISE/.
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating ISE project...
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XCO file found: pll_5.xco
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XMDF file found: pll_5_xmdf.tcl
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5.asy -view all -origin_type imported
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5.ucf -view all -origin_type created
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_
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cg/pll_5.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_5.vho -view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/pll_5"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Resolving generics for 'pll_pal'...
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Applying external generics to 'pll_pal'...
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Delivering associated files for 'pll_pal'...
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WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL
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synthesis
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Delivering EJava files for 'pll_pal'...
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Delivered 3 files into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal
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Delivered 1 file into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating ISE project...
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XCO file found: pll_pal.xco
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XMDF file found: pll_pal_xmdf.tcl
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal.asy -view all -origin_type imported
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal.ucf -view all -origin_type created
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_
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cg/pll_pal.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_pal.vho -view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/pll_pal"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Resolving generics for 'pll_ntsc'...
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Applying external generics to 'pll_ntsc'...
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Delivering associated files for 'pll_ntsc'...
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WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL
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synthesis
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Delivering EJava files for 'pll_ntsc'...
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Delivered 3 files into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc
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Delivered 1 file into directory
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating ISE project...
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XCO file found: pll_ntsc.xco
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XMDF file found: pll_ntsc_xmdf.tcl
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc.asy -view all -origin_type imported
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc.ucf -view all -origin_type created
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_
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cg/pll_ntsc.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p
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ll_ntsc.vho -view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
|
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Please set the new top explicitly by running the "project set top" command.
|
|||
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
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property to true.
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Top level has been set to "/pll_ntsc"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Closed project file.
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