repo2/ultimate_cart/veronica/atari_address_decoder.vhd
| 438 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY atari_address_decoder IS
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PORT (
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| 443 | markw | s4_n : in std_logic;
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s5_n : in std_logic;
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ctl_n : in std_logic;
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| 438 | markw | addr_in: in std_logic_vector(12 downto 0);
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bus_request: in std_logic;
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bank_half_select : in std_logic;
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bank_select : in std_logic;
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config_select : out std_logic;
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sram_select : out std_logic;
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sram_address : out std_logic_vector(16 downto 0)
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);
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END atari_address_decoder;
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ARCHITECTURE vhdl OF atari_address_decoder IS
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| 444 | markw | signal addr_valid : std_logic;
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| 438 | markw | begin
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sram_address(16) <= '1';
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sram_address(15 downto 14) <= bank_select&bank_half_select;
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| 443 | markw | sram_address(13) <= s4_n and not(s5_n);
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| 438 | markw | sram_address(12 downto 0) <= addr_in;
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| 443 | markw | sram_select <= bus_request and not(s4_n and s5_n);
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| 444 | markw | addr_valid <= '1' when addr_in(7 downto 0)=x"c0" else '0';
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config_select <= bus_request and not(ctl_n) and addr_valid;
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| 438 | markw | ||
end vhdl;
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