repo2/ultimate_cart/veronica/config_regs_6502.vhd
| 438 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY config_regs_6502 IS
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PORT (
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CLK: in std_logic;
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RESET_N: in std_logic;
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SEM_OUT: out std_logic;
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BANKA_ENABLE: out std_logic;
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BANK8_ENABLE: out std_logic;
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BANK_HALF_SELECT: out std_logic;
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BANK_SELECT: out std_logic;
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ENABLE_65816: out std_logic;
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| 687 | markw | SEM_WRITE_65816 : in std_logic;
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SEM_VALUE_65816 : in std_logic;
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| 438 | markw | DATA_IN: in std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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RW_N: in std_logic
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);
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END config_regs_6502;
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ARCHITECTURE vhdl OF config_regs_6502 IS
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signal sem_next : std_logic;
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signal sem_reg : std_logic;
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signal banka_enable_next : std_logic;
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signal banka_enable_reg : std_logic;
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signal bank8_enable_next : std_logic;
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signal bank8_enable_reg : std_logic;
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signal bank_half_next : std_logic;
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signal bank_half_reg : std_logic;
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signal bank_select_next : std_logic;
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signal bank_select_reg : std_logic;
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signal enable_65816_next : std_logic;
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signal enable_65816_reg : std_logic;
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begin
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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sem_reg <= '1';
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banka_enable_reg <= '0';
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bank8_enable_reg <= '0';
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bank_half_reg <= '1';
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bank_select_reg <= '0';
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enable_65816_reg <= '0';
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elsif (clk'event and clk='1') then
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sem_reg <= sem_next;
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banka_enable_reg <= banka_enable_next;
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bank8_enable_reg <= bank8_enable_next;
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bank_half_reg <= bank_half_next;
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bank_select_reg <= bank_select_next;
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enable_65816_reg <= enable_65816_next;
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end if;
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end process;
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| 687 | markw | process(data_in,rw_n,sem_reg,banka_enable_reg,bank8_enable_reg,bank_half_reg,bank_select_reg,enable_65816_reg,sem_write_65816,sem_value_65816)
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| 438 | markw | begin
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sem_next <= sem_reg;
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banka_enable_next <= banka_enable_reg;
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bank8_enable_next <= bank8_enable_reg;
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bank_half_next <= bank_half_reg;
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bank_select_next <= bank_select_reg;
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enable_65816_next <= enable_65816_reg;
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if (rw_n='0') then
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sem_next <= data_in(7);
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banka_enable_next <= data_in(5);
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bank8_enable_next <= data_in(4);
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bank_half_next <= data_in(3);
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bank_select_next <= data_in(1);
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enable_65816_next <= data_in(0);
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end if;
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| 687 | markw | ||
if (sem_write_65816='1') then
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sem_next <= sem_value_65816;
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end if;
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| 438 | markw | end process;
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data_out <= sem_reg&'1'&banka_enable_reg&bank8_enable_reg&bank_half_reg&'1'&bank_select_reg&enable_65816_reg;
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sem_out <= sem_reg;
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banka_enable <= banka_enable_reg;
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bank8_enable <= bank8_enable_reg;
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bank_half_select<=bank_half_reg;
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bank_select<=bank_select_reg;
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enable_65816<=enable_65816_reg;
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end vhdl;
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