repo2/ultimate_cart/veronica/config_regs_veronica.vhd
| 438 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY config_regs_veronica IS
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PORT (
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CLK: in std_logic;
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RESET_N: in std_logic;
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SEM_IN: in std_logic;
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WINDOW_ADDRESS: out std_logic;
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BANK_HALF_SELECT: out std_logic;
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| 687 | markw | SEM_WRITE : out std_logic;
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SEM_VALUE : out std_logic;
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| 438 | markw | DATA_IN: in std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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RW_N: in std_logic
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);
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END config_regs_veronica;
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ARCHITECTURE vhdl OF config_regs_veronica IS
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signal window_address_next : std_logic;
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signal window_address_reg : std_logic;
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signal bank_half_next : std_logic;
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signal bank_half_reg : std_logic;
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begin
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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window_address_reg <= '0';
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bank_half_reg <= '1';
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elsif (clk'event and clk='1') then
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window_address_reg <= window_address_next;
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bank_half_reg <= bank_half_next;
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end if;
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end process;
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process(rw_n,window_address_reg,bank_half_reg,data_in)
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begin
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window_address_next <= window_address_reg;
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bank_half_next <= bank_half_reg;
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| 687 | markw | sem_write <= '0';
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sem_value <= '0'; -- Not important
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| 438 | markw | ||
if (rw_n='0') then
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window_address_next <= data_in(6);
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bank_half_next <= data_in(5);
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| 687 | markw | sem_write <= '1';
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sem_value <= not(data_in(7));
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| 438 | markw | end if;
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end process;
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data_out <= not(sem_in)&window_address_reg&bank_half_reg&"11111";
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window_address <= window_address_reg;
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bank_half_select <= bank_half_reg;
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end vhdl;
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