repo2/ultimate_cart/veronica/memory_timing_bridge.vhd
| 446 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY memory_timing_bridge IS
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PORT
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(
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clk : in std_logic;
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clk7x : in std_logic;
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reset_n : in std_logic;
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fast_memory_request : in std_logic;
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registered_read_data : out std_logic_vector(7 downto 0);
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memory_request : out std_logic;
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read_data : in std_logic_vector(7 downto 0)
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);
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END memory_timing_bridge;
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ARCHITECTURE vhdl OF memory_timing_bridge IS
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signal memory_next : std_logic_vector(7 downto 0);
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signal memory_reg : std_logic_vector(7 downto 0);
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signal fast_request_toggle_next : std_logic;
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signal fast_request_toggle_reg : std_logic;
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signal slow_request_toggle_next : std_logic;
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signal slow_request_toggle_reg : std_logic;
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signal make_request_next : std_logic;
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signal make_request_reg : std_logic;
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begin
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-- register
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| 447 | markw | process(clk,reset_n)
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| 446 | markw | begin
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if (reset_n='0') then
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memory_reg <= (others=>'0');
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slow_request_toggle_reg <= '0';
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make_request_reg <= '0';
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elsif (clk'event and clk='1') then
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memory_reg <= memory_next;
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slow_request_toggle_reg <= slow_request_toggle_next;
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make_request_reg <= make_request_next;
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end if;
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end process;
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| 447 | markw | process(clk7x,reset_n)
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| 446 | markw | begin
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if (reset_n='0') then
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fast_request_toggle_reg <= '0';
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| 447 | markw | elsif (clk7x'event and clk7x='1') then
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| 446 | markw | fast_request_toggle_reg <= fast_request_toggle_next;
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end if;
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end process;
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fast_request_toggle_next <= fast_request_toggle_reg xor fast_memory_request;
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| 447 | markw | slow_request_toggle_next <= fast_request_toggle_reg;
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| 446 | markw | ||
process(memory_reg,read_data,make_request_reg)
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begin
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memory_next <= memory_reg;
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if (make_request_reg = '1') then
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memory_next <= read_data;
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end if;
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end process;
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make_request_next <= slow_request_toggle_reg xor fast_request_toggle_reg;
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registered_read_data <= memory_reg;
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memory_request <= make_request_reg;
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end vhdl;
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