Back off by 2 cycles, make it more reliable (was missing some eclairexl writes)
Added testbenches. Do not respond to bus cycles that do not target the cart
Moved memory timing bridge inside slave_timing, its an internal detail really
Adjusted delays and verified in sim
Trivial but important fixes, thanks to quartus warnings
70ns accuracy is not enough for reliable Atari bus sampling, use faster clock we are already using for sram
Register bus_data before we write it
Simulated and repaired 6502 bus and sram bus
First cut implementation of veronica clone for ultimate cart - does not work yet, but getting close. Project to try out Rob Finchs 65816 core.