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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY gtia_priority IS
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PORT
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(
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CLK : in std_logic;
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colour_enable : in std_logic;
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PRIOR : in std_logic_vector(7 downto 0);
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P0 : in std_logic;
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P1 : in std_logic;
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P2 : in std_logic;
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P3 : in std_logic;
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PF0 : in std_logic;
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PF1 : in std_logic;
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PF2 : in std_logic;
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PF3 : in std_logic;
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BK : in std_logic;
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P0_OUT : out std_logic;
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P1_OUT : out std_logic;
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P2_OUT : out std_logic;
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P3_OUT : out std_logic;
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PF0_OUT : out std_logic;
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PF1_OUT : out std_logic;
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PF2_OUT : out std_logic;
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PF3_OUT : out std_logic;
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BK_OUT : out std_logic
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);
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END gtia_priority;
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ARCHITECTURE vhdl OF gtia_priority IS
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signal P01 : std_logic;
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signal P23 : std_logic;
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signal PF01 : std_logic;
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signal PF23 : std_logic;
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signal PRI01 : std_logic;
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signal PRI12 : std_logic;
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signal PRI23 : std_logic;
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signal PRI03 : std_logic;
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signal PRI0 : std_logic;
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signal PRI1 : std_logic;
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signal PRI2 : std_logic;
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signal PRI3 : std_logic;
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signal MULTI : std_logic;
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signal SP0 : std_logic;
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signal SP1 : std_logic;
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signal SP2 : std_logic;
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signal SP3 : std_logic;
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signal SF0 : std_logic;
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signal SF1 : std_logic;
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signal SF2 : std_logic;
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signal SF3 : std_logic;
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signal SB : std_logic;
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signal SP0_next : std_logic;
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signal SP1_next : std_logic;
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signal SP2_next : std_logic;
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signal SP3_next : std_logic;
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signal SF0_next : std_logic;
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signal SF1_next : std_logic;
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signal SF2_next : std_logic;
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signal SF3_next : std_logic;
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signal SB_next : std_logic;
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signal SP0_reg : std_logic;
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signal SP1_reg : std_logic;
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signal SP2_reg : std_logic;
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signal SP3_reg : std_logic;
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signal SF0_reg : std_logic;
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signal SF1_reg : std_logic;
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signal SF2_reg : std_logic;
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signal SF3_reg : std_logic;
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signal SB_reg : std_logic;
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begin
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-- Use actual GTIA logic...
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P01 <= P0 or P1;
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P23 <= P2 or P3;
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PF01 <= PF0 or PF1;
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PF23 <= PF2 or PF3;
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PRI0 <= prior(0);
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PRI1 <= prior(1);
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PRI2 <= prior(2);
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PRI3 <= prior(3);
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MULTI <= prior(5);
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PRI01 <= PRI0 or PRI1;
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PRI12 <= PRI1 or PRI2;
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PRI23 <= PRI2 or PRI3;
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PRI03 <= PRI0 or PRI3;
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SP0 <= P0 and not (PF01 and PRI23) and not (PRI2 and PF23);
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SP1 <= P1 and not (PF01 and PRI23) and not (PRI2 and PF23) and ( not P0 or MULTI);
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SP2 <= P2 and not P01 and not (PF23 and PRI12) and not (PF01 and not PRI0);
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SP3 <= P3 and not P01 and not (PF23 and PRI12) and not (PF01 and not PRI0) and ( not P2 or MULTI);
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SF0 <= PF0 and not (P23 and PRI0) and not (P01 and PRI01) and not SF3;
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SF1 <= PF1 and not (P23 and PRI0) and not (P01 and PRI01) and not SF3;
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SF2 <= PF2 and not (P23 and PRI03) and not (P01 and not PRI2) and not SF3;
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SF3 <= PF3 and not (P23 and PRI03) and not (P01 and not PRI2);
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SB <= not P01 and not P23 and not PF01 and not PF23;
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-- register
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process(clk)
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begin
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if (clk'event and clk='1') then
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SP0_reg <= SP0_next;
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SP1_reg <= SP1_next;
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SP2_reg <= SP2_next;
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SP3_reg <= SP3_next;
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SF0_reg <= SF0_next;
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SF1_reg <= SF1_next;
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SF2_reg <= SF2_next;
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SF3_reg <= SF3_next;
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SB_reg <= SB_next;
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end if;
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end process;
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-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
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process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
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begin
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SP0_next <= SP0_reg;
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SP1_next <= SP1_reg;
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SP2_next <= SP2_reg;
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SP3_next <= SP3_reg;
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SF0_next <= SF0_reg;
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SF1_next <= SF1_reg;
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SF2_next <= SF2_reg;
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SF3_next <= SF3_reg;
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SB_next <= SB_reg;
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if (colour_enable = '1') then
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SP0_next <= SP0;
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SP1_next <= SP1;
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SP2_next <= SP2;
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SP3_next <= SP3;
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SF0_next <= SF0;
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SF1_next <= SF1;
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SF2_next <= SF2;
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SF3_next <= SF3;
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SB_next <= SB;
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end if;
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end process;
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-- output
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P0_OUT <= SP0_reg;
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P1_OUT <= SP1_reg;
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P2_OUT <= SP2_reg;
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P3_OUT <= SP3_reg;
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PF0_OUT <= SF0_reg;
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PF1_OUT <= SF1_reg;
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PF2_OUT <= SF2_reg;
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PF3_OUT <= SF3_reg;
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BK_OUT <= SB_reg;
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end vhdl;
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