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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY SID_amplitudeModulator IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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WAVE : IN STD_LOGIC_VECTOR(11 downto 0);
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ENVELOPE : IN STD_LOGIC_VECTOR(7 downto 0);
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MODULATED : OUT SIGNED(15 downto 0)
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);
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END SID_amplitudeModulator;
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ARCHITECTURE vhdl OF SID_amplitudeModulator IS
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signal mod_reg: signed(15 downto 0);
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signal mod_next: signed(15 downto 0);
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BEGIN
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-- register
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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mod_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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mod_reg <= mod_next;
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end if;
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end process;
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-- next state
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process(mod_reg,enable,wave,envelope)
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variable multres : signed(26 downto 0);
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begin
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mod_next <= mod_reg;
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if (enable = '1') then
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multres := signed("0"&envelope)*(signed(resize(unsigned(wave),18))-2048);
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mod_next <= multres(19 downto 4);
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end if;
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end process;
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-- output
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modulated <= mod_reg;
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END vhdl;
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