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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity pll_reset_sync is
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generic (
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RESET_CYCLES : natural := 64 -- adjust per design
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);
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port (
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clk : in std_logic;
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pll_locked : in std_logic;
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reset_n : out std_logic
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);
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end entity;
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architecture rtl of pll_reset_sync is
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signal locked_sync : std_logic_vector(1 downto 0) := (others => '0');
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signal shreg : std_logic_vector(RESET_CYCLES-1 downto 0) := (others => '0');
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begin
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-- sync
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process(clk)
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begin
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if rising_edge(clk) then
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locked_sync(0) <= pll_locked;
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locked_sync(1) <= locked_sync(0);
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end if;
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end process;
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-- stretch
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process(clk)
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begin
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if rising_edge(clk) then
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if locked_sync(1) = '0' then
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shreg <= (others => '0');
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else
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shreg <= shreg(RESET_CYCLES-2 downto 0) & '1';
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end if;
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end if;
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end process;
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reset_n <= shreg(RESET_CYCLES-1);
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end architecture;
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