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Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate C:\cygwin64\home\Mark\atari800_fpga\atari_800xl\eclaireXL\build_A2EBA\serial_loader.qsys --block-symbol-file --output-directory=C:\cygwin64\home\Mark\atari800_fpga\atari_800xl\eclaireXL\build_A2EBA\serial_loader --family="Cyclone V" --part=5CEBA2F23C8
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Progress: Loading build_A2EBA/serial_loader.qsys
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Progress: Reading input file
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Progress: Adding serial_flash_loader_0 [altera_serial_flash_loader 15.0]
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Progress: Parameterizing module serial_flash_loader_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: ip-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate C:\cygwin64\home\Mark\atari800_fpga\atari_800xl\eclaireXL\build_A2EBA\serial_loader.qsys --synthesis=VERILOG --output-directory=C:\cygwin64\home\Mark\atari800_fpga\atari_800xl\eclaireXL\build_A2EBA\serial_loader\synthesis --family="Cyclone V" --part=5CEBA2F23C8
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Progress: Loading build_A2EBA/serial_loader.qsys
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Progress: Reading input file
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Progress: Adding serial_flash_loader_0 [altera_serial_flash_loader 15.0]
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Progress: Parameterizing module serial_flash_loader_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: serial_loader: Generating serial_loader "serial_loader" for QUARTUS_SYNTH
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Info: serial_flash_loader_0: generating top-level entity altera_serial_flash_loader
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Info: serial_flash_loader_0: "serial_loader" instantiated altera_serial_flash_loader "serial_flash_loader_0"
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Info: serial_loader: Done "serial_loader" with 2 modules, 2 files
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Info: ip-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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