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Revision 1333

Added by markw about 4 years ago

Tighten up some timings.

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atari_chips/pokeyv2/flash_controller.vhd
signal flash_data_burstcount : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(2 downto 0);
signal state_next : std_logic_vector(2 downto 0);
constant state_idle : std_logic_vector(2 downto 0) := "000";
constant state_read : std_logic_vector(2 downto 0) := "001";
constant state_write : std_logic_vector(2 downto 0) := "010";
constant state_read_wait : std_logic_vector(2 downto 0) := "011";
constant state_delay : std_logic_vector(2 downto 0) := "100";
constant state_delay2 : std_logic_vector(2 downto 0) := "101";
constant state_delay3 : std_logic_vector(2 downto 0) := "110";
constant state_delay4 : std_logic_vector(2 downto 0) := "111";
signal state_reg : std_logic_vector(3 downto 0);
signal state_next : std_logic_vector(3 downto 0);
constant state_idle : std_logic_vector(3 downto 0) := "0000";
constant state_read : std_logic_vector(3 downto 0) := "0001";
constant state_write : std_logic_vector(3 downto 0) := "0010";
constant state_read_wait : std_logic_vector(3 downto 0) := "0011";
constant state_delay : std_logic_vector(3 downto 0) := "0100";
constant state_delay2 : std_logic_vector(3 downto 0) := "0101";
constant state_delay3 : std_logic_vector(3 downto 0) := "0110";
constant state_delay4 : std_logic_vector(3 downto 0) := "0111";
constant state_write_wait : std_logic_vector(3 downto 0) := "1000";
signal request_addr_reg : std_logic_vector(addr_bits-1 downto 0);
signal request_addr_next : std_logic_vector(addr_bits-1 downto 0);
......
signal update_robin : std_logic;
signal flash_read : std_logic;
signal flash_readvalid : std_logic;
signal flash_write : std_logic;
signal flash_write_next : std_logic;
signal flash_write_reg : std_logic;
signal flash_waitrequest : std_logic;
signal flash_do : std_logic_vector(31 downto 0);
......
robin_reg <= "10000000";
flash_do_reg <= (others=>'0');
flash_complete_reg <= (others=>'0');
flash_write_reg <= '0';
elsif (clk'event and clk='1') then
state_reg <= state_next;
request_addr_reg <= request_addr_next;
......
robin_reg <= robin_next;
flash_do_reg <= flash_do_next;
flash_complete_reg <= flash_complete_next;
flash_write_reg <= flash_write_next;
end if;
end process;
......
flash_readvalid, flash_waitrequest,
flash_write_reg,
complete,
update_robin
)
......
complete <= '0';
flash_read <= '0';
flash_write <= '0';
flash_write_next <= flash_write_reg;
device := '0';
addr := (others=>'0');
......
flash_read <= '1';
state_next <= state_read_wait;
when state_read_wait =>
flash_read <= flash_waitrequest;
complete <= flash_readvalid;
if (flash_readvalid = '1') then
complete <= '1';
state_next <= state_delay;
end if;
when state_write=>
flash_write <= '1';
complete <= not(flash_waitrequest);
flash_write_next <= '1';
state_next <= state_write_wait;
when state_write_wait=>
if (flash_waitrequest='0') then
flash_write_next <= '0';
complete <= '1';
state_next <= state_delay;
end if;
when state_delay=>
......
when state_delay3=>
state_next <= state_delay4;
when state_delay4=>
state_next <= state_idle;
if (flash_waitrequest='0') then
state_next <= state_idle;
end if;
when others=>
state_next <= state_idle;
end case;
......
-- mux on selected device
process(device_reg, flash_data_do, flash_config_do,
flash_write,flash_read,flash_data_readvalid,flash_data_waitrequest)
flash_write_reg,flash_read,flash_data_readvalid,flash_data_waitrequest)
begin
flash_do <= (others=>'0');
......
if (device_reg='1') then --config
flash_do <= flash_config_do;
flash_config_read <= flash_read;
flash_config_write <= flash_write;
flash_config_write <= flash_write_reg;
flash_readvalid <= '1';
elsif (device_reg='0') then --main
flash_do <= flash_data_do;
flash_data_read <= flash_read;
flash_data_write <= flash_write;
flash_data_write <= flash_write_reg;
flash_readvalid <= flash_data_readvalid;
flash_waitrequest <= flash_data_waitrequest;
end if;

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