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Revision 1398

Added by markw over 1 year ago

Added missing lvds

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atari_chips/pokeyv2/lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v
//lpm_ff CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" LPM_WIDTH=1 clock data q
//VERSION_BEGIN 20.1 cbx_lpm_ff 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//synthesis_resources = lut 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_soft_lvds_rx_twD2Tqf3
(
clock,
data,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input [0:0] data;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] ff_dffe;
wire enable;
// synopsys translate_off
initial
ff_dffe = 0;
// synopsys translate_on
always @ ( posedge clock)
if (enable == 1'b1) ff_dffe <= data;
assign
enable = 1'b1,
q = ff_dffe;
endmodule //altera_soft_lvds_rx_twD2Tqf3
//VALID FILE
atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 20.1 720 linux 2021.04.24.15:12:23
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# lvds_tx
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If lvds_tx is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "lvds_tx"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/fiftyfivenm_ver
vmap fiftyfivenm_ver ./libraries/fiftyfivenm_ver
ensure_lib ./libraries/altera
vmap altera ./libraries/altera
ensure_lib ./libraries/lpm
vmap lpm ./libraries/lpm
ensure_lib ./libraries/sgate
vmap sgate ./libraries/sgate
ensure_lib ./libraries/altera_mf
vmap altera_mf ./libraries/altera_mf
ensure_lib ./libraries/altera_lnsim
vmap altera_lnsim ./libraries/altera_lnsim
ensure_lib ./libraries/fiftyfivenm
vmap fiftyfivenm ./libraries/fiftyfivenm
ensure_lib ./libraries/lvds_tx
vmap lvds_tx ./libraries/lvds_tx
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v" -work fiftyfivenm_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd" -work fiftyfivenm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd" -work fiftyfivenm
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/lvds_tx.vhd"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
atari_chips/pokeyv2/lvds_tx_sim/cadence/cds.lib
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE lvds_tx ./libraries/lvds_tx/
DEFINE altera_ver ./libraries/altera_ver/
DEFINE lpm_ver ./libraries/lpm_ver/
DEFINE sgate_ver ./libraries/sgate_ver/
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/
DEFINE altera ./libraries/altera/
DEFINE lpm ./libraries/lpm/
DEFINE sgate ./libraries/sgate/
DEFINE altera_mf ./libraries/altera_mf/
DEFINE altera_lnsim ./libraries/altera_lnsim/
DEFINE fiftyfivenm ./libraries/fiftyfivenm/
atari_chips/pokeyv2/lvds_rx.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 144)
(text "lvds_rx" (rect 51 -1 81 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "data" (rect 0 0 16 12)(font "Arial" (font_size 8)))
(text "data" (rect 4 61 28 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "clock" (rect 0 0 20 12)(font "Arial" (font_size 8)))
(text "clock" (rect 4 101 34 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 48 112)(line_width 1))
)
(port
(pt 144 72)
(output)
(text "q" (rect 0 0 4 12)(font "Arial" (font_size 8)))
(text "q" (rect 136 61 142 72)(font "Arial" (font_size 8)))
(line (pt 144 72)(pt 96 72)(line_width 1))
)
(drawing
(text "data" (rect 24 43 72 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "data" (rect 53 67 130 144)(font "Arial" (color 0 0 0)))
(text "clock" (rect 20 83 70 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clock" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
(text "q" (rect 97 43 200 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "q" (rect 88 67 182 144)(font "Arial" (color 0 0 0)))
(text " altera_soft_lvds " (rect 70 128 248 266)(font "Arial" ))
(line (pt 48 32)(pt 96 32)(line_width 1))
(line (pt 96 32)(pt 96 128)(line_width 1))
(line (pt 48 128)(pt 96 128)(line_width 1))
(line (pt 48 32)(pt 48 128)(line_width 1))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
(line (pt 50 92)(pt 50 116)(line_width 1))
(line (pt 95 52)(pt 95 76)(line_width 1))
(line (pt 94 52)(pt 94 76)(line_width 1))
(line (pt 0 0)(pt 144 0)(line_width 1))
(line (pt 144 0)(pt 144 144)(line_width 1))
(line (pt 0 144)(pt 144 144)(line_width 1))
(line (pt 0 0)(pt 0 144)(line_width 1))
)
)
atari_chips/pokeyv2/lvds_rx.cmp
component lvds_rx is
port (
data : in std_logic_vector(0 downto 0) := (others => 'X'); -- data
clock : in std_logic := 'X'; -- clock
q : out std_logic_vector(0 downto 0) -- q
);
end component lvds_rx;
atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 20.1 720 linux 2021.04.24.15:12:23
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# lvds_tx
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If lvds_tx is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 20.1 720 linux 2021.04.24.15:12:23
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="lvds_tx"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/lvds_tx/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/fiftyfivenm_ver/
mkdir -p ./libraries/altera/
mkdir -p ./libraries/lpm/
mkdir -p ./libraries/sgate/
mkdir -p ./libraries/altera_mf/
mkdir -p ./libraries/altera_lnsim/
mkdir -p ./libraries/fiftyfivenm/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v" -work fiftyfivenm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd" -work fiftyfivenm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd" -work fiftyfivenm
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/lvds_tx.vhd"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
atari_chips/pokeyv2/lvds_tx_sim/cadence/hdl.var
DEFINE WORK work
atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd
-- lvds_tx.vhd
-- Generated using ACDS version 20.1 720
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lvds_tx is
port (
tx_in : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_in.tx_in
tx_out : out std_logic_vector(0 downto 0) -- tx_out.tx_out
);
end entity lvds_tx;
architecture rtl of lvds_tx is
component altera_soft_lvds_tx_twD5CSXW is
port (
tx_in : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_in
tx_out : out std_logic_vector(0 downto 0) -- tx_out
);
end component altera_soft_lvds_tx_twD5CSXW;
begin
lvds_tx_inst : component altera_soft_lvds_tx_twD5CSXW
port map (
tx_in => tx_in, -- tx_in.tx_in
tx_out => tx_out -- tx_out.tx_out
);
end architecture rtl; -- of lvds_tx
atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/synopsys_sim.setup
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
lvds_tx: ./libraries/lvds_tx/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
fiftyfivenm_ver: ./libraries/fiftyfivenm_ver/
altera: ./libraries/altera/
lpm: ./libraries/lpm/
sgate: ./libraries/sgate/
altera_mf: ./libraries/altera_mf/
altera_lnsim: ./libraries/altera_lnsim/
fiftyfivenm: ./libraries/fiftyfivenm/
LIBRARY_SCAN = TRUE
atari_chips/pokeyv2/lvds_rx.qip
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_VERSION "20.1"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lvds_rx" -name MISC_FILE [file join $::quartus(qip_path) "lvds_rx.cmp"]
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_NAME "bHZkc19yeA=="
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjAuMQ=="
set_global_assignment -entity "lvds_rx" -library "lvds_rx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_NAME "YWx0ZXJhX3NvZnRfbHZkc19yeF90d0QyVHFmMw=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_DISPLAY_NAME "U29mdCBMVkRTIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_VERSION "MjAuMQ=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_DESCRIPTION "U29mdCBMVkRTIEludGVsIEZQR0EgSVAgdXNpbmcgY29yZSBsb2dpYyBlbGVtZW50cy4="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVWSUNFX1RZUEU=::U2luZ2xlIFN1cHBseQ==::UG93ZXIgU3VwcGx5IE1vZGU="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05BTF9NT0RF::Ulg=::RnVuY3Rpb25hbCBtb2Rl"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NIQU5ORUxT::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "V0lEVEg=::MQ==::TnVtYmVyIG9mIGNoYW5uZWxz"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFBNX1dJRFRI::MQ==::TFBNX1dJRFRI"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REVTRVJJQUxJWkFUSU9OX0ZBQ1RPUg==::MQ==::U0VSREVTIGZhY3Rvcg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX1BMTA==::T0ZG::VVNFX0VYVEVSTkFMX1BMTA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09NTU9OX1JYX1RYX1BMTA==::T0ZG::VXNlIGNvbW1vbiBQTEwocykgZm9yIHJlY2VpdmVycyBhbmQgdHJhbnNtaXR0ZXJzLg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX1NFTEZfUkVTRVRfT05fTE9TU19MT0NL::T0ZG::RW5hYmxlIHNlbGYtcmVzZXQgb24gbG9zcyBsb2NrIGluIFBMTA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QRVJJT0Q=::NTAwMA==::SU5DTE9DS19QRVJJT0Q="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9EQVRBX0FMSUdO::UE9SVF9VTlVTRUQ=::RW5hYmxlIGJpdHNsaXAgbW9kZQ=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04=::UE9SVF9VTlVTRUQ=::UE9SVF9SWF9DSEFOTkVMX0RBVEFfQUxJR04="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9EQVRBX0FMSUdOX0lOUFVU::T0ZG::QWRkIGV4dHJhIHJlZ2lzdGVyIGZvciByeF9kYXRhX2FsaWduIHBvcnQ="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9PVVRQVVQ=::T0ZG::UkVHSVNURVJFRF9PVVRQVVQ="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ=::MC4wMA==::T1VUQ0xPQ0tfUEhBU0VfU0hJRlQ="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q09SRUNMT0NLX0RJVklERV9CWQ==::Mg==::Q09SRUNMT0NLX0RJVklERV9CWQ=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19QSEFTRV9TSElGVA==::MA==::SU5DTE9DS19QSEFTRV9TSElGVA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJFRF9JTlBVVA==::T0ZG::UkVHSVNURVJFRF9JTlBVVA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0NPUkVDTE9DS19JTlBVVA==::T0ZG::RW5hYmxlIHR4X2NvcmVjbG9jayBwb3J0"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfUkVTT1VSQ0U=::QVVUTw==::T1VUQ0xPQ0tfUkVTT1VSQ0U="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "QlVGRkVSX0lNUExFTUVOVEFUSU9O::UkFN::QlVGRkVSX0lNUExFTUVOVEFUSU9O"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElOR19VSQ==::ZmFsc2U=::UmVtb3ZlIExWRFNfUlhfUkVHSVNURVIgYXR0cmlidXRlIGVtYmVkZGVkIGludG8gUlRMLg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TFZEU19SWF9SRUdfU0VUVElORw==::T0ZG::TFZEU19SWF9SRUdfU0VUVElORw=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUUFVUX0RBVEFfUkFURQ==::NzIw::RGF0YSByYXRlOg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU1QTEVNRU5UX0lOX0xFUw==::T04=::SU1QTEVNRU5UX0lOX0xFUw=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRF::NzIwLjAgTWJwcw==::REFUQV9SQVRF"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU5fTEVOR1RI::NDg=::Q0FSUllfQ0hBSU5fTEVOR1RI"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU=::MA==::RFBBX0lOSVRJQUxfUEhBU0VfVkFMVUU="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX0NPVU5U::MA==::RFBMTF9MT0NLX0NPVU5U"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RFBMTF9MT0NLX1dJTkRPVw==::MA==::RFBMTF9MT0NLX1dJTkRPVw=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19CT09TVA==::MA==::SU5DTE9DS19CT09TVA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg==::MA==::U0lNX0RQQV9ORVRfUFBNX1ZBUklBVElPTg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ=::MA==::U0lNX0RQQV9PVVRQVVRfQ0xPQ0tfUEhBU0VfU0hJRlQ="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q0FSUllfQ0hBSU4=::TUFOVUFM::Q0FSUllfQ0hBSU4="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ::T04=::Q1lDTE9ORUlJX000S19DT01QQVRJQklMSVRZ"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ::T0ZG::RU5BQkxFX0RQQV9BTElHTl9UT19SSVNJTkdfRURHRV9PTkxZ"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9DQUxJQlJBVElPTg==::T04=::RU5BQkxFX0RQQV9DQUxJQlJBVElPTg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg==::T0ZG::RU5BQkxFX0RQQV9JTklUSUFMX1BIQVNFX1NFTEVDVElPTg=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9NT0RF::T0ZG::RU5BQkxFX0RQQV9NT0RF"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04=::T0ZG::RU5BQkxFX0RQQV9QTExfQ0FMSUJSQVRJT04="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ0RSX01PREU=::T0ZG::RU5BQkxFX1NPRlRfQ0RSX01PREU="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "SU5DTE9DS19EQVRBX0FMSUdOTUVOVA==::RURHRV9BTElHTkVE::SU5DTE9DS19EQVRBX0FMSUdOTUVOVA=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TE9XX1BPV0VSX01PREU=::QVVUTw==::TE9XX1BPV0VSX01PREU="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ=::T0ZG::U0lNX0RQQV9JU19ORUdBVElWRV9QUE1fRFJJRlQ="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX0RQTExfUkFXUEVSUk9S::T0ZG::VVNFX0RQTExfUkFXUEVSUk9S"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "VVNFX05PX1BIQVNFX1NISUZU::T04=::VVNFX05PX1BIQVNFX1NISUZU"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "WF9PTl9CSVRTTElQ::T04=::WF9PTl9CSVRTTElQ"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RElGRkVSRU5USUFMX0RSSVZF::MA==::RElGRkVSRU5USUFMX0RSSVZF"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMS19MQVRFTkNZ::T0ZG::RU5BQkxFX0NMS19MQVRFTkNZ"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "TVVMVElfQ0xPQ0s=::T0ZG::TVVMVElfQ0xPQ0s="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfQUxJR05NRU5U::RURHRV9BTElHTkVE::T1VUQ0xPQ0tfQUxJR05NRU5U"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "T1VUQ0xPQ0tfTVVMVElQTFlfQlk=::MQ==::T1VUQ0xPQ0tfTVVMVElQTFlfQlk="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UExMX0NPTVBFTlNBVElPTl9NT0RF::QVVUTw==::UExMX0NPTVBFTlNBVElPTl9NT0RF"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "UFJFRU1QSEFTSVNfU0VUVElORw==::MA==::UFJFRU1QSEFTSVNfU0VUVElORw=="
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_COMPONENT_PARAMETER "Vk9EX1NFVFRJTkc=::MA==::Vk9EX1NFVFRJTkc="
set_global_assignment -library "lvds_rx" -name VHDL_FILE [file join $::quartus(qip_path) "lvds_rx.vhd"]
set_global_assignment -library "lvds_rx" -name VERILOG_FILE [file join $::quartus(qip_path) "lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v"]
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_VERSION "20.1"
set_global_assignment -entity "altera_soft_lvds_rx_twD2Tqf3" -library "lvds_rx" -name IP_TOOL_ENV "mwpim"
atari_chips/pokeyv2/lvds_rx.sip
set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_NAME "altera_soft_lvds"
set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_VERSION "20.1"
set_global_assignment -entity "lvds_rx" -library "lib_lvds_rx" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_lvds_rx" -name SPD_FILE [file join $::quartus(sip_path) "lvds_rx.spd"]
set_global_assignment -library "lib_lvds_rx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_rx_sim/lvds_rx.vhd"]
set_global_assignment -library "lib_lvds_rx" -name MISC_FILE [file join $::quartus(sip_path) "lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v"]
atari_chips/pokeyv2/lvds_rx.spd
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v"
type="VERILOG"
library="lvds_rx" />
<file path="lvds_rx_sim/lvds_rx.vhd" type="VHDL" />
<topLevel name="lvds_rx" />
<deviceFamily name="max10" />
</simPackage>
atari_chips/pokeyv2/lvds_rx.vhd
-- megafunction wizard: %Soft LVDS Intel FPGA IP v20.1%
-- GENERATION: XML
-- lvds_rx.vhd
-- Generated using ACDS version 20.1 720
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lvds_rx is
port (
data : in std_logic_vector(0 downto 0) := (others => '0'); -- data.data
clock : in std_logic := '0'; -- clock.clock
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity lvds_rx;
architecture rtl of lvds_rx is
component altera_soft_lvds_rx_twD2Tqf3 is
port (
data : in std_logic_vector(0 downto 0) := (others => 'X'); -- data
clock : in std_logic := 'X'; -- clock
q : out std_logic_vector(0 downto 0) -- q
);
end component altera_soft_lvds_rx_twD2Tqf3;
begin
lvds_rx_inst : component altera_soft_lvds_rx_twD2Tqf3
port map (
data => data, -- data.data
clock => clock, -- clock.clock
q => q -- q.q
);
end architecture rtl; -- of lvds_rx
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2021 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_soft_lvds" version="20.1" >
-- Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
-- Retrieval info: <generic name="DEVICE_TYPE" value="Single Supply" />
-- Retrieval info: <generic name="FUNCTIONAL_MODE" value="RX" />
-- Retrieval info: <generic name="NUMBER_OF_CHANNELS" value="1" />
-- Retrieval info: <generic name="DESERIALIZATION_FACTOR" value="1" />
-- Retrieval info: <generic name="USE_EXTERNAL_PLL_UI" value="false" />
-- Retrieval info: <generic name="INPUT_DATA_RATE" value="720.0" />
-- Retrieval info: <generic name="VALID_FREQ" value="200.00" />
-- Retrieval info: <generic name="ENABLE_RX_LOCKED_PORT_UI" value="false" />
-- Retrieval info: <generic name="ENABLE_TX_LOCKED_PORT_UI" value="false" />
-- Retrieval info: <generic name="ENABLE_PLL_ARESET_PORT_UI" value="true" />
-- Retrieval info: <generic name="ENABLE_PLL_TX_DATA_RESET_PORT_UI" value="false" />
-- Retrieval info: <generic name="ENABLE_PLL_RX_DATA_RESET_PORT_UI" value="false" />
-- Retrieval info: <generic name="COMMON_RX_TX_PLL_UI" value="false" />
-- Retrieval info: <generic name="PLL_SELF_RESET_ON_LOSS_LOCK_UI" value="false" />
-- Retrieval info: <generic name="PORT_RX_DATA_ALIGN_UI" value="false" />
-- Retrieval info: <generic name="PORT_RX_CHANNEL_DATA_ALIGN_UI" value="false" />
-- Retrieval info: <generic name="USE_CDA_RESET_UI" value="true" />
-- Retrieval info: <generic name="PORT_RX_DATA_ALIGN_RESET_UI" value="false" />
-- Retrieval info: <generic name="REGISTERED_DATA_ALIGN_INPUT_UI" value="false" />
-- Retrieval info: <generic name="DATA_ALIGN_ROLLOVER" value="4" />
-- Retrieval info: <generic name="REGISTERED_OUTPUT_UI" value="true" />
-- Retrieval info: <generic name="ENABLE_TX_OUTCLOCK_PORT_UI" value="true" />
-- Retrieval info: <generic name="OUTCLOCK_DIVIDE_BY_UI" value="1" />
-- Retrieval info: <generic name="OUTCLOCK_DUTY_CYCLE_UI" value="50" />
-- Retrieval info: <generic name="TX_OUTCLOCK_PHASE_SHIFT_UI" value="0.00" />
-- Retrieval info: <generic name="TX_INCLOCK_PHASE_SHIFT_UI" value="0.00" />
-- Retrieval info: <generic name="RX_INCLOCK_PHASE_SHIFT_UI" value="0.00" />
-- Retrieval info: <generic name="RX_OUTCLOCK_PHASE_SHIFT_UI" value="0.00" />
-- Retrieval info: <generic name="REGISTERED_INPUT_ENABLED_UI" value="false" />
-- Retrieval info: <generic name="REGISTERED_INPUT_UI" value="tx_coreclock" />
-- Retrieval info: <generic name="ENABLE_TX_CORECLOCK_PORT_UI" value="false" />
-- Retrieval info: <generic name="OUTCLOCK_RESOURCE_UI" value="Auto selection" />
-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_RAM_UI" value="false" />
-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_MUX_UI" value="false" />
-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_LE_UI" value="false" />
-- Retrieval info: <generic name="LVDS_RX_REG_SETTING_UI" value="false" />
-- Retrieval info: <generic name="IMPLEMENT_IN_LES" value="ON" />
-- Retrieval info: <generic name="CARRY_CHAIN_LENGTH" value="48" />
-- Retrieval info: <generic name="DPA_INITIAL_PHASE_VALUE" value="0" />
-- Retrieval info: <generic name="DPLL_LOCK_COUNT" value="0" />
-- Retrieval info: <generic name="DPLL_LOCK_WINDOW" value="0" />
-- Retrieval info: <generic name="INCLOCK_BOOST" value="0" />
-- Retrieval info: <generic name="SIM_DPA_NET_PPM_VARIATION" value="0" />
-- Retrieval info: <generic name="SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT" value="0" />
-- Retrieval info: <generic name="CARRY_CHAIN" value="MANUAL" />
-- Retrieval info: <generic name="CYCLONEII_M4K_COMPATIBILITY" value="ON" />
-- Retrieval info: <generic name="ENABLE_DPA_ALIGN_TO_RISING_EDGE_ONLY" value="OFF" />
-- Retrieval info: <generic name="ENABLE_DPA_CALIBRATION" value="ON" />
-- Retrieval info: <generic name="ENABLE_DPA_INITIAL_PHASE_SELECTION" value="OFF" />
-- Retrieval info: <generic name="ENABLE_DPA_MODE" value="OFF" />
-- Retrieval info: <generic name="ENABLE_DPA_PLL_CALIBRATION" value="OFF" />
-- Retrieval info: <generic name="ENABLE_SOFT_CDR_MODE" value="OFF" />
-- Retrieval info: <generic name="INCLOCK_DATA_ALIGNMENT" value="EDGE_ALIGNED" />
-- Retrieval info: <generic name="LOW_POWER_MODE" value="AUTO" />
-- Retrieval info: <generic name="SIM_DPA_IS_NEGATIVE_PPM_DRIFT" value="OFF" />
-- Retrieval info: <generic name="USE_DPLL_RAWPERROR" value="OFF" />
-- Retrieval info: <generic name="USE_NO_PHASE_SHIFT" value="ON" />
-- Retrieval info: <generic name="X_ON_BITSLIP" value="ON" />
-- Retrieval info: <generic name="DIFFERENTIAL_DRIVE" value="0" />
-- Retrieval info: <generic name="ENABLE_CLK_LATENCY" value="OFF" />
-- Retrieval info: <generic name="MULTI_CLOCK" value="OFF" />
-- Retrieval info: <generic name="OUTCLOCK_ALIGNMENT" value="EDGE_ALIGNED" />
-- Retrieval info: <generic name="PLL_COMPENSATION_MODE" value="AUTO" />
-- Retrieval info: <generic name="PREEMPHASIS_SETTING" value="0" />
-- Retrieval info: <generic name="VOD_SETTING" value="0" />
-- Retrieval info: </instance>
-- IPFS_FILES : lvds_rx.vho
-- RELATED_FILES: lvds_rx.vhd, altera_soft_lvds_rx_twD2Tqf3.v
atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 20.1 720 linux 2021.04.24.15:13:51
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# lvds_rx
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If lvds_rx is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "lvds_rx"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/20.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/fiftyfivenm_ver
vmap fiftyfivenm_ver ./libraries/fiftyfivenm_ver
ensure_lib ./libraries/altera
vmap altera ./libraries/altera
ensure_lib ./libraries/lpm
vmap lpm ./libraries/lpm
ensure_lib ./libraries/sgate
vmap sgate ./libraries/sgate
ensure_lib ./libraries/altera_mf
vmap altera_mf ./libraries/altera_mf
ensure_lib ./libraries/altera_lnsim
vmap altera_lnsim ./libraries/altera_lnsim
ensure_lib ./libraries/fiftyfivenm
vmap fiftyfivenm ./libraries/fiftyfivenm
ensure_lib ./libraries/lvds_rx
vmap lvds_rx ./libraries/lvds_rx
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v" -work fiftyfivenm_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd" -work fiftyfivenm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd" -work fiftyfivenm
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v" -work lvds_rx
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/lvds_rx.vhd"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
atari_chips/pokeyv2/lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v
//lpm_ff CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" LPM_WIDTH=1 clock data q
//VERSION_BEGIN 20.1 cbx_lpm_ff 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//synthesis_resources = lut 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_soft_lvds_rx_twD2Tqf3
(
clock,
data,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input [0:0] data;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] ff_dffe;
wire enable;
// synopsys translate_off
initial
ff_dffe = 0;
// synopsys translate_on
always @ ( posedge clock)
if (enable == 1'b1) ff_dffe <= data;
assign
enable = 1'b1,
q = ff_dffe;
endmodule //altera_soft_lvds_rx_twD2Tqf3
//VALID FILE
atari_chips/pokeyv2/lvds_rx_sim/cadence/cds.lib
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE lvds_rx ./libraries/lvds_rx/
DEFINE altera_ver ./libraries/altera_ver/
DEFINE lpm_ver ./libraries/lpm_ver/
DEFINE sgate_ver ./libraries/sgate_ver/
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/
DEFINE altera ./libraries/altera/
DEFINE lpm ./libraries/lpm/
DEFINE sgate ./libraries/sgate/
DEFINE altera_mf ./libraries/altera_mf/
DEFINE altera_lnsim ./libraries/altera_lnsim/
DEFINE fiftyfivenm ./libraries/fiftyfivenm/
atari_chips/pokeyv2/lvds_rx_sim/cadence/cds_libs/lvds_rx.cds.lib
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./../libraries/work/
DEFINE altera_ver ./../libraries/altera_ver/
DEFINE lpm_ver ./../libraries/lpm_ver/
DEFINE sgate_ver ./../libraries/sgate_ver/
DEFINE altera_mf_ver ./../libraries/altera_mf_ver/
DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/
DEFINE altera ./../libraries/altera/
DEFINE lpm ./../libraries/lpm/
DEFINE sgate ./../libraries/sgate/
DEFINE altera_mf ./../libraries/altera_mf/
DEFINE altera_lnsim ./../libraries/altera_lnsim/
DEFINE fiftyfivenm ./../libraries/fiftyfivenm/
DEFINE lvds_rx ./../libraries/lvds_rx/
atari_chips/pokeyv2/lvds_rx_sim/cadence/hdl.var
DEFINE WORK work
atari_chips/pokeyv2/lvds_rx_sim/cadence/ncsim_setup.sh
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 20.1 720 linux 2021.04.24.15:13:51
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# lvds_rx
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
#
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