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--Copyright (C) 2024 Intel Corporation. All rights reserved.
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--Your use of Intel Corporation's design tools, logic functions
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|
--and other software and tools, and any partner logic
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|
--functions, and any output files from any of the foregoing
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|
--(including device programming or simulation files), and any
|
|
--associated documentation or information are expressly subject
|
|
--to the terms and conditions of the Intel Program License
|
|
--Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
--the Intel FPGA IP License Agreement, or other applicable license
|
|
--agreement, including, without limitation, that your use is for
|
|
--the sole purpose of programming logic devices manufactured by
|
|
--Intel and sold by Intel or its authorized distributors. Please
|
|
--refer to the applicable agreement for further details, at
|
|
--https://fpgasoftware.intel.com/eula.
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|
|
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component fir_buffer
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|
PORT
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|
(
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data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
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rdclock : IN STD_LOGIC ;
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|
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
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|
wrclock : IN STD_LOGIC := '1';
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|
wren : IN STD_LOGIC := '0';
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|
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
|
);
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|
end component;
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