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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.all;
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LIBRARY work;
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-- takes about 5-6 cycles per read (depending on family)
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-- So at 116MHz can service all 8 clients at >2MHz - if they all request at once
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ENTITY flash_controller IS
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GENERIC
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(
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addr_bits: integer := 16
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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CLK_SLOW : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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-- Request from device 1 (cpu)
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flash_req1_addr_config : IN STD_LOGIC; -- 1 access config, 0 access main flash
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flash_req1_data_in : IN STD_LOGIC_VECTOR(31 downto 0);
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flash_req1_write_n: IN STD_LOGIC;
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flash_req_request : IN STD_LOGIC_VECTOR(7 downto 0);
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flash_req_complete : OUT STD_LOGIC_VECTOR(7 downto 0);
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flash_req_complete_slow : OUT STD_LOGIC_VECTOR(7 downto 0);
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flash_req1_addr : IN STD_LOGIC_VECTOR(addr_bits-1 downto 0) := (others=>'0');
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flash_req2_addr : IN STD_LOGIC_VECTOR(12 downto 0) := (others=>'0');
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flash_req3_addr : IN STD_LOGIC_VECTOR(12 downto 0) := (others=>'0');
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flash_req4_addr : IN STD_LOGIC_VECTOR(addr_bits-1 downto 0) := (others=>'0');
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flash_req5_addr : IN STD_LOGIC_VECTOR(addr_bits-1 downto 0) := (others=>'0');
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flash_req6_addr : IN STD_LOGIC_VECTOR(12 downto 0) := (others=>'0');
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flash_req7_addr : IN STD_LOGIC_VECTOR(12 downto 0) := (others=>'0');
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flash_req8_addr : IN STD_LOGIC_VECTOR(12 downto 0) := (others=>'0');
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-- Output
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flash_data_out : OUT STD_LOGIC_VECTOR(31 downto 0);
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flash_data_out_slow : OUT STD_LOGIC_VECTOR(31 downto 0)
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);
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END flash_controller;
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ARCHITECTURE vhdl OF flash_controller IS
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component flash is
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port (
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clock : in std_logic := '0'; -- clk.clk
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avmm_csr_addr : in std_logic := '0'; -- csr.address
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avmm_csr_read : in std_logic := '0'; -- .read
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avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
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avmm_csr_write : in std_logic := '0'; -- .write
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avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
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avmm_data_addr : in std_logic_vector(addr_bits-1 downto 0) := (others => '0'); -- data.address
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avmm_data_read : in std_logic := '0'; -- .read
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avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
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avmm_data_write : in std_logic := '0'; -- .write
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avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata
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avmm_data_waitrequest : out std_logic; -- .waitrequest
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avmm_data_readdatavalid : out std_logic; -- .readdatavalid
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avmm_data_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
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reset_n : in std_logic := '0' -- nreset.reset_n
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);
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end component;
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signal flash_config_addr : std_logic;
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signal flash_config_read : std_logic;
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signal flash_config_di : std_logic_vector(31 downto 0);
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signal flash_config_write : std_logic;
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signal flash_config_do : std_logic_vector(31 downto 0);
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signal flash_data_addr : std_logic_vector(addr_bits-1 downto 0);
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signal flash_data_read : std_logic;
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signal flash_data_di : std_logic_vector(31 downto 0);
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signal flash_data_write : std_logic;
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signal flash_data_do : std_logic_vector(31 downto 0);
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signal flash_data_waitrequest : std_logic;
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signal flash_data_readvalid : std_logic;
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signal flash_data_burstcount : std_logic_vector(1 downto 0);
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signal state_reg : std_logic_vector(3 downto 0);
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signal state_next : std_logic_vector(3 downto 0);
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constant state_idle : std_logic_vector(3 downto 0) := "0000";
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constant state_read : std_logic_vector(3 downto 0) := "0001";
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constant state_write : std_logic_vector(3 downto 0) := "0010";
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constant state_read_wait : std_logic_vector(3 downto 0) := "0011";
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constant state_delay : std_logic_vector(3 downto 0) := "0100";
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constant state_delay2 : std_logic_vector(3 downto 0) := "0101";
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constant state_delay3 : std_logic_vector(3 downto 0) := "0110";
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constant state_delay4 : std_logic_vector(3 downto 0) := "0111";
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constant state_write_wait : std_logic_vector(3 downto 0) := "1000";
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signal request_addr_reg : std_logic_vector(addr_bits-1 downto 0);
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signal request_addr_next : std_logic_vector(addr_bits-1 downto 0);
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signal request_di_reg : std_logic_vector(31 downto 0);
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signal request_di_next : std_logic_vector(31 downto 0);
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signal device_reg : std_logic;
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signal device_next : std_logic;
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signal output_reg : std_logic_vector(7 downto 0);
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signal output_next : std_logic_vector(7 downto 0);
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signal robin_reg : std_logic_vector(7 downto 0);
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signal robin_next : std_logic_vector(7 downto 0);
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signal complete : std_logic;
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signal update_robin : std_logic;
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signal flash_read_next : std_logic;
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signal flash_read_reg : std_logic;
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signal flash_readvalid : std_logic;
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signal flash_write_next : std_logic;
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signal flash_write_reg : std_logic;
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signal flash_waitrequest : std_logic;
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signal flash_do : std_logic_vector(31 downto 0);
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signal flash_do_next : std_logic_vector(31 downto 0);
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signal flash_do_reg : std_logic_vector(31 downto 0);
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signal flash_complete_next : std_logic_vector(7 downto 0);
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signal flash_complete_reg : std_logic_vector(7 downto 0);
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signal flash_do_slow_next : std_logic_vector(31 downto 0);
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signal flash_do_slow_reg : std_logic_vector(31 downto 0);
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signal flash_complete_slow_next : std_logic_vector(7 downto 0);
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signal flash_complete_slow_reg : std_logic_vector(7 downto 0);
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BEGIN
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flash1 : flash
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port map
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(
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clock => clk,
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avmm_csr_addr => request_addr_reg(0),
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avmm_csr_read => flash_config_read,
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avmm_csr_writedata => request_di_reg,
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avmm_csr_write => flash_config_write,
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avmm_csr_readdata => flash_config_do,
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avmm_data_addr => request_addr_reg,
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avmm_data_read => flash_data_read,
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avmm_data_writedata => request_di_reg,
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avmm_data_write => flash_data_write,
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avmm_data_readdata => flash_data_do,
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avmm_data_waitrequest => flash_data_waitrequest,
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avmm_data_readdatavalid => flash_data_readvalid,
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--avmm_data_burstcount => "10",
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avmm_data_burstcount => "01",
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reset_n => reset_n
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);
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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state_reg <= state_idle;
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request_addr_reg <= (others=>'0');
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request_di_reg <= (others=>'0');
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device_reg <= '0';
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output_reg <= (others=>'0');
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robin_reg <= "10000000";
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flash_do_reg <= (others=>'0');
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flash_complete_reg <= (others=>'0');
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flash_write_reg <= '0';
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flash_read_reg <= '0';
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elsif (clk'event and clk='1') then
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state_reg <= state_next;
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request_addr_reg <= request_addr_next;
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request_di_reg <= request_di_next;
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device_reg <= device_next;
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output_reg <= output_next;
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robin_reg <= robin_next;
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flash_do_reg <= flash_do_next;
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flash_complete_reg <= flash_complete_next;
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flash_write_reg <= flash_write_next;
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flash_read_reg <= flash_read_next;
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end if;
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end process;
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process(clk_slow,reset_n)
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begin
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if (reset_n='0') then
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flash_complete_slow_reg <= (others=>'0');
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flash_do_slow_reg <= (others=>'0');
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elsif (clk_slow'event and clk_slow='1') then
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flash_complete_slow_reg <= flash_complete_slow_next;
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flash_do_slow_reg <= flash_do_slow_next;
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end if;
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end process;
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-- state machine
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-- Requests handled round robin
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-- TODO burst!
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process(state_reg,request_addr_reg,request_di_reg,device_reg,output_reg,
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robin_reg,
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flash_req_request,
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flash_req1_addr, flash_req1_data_in, flash_req1_write_n, flash_req1_addr_config,
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flash_req2_addr, flash_req3_addr, flash_req4_addr,
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flash_req5_addr, flash_req6_addr, flash_req7_addr, flash_req8_addr,
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flash_readvalid, flash_waitrequest,
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flash_write_reg, flash_read_reg,
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complete,
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update_robin
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)
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variable addr : std_logic_vector(addr_bits-1 downto 0);
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variable device : std_logic;
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variable request: std_logic;
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begin
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state_next <= state_reg;
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request_addr_next <= request_addr_reg;
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request_di_next <= request_di_reg;
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device_next <= device_reg;
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output_next <= output_reg;
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robin_next <= robin_reg;
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complete <= '0';
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flash_read_next <= flash_read_reg;
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flash_write_next <= flash_write_reg;
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device := '0';
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addr := (others=>'0');
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case robin_reg is
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when x"01" =>
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addr := flash_req1_addr;
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device := flash_req1_addr_config;
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when x"02" =>
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addr(12 downto 0) := flash_req2_addr;
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when x"04" =>
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addr(12 downto 0) := flash_req3_addr;
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when x"08" =>
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addr := flash_req4_addr;
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when x"10" =>
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addr := flash_req5_addr;
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when x"20" =>
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addr(12 downto 0) := flash_req6_addr;
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when x"40" =>
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addr(12 downto 0) := flash_req7_addr;
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when others =>
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addr(12 downto 0) := flash_req8_addr;
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end case;
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update_robin <= complete;
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if (update_robin='1') then
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robin_next <= robin_reg(6 downto 0)&robin_reg(7);
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end if;
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case state_reg is
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when state_idle=>
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if (or_reduce(robin_reg and flash_req_request)='1') then
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request_addr_next <= addr;
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request_di_next <= flash_req1_data_in;
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if (robin_reg(0)='1' and flash_req1_write_n='0') then --write
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state_next <= state_write;
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else
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state_next <= state_read;
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end if;
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output_next <= robin_reg;
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device_next <= device;
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else
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update_robin <= '1';
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end if;
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when state_read=>
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flash_read_next <= '1';
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state_next <= state_read_wait;
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when state_read_wait =>
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if (flash_waitrequest = '0') then
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flash_read_next <= '0';
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end if;
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if (flash_readvalid = '1') then
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complete <= '1';
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state_next <= state_delay;
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end if;
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when state_write=>
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flash_write_next <= '1';
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state_next <= state_write_wait;
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when state_write_wait=>
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if (flash_waitrequest='0') then
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flash_write_next <= '0';
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complete <= '1';
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state_next <= state_delay;
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end if;
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when state_delay=>
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state_next <= state_delay2; -- client sees complete here, allow client to drop request line before we take next
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when state_delay2=>
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state_next <= state_delay3; -- without a 3rd delay we never get readdatavalid!!
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when state_delay3=>
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state_next <= state_delay4;
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when state_delay4=>
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if (flash_waitrequest='0') then
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state_next <= state_idle;
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end if;
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when others=>
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state_next <= state_idle;
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end case;
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end process;
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-- mux on selected device
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process(device_reg, flash_data_do, flash_config_do,
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flash_write_reg,flash_read_reg,flash_data_readvalid,flash_data_waitrequest)
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begin
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flash_do <= (others=>'0');
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flash_config_read <= '0';
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flash_config_write <= '0';
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flash_data_read <= '0';
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flash_data_write <= '0';
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flash_readvalid <= '0';
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flash_waitrequest <= '0';
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if (device_reg='1') then --config
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flash_do <= flash_config_do;
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flash_config_read <= flash_read_reg;
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flash_config_write <= flash_write_reg;
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flash_readvalid <= '1';
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elsif (device_reg='0') then --main
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flash_do <= flash_data_do;
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flash_data_read <= flash_read_reg;
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flash_data_write <= flash_write_reg;
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flash_readvalid <= flash_data_readvalid;
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flash_waitrequest <= flash_data_waitrequest;
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end if;
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end process;
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-- register complete
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flash_complete_next <= output_reg and (complete&complete&complete&complete&complete&complete&complete&complete);
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flash_complete_slow_next <= flash_complete_next or flash_complete_reg;
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process(flash_do_reg,flash_do,complete)
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begin
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flash_do_next <= flash_do_reg;
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flash_do_slow_next <= flash_do_reg;
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if (complete='1') then
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flash_do_next <= flash_do;
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flash_do_slow_next <= flash_do;
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end if;
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end process;
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-- mux on who requested
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flash_req_complete <= flash_complete_reg;
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flash_req_complete_slow <= flash_complete_slow_reg;
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-- outputs
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flash_data_out <= flash_do_reg;
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flash_data_out_slow <= flash_do_slow_reg;
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end vhdl;
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