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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.all;
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use work.AudioTypes.all;
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LIBRARY work;
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ENTITY mixer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE_CYCLE : IN STD_LOGIC;
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DETECT_RIGHT : IN STD_LOGIC;
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POST_DIVIDE : IN STD_LOGIC_VECTOR(7 downto 0);
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FANCY_ENABLE : IN STD_LOGIC;
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GTIA_EN : IN STD_LOGIC_VECTOR(3 downto 0);
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ADC_EN : IN STD_LOGIC_VECTOR(3 downto 0);
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CH0 : IN UNSIGNED(15 downto 0); --pokey0
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CH1 : IN UNSIGNED(15 downto 0); --pokey1
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CH2 : IN UNSIGNED(15 downto 0); --pokey2
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CH3 : IN UNSIGNED(15 downto 0); --pokey3
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CH4 : IN UNSIGNED(15 downto 0); --sample0
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CH5 : IN UNSIGNED(15 downto 0); --sample1
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CH6 : IN UNSIGNED(15 downto 0); --sid0
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CH7 : IN UNSIGNED(15 downto 0); --sid1
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CH8 : IN UNSIGNED(15 downto 0); --psg0
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CH9 : IN UNSIGNED(15 downto 0); --psg1
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CHA : IN UNSIGNED(15 downto 0); --gtia0
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CHB : IN UNSIGNED(15 downto 0); --adc
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AUDIO_0_UNSIGNED : out unsigned(15 downto 0);
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AUDIO_1_UNSIGNED : out unsigned(15 downto 0);
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AUDIO_2_UNSIGNED : out unsigned(15 downto 0);
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AUDIO_3_UNSIGNED : out unsigned(15 downto 0)
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);
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END mixer;
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ARCHITECTURE vhdl OF mixer IS
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-- DETECT RIGHT PLAYING
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signal RIGHT_PLAYING_RECENTLY : std_logic;
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signal RIGHT_NEXT : std_logic;
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signal RIGHT_REG : std_logic;
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signal RIGHT_PLAYING_COUNT_NEXT : unsigned(23 downto 0);
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signal RIGHT_PLAYING_COUNT_REG : unsigned(23 downto 0);
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-- sums
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signal audio0_reg : unsigned(15 downto 0);
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signal audio0_next : unsigned(15 downto 0);
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signal audio1_reg : unsigned(15 downto 0);
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signal audio1_next : unsigned(15 downto 0);
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signal audio2_reg : unsigned(15 downto 0);
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signal audio2_next : unsigned(15 downto 0);
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signal audio3_reg : unsigned(15 downto 0);
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signal audio3_next : unsigned(15 downto 0);
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signal acc_reg : unsigned(19 downto 0);
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signal acc_next : unsigned(19 downto 0);
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signal secondBatch_reg : std_logic;
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signal secondBatch_next : std_logic;
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signal state_reg : unsigned(3 downto 0);
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signal state_next : unsigned(3 downto 0);
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constant state_pokeyA_L : unsigned(3 downto 0) := "0000";
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constant state_pokeyB_L : unsigned(3 downto 0) := "0001";
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constant state_sample_L : unsigned(3 downto 0) := "0010";
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constant state_sid_L : unsigned(3 downto 0) := "0011";
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constant state_psg_L : unsigned(3 downto 0) := "0100";
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constant state_adc_L : unsigned(3 downto 0) := "0101";
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constant state_gtia_L : unsigned(3 downto 0) := "0110";
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constant state_clear_L : unsigned(3 downto 0) := "0111";
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constant state_pokeyA_R : unsigned(3 downto 0) := "1000";
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constant state_pokeyB_R : unsigned(3 downto 0) := "1001";
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constant state_sample_R : unsigned(3 downto 0) := "1010";
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constant state_sid_R : unsigned(3 downto 0) := "1011";
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constant state_psg_R : unsigned(3 downto 0) := "1100";
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constant state_adc_R : unsigned(3 downto 0) := "1101";
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constant state_gtia_R : unsigned(3 downto 0) := "1110";
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constant state_clear_R : unsigned(3 downto 0) := "1111";
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signal channelsel : std_logic_vector(3 downto 0);
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signal volume : unsigned(15 downto 0);
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signal saturated : unsigned(15 downto 0);
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signal ready : std_logic;
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signal write_0 : std_logic;
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signal write_1 : std_logic;
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signal write_2 : std_logic;
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signal write_3 : std_logic;
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BEGIN
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-- DETECT IF RIGHT CHANNEL PLAYING
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-- TODO: into another entity
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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RIGHT_REG <= '0';
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RIGHT_PLAYING_COUNT_REG <= (others=>'0');
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audio0_reg <= (others=>'0');
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audio1_reg <= (others=>'0');
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audio2_reg <= (others=>'0');
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audio3_reg <= (others=>'0');
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acc_reg <= (others=>'0');
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secondBatch_reg <= '0';
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state_reg <= state_pokeyA_L;
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elsif (clk'event and clk='1') then
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RIGHT_REG <= RIGHT_NEXT;
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RIGHT_PLAYING_COUNT_REG <= RIGHT_PLAYING_COUNT_NEXT;
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audio0_reg <= audio0_next;
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audio1_reg <= audio1_next;
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audio2_reg <= audio2_next;
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audio3_reg <= audio3_next;
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acc_reg <= acc_next;
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secondBatch_reg <= secondBatch_next;
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state_reg <= state_next;
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end if;
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end process;
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process(RIGHT_NEXT,RIGHT_REG,ENABLE_CYCLE,RIGHT_PLAYING_RECENTLY,RIGHT_PLAYING_COUNT_REG)
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begin
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RIGHT_PLAYING_COUNT_NEXT <= RIGHT_PLAYING_COUNT_REG;
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if (ENABLE_CYCLE='1' and RIGHT_PLAYING_RECENTLY='1') then
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RIGHT_PLAYING_COUNT_NEXT <= RIGHT_PLAYING_COUNT_REG-1;
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end if;
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if (RIGHT_NEXT/=RIGHT_REG) then
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RIGHT_PLAYING_COUNT_NEXT <= (others=>'1');
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end if;
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end process;
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RIGHT_PLAYING_RECENTLY <= or_reduce(std_logic_vector(RIGHT_PLAYING_COUNT_REG));
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process(state_reg,secondBatch_reg,acc_reg,volume,ready,
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POST_DIVIDE,FANCY_ENABLE,RIGHT_PLAYING_RECENTLY,DETECT_RIGHT,RIGHT_REG,SATURATED,GTIA_EN,ADC_EN)
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variable postdivide : std_logic_vector(1 downto 0);
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variable presaturate : unsigned(19 downto 0);
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variable leftOnRight : std_logic;
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variable clearAcc : std_logic;
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variable R : std_logic;
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variable pdsel : std_logic_vector(1 downto 0);
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begin
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state_next <= state_reg;
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secondBatch_next <= secondBatch_reg;
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acc_next <= acc_reg;
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RIGHT_NEXT <= RIGHT_REG;
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leftOnRight := not(FANCY_ENABLE) or (not(RIGHT_PLAYING_RECENTLY) AND DETECT_RIGHT);
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clearAcc := '0';
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write_0 <= '0';
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write_1 <= '0';
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write_2 <= '0';
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write_3 <= '0';
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R := '0';
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channelsel <= (others=>'0');
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saturated <= (others=>'0');
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if (ready='1') then
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case state_reg is
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when state_pokeyA_L =>
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channelsel <= x"0";
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state_next <= state_pokeyB_L;
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when state_pokeyB_L =>
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channelsel <= x"2";
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state_next <= state_sample_L;
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when state_sample_L =>
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channelsel <= x"4";
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state_next <= state_sid_L;
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when state_sid_L =>
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channelsel <= x"6";
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state_next <= state_psg_L;
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when state_psg_L =>
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channelsel <= x"8";
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state_next <= state_adc_L;
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when state_adc_L =>
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channelsel <= x"b";
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write_0 <= not(adc_en(0));
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write_1 <= not(adc_en(0)) and leftOnRight;
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write_2 <= not(adc_en(2));
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write_3 <= not(adc_en(2)) and leftOnRight;
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state_next <= state_gtia_L;
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when state_gtia_L =>
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channelsel <= x"a";
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write_0 <= not(gtia_en(0));
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write_1 <= not(gtia_en(0)) and leftOnRight;
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write_2 <= not(gtia_en(2));
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write_3 <= not(gtia_en(2)) and leftOnRight;
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state_next <= state_clear_L;
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when state_clear_L =>
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clearAcc := '1';
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write_0 <= gtia_en(0);
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write_1 <= gtia_en(0) and leftOnRight;
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write_2 <= gtia_en(2);
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write_3 <= gtia_en(2) and leftOnRight;
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state_next <= state_pokeyA_R;
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when state_pokeyA_R =>
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channelsel <= x"1";
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R := '1';
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state_next <= state_pokeyB_R;
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when state_pokeyB_R =>
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channelsel <= x"3";
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R := '1';
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state_next <= state_sample_R;
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when state_sample_R =>
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channelsel <= x"5";
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R := '1';
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state_next <= state_sid_R;
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when state_sid_R =>
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channelsel <= x"7";
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R := '1';
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state_next <= state_psg_R;
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when state_psg_R =>
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channelsel <= x"9";
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R := '1';
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state_next <= state_adc_R;
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when state_adc_R =>
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channelsel <= x"b";
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R := '1';
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write_1 <= not(adc_en(1)) and not(leftOnRight);
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write_3 <= not(adc_en(3)) and not(leftOnRight);
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-- NEEDS DOING WITHOUT ADC GTIA mixed, since those plays on all channels!!
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RIGHT_NEXT <= xor_reduce(std_logic_vector(saturated));
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state_next <= state_gtia_R;
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when state_gtia_R =>
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channelsel <= x"a";
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R := '1';
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write_1 <= not(gtia_en(1)) and not(leftOnRight);
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write_3 <= not(gtia_en(3)) and not(leftOnRight);
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state_next <= state_clear_R;
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when state_clear_R =>
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clearAcc := '1';
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R := '1';
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write_1 <= gtia_en(1) and not(leftOnRight);
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write_3 <= gtia_en(3) and not(leftOnRight);
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state_next <= state_pokeyA_L;
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secondBatch_next <= not(secondBatch_reg);
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when others =>
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state_next <= state_pokeyA_L;
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end case;
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pdsel(1) := secondBatch_reg;
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pdsel(0) := R;
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case pdsel is
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when "00" =>
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postdivide:=POST_DIVIDE(1 downto 0);
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when "01" =>
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postdivide:=POST_DIVIDE(3 downto 2);
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when "10" =>
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postdivide:=POST_DIVIDE(5 downto 4);
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when "11" =>
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postdivide:=POST_DIVIDE(7 downto 6);
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when others =>
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end case;
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case postdivide is
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when "00" =>
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presaturate := resize(acc_reg(19 downto 0),20);
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when "01" =>
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presaturate := resize(acc_reg(19 downto 1),20);
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when "10" =>
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presaturate := resize(acc_reg(19 downto 2),20);
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when "11" =>
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presaturate := resize(acc_reg(19 downto 3),20);
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when others =>
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end case;
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if or_reduce(std_logic_vector(presaturate(19 downto 16)))='1' then
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saturated <= (others=>'1');
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else
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saturated <= presaturate(15 downto 0);
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end if;
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if (clearAcc='1') then
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acc_next <= (others=>'0');
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else
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acc_next <= acc_reg + resize(volume,19);
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end if;
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end if;
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end process;
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process(state_reg,channelsel,
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ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,cha,chb
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)
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begin
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volume <= (others=>'0');
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ready <= '1';
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case channelsel is
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when x"0" =>
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volume <= ch0;
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when x"1" =>
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volume <= ch1;
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when x"2" =>
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volume <= ch2;
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when x"3" =>
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volume <= ch3;
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when x"4" =>
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volume <= ch4;
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when x"5" =>
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volume <= ch5;
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when x"6" =>
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volume <= ch6;
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when x"7" =>
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volume <= ch7;
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when x"8" =>
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volume <= ch8;
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when x"9" =>
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volume <= ch9;
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when x"a" =>
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volume <= cha;
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when x"b" =>
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volume <= chb;
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when others =>
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end case;
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end process;
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process(saturated,secondBatch_reg,write_0,write_1,write_2,write_3,audio0_reg,audio1_reg,audio2_reg,audio3_reg)
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begin
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audio0_next <= audio0_reg;
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audio1_next <= audio1_reg;
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audio2_next <= audio2_reg;
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audio3_next <= audio3_reg;
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if (write_0='1' and secondBatch_reg='0') then
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audio0_next <= saturated;
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end if;
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if (write_1='1' and secondBatch_reg='0') then
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audio1_next <= saturated;
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end if;
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if (write_2='1' and secondBatch_reg='1') then
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audio2_next <= saturated;
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end if;
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if (write_3='1' and secondBatch_reg='1') then
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audio3_next <= saturated;
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end if;
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end process;
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-- output
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AUDIO_0_UNSIGNED <= audio0_reg;
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AUDIO_1_UNSIGNED <= audio1_reg;
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AUDIO_2_UNSIGNED <= audio2_reg;
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AUDIO_3_UNSIGNED <= audio3_reg;
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end vhdl;
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