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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 19:35:48 June 01, 2018
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# pokeymax_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name TOP_LEVEL_ENTITY pokeymax
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:48 JUNE 01, 2018"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_location_assignment PIN_B3 -to PHI2 #B3,LVLA4,PHI
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set_location_assignment PIN_A3 -to D[7] #A3,LVLA3,D7
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set_location_assignment PIN_B2 -to D[6] #B2,LVLA2,D6
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set_location_assignment PIN_A2 -to D[5] #A2,LVLA1,LVL5,D5
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set_location_assignment PIN_B1 -to D[4] #B1,LVLA0,D4
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set_location_assignment PIN_A4 -to D[3] #A4,LVLA5,D3
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set_location_assignment PIN_A11 -to D[2] #A11,LVLA17,D2
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set_location_assignment PIN_B10 -to D[1] #B10,LVLA16,D1
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set_location_assignment PIN_A10 -to D[0] #A10,LVLA15,D0
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set_location_assignment PIN_A5 -to CS0_N #A5,LVLA,CS0_N
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set_location_assignment PIN_B6 -to CS1 #B6,LVLA10,CS1
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set_location_assignment PIN_B4 -to IRQ #B4,LVLA6,IRQ_N
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set_location_assignment PIN_B5 -to W_N #B5,LVLA8,RW
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set_location_assignment PIN_A7 -to SID #A7,LVLA11,SID
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set_location_assignment PIN_A9 -to SOD #A9,LVLA14,SOD
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set_location_assignment PIN_A8 -to ACLK #A8,LVLA13,ACLK
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set_location_assignment PIN_B7 -to BCLK #B7,LVLA12,BCLK
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set_location_assignment PIN_B11 -to A[0] #B11,LVLA18,A0
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set_location_assignment PIN_B12 -to A[1] #B12,LVLA20,A1
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set_location_assignment PIN_C13 -to A[2] #C13,LVLA22,A2
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set_location_assignment PIN_A6 -to A[3] #A6,LVLA9,A3
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set_location_assignment PIN_N2 -to PADDLE[5] #11=N2 POT7 p5
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set_location_assignment PIN_N3 -to PADDLE[1] #15=N3 POT6 p1
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set_location_assignment PIN_N4 -to PADDLE[4] #10=N4 POT5 p4
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set_location_assignment PIN_N5 -to PADDLE[7] #9 =N5 POT4 p7
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set_location_assignment PIN_N6 -to PADDLE[6] #8 =N6 POT3 p6
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set_location_assignment PIN_N7 -to PADDLE[0] #14=N7 POT2 p0
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set_location_assignment PIN_N8 -to PADDLE[3] #13=N8 POT1 p3
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set_location_assignment PIN_N9 -to PADDLE[2] #12=N9 POT0 p2
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set_location_assignment PIN_M2 -to POTRESET_N #POTRESET - M2
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set_location_assignment PIN_C11 -to AUD[1] #AUD1 - C11
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set_location_assignment PIN_D11 -to AUD[3] #AUD3 - D11
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set_location_assignment PIN_C12 -to AUD[2] #AUD2 - C12
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set_location_assignment PIN_D12 -to AUD[4] #AUD4 - D12
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set_location_assignment PIN_M3 -to IOX_RST #IOX_RST - M3
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set_location_assignment PIN_M4 -to IOX_SDA #IOX_SDA - M4
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set_location_assignment PIN_M5 -to IOX_SCL #IOX_SCL - M5
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set_location_assignment PIN_M7 -to IOX_INT #IOX_INT - M7
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set_location_assignment PIN_G9 -to CLK_SLOW #CLK2 - G9
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set_location_assignment PIN_H8 -to CLK_OUT #OUT - H8
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set_location_assignment PIN_H6 -to CLK0 #CLK0 - H6
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set_location_assignment PIN_H4 -to CLK1 #CLK1 - H4
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set_location_assignment PIN_A12 -to EXT[1] #A12,LVLA19,EXT3
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set_location_assignment PIN_B13 -to EXT[2] #B13,LVLA21,EXT2
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set_location_assignment PIN_D13 -to EXT[3] #D13,LVLA23,EXT1
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set_location_assignment PIN_M9 -to EXT[4] #LVLB0 EXT4 - M9
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set_location_assignment PIN_M10 -to EXT[5] #LVLB1 EXT5 - M10
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set_location_assignment PIN_N10 -to EXT[6] #LVLB2 EXT6 - N10
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set_location_assignment PIN_M11 -to EXT[7] #LVLB3 EXT7 - M11
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set_location_assignment PIN_N11 -to EXT[8] #LVLB4 EXT8 - N11
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set_location_assignment PIN_M12 -to EXT[9] #LVLB5 EXT9 - M12
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set_location_assignment PIN_N12 -to EXT[10] #LVLB6 EXT10 - N12
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set_location_assignment PIN_M13 -to EXT[11] #LVLB7 EXT11 - M13
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_RST
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_INT
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SDA
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SCL
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[0]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[1]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[2]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[3]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[4]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[5]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[6]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[7]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[3]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[4]
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CLK_OUT
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set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SID
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set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to BCLK
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name VHDL_FILE flash_controller.vhd
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set_global_assignment -name VHDL_FILE stereo_detect.vhd
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set_global_assignment -name VHDL_FILE iox_glue.vhdl
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set_global_assignment -name VHDL_FILE i2c_master.vhd
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set_global_assignment -name VHDL_FILE slave_timing_6502.vhd
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set_global_assignment -name SDC_FILE pokeymax.sdc
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set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
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set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
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set_global_assignment -name VHDL_FILE enable_divider.vhdl
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set_global_assignment -name VHDL_FILE delay_line.vhdl
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set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
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set_global_assignment -name VHDL_FILE latch_delay_line.vhdl
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set_global_assignment -name VHDL_FILE sigmadelta_1storder.vhd
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set_global_assignment -name VHDL_FILE sigmadelta_2ndorder.vhd
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set_global_assignment -name VHDL_FILE filtered_sigmadelta.vhd
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set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
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set_global_assignment -name VHDL_FILE simple_low_pass_filter.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_poly_17_9.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_poly_5.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_poly_4.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_noise_filter.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_mixer_mux.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_mixer.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_keyboard_scanner.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey_countdown_timer.vhdl
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set_global_assignment -name VHDL_FILE pokey/pokey.vhdl
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set_global_assignment -name VHDL_FILE phi_mult.vhdl
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set_global_assignment -name VHDL_FILE synchronizer.vhdl
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set_global_assignment -name VHDL_FILE audiotypes.vhdl
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set_global_assignment -name VHDL_FILE mixer.vhdl
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set_global_assignment -name VHDL_FILE clockgen.vhd
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set_global_assignment -name VHDL_FILE spdif_transmitter.vhdl
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set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
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set_global_assignment -name VHDL_FILE ps2_to_atari800.vhdl
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set_global_assignment -name VHDL_FILE pokeymax.vhd
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set_global_assignment -name VHDL_FILE PSG/envelope.vhdl
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set_global_assignment -name VHDL_FILE PSG/noise.vhdl
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set_global_assignment -name VHDL_FILE PSG/top.vhdl
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set_global_assignment -name VHDL_FILE PSG/freqdiv.vhdl
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set_global_assignment -name VHDL_FILE PSG/mixer.vhdl
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set_global_assignment -name VHDL_FILE PSG/volume.vhdl
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set_global_assignment -name VHDL_FILE PSG/volume_profile.vhdl
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set_global_assignment -name VHDL_FILE SID/top.vhdl
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set_global_assignment -name VHDL_FILE SID/oscillator.vhdl
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set_global_assignment -name VHDL_FILE SID/wavegen.vhdl
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set_global_assignment -name VHDL_FILE SID/envelope.vhdl
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set_global_assignment -name VHDL_FILE SID/envelope_tapmatch.vhdl
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set_global_assignment -name VHDL_FILE SID/amplitudeModulator.vhdl
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set_global_assignment -name VHDL_FILE SID/preFilterSum.vhdl
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set_global_assignment -name VHDL_FILE SID/filter.vhdl
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set_global_assignment -name VHDL_FILE SID/f_distortion.vhdl
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set_global_assignment -name VHDL_FILE SID/f_distortion_mux.vhdl
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set_global_assignment -name VHDL_FILE SID/postFilterSum.vhdl
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set_global_assignment -name VHDL_FILE sample/channel.vhdl
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set_global_assignment -name VHDL_FILE sample/adpcm.vhdl
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set_global_assignment -name VHDL_FILE sample/top.vhdl
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set_global_assignment -name VHDL_FILE covox/top.vhdl
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set_global_assignment -name QIP_FILE int_osc/synthesis/int_osc.qip
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set_global_assignment -name QIP_FILE pll.qip
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set_global_assignment -name QIP_FILE flash/synthesis/flash.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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#AUD1
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#AUD2
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#AUD3
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#AUD4
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#AUDIN3
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#AUDIN4
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#GND
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#LVLA19 EXT1 - A12
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#LVLA21 EXT2 - B13
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#LVLA23 EXT3 - D13
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#LVLB0 EXT4 - M9
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#LVLB1 EXT5 - M10
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#LVLB2 EXT6 - N10
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#LVLB3 EXT7 - M11
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#LVLB4 EXT8 - N11
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#LVLB5 EXT9 - M12
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#LVLB6 EXT10 - N12
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#LVLB7 EXT11 - M13
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#1 =GND
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#2 =LVLA5 - A4
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#3 =LVLA0 - B1
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#4 =LVLA1 - A2
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#5 =LVLA2 - B2
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#6 =LVLA3 - A3
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#7 =LVLA4 - B3
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#8 =POT3 p6
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#9 =POT4 p7
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#10=POT5 p4
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#11=POT7 p5
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#12=POT0 p2
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#13=POT1 p3
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#14=POT2 p0
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#15=POT6 p1
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#16=KR2
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#17=5V
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#18=K5
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#19=K4
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#20=K3
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#40=LVLA17 - A11
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#39=LVLA16 - B10
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#38=LVLA15 - A10
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#37=AUDF1
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#36=LVLA18 - B11
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#35=LVLA20 - B12
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#34=LVLA22 - C13
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#33=LVLA9 - A6
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#32=LVLA8 - B5
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#31=LVLA10 - B6
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#30=LVLA7 - A5
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#29=LVLA6 - B4
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#28=LVLA14 - A9
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#27=LVLA13 - A8
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#26=LVLA12 - B7
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#25=KR1
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#24=LVLA11 - A7
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#23=K0
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#22=K1
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#21=K2
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#IOX
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#IOX_RST - M3
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#IOX_SDA - M4
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#IOX_SCL - M5
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#IOX_INT - M7
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#POT
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#POTRESET - M2
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#PIN3 - N2 - POT7
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#PIN2 - N3 - POT6
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#PIN0 - N4 - POT5
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#PIN1 - N5 - POT4
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#PIN7 - N6 - POT3
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#PIN6 - N7 - POT2
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#PIN4 - N8 - POT1
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#PIN5 - N9 - POT0
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#AUD - straight...
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#AUD1 - C11
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#AUD3 - D11
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#AUD2 - C12
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#AUD4 - D12
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#CLK
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#OUT - H8
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#CLK2 - G9
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#CLK0 - H6
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#CLK1 - H4
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