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---------------------------------------------------------------------------
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-- (c) 2018 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY stereo_detect IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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A : IN STD_LOGIC; -- raw
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DETECT : OUT STD_LOGIC
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);
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END stereo_detect;
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ARCHITECTURE vhdl OF stereo_detect IS
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signal addr_bit_sync : std_logic;
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signal addr_bit_sync_reg : std_logic;
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signal addr_bit_toggle_count_next : std_logic_vector(1 downto 0);
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signal addr_bit_toggle_count_reg : std_logic_vector(1 downto 0);
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BEGIN
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synchronizer_4 : entity work.synchronizer
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port map (clk=>clk, raw=>a, sync=>addr_bit_sync);
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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addr_bit_sync_reg <= '1';
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addr_bit_toggle_count_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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addr_bit_sync_reg <= addr_bit_sync;
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addr_bit_toggle_count_reg <= addr_bit_toggle_count_next;
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end if;
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end process;
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process(addr_bit_toggle_count_reg,addr_bit_sync,addr_bit_sync_reg)
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begin
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DETECT <= '0';
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addr_bit_toggle_count_next <= addr_bit_toggle_count_reg;
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if (addr_bit_toggle_count_reg="11") then
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DETECT <= '1';
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else
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if (not(addr_bit_sync = addr_bit_sync_reg)) then
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addr_bit_toggle_count_next <= std_logic_vector(unsigned(addr_bit_toggle_count_reg)+1);
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end if;
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end if;
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end process;
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end vhdl;
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