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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.all;
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LIBRARY work;
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ENTITY covox_top IS
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PORT
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(
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CLK : in std_logic;
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RESET_N : in std_logic;
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WRITE_ENABLE : in std_logic;
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ADDR : in std_logic_vector(1 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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AUDIO0 : out std_logic_vector(15 downto 0);
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AUDIO1 : out std_logic_vector(15 downto 0)
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);
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END covox_top;
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ARCHITECTURE vhdl OF covox_top IS
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signal addr_decoded: std_logic_vector(3 downto 0);
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signal CH1_REG : std_logic_vector(7 downto 0);
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signal CH0_REG : std_logic_vector(7 downto 0);
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signal CH1_NEXT : std_logic_vector(7 downto 0);
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signal CH0_NEXT : std_logic_vector(7 downto 0);
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signal CH3_REG : std_logic_vector(7 downto 0);
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signal CH2_REG : std_logic_vector(7 downto 0);
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signal CH3_NEXT : std_logic_vector(7 downto 0);
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signal CH2_NEXT : std_logic_vector(7 downto 0);
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BEGIN
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process(addr_decoded,CH0_REG,CH1_REG,CH2_REG,CH3_REG)
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begin
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DO <= (others=>'0');
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if (addr_decoded(0)='1') then
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DO <= CH0_REG;
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end if;
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if (addr_decoded(1)='1') then
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DO <= CH1_REG;
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end if;
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if (addr_decoded(2)='1') then
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DO <= CH2_REG;
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end if;
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if (addr_decoded(3)='1') then
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DO <= CH3_REG;
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end if;
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end process;
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decode_addr2 : entity work.complete_address_decoder
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generic map(width=>2)
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port map (addr_in=>ADDR(1 downto 0), addr_decoded=>addr_decoded);
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process(addr_decoded, WRITE_ENABLE,
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CH0_REG,CH1_REG,CH2_REG,CH3_REG,DI)
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variable l : unsigned(8 downto 0);
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variable r : unsigned(8 downto 0);
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begin
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CH0_NEXT <= CH0_REG;
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CH1_NEXT <= CH1_REG;
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CH2_NEXT <= CH2_REG;
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CH3_NEXT <= CH3_REG;
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l := resize(unsigned(CH0_REG),9) + resize(unsigned(CH3_REG),9);
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r := resize(unsigned(CH1_REG),9) + resize(unsigned(CH2_REG),9);
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AUDIO0 <= std_logic_vector(l)&"0000000";
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AUDIO1 <= std_logic_vector(r)&"0000000";
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if (WRITE_ENABLE='1') then
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if (addr_decoded(0)='1') then
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CH0_NEXT <= DI;
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end if;
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if (addr_decoded(1)='1') then
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CH1_NEXT <= DI;
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end if;
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if (addr_decoded(2)='1') then
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CH2_NEXT <= DI;
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end if;
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if (addr_decoded(3)='1') then
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CH3_NEXT <= DI;
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end if;
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end if;
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end process;
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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CH0_REG <= (others=>'0');
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CH1_REG <= (others=>'0');
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CH2_REG <= (others=>'0');
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CH3_REG <= (others=>'0');
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elsif (clk'event and clk='1') then
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CH0_REG <= CH0_NEXT;
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CH1_REG <= CH1_NEXT;
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CH2_REG <= CH2_NEXT;
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CH3_REG <= CH3_NEXT;
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end if;
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end process;
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END vhdl;
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