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---------------------------------------------------------------------------
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-- (c) 2018 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- TALK to PCAL6416A io expander over i2c
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-- goals:
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-- keyboard:
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-- set keyboard 6 lines to output
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-- drive keyboard 6 lines constantly
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-- receive keyboard 2 lines constantly
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-- review if we need pull ups on 2 keyboard inputs
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-- work out which pins in invert on keyboard
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-- pot:
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-- need to drive to 0 to reset
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-- otherwise need to sit at high impedence input
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-- so a single bit input is fed in to do this...
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ENTITY iox_glue IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENA : OUT STD_LOGIC;
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ADDR : OUT STD_LOGIC_VECTOR(7 downto 1);
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RW : OUT STD_LOGIC;
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WRITE_DATA : OUT STD_LOGIC_VECTOR(7 downto 0);
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BUSY : IN STD_LOGIC;
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READ_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
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ERROR : IN STD_LOGIC;
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INT : IN STD_LOGIC;
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POT_RESET : IN STD_LOGIC;
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KEYBOARD_SCAN : IN STD_LOGIC_VECTOR(5 downto 0);
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KEYBOARD_RESPONSE : OUT STD_LOGIC_VECTOR(1 downto 0);
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KEYBOARD_SCAN_UPDATE : IN STD_LOGIC;
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KEYBOARD_SCAN_ENABLE : OUT STD_LOGIC
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);
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END iox_glue;
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ARCHITECTURE vhdl OF iox_glue IS
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-- requests to send to i2c
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signal state_reg : std_logic_vector(3 downto 0);
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signal state_next : std_logic_vector(3 downto 0);
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constant state_setup1 : std_logic_vector(3 downto 0) := "0000";
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constant state_setup2 : std_logic_vector(3 downto 0) := "0001";
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constant state_setup3 : std_logic_vector(3 downto 0) := "0010";
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constant state_setup4 : std_logic_vector(3 downto 0) := "0011";
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constant state_setup5 : std_logic_vector(3 downto 0) := "0100";
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constant state_setup6 : std_logic_vector(3 downto 0) := "0101";
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--addr,$4f (open drain),00000001 (port 0 is open drain, port 1 is driven)
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--addr,$06 (cfg port0), 00000000
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--addr,$07 (cfg port1), 00000011 (p1_0,p1_1 are inputs)
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--addr,$47 (pull up/down),00000011 (use pull ups/downs)
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--addr,$49 (pull up/down),00000011 (use pull up 100ks)
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constant state_kbscan : std_logic_vector(3 downto 0) := "0110";
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constant state_kbread : std_logic_vector(3 downto 0) := "0111";
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constant state_potreset : std_logic_vector(3 downto 0) := "1000";
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constant state_setup7 : std_logic_vector(3 downto 0) := "1001";
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-- address, write input port0(02),val
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-- address, read input port1(01),0xff(in)
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-- address, write input port1(03),val
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signal w2 : std_logic;
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signal write1 : std_logic_vector(7 downto 0);
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signal write2 : std_logic_vector(7 downto 0);
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signal i2c_state_reg : std_logic_vector(1 downto 0);
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signal i2c_state_next : std_logic_vector(1 downto 0);
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constant i2c_state_part1 : std_logic_vector(1 downto 0) := "00";
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constant i2c_state_part2 : std_logic_vector(1 downto 0) := "01";
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constant i2c_state_part3 : std_logic_vector(1 downto 0) := "10";
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signal op_complete : std_logic;
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signal busy_reg : std_logic;
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signal pot_next : std_logic;
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signal pot_reg : std_logic;
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begin
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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state_reg <= state_setup1;
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i2c_state_reg <= i2c_state_part1;
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busy_reg <= '0';
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pot_reg <= '0';
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elsif (clk'event and clk='1') then
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state_reg <= state_next;
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i2c_state_reg <= i2c_state_next;
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busy_reg <= busy;
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pot_reg <= pot_next;
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end if;
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end process;
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process(i2c_state_reg,w2,write1,write2,busy_reg,busy)
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variable busy_latched : std_logic;
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begin
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i2c_state_next <= i2c_state_reg;
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ena <= '0';
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addr <= "0100000"; -- $40
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rw <= '1';
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write_data <= (others=>'0');
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op_complete <= '0';
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busy_latched := '0';
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if(busy_reg = '0' AND busy = '1') then
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busy_latched := '1';
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end if;
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case (i2c_state_reg) is
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when i2c_state_part1 =>
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ena <= '1';
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rw <= '0';
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write_data <= write1;
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if (busy_latched='1') then
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i2c_state_next <= i2c_state_part2;
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end if;
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when i2c_state_part2 =>
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ena <= '1';
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rw <= not(w2);
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write_data <= write2;
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if (busy_latched='1') then
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i2c_state_next <= i2c_state_part3;
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end if;
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when i2c_state_part3 =>
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ena <= '0';
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if (busy='0') then
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i2c_state_next <= i2c_state_part1;
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op_complete <= '1';
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end if;
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when others =>
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i2c_state_next <= i2c_state_part1;
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end case;
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end process;
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process(state_reg,pot_reset,keyboard_scan,busy,busy_reg,read_data,op_complete,pot_reg)
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begin
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state_next <= state_reg;
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pot_next <= pot_reg;
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keyboard_response <= "11";
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keyboard_scan_enable <= '0';
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w2 <= '0';
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write1 <= x"ff";
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write2 <= x"ff";
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case (state_reg) is
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when state_setup1 =>
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w2 <= '1';
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write1 <= x"4f";
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write2 <= "00000001";
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if (op_complete='1') then
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state_next <= state_setup2;
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end if;
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when state_setup2 =>
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w2 <= '1';
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write1 <= x"06";
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write2 <= "00000000";
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if (op_complete='1') then
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state_next <= state_setup3;
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end if;
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when state_setup3 =>
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w2 <= '1';
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write1 <= x"07";
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write2 <= "00000011";
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if (op_complete='1') then
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state_next <= state_setup4;
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end if;
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when state_setup4 =>
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w2 <= '1';
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write1 <= x"47";
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write2 <= "00000011";
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if (op_complete='1') then
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state_next <= state_setup5;
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end if;
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when state_setup5 =>
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w2 <= '1';
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write1 <= x"49";
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write2 <= "00000011";
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if (op_complete='1') then
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state_next <= state_setup6;
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end if;
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when state_setup6 =>
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w2 <= '1';
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write1 <= x"4b";
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write2 <= "11111100";
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if (op_complete='1') then
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state_next <= state_setup7;
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end if;
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when state_setup7 =>
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w2 <= '1';
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write1 <= x"4f";
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write2 <= "00000001";
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if (op_complete='1') then
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state_next <= state_kbscan;
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end if;
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when state_potreset =>
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w2 <= '1';
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write1 <= x"02";
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write2 <= not(pot_reset&pot_reset&pot_reset&pot_reset&pot_reset&pot_reset&pot_reset&pot_reset);
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pot_next <= pot_reset;
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if (op_complete='1') then
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state_next <= state_kbscan;
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end if;
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when state_kbread =>
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w2 <= '0';
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write1 <= x"01";
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write2 <= x"ff";
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if (op_complete='1') then
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keyboard_response <= read_data(0)&read_data(1);
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keyboard_scan_enable <= '1';
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state_next <= state_kbscan;
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end if;
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when state_kbscan =>
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w2 <= '1';
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write1 <= x"03";
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-- Some pokey bits are inverted (k2,k1,k0,k5), handle FPGA side
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--write2 <= not(keyboard_scan(5))&keyboard_scan(4)&keyboard_scan(3)¬(keyboard_scan(0)&keyboard_scan(1)&keyboard_scan(2))&"00";
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write2 <= keyboard_scan(5)&keyboard_scan(4)&keyboard_scan(3)&keyboard_scan(0)&keyboard_scan(1)&keyboard_scan(2)&"00";
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if (op_complete='1') then
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if(not(pot_reset=pot_reg)) then
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state_next <= state_potreset;
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else
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state_next <= state_kbread;
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end if;
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end if;
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when others =>
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state_next <= state_setup1;
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end case;
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end process;
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end vhdl;
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