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-- megafunction wizard: %Soft LVDS Intel FPGA IP v23.1%
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-- GENERATION: XML
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-- lvds_rx.vhd
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-- Generated using ACDS version 23.1 993
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity lvds_rx is
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port (
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data : in std_logic_vector(0 downto 0) := (others => '0'); -- data.data
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clock : in std_logic := '0'; -- clock.clock
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q : out std_logic_vector(0 downto 0) -- q.q
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);
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end entity lvds_rx;
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architecture rtl of lvds_rx is
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component altera_soft_lvds_rx_uCmNW05P is
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port (
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data : in std_logic_vector(0 downto 0) := (others => 'X'); -- data
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clock : in std_logic := 'X'; -- clock
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q : out std_logic_vector(0 downto 0) -- q
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);
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end component altera_soft_lvds_rx_uCmNW05P;
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begin
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lvds_rx_inst : component altera_soft_lvds_rx_uCmNW05P
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port map (
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data => data, -- data.data
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clock => clock, -- clock.clock
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q => q -- q.q
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);
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end architecture rtl; -- of lvds_rx
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-- Retrieval info: <?xml version="1.0"?>
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--<!--
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-- Generated by Altera MegaWizard Launcher Utility version 1.0
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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-- ************************************************************
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-- Copyright (C) 1991-2024 Altera Corporation
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-- Any megafunction design, and related net list (encrypted or decrypted),
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-- support information, device programming or simulation file, and any other
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-- associated documentation or information provided by Altera or a partner
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-- under Altera's Megafunction Partnership Program may be used only to
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-- program PLD devices (but not masked PLD devices) from Altera. Any other
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-- use of such megafunction design, net list, support information, device
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-- programming or simulation file, or any other related documentation or
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-- information is prohibited for any other purpose, including, but not
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-- limited to modification, reverse engineering, de-compiling, or use with
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-- any other silicon devices, unless such use is explicitly licensed under
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-- a separate agreement with Altera or a megafunction partner. Title to
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-- the intellectual property, including patents, copyrights, trademarks,
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-- trade secrets, or maskworks, embodied in any such megafunction design,
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-- net list, support information, device programming or simulation file, or
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-- any other related documentation or information provided by Altera or a
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-- megafunction partner, remains with Altera, the megafunction partner, or
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-- their respective licensors. No other licenses, including any licenses
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-- needed under any third party's intellectual property, are provided herein.
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---->
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-- Retrieval info: <instance entity-name="altera_soft_lvds" version="23.1" >
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-- Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
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-- Retrieval info: <generic name="DEVICE_TYPE" value="Single Supply" />
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-- Retrieval info: <generic name="FUNCTIONAL_MODE" value="RX" />
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-- Retrieval info: <generic name="NUMBER_OF_CHANNELS" value="1" />
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-- Retrieval info: <generic name="DESERIALIZATION_FACTOR" value="1" />
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-- Retrieval info: <generic name="USE_EXTERNAL_PLL_UI" value="false" />
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-- Retrieval info: <generic name="INPUT_DATA_RATE" value="720.0" />
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-- Retrieval info: <generic name="VALID_FREQ" value="200.00" />
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-- Retrieval info: <generic name="ENABLE_RX_LOCKED_PORT_UI" value="false" />
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-- Retrieval info: <generic name="ENABLE_TX_LOCKED_PORT_UI" value="false" />
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-- Retrieval info: <generic name="ENABLE_PLL_ARESET_PORT_UI" value="true" />
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-- Retrieval info: <generic name="ENABLE_PLL_TX_DATA_RESET_PORT_UI" value="false" />
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-- Retrieval info: <generic name="ENABLE_PLL_RX_DATA_RESET_PORT_UI" value="false" />
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-- Retrieval info: <generic name="COMMON_RX_TX_PLL_UI" value="false" />
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-- Retrieval info: <generic name="PLL_SELF_RESET_ON_LOSS_LOCK_UI" value="false" />
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-- Retrieval info: <generic name="PORT_RX_DATA_ALIGN_UI" value="false" />
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-- Retrieval info: <generic name="PORT_RX_CHANNEL_DATA_ALIGN_UI" value="false" />
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-- Retrieval info: <generic name="USE_CDA_RESET_UI" value="true" />
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-- Retrieval info: <generic name="PORT_RX_DATA_ALIGN_RESET_UI" value="false" />
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-- Retrieval info: <generic name="REGISTERED_DATA_ALIGN_INPUT_UI" value="false" />
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-- Retrieval info: <generic name="DATA_ALIGN_ROLLOVER" value="4" />
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-- Retrieval info: <generic name="REGISTERED_OUTPUT_UI" value="true" />
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-- Retrieval info: <generic name="ENABLE_TX_OUTCLOCK_PORT_UI" value="true" />
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-- Retrieval info: <generic name="OUTCLOCK_DIVIDE_BY_UI" value="1" />
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-- Retrieval info: <generic name="OUTCLOCK_DUTY_CYCLE_UI" value="50" />
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-- Retrieval info: <generic name="TX_OUTCLOCK_PHASE_SHIFT_UI" value="0.00" />
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-- Retrieval info: <generic name="TX_INCLOCK_PHASE_SHIFT_UI" value="0.00" />
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-- Retrieval info: <generic name="RX_INCLOCK_PHASE_SHIFT_UI" value="0.00" />
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-- Retrieval info: <generic name="RX_OUTCLOCK_PHASE_SHIFT_UI" value="0.00" />
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-- Retrieval info: <generic name="REGISTERED_INPUT_ENABLED_UI" value="false" />
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-- Retrieval info: <generic name="REGISTERED_INPUT_UI" value="tx_coreclock" />
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-- Retrieval info: <generic name="ENABLE_TX_CORECLOCK_PORT_UI" value="false" />
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-- Retrieval info: <generic name="OUTCLOCK_RESOURCE_UI" value="Auto selection" />
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-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_RAM_UI" value="false" />
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-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_MUX_UI" value="false" />
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-- Retrieval info: <generic name="BUFFER_IMPLEMENTATION_LE_UI" value="false" />
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-- Retrieval info: <generic name="LVDS_RX_REG_SETTING_UI" value="false" />
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-- Retrieval info: <generic name="IMPLEMENT_IN_LES" value="ON" />
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-- Retrieval info: <generic name="CARRY_CHAIN_LENGTH" value="48" />
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-- Retrieval info: <generic name="DPA_INITIAL_PHASE_VALUE" value="0" />
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-- Retrieval info: <generic name="DPLL_LOCK_COUNT" value="0" />
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-- Retrieval info: <generic name="DPLL_LOCK_WINDOW" value="0" />
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-- Retrieval info: <generic name="INCLOCK_BOOST" value="0" />
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-- Retrieval info: <generic name="SIM_DPA_NET_PPM_VARIATION" value="0" />
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-- Retrieval info: <generic name="SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT" value="0" />
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-- Retrieval info: <generic name="CARRY_CHAIN" value="MANUAL" />
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-- Retrieval info: <generic name="CYCLONEII_M4K_COMPATIBILITY" value="ON" />
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-- Retrieval info: <generic name="ENABLE_DPA_ALIGN_TO_RISING_EDGE_ONLY" value="OFF" />
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-- Retrieval info: <generic name="ENABLE_DPA_CALIBRATION" value="ON" />
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-- Retrieval info: <generic name="ENABLE_DPA_INITIAL_PHASE_SELECTION" value="OFF" />
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-- Retrieval info: <generic name="ENABLE_DPA_MODE" value="OFF" />
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-- Retrieval info: <generic name="ENABLE_DPA_PLL_CALIBRATION" value="OFF" />
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-- Retrieval info: <generic name="ENABLE_SOFT_CDR_MODE" value="OFF" />
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-- Retrieval info: <generic name="INCLOCK_DATA_ALIGNMENT" value="EDGE_ALIGNED" />
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-- Retrieval info: <generic name="LOW_POWER_MODE" value="AUTO" />
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-- Retrieval info: <generic name="SIM_DPA_IS_NEGATIVE_PPM_DRIFT" value="OFF" />
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-- Retrieval info: <generic name="USE_DPLL_RAWPERROR" value="OFF" />
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-- Retrieval info: <generic name="USE_NO_PHASE_SHIFT" value="ON" />
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-- Retrieval info: <generic name="X_ON_BITSLIP" value="ON" />
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-- Retrieval info: <generic name="DIFFERENTIAL_DRIVE" value="0" />
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-- Retrieval info: <generic name="ENABLE_CLK_LATENCY" value="OFF" />
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-- Retrieval info: <generic name="MULTI_CLOCK" value="OFF" />
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-- Retrieval info: <generic name="OUTCLOCK_ALIGNMENT" value="EDGE_ALIGNED" />
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-- Retrieval info: <generic name="PLL_COMPENSATION_MODE" value="AUTO" />
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-- Retrieval info: <generic name="PREEMPHASIS_SETTING" value="0" />
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-- Retrieval info: <generic name="VOD_SETTING" value="0" />
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-- Retrieval info: </instance>
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-- IPFS_FILES : lvds_rx.vho
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-- RELATED_FILES: lvds_rx.vhd, altera_soft_lvds_rx_uCmNW05P.v
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